A pressure sensor and method of forming the same

Abstract

The application discloses a pressure sensor and a forming method thereof. The pressure sensor comprises a first substrate, a second substrate, a first pressure-sensitive resistor and a second pressure-sensitive resistor. The first substrate has a first surface, a first groove, a second groove and an integrated first supporting column. The first supporting column is located between the first groove and the second groove, and the first groove and the second groove are not communicated. The second substrate comprises a first area and a second area. The first area has a first projection on a second surface. The first groove has a second projection on the second surface. The first projection is within the range of the second projection. The second area has a third projection on the second surface. The second groove has a fourth projection on the second surface. The third projection is within the range of the fourth projection. The first pressure-sensitive resistor is located on a third surface of the first area. The second pressure-sensitive resistor is located on a third surface of the second area. The application can meet the pressure measurement requirements of two ranges with a single chip, and is beneficial to reducing the overall volume of the pressure sensor and improving the integration.

Description

Technical Field

[0001] This application relates to the field of MEMS sensor technology, and in particular to a pressure sensor and a method for forming the same. Background Technology

[0002] Pressure sensors are used for pressure measurement and monitoring. A piezoresistive resistor is the core component of a pressure sensor. The resistance of a piezoresistive resistor changes with the applied pressure; this characteristic (piezoresistive effect) allows it to convert mechanical pressure signals into electrical signals. Specifically, when a piezoresistive resistor is subjected to external force (pressure), the crystal lattice structure inside the material deforms, causing a change in the mobility of charge carriers (electrons or holes), thus resulting in a change in the resistance value. Consequently, the voltage signal of the piezoresistive resistor changes. This voltage signal is then output to a control module, which converts the voltage signal into a pressure value, thereby enabling pressure measurement and monitoring.

[0003] MEMS (micro-electro-mechanical systems) piezoresistive pressure sensors are widely used in consumer electronics, wearable devices, smart homes, medical devices, automotive electronics, and industrial control due to their high sensitivity and good linearity. In wearable devices (such as smartwatches and smart bracelets), users require both short-range pressure sensitivity for monitoring weather conditions (e.g., by measuring atmospheric pressure) and short-range altitude changes for calculating calories burned when climbing stairs. Simultaneously, users also require long-range pressure measurement capabilities, such as deep-water pressure detection in underwater operations, providing precise vertical positioning. Therefore, single-range pressure chips are insufficient to meet these requirements. Summary of the Invention

[0004] This application provides a pressure sensor and a method for forming the same, to at least partially solve the above-mentioned technical problems.

[0005] To achieve the above objectives, according to a first aspect of this application, a pressure sensor is provided, comprising: The first substrate has a first surface, a first groove recessed relative to the first surface, a second groove recessed relative to the first surface, and an integrated first support post, wherein the first support post is located between the first groove and the second groove, and the first groove and the second groove are not connected. A second substrate is stacked with the first substrate along a first direction, the second substrate having a second surface and a third surface opposite to each other, the second surface being bonded and fixed to the first surface; The second substrate includes a first region and a second region. The first region has a first projection on the second surface, and the first groove has a second projection on the second surface, with the first projection within the range of the second projection. The second region has a third projection on the second surface, and the second groove has a fourth projection on the second surface, with the third projection within the range of the fourth projection. A first varistor is located on the third surface of the first region, and the first varistor is used to output a first voltage signal; The second varistor is located on the third surface of the second region, and the second varistor is used to output a second voltage signal.

[0006] In some embodiments, the second groove surrounds the first support post, and the first support post surrounds the first groove; The shape of the second projection includes a rectangle, and the shape of the fourth projection includes a square.

[0007] In some embodiments, the pressure sensor further includes: a first dielectric layer located on the third surface; The first conductive structure includes a first via structure penetrating the first dielectric layer, the first via structure being coupled to the first varistor; The second conductive structure includes a second via structure that penetrates the first dielectric layer, and the second via structure is coupled to the second varistor.

[0008] In some embodiments, the first conductive structure further includes: a first conductor and a first pad located on the surface of the first dielectric layer and coupled to each other, wherein the first conductor is coupled to the first via structure; The second conductive structure further includes: a second conductor and a second pad located on the surface of the first dielectric layer and coupled to each other, wherein the second conductor is coupled to the second via structure.

[0009] In some embodiments, the pressure sensor further includes: a second dielectric layer located on the surface of the first dielectric layer; The third conductive structure includes a third via structure that penetrates the second dielectric layer, the third via structure being coupled to the first pad; The fourth conductive structure includes a fourth via structure penetrating the second dielectric layer, the fourth via structure being coupled to the second pad.

[0010] In some embodiments, the third conductive structure further includes: a third conductor and a first connection portion located on the surface of the second dielectric layer and coupled to each other, wherein the third conductor is coupled to the third via structure; The fourth conductive structure further includes: a fourth conductor and a second connecting portion located on the surface of the second dielectric layer and coupled to each other, wherein the fourth conductor is coupled to the fourth via structure.

[0011] In some embodiments, in the second direction, the first connecting portion is located on one side of the second groove, and the second connecting portion is located on the other side of the second groove; or, in the third direction, the first connecting portion is located on one side of the second groove, and the second connecting portion is located on the other side of the second groove; wherein, the second direction and the third direction intersect each other and are both perpendicular to the first direction.

[0012] In some embodiments, the first connection portion includes a third pad, a fourth pad, a fifth pad, and a sixth pad; the second connection portion includes a seventh pad, an eighth pad, a ninth pad, and a tenth pad. In either the second or third direction, the third pad and the fourth pad are located on one side of the second groove, and the fifth pad and the sixth pad are located on the other side of the second groove; In the second direction or the third direction, the seventh and eighth pads are located on one side of the second groove, and the ninth and tenth pads are located on the other side of the second groove; wherein the second direction and the third direction intersect each other and are both perpendicular to the first direction.

[0013] In some embodiments, the first substrate further includes an integrated second support post, the second support post surrounding the second groove; The surface of the first support column opposite to the bottom of the second groove is bonded and fixed to the second surface, and the surface of the second support column opposite to the bottom of the second groove is bonded and fixed to the second surface.

[0014] According to a second aspect of this application, a method for forming a pressure sensor as described in any of the foregoing embodiments is provided, comprising: A first substrate is provided, the first substrate having a first surface; The first substrate is patterned to form a first groove recessed relative to the first surface, a second groove recessed relative to the first surface, and an integrated first support post. The first support post is located between the first groove and the second groove, and the first groove and the second groove are not connected. A second substrate is provided, the second substrate having opposing second and third surfaces, the second substrate including a first region and a second region, the first region having a first projection on the second surface, and the second region having a third projection on the second surface; The second surface of the second substrate is bonded and fixed to the first surface of the first substrate. The first groove has a second projection on the second surface, and the first projection is within the range of the second projection. The second groove has a fourth projection on the second surface, and the third projection is within the range of the fourth projection. A first varistor is formed on the third surface of the first region, and the first varistor is used to output a first voltage signal; A second varistor is formed on the third surface of the second region, and the second varistor is used to output a second voltage signal.

[0015] The embodiments of this application have the following beneficial effects: Based on the pressure sensor provided in this application embodiment, since the stiffness of the first region is less than that of the second region, when the second substrate is subjected to external pressure (stress), the first piezoresistor located in the first region is in a high-stress state, and the first pressure signal output by the first piezoresistor is relatively large, which is suitable for small-range pressure measurement. That is, when sensing a small pressure, the first pressure signal is converted into a target pressure value as the final measurement result of the pressure sensor. The second piezoresistor is in a low-stress state, and the second pressure signal output by the second piezoresistor is relatively small, which is suitable for large-range pressure measurement. That is, when sensing a large pressure, the second pressure signal is converted into a target pressure value as the final measurement result of the pressure sensor. This realizes the simultaneous measurement of pressure in two ranges using a single sensor chip, effectively reducing the size of the pressure sensor, meeting the pressure measurement needs of multiple scenarios, and simultaneously meeting the compact size requirements of wearable devices.

[0016] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0018] Figure 1 This is a partial cross-sectional view of a pressure sensor provided in an exemplary embodiment of this disclosure; Figure 2 This is a cross-sectional view of the first substrate provided in an exemplary embodiment of this disclosure; Figure 3 This is a top view of the first substrate provided in an exemplary embodiment of this disclosure; Figure 4 This is a partial cross-sectional view of a pressure sensor provided in an exemplary embodiment of this disclosure; Figure 5 This is a top view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 6 This is a partial cross-sectional view of a pressure sensor provided in an exemplary embodiment of this disclosure; Figure 7 This is a top view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 8 This is a partial cross-sectional view of a pressure sensor provided in an exemplary embodiment of this disclosure; Figure 9 This is a top view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 10 This is a top view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 11 This is a cross-sectional view of a pressure sensor provided in an exemplary embodiment of this disclosure; Figure 12 This is a top view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 13 This is a top view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 14 This is a top view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 15 This is a schematic flowchart illustrating a method for forming a pressure sensor provided in an exemplary embodiment of this disclosure.

[0019] Explanation of reference numerals in the attached figures: 1-First substrate; 11-First surface; 12-First groove; 13-Second groove; 14-First support post; 15-Second support post; 2-Second substrate; 21-Second surface; 22-Third surface; 23-First region; 24-Second region; 31-First varistor; 32-Second varistor; 41-First dielectric layer; 42-Second dielectric layer; 51-First via structure; 52-Second via structure; 53-First conductor; 54-First pad; 55-Second conductor; 56-Second pad; 61-Third via structure; 62-Fourth via structure; 63-Third conductor; 64-First connector; 641-Third pad; 642-Fourth pad; 643-Fifth pad; 644-Sixth pad; 65-Fourth conductor; 66-Second connector; 661-Seventh pad; 662-Eighth pad; 663-Ninth pad; 664-Tenth pad; 71-First heavily doped conductive region; 72-Second heavily doped conductive region; 8-Second via; Z - First direction; Y - Second direction; X - Third direction. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0021] This application provides a pressure sensor, see the following embodiment. Figure 1 As shown, the pressure sensor includes: The first substrate 1 has a first surface 11, a first groove 12 recessed relative to the first surface 11, a second groove 13 recessed relative to the first surface 11, and an integrated first support post 14. The first support post 14 is located between the first groove 12 and the second groove 13, and the first groove 12 and the second groove 13 are not connected. A second substrate 2 is stacked with the first substrate 1 along the first direction Z. The second substrate 2 has a second surface 21 and a third surface 22 opposite to each other. The second surface 21 is bonded and fixed to the first surface 11. The second substrate 2 includes a first region 23 and a second region 24. The first region 23 has a first projection on the second surface 21, and the first groove 12 has a second projection on the second surface 21. The first projection is within the range of the second projection. The second region 24 has a third projection on the second surface 21, and the second groove 13 has a fourth projection on the second surface 21. The third projection is within the range of the fourth projection. The first varistor 31 is located on the third surface 22 of the first region 23. The first varistor 31 is used to output the first voltage signal. The second varistor 32 is located on the third surface 22 of the second region 24, and the second varistor 32 is used to output the second voltage signal.

[0022] In some embodiments, the first projection and the second projection can completely overlap, and the third projection and the fourth projection can completely overlap.

[0023] In this embodiment, the first region 23 is disposed above the first groove 12, which provides a suspended deformation space for the first region 23, making it easier for the first region 23 to deform under pressure. Therefore, the equivalent stiffness of the first region 23 is relatively small (compared to the second region 24). The second region 24 is disposed above the second groove 13, with its inner side adjacent to the first support column 14 and its outer side adjacent to the bonding support area, thus forming a more adequately supported force-bearing structure. This results in a relatively smaller deformation of the second region 24 under pressure, and therefore a relatively larger equivalent stiffness (compared to the first region 23). Under the same stress conditions, the first piezoresistive resistor 31 located in the first region 23 senses a larger strain and outputs a larger first voltage signal. Therefore, the first piezoresistive resistor 31 has higher sensitivity and is suitable for detecting small-range pressure. The second piezoresistive resistor 32 located in the second region 24 senses a relatively smaller strain and outputs a smaller second voltage signal. Therefore, the second piezoresistive resistor 32 has lower sensitivity and is suitable for detecting large-range pressure.

[0024] In some embodiments, the pressure sensor and the control module (IC chip) are coupled together. A first voltage signal and a second voltage signal are output to the control module. The control module calculates and analyzes the first voltage signal or the second voltage signal to obtain the target pressure value, which is used as the final measurement result of the pressure sensor.

[0025] Because the stiffness of the first region 23 is less than that of the second region 24, when the second substrate 2 is subjected to external pressure (stress), the first piezoresistor 31 located in the first region 23 is in a high-stress state. The first pressure signal output by the first piezoresistor 31 is relatively large, suitable for small-range pressure measurement. That is, when sensing small pressure, the first pressure signal is converted into a target pressure value, which is used as the final measurement result of the pressure sensor. The second piezoresistor 32 is in a low-stress state, and the second pressure signal output by the second piezoresistor 32 is relatively small, suitable for large-range pressure measurement. That is, when sensing large pressure, the second pressure signal is converted into a target pressure value, which is used as the final measurement result of the pressure sensor. It should be noted that when the second substrate 2 is subjected to external pressure (stress), the first piezoresistor 31 outputs a first voltage signal to the control module, and at the same time, the second piezoresistor 32 outputs a second voltage signal to the control module. The control module determines which voltage signal's calculation result to use as the target pressure value.

[0026] Specifically, the control module receives and analyzes a first voltage signal, calculates a first pressure value, and if the first pressure value meets a preset small-range pressure interval, it is used as the target pressure value acquired by the pressure sensor. If the first pressure value does not meet the preset small-range pressure interval, the control module receives and analyzes a second voltage signal, calculates a second pressure value, and uses the second pressure value as the target pressure value acquired by the pressure sensor. In other embodiments, the control module may also preferentially calculate the second pressure value using the second voltage signal, detect whether the second pressure value meets a preset large-range pressure interval, and if the second pressure value meets the preset large-range pressure interval, it is used as the target pressure value acquired by the pressure sensor. If the second pressure value does not meet the preset large-range pressure interval, the first pressure value is calculated using the first voltage signal and used as the target pressure value acquired by the pressure sensor.

[0027] It should be noted that, in some embodiments, the small-range pressure range is 30 kPa to 400 kPa, and the large-range pressure range is 1 MPa to 2 MPa.

[0028] Through the above embodiments, sensing areas suitable for small-range pressure detection and large-range pressure detection are integrated into the same pressure sensor chip, so that a single chip can meet the pressure measurement needs of different ranges without the need to set up separate sensor chips for different ranges. This helps to reduce the overall size of the pressure sensor, improve the integration, and meet the requirements of wearable devices for compact size and multi-scenario applications.

[0029] The pressure sensor and its manufacturing method will be explained in detail below with reference to the accompanying drawings.

[0030] In some implementations, the pressure sensor has a first direction Z, a second direction Y, and a third direction X that are mutually perpendicular to each other.

[0031] In some embodiments, see Figure 2 and Figure 3 As shown, Figure 2 yes Figure 3 The cross-sectional view at point AA' shows that the first substrate 1 has a first surface 11 (upper surface), a first groove 12 recessed relative to the first surface 11, a second groove 13 recessed relative to the first surface 11, and an integrated first support post 14. The first support post 14 is continuous and located between the first groove 12 and the second groove 13. Due to the separating effect of the first support post 14, the first groove 12 and the second groove 13 are not connected. The second groove 13 surrounds the first support post 14, and the first support post 14 surrounds the first groove 12. The shape of the second projection includes a rectangle, and the shape of the fourth projection includes a square. The material of the first substrate 1 includes silicon.

[0032] In some embodiments, see Figure 2 and Figure 3 As shown, the first substrate 1 also has an integrated second support post 15, which surrounds the second groove 13. The second support post 15 has a fifth projection on the second surface 21, and the shape of the fifth projection includes a square shape. It should be noted that the shapes of the second projection, the fourth projection, and the fifth projection are matched. If the second projection is rectangular, then the fourth projection is square, and the fifth projection is square.

[0033] In some embodiments, the dimension (depth) of the first groove 12 along the first direction Z is equal to the dimension of the second groove 13 along the first direction Z. The dimension of the first groove 12 along the first direction Z ranges from 2 μm to 20 μm.

[0034] In some embodiments, see Figure 3 As shown, the dimension L1 of the first support column 14 along the third direction X is greater than 30 μm. The dimension L2 of the first support column 14 along the second direction Y is greater than 30 μm.

[0035] In some embodiments, the second substrate 2 is a cuboid, and the projection of the second substrate 2 along the first direction Z coincides with the projection of the first substrate 1 along the first direction Z. The material of the second substrate 2 includes silicon. The second substrate 2 has a second surface 21 (lower surface) and a third surface 22 (upper surface) opposite each other.

[0036] In some embodiments, see Figure 4 As shown, the second surface 21 is bonded and fixed to the first surface 11, and then thinned to a suitable thickness by chemical mechanical polishing. Specifically, the surface of the first support post 14 facing away from the bottom of the second groove 13 is bonded and fixed to the second surface 21, and the surface of the second support post 15 facing away from the bottom of the second groove 13 is bonded and fixed to the second surface 21. The first groove 12 forms the first cavity structure, and the second groove 13 forms the second cavity structure. It is worth mentioning that, in this embodiment, the surface of the first support post 14 facing away from the bottom of the second groove 13 is flush with the first surface 11, and the surface of the second support post 15 facing away from the bottom of the second groove 13 is flush with the first surface 11.

[0037] In some embodiments, see Figure 4 As shown, the first region 23 and the first groove 12 are stacked along the first direction Z, and the second region 24 and the second groove 13 are stacked along the first direction Z.

[0038] In some embodiments, see Figure 1 and Figure 5 As shown, Figure 1 yes Figure 5The cross-sectional view at BB' shows that on the third surface 22, a first varistor 31 and a second varistor 32 are formed by diffusion or ion implantation. Furthermore, a first heavily doped conductive region 71 (not shown) coupled to the first varistor 31 and a second heavily doped conductive region 72 (not shown) coupled to the second varistor 32 can be formed simultaneously. The first varistor 31 and the first heavily doped conductive region 71 are integrally formed and disposed in the same layer. The doping concentrations of the first varistor 31 and the first heavily doped conductive region 71 are different, resulting in different resistance values. The second varistor 32 and the second heavily doped conductive region 72 are integrally formed and disposed in the same layer. The doping concentrations of the second varistor 32 and the second heavily doped conductive region 72 are different, resulting in different resistance values. The first heavily doped conductive region 71 is used to increase the contact area of ​​the first varistor 31, and the second heavily doped conductive region 72 is used to increase the contact area of ​​the second varistor 32, facilitating the extraction of voltage signals.

[0039] In some embodiments, see Figure 6 and Figure 7 As shown, it should be noted that in Figure 7 For ease of illustration, the first dielectric layer 41 is omitted. A first dielectric layer 41 is grown on the third surface 22 of the second substrate 2. The material of the first dielectric layer 41 includes silicon oxide, silicon nitride, and a silicon oxide-silicon nitride composite. A first via (not shown) is etched into the first dielectric layer 41, penetrating the first dielectric layer 41 along a first direction Z. The first via and a first heavily doped conductive region 71 are stacked along the first direction Z, and the first via and the second heavily doped conductive region 72 are stacked along the first direction Z. A first via structure 51 is formed in the first via corresponding to the first heavily doped conductive region 71. A first varistor 31 is coupled to the first heavily doped conductive region 71, and the first heavily doped conductive region 71 is coupled to the first via structure 51. A second via structure 52 is formed in the first via corresponding to the second heavily doped conductive region 72. A second varistor 32 and the second heavily doped conductive region 72 are coupled, and the second heavily doped conductive region 72 and the second via structure 52 are coupled. The first via structure 51 constitutes the first conductive structure. The second via structure 52 constitutes the second conductive structure.

[0040] In some embodiments, see Figure 6 and Figure 7As shown, a first conductive structure and a second conductive structure are further formed on the surface of the first dielectric layer 41. The first conductive structure further includes a first conductor 53 and a first pad 54 located on the surface of the first dielectric layer 41 and coupled to each other, with the first conductor 53 coupled to a first via structure 51. The second conductive structure further includes a second conductor 55 and a second pad 56 located on the surface of the first dielectric layer 41 and coupled to each other, with the second conductor 55 coupled to a second via structure 52. Multiple first varistors 31 are interconnected through the first conductor 53, forming a Wheatstone bridge. Multiple second varistors 32 are interconnected through the second conductor 55, forming a Wheatstone bridge. The first conductor 53 and the first pad 54 are made of aluminum. The second conductor 55 and the second pad 56 are made of aluminum.

[0041] In some implementations, refer to Figure 8 As shown, a second dielectric layer 42 is formed on the surface of the first dielectric layer 41. A first conductive structure is located between the first dielectric layer 41 and the second dielectric layer 42, and a second conductive structure is located between the first dielectric layer 41 and the second dielectric layer 42. The material of the second dielectric layer 42 includes silicon oxide, silicon nitride, and a silicon nitride-silicon oxide composite. After the second dielectric layer 42 is formed, its surface can be chemically mechanically polished to smooth it out and avoid surface undulations caused by the presence of the first and second conductive structures.

[0042] In some embodiments, see Figure 9 , Figure 10 and Figure 11 As shown, a second via 8 is etched into the second dielectric layer 42, penetrating the second dielectric layer 42 along the first direction Z. The second via 8 and the first pad 54 are stacked along the first direction Z, and the second via 8 and the second pad 56 are stacked along the first direction Z. A third via structure 61 is formed in the second via 8 corresponding to the first pad 54, and the third via structure 61 is coupled to the first pad 54. A fourth via structure 62 is formed in the second via 8 corresponding to the second pad 56, and the fourth via structure 62 is coupled to the second pad 56. The third via structure 61 constitutes a third conductive structure. The fourth via structure 62 constitutes a fourth conductive structure.

[0043] In some embodiments, see Figure 10 and Figure 11 As shown, Figure 10The first dielectric layer 41 and the second dielectric layer 42 are omitted. A third conductive structure and a fourth conductive structure are formed on the surface of the second dielectric layer 42. The third conductive structure further includes a third conductor 63 and a first connection portion 64 located on the surface of the second dielectric layer 42 and coupled to each other. The third conductor 63 is coupled to the third via structure 61. The fourth conductive structure further includes a fourth conductor 65 and a second connection portion 66 located on the surface of the second dielectric layer 42 and coupled to each other. The fourth conductor 65 is coupled to the fourth via structure 62. The materials of the third conductor 63 and the first connection portion 64 are aluminum. The materials of the fourth conductor 65 and the second connection portion 66 are aluminum. The first connection portion 64 is coupled to the control module. The second connection portion 66 is coupled to the control module. The first connection portion 64 includes multiple pads. The second connection portion 66 includes multiple pads.

[0044] In some embodiments, a first voltage signal is transmitted to the control module through a first heavily doped conductive region 71, a first via structure 51, a first conductive wire 53, a first pad 54, a third via structure 61, a third conductive wire 63, and a first connection portion 64. A second voltage signal is transmitted to the control module through a second heavily doped conductive region 72, a second via structure 52, a second conductive wire 55, a second pad 56, a fourth via structure 62, a fourth conductive wire 65, and a second connection portion 66.

[0045] Through the above embodiments, the use of a two-layer wiring structure (the first conductor 53 and the second conductor 55 are the first layer of wiring, and the third conductor 63 and the fourth conductor 65 are the second layer of wiring) avoids the problem of cross-short circuit between the first voltage signal and the second voltage signal during transmission.

[0046] In some implementations, refer to Figure 10 As shown, the first connecting portion 64 and the second support column 15 are stacked along the first direction Z. The second connecting portion 66 and the second support column 15 are stacked along the first direction Z.

[0047] In some embodiments, the first connecting portion 64 has a sixth projection on the second surface 21, the sixth projection being within the range of the fifth projection; the second connecting portion 66 has a seventh projection on the second surface 21, the seventh projection being within the range of the fifth projection.

[0048] In some embodiments, see Figure 10 As shown, in the second direction Y, the first connecting portion 64 is located on one side of the second groove 13, and the second connecting portion 66 is located on the other side of the second groove 13. In other embodiments, in the third direction X, the first connecting portion 64 is located on one side of the second groove 13, and the second connecting portion 66 is located on the other side of the second groove 13.

[0049] By placing the first connecting part 64 and the second connecting part 66 on different edges of the pressure sensor through the above embodiments, the control module can more easily distinguish between the two different voltage signals from the first connecting part 64 and the second connecting part 66.

[0050] In some embodiments, see Figure 12 As shown, Figure 12 The first dielectric layer 41 is omitted, and the positions of the first pad 54 and the second pad 56 can be changed. The corners of the four first pads 54 and the first support pillar 14 are stacked along the first direction Z, and the corners of the four second pads 56 and the second support pillar 15 are stacked along the first direction Z.

[0051] In some embodiments, Figure 13 yes Figure 12 The corresponding structural diagram shows the structure after the second through hole 8 is provided on the second dielectric layer 42. The position of the second through hole 8 changes with the positions of the first pad 54 and the second pad 56.

[0052] In some embodiments, Figure 14 yes Figure 12 The corresponding structural schematic diagrams of the first connecting portion 64 and the second connecting portion 66 are shown. The third direction X is perpendicular to the first direction Z; the first connecting portion 64 includes a third pad 641, a fourth pad 642, a fifth pad 643 and a sixth pad 644; the second connecting portion 66 includes a seventh pad 661, an eighth pad 662, a ninth pad 663 and a tenth pad 664.

[0053] Reference Figure 14 In some embodiments, in the second direction Y, the third pad 641 and the fourth pad 642 are located on one side of the second groove 13, and the fifth pad 643 and the sixth pad 644 are located on the other side of the second groove 13; in the third direction X, the seventh pad 661 and the eighth pad 662 are located on one side of the second groove 13, and the ninth pad 663 and the tenth pad 664 are located on the other side of the second groove 13.

[0054] In other embodiments, in the third direction X, the third pad 641 and the fourth pad 642 are located on one side of the second groove 13, and the fifth pad 643 and the sixth pad 644 are located on the other side of the second groove 13; in the second direction Y, the seventh pad 661 and the eighth pad 662 are located on one side of the second groove 13, and the ninth pad 663 and the tenth pad 664 are located on the other side of the second groove 13.

[0055] By setting the first pad 54 and the second pad 56 at the corners of the support column in the above manner, references that require four-corner wiring can be taken into account. Furthermore, the multiple pads in the first connection part 64 and the multiple pads in the second connection part 66 are symmetrically arranged on the surface of the pressure sensor. The wiring area is small, and the symmetrical arrangement can also reduce the signal transmission hysteresis to a certain extent.

[0056] This application also provides a method for forming a pressure sensor as described in any of the above embodiments, see below. Figure 15 As shown, the method includes: S101: A first substrate 1 is provided, the first substrate 1 having a first surface 11; S102: The first substrate 1 is patterned to form a first groove 12 recessed relative to the first surface 11, a second groove 13 recessed relative to the first surface 11, and an integrated first support post 14. The first support post 14 is located between the first groove 12 and the second groove 13, and the first groove 12 and the second groove 13 are not connected. S103: Provide a second substrate 2, the second substrate 2 having a second surface 21 and a third surface 22 opposite to each other, the second substrate 2 including a first region 23 and a second region 24, the first region 23 having a first projection on the second surface 21, and the second region 24 having a third projection on the second surface 21. S104: The second surface 21 of the second substrate 2 is bonded and fixed to the first surface 11 of the first substrate 1. The first groove 12 has a second projection on the second surface 21. The first projection is within the range of the second projection. The second groove 13 has a fourth projection on the second surface 21. The third projection is within the range of the fourth projection. S105: A first varistor 31 is formed on the third surface 22 of the first region 23. The first varistor 31 is used to output a first voltage signal. S106: A second varistor 32 is formed on the third surface 22 of the second region 24. The second varistor 32 is used to output a second voltage signal.

[0057] In some embodiments, a specific method for patterning the first substrate 1 includes: covering the first surface 11 of the first substrate 1 with a first mask and a second mask, wherein the projection of the first mask on the first surface 11 and the projection of the first support post 14 on the first surface 11 coincide, and the projection of the second mask on the first surface 11 and the projection of the second support post 15 on the first surface 11 coincide, and then performing an etching process to remove the first surface 11 that is not covered by the first mask and the second mask, so that the first groove 12 and the second groove 13 can be formed simultaneously with only one etching.

[0058] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0059] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0060] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0061] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A pressure sensor, characterized in that, include: The first substrate (1) has a first surface (11), a first groove (12) recessed relative to the first surface (11), a second groove (13) recessed relative to the first surface (11), and an integrated first support post (14), the first support post (14) being located between the first groove (12) and the second groove (13), and the first groove (12) and the second groove (13) not communicating with each other; A second substrate (2) is stacked with the first substrate (1) along a first direction (Z), the second substrate (2) having a second surface (21) and a third surface (22) opposite to each other, the second surface (21) being bonded and fixed to the first surface (11); The second substrate (2) includes a first region (23) and a second region (24). The first region (23) has a first projection on the second surface (21), and the first groove (12) has a second projection on the second surface (21). The first projection is within the range of the second projection. The second region (24) has a third projection on the second surface (21), and the second groove (13) has a fourth projection on the second surface (21). The third projection is within the range of the fourth projection. A first varistor (31) is located on the third surface (22) of the first region (23), and the first varistor (31) is used to output a first voltage signal; The second varistor (32) is located on the third surface (22) of the second region (24) and is used to output a second voltage signal.

2. The pressure sensor according to claim 1, characterized in that, The second groove (13) surrounds the first support column (14), and the first support column (14) surrounds the first groove (12); The shape of the second projection includes a rectangle, and the shape of the fourth projection includes a square.

3. The pressure sensor according to claim 1, characterized in that, Also includes: The first dielectric layer (41) is located on the third surface (22); The first conductive structure includes a first via structure (51) penetrating the first dielectric layer (41), and the first via structure (51) is coupled to the first varistor (31). The second conductive structure includes a second via structure (52) penetrating the first dielectric layer (41), and the second via structure (52) is coupled to the second varistor (32).

4. The pressure sensor according to claim 3, characterized in that, The first conductive structure further includes: a first conductor (53) and a first pad (54) located on the surface of the first dielectric layer (41) and coupled to each other, wherein the first conductor (53) is coupled to the first via structure (51); The second conductive structure further includes a second conductor (55) and a second pad (56) located on the surface of the first dielectric layer (41) and coupled to each other, wherein the second conductor (55) is coupled to the second via structure (52).

5. The pressure sensor according to claim 4, characterized in that, Also includes: A second dielectric layer (42) located on the surface of the first dielectric layer (41); The third conductive structure includes a third via structure (61) penetrating the second dielectric layer (42), the third via structure (61) being coupled to the first pad (54); The fourth conductive structure includes a fourth via structure (62) penetrating the second dielectric layer (42) and coupled to the second pad (56).

6. The pressure sensor according to claim 5, characterized in that, The third conductive structure further includes a third conductor (63) and a first connection portion (64) located on the surface of the second dielectric layer (42) and coupled to each other, wherein the third conductor (63) is coupled to the third via structure (61); The fourth conductive structure further includes a fourth conductor (65) and a second connection portion (66) located on the surface of the second dielectric layer (42) and coupled to each other, wherein the fourth conductor (65) is coupled to the fourth via structure (62).

7. The pressure sensor according to claim 6, characterized in that, In the second direction, the first connecting part (64) is located on one side of the second groove (13), and the second connecting part (66) is located on the other side of the second groove; or, in the third direction, the first connecting part (64) is located on one side of the second groove (13), and the second connecting part (66) is located on the other side of the second groove (13); wherein the second direction and the third direction intersect each other and are both perpendicular to the first direction.

8. The pressure sensor according to claim 6, characterized in that, The first connection portion (64) includes a third pad (641), a fourth pad (642), a fifth pad (643), and a sixth pad (644); the second connection portion (66) includes a seventh pad (661), an eighth pad (662), a ninth pad (663), and a tenth pad (664); In either the second or third direction, the third pad (641) and the fourth pad (642) are located on one side of the second groove (13), and the fifth pad (643) and the sixth pad (644) are located on the other side of the second groove (13). In the second direction or the third direction, the seventh pad (661) and the eighth pad (662) are located on one side of the second groove (13), and the ninth pad (663) and the tenth pad (664) are located on the other side of the second groove (13); wherein the second direction and the third direction intersect each other and are both perpendicular to the first direction.

9. The pressure sensor according to claim 1, characterized in that, The first substrate (1) also has an integrated second support post (15) surrounding the second groove (13); The first support column (14) is bonded to the second surface (21) on the side surface away from the bottom of the second groove (13), and the second support column (15) is bonded to the second surface (21) on the side surface away from the bottom of the second groove (13).

10. A method for forming a pressure sensor as described in any one of claims 1 to 9, characterized in that, include: A first substrate (1) is provided, the first substrate (1) having a first surface (11); The first substrate (1) is patterned to form a first groove (12) recessed relative to the first surface (11), a second groove (13) recessed relative to the first surface (11), and an integrated first support post (14). The first support post (14) is located between the first groove (12) and the second groove (13), and the first groove (12) and the second groove (13) are not connected. A second substrate (2) is provided, the second substrate (2) having opposing second surfaces (21) and third surfaces (22), the second substrate (2) including a first region (23) and a second region (24), the first region (23) having a first projection on the second surface (21), and the second region (24) having a third projection on the second surface (21); The second surface (21) of the second substrate (2) is bonded and fixed to the first surface (11) of the first substrate (1). The first groove (12) has a second projection on the second surface (21), and the first projection is within the range of the second projection. The second groove (13) has a fourth projection on the second surface (21), and the third projection is within the range of the fourth projection. A first varistor (31) is formed on the third surface (22) of the first region (23), and the first varistor (31) is used to output a first voltage signal; A second varistor (32) is formed on the third surface (22) of the second region (24), and the second varistor (32) is used to output a second voltage signal.

Images