Crystal orientation-dependent etching interface defect analysis method

Abstract

The application belongs to the field of semiconductor simulation, and discloses a crystal direction-dependent etching interface defect analysis method. The method accurately extracts the density, energy level, type and time constant of etching interface defects of different crystal directions by comprehensively combining various electrical tests such as variable-temperature I-V, variable-frequency C-V, pulse C-V and ultraviolet light-assisted C-V, and cross-verification of TEM characterization and defect library information; and then the defect parameters are substituted into the thermoelectric coupling model and experimental data fitting to clarify the physical mechanism of its influence on the I-V and C-V characteristics of the device from the perspective of multi-physical field. The application realizes advanced characterization of interface defects of complex crystal structures, and provides accurate theoretical guidance and technical solutions for optimizing etching crystal direction, formulating defect passivation strategies and improving the thermoelectric performance and reliability of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor modeling technology, specifically relating to a method for analyzing crystal orientation-dependent etching interface defects. Background Technology

[0002] For (ultra)wide bandgap semiconductor power devices, the use of MOS-TYPE trench structures can introduce the peak electric field of the device into three-dimensional space, which can alleviate the leakage current management problem caused by the one-dimensional distribution of the surface electric field (Esurf) of planar devices. This enables (ultra)wide bandgap semiconductor power devices to achieve the superior electrical performance recommended by Baliga's Figure of Merit (BFOM).

[0003] However, the interface quality between the trench structure oxide layer and the semiconductor (i.e., interface etching defects) directly affects the forward conduction and reverse breakdown characteristics of the device, and is a key factor restricting the application and reliability improvement of (ultra)wide bandgap semiconductor power devices in high-power scenarios. The complex crystal structure of (ultra)wide bandgap semiconductors (such as β-Ga2O3) results in significant anisotropy. The atomic arrangement, dangling bond type, and defect formation energy of surfaces with different crystal orientations are fundamentally different, leading to significantly different trench interfaces formed by etching along different crystal orientations, and their etching defect characteristics and formation mechanisms are also fundamentally different. Therefore, in order to accurately control the trench etching interface quality and improve the performance and reliability of trench power devices, an advanced characterization and analysis method for etching interface defects that are crystal orientation dependent on such complex crystal structures is urgently needed. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a crystal orientation-dependent etching interface defect analysis method.

[0005] The technical problem to be solved by this invention is achieved through the following technical solution: A crystal orientation-dependent method for analyzing etching interface defects includes: Step 1: Evaluate the types of defects that may exist at the etching interface of devices with different crystal orientations using material characterization techniques; Step 2: By performing variable-temperature IV electrical characteristic tests on devices with different crystal orientations, obtain the forward and reverse IV characteristic curves of devices with different crystal orientations at different temperatures; Step 3: By conducting bidirectional CV electrical characteristic tests on devices with different crystal orientations at room temperature and frequency dependence, a group of CV characteristic curves of devices with different crystal orientations at different frequencies is obtained. By processing and analyzing the group of CV characteristic curves at different frequencies, the magnitude of the comprehensive influence of the etching interface defect characteristics of devices with different crystal orientations on the carrier behavior of the devices is initially obtained. Step 4: By conducting pulsed CV electrical characteristic tests on devices with different crystal orientations at room temperature, obtain pulsed CV characteristic curves of devices with different crystal orientations under gradually extended trapping time and fixed de-trapping time. By processing and analyzing the pulsed CV characteristic curves, obtain the judgment result that the devices with different crystal orientations contain one type of etching interface defect or multiple types of etching interface defects. Step 5: By performing CV electrical characteristic tests on devices with different crystal orientations at room temperature using the UV-assisted method or the Terman method, and processing and analyzing the corresponding test data, obtain the curves showing the relationship between defect density and defect energy level for devices with different crystal orientations, which decouple the influence of the time constant of the etching interface defects. Step 6: For devices with different crystal orientations, if the judgment result indicates that it contains one type of defect, then by performing single-peak Gaussian fitting on the corresponding relationship curve described in Step 5, one type of defect energy level and corresponding defect density corresponding to the peak value in the fitted curve are extracted. If the judgment result indicates that it contains multiple types of defects, then by performing multi-peak Gaussian fitting on the corresponding relationship curve described in Step 5, multiple defect energy levels and corresponding defect densities corresponding to multiple peak values ​​in the fitted curve are extracted. Step 7: Combining the possible defect types assessed in Step 1, the defect energy levels extracted in Step 6, and the interface defect characteristic information in the published defect library, the defect types and defect time constants of the etching interfaces of devices with different crystal orientations are finally determined. Step 8: Introduce the defect energy level and defect density obtained in Step 6, and the defect time constant obtained in Step 7 into the thermoelectric coupling model of the forward device, and fit it with the forward and reverse IV characteristic curves obtained in Step 2 and the CV characteristic curves obtained in Step 3, so as to provide a multi-physics field perspective on the influence of crystal orientation-dependent etching interface defect characteristics on the thermoelectric characteristics of the device, and clarify the physical mechanism of its influence on the IV characteristics and CV characteristics of the device at different temperatures and different frequencies.

[0006] This invention provides a method for analyzing crystal orientation-dependent etching interface defects. It comprehensively utilizes multiple electrical characterization techniques, including variable-temperature IV, variable-frequency CV, pulsed CV, and UV-assisted CV, to acquire data from multiple dimensions. Pulsed CV curves are used to determine single / multiple defect types, and Gaussian fitting is used to extract the defect energy level distribution. This distribution is then cross-validated with material characterization results and defect library information to accurately and quantitatively extract the density, energy level, type, and time constant of etching interface defects in different crystal orientations. Furthermore, the extracted defect parameters are substituted into a forward device thermoelectric coupling model and fitted with experimentally measured IV and CV curves at different temperatures and frequencies. This reveals the physical mechanism by which defects affect the thermoelectric properties of the device from a multiphysics coupling perspective. This method enables the observation of the multiphysics process by which crystal orientation-dependent etching interface defects affect the thermoelectric properties of devices with different crystal orientations, thereby deeply elucidating the physical mechanism by which crystal orientation-dependent etching interface defects cause changes in the thermoelectric properties of devices. It achieves advanced characterization and analysis of crystal orientation-dependent etching interface defects in complex crystal structures.

[0007] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a schematic flowchart of a crystal orientation-dependent etching interface defect analysis method provided in an embodiment of the present invention; Figure 2 This is a technical roadmap of a crystal orientation-dependent etching interface defect analysis method provided by an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a MOS-Type trench diode and a trench MOSCAP; Figure 4 The diagram shows the relationship curves of the device with different crystal orientations as a function of trapping time, obtained by performing pulsed CV electrical characteristic tests at room temperature on devices with different crystal orientations; Figure 5 The CV characteristic curves of the trench MOSCAP device are shown, which were obtained from bidirectional CV electrical characteristic tests at frequencies 1 and 2, respectively. Detailed Implementation

[0009] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0010] Currently, there is a lack of systematic characterization methods for the orientation-dependent etching interface defects caused by the complex crystal structure of (ultra)wide bandgap semiconductors. This makes it difficult to accurately quantify and describe the characteristics and formation mechanisms of trench interface defects formed along different crystal orientations, and thus cannot provide accurate theoretical guidance and technical support for selecting the optimal etching direction, formulating effective interface defect optimization strategies, and thermoelectric co-design of devices. This technological gap severely restricts the application and reliability improvement of (ultra)wide bandgap semiconductor power devices in high-power scenarios.

[0011] Techniques such as TEM (Transmission Electron Microscopy) can directly observe atomic-scale defect structures, such as dislocations and stacking faults, revealing the atomic configuration and distribution characteristics of defects across different crystal orientations. However, while TEM offers high resolution, it only acquires microstructural information of localized areas, making it difficult to obtain statistical information on large-area, orientation-dependent etching interface defects. Furthermore, TEM has limitations in identifying defect types, such as its inability to characterize the specific charge state of a particular defect type. Simultaneously, TEM cannot apply the same field stress as during device operation, failing to provide qualitative or quantitative information on the impact of different defect states on the device's thermoelectric properties. TEM is an invasive and destructive characterization method, making it impossible to simultaneously combine the study of interface defect characterization with the study of defect-induced thermoelectric properties of the device.

[0012] Electrical characteristic testing involves analyzing the CV and IV characteristic curves of planar metal-oxide-semiconductor (MOSCAP) structures to extract the interface defect characteristics between the oxide layer and the semiconductor. For example, by extracting the slope and intercept of the IV characteristic curve, the conduction band energy difference between the oxide layer and the semiconductor is calculated to evaluate the interface quality; by measuring the CV characteristic curve, conductivity calculations are performed to extract the interface defect density and interface defect energy levels. By applying periodically varying gate voltages to the MOS-TYPE structure device, the interface states are induced to continuously trap and release charge carriers, thereby generating a net substrate current (i.e., charge pump current), the magnitude of which is directly proportional to the interface state density. The interface defect density is extracted by performing 1 / f noise testing on the MOS-TYPE structure device. However, the result of charge trapping by defects varies depending on the type of defect density. and defect time constant This is a joint decision. Current tests for interface defects (such as room temperature CV testing, charge pumping, 1 / f noise, etc.) cannot accurately measure the density of interface defects. and interface defect time constant Decoupling is performed, and when different types of defects exist at the interface, the interface defect density is measured based on this. 1) It cannot decouple and provide information on the characteristics of different types of defects; 2) The existing deep level transient spectroscopy (DLTS) technology based on variable-temperature CV testing has limited testing accuracy: DLTS obtains defect characteristics by monitoring the capacitance transients (i.e., DLTS signals) caused by the emission of charge carriers from defects in the depletion region at different temperatures. Although this technology is widely used in defect analysis, in (ultra)wide bandgap semiconductors such as β-Ga2O3, due to the complexity of the types of defects (bulk defects, interface defects, etc.) and their similar energy levels, and the combined influence of mobile charges in the oxide layer, oxide-semiconductor interface defects, and point defects in the semiconductor material itself, the DLTS signals overlap significantly, making it difficult to effectively separate and distinguish interface defects from other types of defects. As a result, this technology often cannot accurately provide the characteristic information of the aforementioned defects in (ultra)wide bandgap semiconductor materials. Furthermore, the variable-temperature process it relies on may cause the evolution of interface characteristics, affecting the testing accuracy and making it impossible to accurately distinguish defects with energy levels greater than 0.5 eV. The above-mentioned shortcomings mean that current characterization and testing techniques cannot provide a reference for selecting the optimal etching direction, formulating effective interface defect optimization strategies, and improving device performance, reliability, and temperature stability design for (ultra)wide bandgap semiconductor power devices.

[0013] Therefore, this invention provides a crystal orientation-dependent etching interface defect analysis method, which aims to achieve advanced characterization and analysis of crystal orientation-dependent etching interface defects in complex crystal structures. It provides a new technical solution for quantitatively elucidating the defect characteristics, formation mechanism and other key information of etching interface defects in devices with different crystal orientations, and lays a precise theoretical foundation and technical support for selecting the optimal etching direction, formulating effective interface defect optimization strategies, and improving device performance, reliability and temperature stability design.

[0014] See Figure 1 and combined Figure 2 As shown, the method for analyzing etching interface defects that provides crystal orientation dependence according to the present invention includes the following steps: Step 1: Evaluate the types of defects that may exist at the etching interface of devices with different crystal orientations using material characterization techniques.

[0015] Specifically, electron microscopy characterization techniques are used to observe the trench sidewalls formed by etching in devices with different crystal orientations from a microscopic perspective. The types of defects that may exist at the etching interface of devices with different crystal orientations are assessed based on the observed atomic-scale defect structures. These devices with different crystal orientations include MOS-Type trench diodes with different crystal orientations and trench MOSCAPs with different crystal orientations (such as...). Figure 3As shown in the figure, it is not limited to this. In actual analysis, device cross-sectional samples containing trench structures with specific crystal orientations can be specially prepared. Electron microscopy characterization techniques can be used to observe the trench sidewalls formed by etching in devices with different crystal orientations, that is, at the interface between the semiconductor and the oxide layer (mainly focusing on the gallium oxide side). Based on the observed atomic configuration (such as the atomic arrangement at the interface, lattice mismatch, etc.) and the atomic-scale defect structure (such as dislocations, stacking faults, etc.), the types of defects that may exist at the etching interface of devices with different crystal orientations can be evaluated, thereby providing global information on crystal orientation-dependent etching interface defects from a microscopic perspective.

[0016] For example, for gallium oxide MOS-Type trench diodes or gallium oxide trench MOSCAPs, by manually analyzing the atomic arrangement of their etched interfaces, if a missing atom is observed at a certain lattice site, it can be determined that a vacancy defect of that element exists at that location. If gallium atoms are missing in a certain crystal orientation of gallium oxide material observed by TEM, it is inferred that a gallium vacancy interface defect has occurred in that crystal orientation. By directly observing the atomic-scale defect structure, such as dislocations and stacking faults, using techniques such as TEM, the atomic configuration of the defects and their distribution characteristics in different crystal orientations can be revealed.

[0017] Step 2: By performing variable-temperature IV electrical characteristic tests on devices with different crystal orientations, the forward and reverse IV characteristic curves of devices with different crystal orientations at different temperatures are obtained.

[0018] Here, variable-temperature IV electrical characteristic testing includes IV electrical characteristic testing at low temperature, room temperature, and high temperature. For example, forward and reverse IV measurements can be performed on devices with different crystal orientations within a temperature range of 25°C to 300°C (in 25°C increments).

[0019] In forward IV measurements, a forward bias voltage is applied to the anode region of the device, and the anode current is measured from 0V until the device is normally turned on. Taking a gallium oxide MOS-Type trench device as an example, the forward voltage can be applied from 0V to 8V. In reverse IV measurements, a reverse bias voltage is applied to the anode region of the device, and the anode current is measured. A reverse voltage is applied starting from 0V, and the change in the reverse voltage can be observed. Furthermore, a maximum safe current limit is set during testing to prevent premature device failure. Taking a gallium oxide MOS-Type trench device as an example, the maximum safe current limit can be set to 250nA.

[0020] Therefore, by conducting variable-temperature IV electrical characteristic tests on devices with different crystal orientations, the forward and reverse IV characteristic curves of these devices at different temperatures are obtained. For each crystal orientation device, there is one forward IV characteristic curve and one reverse IV characteristic curve at various temperatures. These IV characteristic curves can reveal the comprehensive influence of all interface defects on the forward and reverse IV characteristics of devices with different crystal orientations from a macroscopic perspective. Therefore, they can be used as the fitting basis for subsequent joint simulation of defect characteristics and forward device thermoelectric modeling techniques.

[0021] Step 3: By conducting bidirectional CV electrical characteristic tests on devices with different crystal orientations at room temperature and frequency dependence, a group of CV characteristic curves of devices with different crystal orientations at different frequencies is obtained. By processing and analyzing the group of CV characteristic curves at different frequencies, the magnitude of the comprehensive influence of the etching interface defect characteristics of devices with different crystal orientations on the carrier behavior of the devices is initially obtained.

[0022] Here, frequency-dependent bidirectional CV electrical characteristic testing refers to testing the bidirectional CV electrical characteristics at different frequencies. Specifically, at room temperature (e.g., 25°C), using a Keithley 4200 semiconductor parameter analyzer, a bias voltage is applied to the anode region of the device (voltage setting range see step 2), and the capacitance of the device as a function of voltage (forward and reverse) at different frequencies is tested. This is achieved by adjusting the test frequency. f， By altering the charge trapping and de-trapping times of interface defects, the ability of these processes to follow signal changes can be altered, allowing for a macroscopic comparison of interface defect characteristics (including defect energy levels). Defect density Defect time constant The combined effect on the CV characteristics of devices with different crystal orientations.

[0023] Taking trench MOSCAP devices with different crystal orientations as an example, the frequency scanning range can generally be selected from 1KHz to 1MHz, and the test voltage can be increased from -20V (depletion) to 10V (accumulation) to deplete the MOSCAP and bring it to the accumulation region.

[0024] After obtaining the CV characteristic curves of devices with different crystal orientations at different frequencies, the low-frequency CV curves of devices with different crystal orientations under a fixed bias voltage were used. C LF and high-frequency CV curves C HF Differences between △C (As shown in formula (1)), a preliminary judgment is made on the differences in interface defects of devices with different crystal orientations: for the same type of defects in devices with different crystal orientations, △C Manifestation The differences; for defects of different types in devices with different crystal orientations, △C Manifestation and These factors collectively influence the differences in interface defect trapping results. This is because... △C Originating from the time constant of interface defects (Determined by the de-trapping charge time, as shown in formula (2)) and frequency f The competitive relationship, when f ≤1 / At that time, the surface defects follow the small AC signal to complete the trapping and detrapping charge processes. The contribution to capacitance is shown in formula (3). And when f >1 / At that time, the interface defects cannot follow the small AC signal to complete the trapping and detrapping charge processes, resulting in Contribution to capacitance It disappears, as shown in formula (4).

[0025] Therefore, after obtaining ΔC, if it is a defect of the same type in devices with different crystal orientations (generally, devices with the same crystal orientation have the same defect type), since △C Manifestation The difference can be used to calculate the interface defect density using formulas (5) and (6) based on the obtained ΔC. If the interface defect density is calculated in this way for different types of defects in devices with different crystal orientations, then this method is used. This is inaccurate; other methods are needed to obtain the interface defect density. For details, please refer to the following steps.

[0026] (1); (2); (3); (4); (5); (6) in, q For a unit charge, s For defect capture section, N C The effective state density of conduction band electrons, v T The average thermal velocity of charge carriers, For the bottom energy level of the conduction band, For defect energy levels, K Boltzmann's constant, T For temperature; C OX For oxide layer capacitance, C D For semiconductor depletion layer capacitance, C it Capacitance related to interface defects.

[0027] It is worth noting that, under the low-frequency testing limit (typically 1 kHz) of conventional CV testing equipment, the detectable defect energy level range at room temperature only covers a region of approximately 0.47 eV from the bottom of the conduction band down, which is far smaller than the bandgap width of (ultra)wide bandgap semiconductor materials (in terms of...). β Taking Ga2O3 as an example, its bandgap is approximately 4.8 eV. Therefore, this invention employs frequency-dependent bidirectional CV electrical characteristic testing (variable frequency CV scanning) to detect defect information at different energy level positions.

[0028] Step 4: By conducting pulsed CV electrical characteristic tests on devices with different crystal orientations at room temperature, obtain a group of pulsed CV characteristic curves of devices with different crystal orientations under gradually extended trapping time and fixed de-trapping time. By processing and analyzing the group of pulsed CV characteristic curves, obtain the judgment result that the devices with different crystal orientations contain one type of etching interface defect or contain multiple types of etching interface defects.

[0029] Specifically, at room temperature, a trapezoidal voltage pulse sequence (voltage) with increasing pulse width (i.e., gradually extending the trapping time (gradually extending the forward scan time)) and constant transition time (i.e., fixing the de-trapping time (fixing the retrace time)) is generated using the arbitrary waveform generator of a Keithley 4200 semiconductor parameter analyzer. V (Refer to the size settings in step 3), such as Figure 4 As shown, the de-trapping pulse time is fixed at 50 μs, the initial width of the trapping pulse is 150 μs, and it is gradually extended thereafter, with a 30 μs interval between consecutive trapping periods. Simultaneously, the pulse edge displacement current is measured synchronously. i C (t) The measured current i C (t) The capacitance value is calculated using equation (7), and then the pulse CV characteristic curves under different trapping times are obtained.

[0030] (7) Then, the pulse CV characteristic curve group is processed and analyzed to obtain the judgment results of whether different crystal orientation devices contain one type of etching interface defect or multiple types of etching interface defects, specifically including: Step 4-1: In the group of pulse CV characteristic curves with gradually extended trapping time and fixed de-trapping time for devices with different crystal orientations, obtain the capacitance corresponding to the accumulation region for each pulse CV characteristic curve, i.e., the oxide layer capacitance. C ox1 According to the oxide layer capacitance C ox1 Calculate the flat-band capacitance corresponding to each pulse CV characteristic curve. C FB1 : (8); in, e The relative permittivity of a semiconductor is _____. A The anode area of ​​MOSCAP devices with different crystal orientations. l D The length of the Debye.

[0031] Step 4-2: Calculate the first half of the CV characteristic curve corresponding to the trapping time and the second half of the curve corresponding to the de-trapping time for each pulse. C FB1 The flat band voltage difference ΔV 1. Obtain the relationship curves of different crystal orientation devices with trapping time. ΔV 1; Figure 3 The left side shows the trapezoidal voltage pulse waveforms applied to the anode of a trench MOSCAP device with different crystal orientations, measured by current measurement. i C (t) to further convert it into Figure 3 The CV characteristic curve shown on the right can be used to calculate the same capacitance (i.e., the capacitance obtained by referring to the calculation methods given in steps 4-1 to 4-2) C FB1 Voltage difference under) ΔV 1 。 Similarly, by increasing the pulse width (the range can be selected on the order of hundreds of μs) while keeping the switching time fixed (on the order of μs), measurements are taken for each pulse width. △V， This yields the relationship curve between the pulse width and the tapering width (gradually extending the tapering). ΔV 1.

[0032] Step 4-3: For devices with different crystal orientations, if their relationship curves are traced... ΔV In 1, as the trapping time increases, ΔV 1. If the linear decrease in etching rate over a certain period of trapping time is followed by a stable trend, then the device with that crystal orientation is determined to contain only one type of interface etching defect; if the etching rate increases with the extension of the trapping time, ΔV If the crystal orientation device contains multiple types of interface etching defects simultaneously, it is determined that the device exhibits a linear decrease in temperature over a continuous trapping period before stabilizing or fails to stabilize.

[0033] Thus, the magnitude of the combined influence of the characteristics of the etching interface defects on the charge carrier behavior of devices with different crystal orientations was initially obtained.

[0034] Step 5: By performing CV electrical characteristic tests on devices with different crystal orientations at room temperature using the UV-assisted method or the Terman method, and processing and analyzing the corresponding test data, obtain the curves showing the relationship between defect density and defect energy level for devices with different crystal orientations, decoupled from the influence of the time constant of the etching interface defects.

[0035] Specifically, by conducting CV electrical characteristic tests on devices with different crystal orientations at room temperature using an ultraviolet light-assisted method and processing and analyzing the corresponding test data, the correlation curves between defect density and defect energy levels for devices with different crystal orientations, decoupled from the influence of the etching interface defect time constant, were obtained. These curves specifically include: Step 5-1: Obtain the CV characteristic curves of devices with different crystal orientations before ultraviolet irradiation by testing their CV electrical characteristics at room temperature. Step 5-2: With the device under depletion bias, irradiate the surface of devices with different crystal orientations with ultraviolet light whose photon energy is greater than or equal to the bandgap of the semiconductor material, and then perform CV electrical characteristic tests on the devices at room temperature to obtain the CV characteristic curves of devices with different crystal orientations after ultraviolet irradiation. Step 5-3: Translate the CV characteristic curve before ultraviolet irradiation so that it coincides with the CV characteristic curve after ultraviolet irradiation in the deep depletion region to obtain the ideal CV curve without interface defects for devices with different crystal orientations. Step 5-4: Calculate the voltage difference between the ideal CV curves (without interface defects) and the CV characteristic curves after UV irradiation for devices with different crystal orientations when the capacitance is the same. ΔV 2; Step 5-5: Based on the voltage difference when different crystal orientation devices correspond to different capacitances ΔV 2. Calculate the interface defect density for devices with different crystal orientations and corresponding capacitances; Here, the formula for calculating the interface defect density is shown in formula (9) below.

[0036] Steps 5-6: Calculate the surface potential for devices with different crystal orientations and corresponding capacitances. And based on the surface potential Calculate the interface defect energy levels for devices with different crystal orientations and corresponding capacitances. ; Here, the surface potential is calculated. The formula is shown in formula (10) below, which calculates the interface defect energy level. The formula is shown in formula (11) below. Formula (11) actually calculates the... - , It is the bottom of the conduction band, calculated - Then it can be calculated .

[0037] Step 5-7: Based on the interface defect density calculated in Step 5-5 and the interface defect energy level calculated in Step 5-6, obtain the curves showing the relationship between defect density and defect energy level for devices with different crystal orientations, after decoupling the influence of the etching interface defect time constant.

[0038] The principle of CV electrical characteristic testing based on the UV-assisted method is as follows: UV light with photon energy greater than or equal to the bandgap of the semiconductor material is used to irradiate the device surface, exciting the semiconductor material to generate electron-hole pairs. When devices with different crystal orientations are in depletion bias, photogenerated holes migrate to the oxide / semiconductor interface under the drive of an electric field, recombine with electrons trapped by interface defects, thus causing these interface defects to change from a charge-filled state to an empty state. Subsequently, CV characteristic curves are measured after UV irradiation. These CV characteristic curves contain response information from the interface defects. By translating the dark-state CV curve before UV irradiation (the CV characteristic curve before UV irradiation) along the voltage axis (V-axis) to make it coincide with the deep depletion region of the CV curve after UV irradiation, an ideal CV curve without interface defects is obtained. The voltage difference between the CV curve after UV irradiation and the ideal CV curve at the corresponding capacitance is then calculated. The interface defect density is calculated using formula (9). And calculate using formulas (10)-(11) corresponding Thus, the defect energy level is obtained. Thus, the interface defects under different capacitances can be obtained. With defect energy levels The correspondence.

[0039] (9) (10) (11) in, It is the bottom of the conduction band. A For devices with different crystal orientations; The surface potential is determined by different capacitance values, which correspond to different surface potentials, and these surface potentials correspond to different defect energy levels. . e The relative permittivity of a semiconductor is _____. e 0 is the vacuum permittivity. N d Doping concentration, C s This is for depletion layer capacitance; C OX For oxide layer capacitance, E g For the no-bandwidth, n i Intrinsic carrier concentration, K Boltzmann's constant, T For temperature.

[0040] It should be noted that the calculation here uses formula (8). This is achieved through the response of defects to DC voltage. Holes are generated by ultraviolet light and rapidly concentrated at the oxide / semiconductor interface under a strong electric field. These holes recombine with interface defects that have trapped electrons, selectively causing the interface defects to release electrons. The capacitance test result then reflects only the result of electron trapping by the interface defects, making trapping and release independent, rather than simultaneous. (Electrons are released from the interface defects first, then trapping occurs). Because ultraviolet light irradiation clears (releases) electrons from deep-level interface defects, the subsequent CV curve shows a voltage shift ΔV. The measured voltage at this point... Only related to defect density Related to, and related to, time constant Irrelevant. Therefore, the formula uses voltage offset. and surface potential As the primary variable, it can independently and accurately extract pure values ​​and further obtain defect energy levels. It effectively separates interface defects from bulk defects, reflecting only the characteristics of interface defects and reducing the density of interface defects. and interface defect time constant Decoupling is achieved. Conventional variable frequency CV testing extracts defects by changing the frequency (simultaneously altering the defect capture and release times) and analyzing the defect's response to the AC signal frequency. The extracted defect density The result contains and The overall result, when facing different types (different) When there is an interface defect, the change in ΔC cannot be distinguished. What caused it was This is caused by [the following], making it impossible to accurately extract the true [data / property]. The defect density extracted by the present invention based on the ultraviolet light-assisted method is superior. precise.

[0041] In step 5, by performing CV electrical characteristic tests on devices with different crystal orientations at room temperature using the Terman method and processing and analyzing the corresponding test data, the corresponding relationship curves between defect density and defect energy levels for devices with different crystal orientations, decoupled from the influence of the etching interface defect time constant, are obtained. Specifically, this includes: Step 5-a: Obtain the CV electrical characteristic curves of devices with different crystal orientations based on the Terman method by performing CV electrical characteristic tests at room temperature using the Terman method. Step 5-b: Calculate the ideal CV curves of devices with different crystal orientations without interface defects based on the Terman method; Here, the ideal CV curve is calculated using the following formula: (12) (13) in, For surface potential, different capacitance values ​​in an ideal CV curve correspond to different surface potentials. The voltage in the ideal CV curve. e S The relative permittivity of a semiconductor is _____. f m For the work function of metals, x For semiconductor affinity, N C This represents the effective state density of the semiconductor conduction band. N D This represents the semiconductor doping concentration.

[0042] Step 5-c: Calculate the ideal CV curves of devices with different crystal orientations and no interface defects. The voltage difference between the CV electrical characteristic curves based on the Terman method and the curves corresponding to the same capacitance ΔV 3; Step 5-d: Based on the voltage difference when different crystal orientation devices correspond to different capacitances ΔV 3. Calculate the interface defect density for devices with different crystal orientations and corresponding capacitances; Here, the interface defect density is calculated. The formula is referenced in formula (9). ΔV 3 Substitute into formula (9) ΔV 2.

[0043] Step 5-e: Calculate the surface potential for different capacitances corresponding to devices with different crystal orientations. And based on the surface potential Calculate the defect energy levels for devices with different crystal orientations and corresponding capacitances. ; Here, the surface potential is calculated. The formula is given in formula (10), and the energy level of the interface defect is calculated. The formula is shown in formula (11).

[0044] Step 5-f: Based on the defect density obtained in step 5-d and the defect energy level calculated in step 5-e, obtain the curves showing the relationship between defect density and defect energy level for devices with different crystal orientations, decoupled from the influence of the time constant of the etching interface defect.

[0045] In step 5, two different methods were used to obtain the curves of the relationship between defect density and defect energy level for devices with different crystal orientations, which decoupled the effect of the time constant of the etching interface defect. The ultraviolet light-assisted method can effectively detect the deepest defect energy level farthest from the bottom of the conduction band or the top of the valence band, reaching 1 eV, while the Terman method can effectively detect the deepest defect energy level farthest from the bottom of the conduction band or the top of the valence band, which can be expressed as 0.7 eV.

[0046] Step 6: For devices with different crystal orientations, if the judgment result in Step 4 indicates that it contains one type of defect, then by performing single-peak Gaussian fitting on the corresponding relationship curve obtained in Step 5, extract the defect energy level corresponding to the peak value in the fitted curve and the corresponding defect density. If the judgment result in Step 4 indicates that it contains multiple types of defects, then by performing multi-peak Gaussian fitting on the corresponding relationship curve obtained in Step 5, extract the multiple defect energy levels corresponding to the multiple peak values ​​in the fitted curve and the corresponding defect density.

[0047] Specifically, if a certain crystal orientation device has only one type of defect, and its and If the relationship curve exhibits a single narrow peak, then a single-peak fitting is performed on the curve, and the peak value corresponding to the peak value is extracted. Value, thereby obtaining and the corresponding If a certain crystal orientation device has multiple defects simultaneously, and its and If the relationship curve exhibits broad peaks, multi-peak fitting is employed to extract the corresponding peak values. Value, thereby obtaining and the corresponding .

[0048] In step 6, the judgment results from step 4 and the corresponding relationship curves obtained in step 5 are combined for further fitting analysis, which effectively improves the accuracy of the final determined defect type.

[0049] Step 7: Combining the possible defect types assessed in Step 1, the defect energy levels extracted in Step 6, and the interface defect characteristic information in the published defect library, the defect types and defect time constants of the etching interfaces of devices with different crystal orientations are finally determined.

[0050] Specifically, step 1 has already assessed the possible defect types, and step 6 has obtained the specific defect energy levels. Based on this, and combined with the interface defect characteristic information in existing published defect libraries, the defect types of etching interfaces for devices with different crystal orientations can be finally determined. For example, if the energy level position of a defect at a certain crystal orientation interface... Located at the bottom of the conductor belt At approximately 0.7 eV below the conduction band, and given that TEM analysis in step 1 confirmed the presence of gallium atom lattice site deficiencies in this crystal orientation, coupled with the gallium vacancy defect energy levels reported in published defect libraries also located around 0.7 eV below the conduction band, these three factors corroborate each other, confirming that the defect type generated in this crystal orientation under etching conditions is a gallium vacancy. Then, based on the finally determined defect type, relevant literature is consulted to obtain the corresponding trapping cross-section. s Then, the defect time constant is calculated using formula (2) above. .

[0051] Step 8: Introduce the defect energy level and defect density obtained in Step 6, and the defect time constant obtained in Step 7 into the thermoelectric coupling model of the forward device, and fit it with the forward and reverse IV characteristic curves obtained in Step 2 and the CV characteristic curves obtained in Step 3, so as to provide a multi-physics field perspective on the influence of crystal orientation-dependent etching interface defect characteristics on the thermoelectric characteristics of the device, and clarify the physical mechanism of its influence on the IV characteristics and CV characteristics of the device at different temperatures and different frequencies.

[0052] Specifically, firstly, a basic thermoelectric coupling model of the device was established in TCAD software, and key parameters of crystal orientation-dependent etching interface defects extracted from experiments—including defect energy levels—were then incorporated. Defect density Defect time constant —Introduced as the core input to the physical model. Subsequently, to accurately characterize the carrier transport and recombination processes near the defects, local mesh refinement and overall optimization of the simulation mesh are required for the interface region where the defects are introduced. Finally, by running the parameterized and mesh-optimized model, the electrical characteristics of the device under different ambient temperatures are simulated and calculated. The goal is to achieve an accurate fit with the experimentally measured forward and reverse IV characteristic curves, verifying the effectiveness and accuracy of the model and the extracted defect parameters. This allows for the observation of the multiphysics process by which orientation-dependent etching interface defects affect the characteristics of devices with different crystal orientations, thereby deeply elucidating the physical mechanism by which orientation-dependent etching interface defects cause changes in the thermoelectric properties of devices. This provides an important mechanistic basis for etching process optimization, interface quality optimization, and thermoelectric co-design of devices.

[0053] Optionally, in one implementation, the crystal orientation-dependent etching interface defect analysis method provided by the present invention may further include the following steps: Step i: By performing frequency-dependent bidirectional CV electrical characteristic tests on devices with different crystal orientations, obtain the oxide layer capacitance corresponding to the CV characteristic curves at different frequencies in the accumulation region. C ox2 .

[0054] For details, see Figure 5 , Figure 5 The CV characteristic curves of the trench MOSCAP device at frequencies 1 and 2 are shown, illustrating the location of the accumulation region. The capacitance value extracted from this location represents the oxide layer capacitance corresponding to the accumulation region. C ox2 .

[0055] Step ii, based on C ox2 The flat-band capacitance corresponding to the CV curve at different frequencies is calculated using the following formulas (14) and (15). C FB2 Calculate the forward scan curve and the retrace curve corresponding to the CV characteristic curves at different frequencies. C FB2 The flat band voltage difference V FB2 And the oxide layer defect density of the defect is calculated using formula (16). N bt ; (14); (15); (16); in, eThe relative permittivity of a semiconductor is _____. A The anode area of ​​MOSCAP devices with different crystal orientations. l D For Debye length, K Boltzmann's constant, T For temperature, q For a unit charge, N D This represents the doping concentration.

[0056] It should be noted that the crystal orientation-dependent etching defect analysis method proposed in this invention is not limited to... β -Ga2O3 devices are also applicable to devices made of other semiconductor materials, such as silicon carbide (SiC) devices. Furthermore, the crystal orientation-dependent etching defect analysis technique proposed in this invention is not limited to the

[010] and

[100] crystal orientations, but is also applicable to other crystal orientations such as

[001] and

[110] .

[0057] Furthermore, the test equipment and test conditions described above are not limited to the equipment and values ​​mentioned in the text. For example, the variable-temperature IV electrical characteristic test temperature can be adjusted according to the device structure and test equipment limitations; the test equipment is not limited to the Keithley 4200 semiconductor parameter analyzer, but can also be a Keysight 1500 semiconductor parameter analyzer; the variable-frequency CV test frequency is not limited to 1kHz to 1MHz; and the wavelength of the light used in the UV-assisted CV test is not limited to the 254nm mentioned in the text, as long as the photon energy of the UV light source is greater than or equal to the bandgap of the semiconductor material. All parameters mentioned in the text, such as test frequency, accumulation region bias time, depletion region bias time, and settling time, are not limited to the values ​​mentioned above, and the specific values ​​need to be adjusted according to the actual device conditions.

[0058] In summary, this invention addresses the inability of existing technologies to decouple [the components / properties]. and To address the limitations of testing accuracy and the influence of different crystal orientations on the thermoelectric properties of devices, which hinders the accurate provision of defect characteristic information for (ultra)wide bandgap semiconductor materials, this paper presents a crystal orientation-dependent etching interface defect analysis technique. This technique quantitatively extracts the density of crystal orientation-dependent interface defects using electrical property testing techniques. ,energy level Distribution, Defect Type, Time Constant Cross-validation with defect types determined by TEM material characterization and published defect database information ensured the accuracy of interface defect type analysis. Through room-temperature variable-frequency CV, room-temperature pulsed CV, and room-temperature UV-assisted CV electrical property testing techniques, the characteristic parameters of interface defects (including...) were determined. , Type The precise acquisition and quantitative analysis of interface defect characteristics were achieved. By combining the acquired interface defect characteristics with forward device thermoelectric modeling techniques, the multiphysics process of observing the influence of crystal orientation-dependent etching interface defect characteristics on the thermoelectric properties of devices with different crystal orientations was realized, and the physical mechanism of changes in device thermoelectric properties caused by crystal orientation-dependent etching interface defects was elucidated. By conducting frequency-dependent bidirectional CV electrical characteristic tests on devices with different crystal orientations, the oxide layer capacitance corresponding to the CV characteristic curves at different frequencies in the accumulation region was obtained, thereby obtaining the oxide layer defect density of the defects. N bt Therefore, this invention provides a novel technical solution for quantitatively elucidating key information such as the defect characteristics and formation mechanism of etching interface defects in devices with different crystal orientations. Combined with forward device thermoelectric modeling technology, it can realize the observation of the multi-physics field process by which the characteristics of crystal orientation-dependent etching interface defects affect the thermoelectric properties of devices with different crystal orientations. This allows for a deeper understanding of the physical mechanism by which crystal orientation-dependent etching interface defects cause changes in the thermoelectric properties of devices, thus providing an important mechanistic basis for etching process optimization, interface quality optimization, and thermoelectric co-design of devices.

[0059] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0060] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0061] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0062] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0063] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0064] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0065] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A crystal orientation-dependent method for analyzing etching interface defects, characterized in that, include: Step 1: Evaluate the types of defects that may exist at the etching interface of devices with different crystal orientations using material characterization techniques; Step 2: By performing variable-temperature IV electrical characteristic tests on devices with different crystal orientations, obtain the forward and reverse IV characteristic curves of devices with different crystal orientations at different temperatures; Step 3: By conducting bidirectional CV electrical characteristic tests on devices with different crystal orientations at room temperature and frequency dependence, a group of CV characteristic curves of devices with different crystal orientations at different frequencies is obtained. By processing and analyzing the group of CV characteristic curves at different frequencies, the magnitude of the comprehensive influence of the etching interface defect characteristics of devices with different crystal orientations on the carrier behavior of the devices is initially obtained. Step 4: By conducting pulsed CV electrical characteristic tests on devices with different crystal orientations at room temperature, obtain pulsed CV characteristic curves of devices with different crystal orientations under gradually extended trapping time and fixed de-trapping time. By processing and analyzing the pulsed CV characteristic curves, obtain the judgment result that the devices with different crystal orientations contain one type of etching interface defect or multiple types of etching interface defects. Step 5: By performing CV electrical characteristic tests on devices with different crystal orientations at room temperature using the UV-assisted method or the Terman method, and processing and analyzing the corresponding test data, obtain the curves showing the relationship between defect density and defect energy level for devices with different crystal orientations, which decouple the influence of the time constant of the etching interface defects. Step 6: For devices with different crystal orientations, if the judgment result indicates that it contains one type of defect, then by performing single-peak Gaussian fitting on the corresponding relationship curve described in Step 5, one type of defect energy level and corresponding defect density corresponding to the peak value in the fitted curve are extracted. If the judgment result indicates that it contains multiple types of defects, then by performing multi-peak Gaussian fitting on the corresponding relationship curve described in Step 5, multiple defect energy levels and corresponding defect densities corresponding to multiple peak values ​​in the fitted curve are extracted. Step 7: Combining the possible defect types assessed in Step 1, the defect energy levels extracted in Step 6, and the interface defect characteristic information in the published defect library, the defect types and defect time constants of the etching interfaces of devices with different crystal orientations are finally determined. Step 8: Introduce the defect energy level and defect density obtained in Step 6, and the defect time constant obtained in Step 7 into the thermoelectric coupling model of the forward device, and fit it with the forward and reverse IV characteristic curves obtained in Step 2 and the CV characteristic curves obtained in Step 3, so as to provide a multi-physics field perspective on the influence of crystal orientation-dependent etching interface defect characteristics on the thermoelectric characteristics of the device, and clarify the physical mechanism of its influence on the IV characteristics and CV characteristics of the device at different temperatures and different frequencies.

2. The crystal orientation-dependent etching interface defect analysis method according to claim 1, characterized in that, Step 4 involves processing and analyzing the pulse CV characteristic curves to obtain the judgment results of whether different crystal orientation devices contain one type of etching interface defect or multiple types of etching interface defects. Specifically, this includes: Step 4-1: In the group of pulse CV characteristic curves with gradually extended trapping time and fixed de-trapping time for devices with different crystal orientations, obtain the capacitance corresponding to the accumulation region for each pulse CV characteristic curve, i.e., the oxide layer capacitance. C ox1 According to the oxide layer capacitance C ox1 Calculate the flat-band capacitance corresponding to each pulse CV characteristic curve. C FB1 ; Step 4-2: Calculate the first half of the CV characteristic curve corresponding to the trapping time and the second half of the curve corresponding to the de-trapping time for each pulse. C FB1 The flat band voltage difference ΔV 1. Obtain the relationship curves of different crystal orientation devices with trapping time. ΔV 1; Step 4-3: For devices with different crystal orientations, if their relationship curves are traced... ΔV In 1, as the trapping time increases, ΔV 1. If the linear decrease in etching rate over a certain period of trapping time is followed by a stable trend, then the device with that crystal orientation is determined to contain only one type of interface etching defect; if the etching rate increases with the extension of the trapping time, ΔV If the crystal orientation device contains multiple types of interface etching defects simultaneously, it is determined that the device exhibits a linear decrease in temperature over a continuous trapping period before stabilizing or fails to stabilize.

3. The method for analyzing crystal orientation-dependent etching interface defects according to claim 1, characterized in that, Step 5 specifically includes: Step 5-1: Obtain the CV characteristic curves of devices with different crystal orientations before ultraviolet irradiation by testing their CV electrical characteristics at room temperature. Step 5-2: With the device under depletion bias, irradiate the surface of devices with different crystal orientations with ultraviolet light whose photon energy is greater than or equal to the bandgap of the semiconductor material, and then perform CV electrical characteristic tests on the devices at room temperature to obtain the CV characteristic curves of devices with different crystal orientations after ultraviolet irradiation. Step 5-3: Translate the CV characteristic curve before ultraviolet irradiation so that it coincides with the CV characteristic curve after ultraviolet irradiation in the deep depletion region to obtain the ideal CV curve without interface defects for devices with different crystal orientations. Step 5-4: Calculate the voltage difference between the ideal CV curves (without interface defects) and the CV characteristic curves after UV irradiation for devices with different crystal orientations when the capacitance is the same. ΔV 2; Step 5-5: Based on the voltage difference when different crystal orientation devices correspond to different capacitances ΔV 2. Calculate the interface defect density for devices with different crystal orientations and corresponding capacitances; Steps 5-6: Calculate the surface potential for devices with different crystal orientations and corresponding capacitances, and calculate the interface defect energy levels for devices with different crystal orientations and corresponding capacitances based on the surface potential. Step 5-7: Based on the interface defect density calculated in Step 5-5 and the interface defect energy level calculated in Step 5-6, obtain the curves showing the relationship between defect density and defect energy level for devices with different crystal orientations, after decoupling the influence of the etching interface defect time constant.

4. The method for analyzing crystal orientation-dependent etching interface defects according to claim 1, characterized in that, Step 5 specifically includes: Step 5-a: Obtain the CV electrical characteristic curves of devices with different crystal orientations based on the Terman method by performing CV electrical characteristic tests at room temperature using the Terman method. Step 5-b: Calculate the ideal CV curves of devices with different crystal orientations without interface defects based on the Terman method; Step 5-c: Calculate the voltage difference between the ideal CV curves (without interface defects) and the CV electrical characteristic curves (based on the Terman method) of devices with different crystal orientations when they correspond to the same capacitance. ΔV 3; Step 5-d: Based on the voltage difference when different crystal orientation devices correspond to different capacitances ΔV 3. Calculate the interface defect density for devices with different crystal orientations and corresponding capacitances; Step 5-e: Calculate the surface potential for devices with different crystal orientations and corresponding capacitances, and calculate the defect energy level for devices with different crystal orientations and corresponding capacitances based on the surface potential. Step 5-f: Based on the defect density obtained in step 5-d and the defect energy level calculated in step 5-e, obtain the curves showing the relationship between defect density and defect energy level for devices with different crystal orientations, decoupled from the influence of the time constant of the etching interface defect.

5. The method for analyzing crystal orientation-dependent etching interface defects according to claim 1, characterized in that, Step 1 specifically includes: using electron microscopy to observe the trench sidewalls formed by etching in devices with different crystal orientations, and evaluating the possible defect types at the etching interface of devices with different crystal orientations based on the observed atomic-scale defect structures.

6. The method for analyzing crystal orientation-dependent etching interface defects according to claim 1, characterized in that, The temperature range for the variable-temperature IV electrical characteristic test in step 2 is 25°C-300°C.

7. The method for analyzing crystal orientation-dependent etching interface defects according to claim 1, characterized in that, In step 3, the frequency scan range for the frequency-dependent bidirectional CV electrical characteristic test at room temperature is 1kHz-1MHz.

8. The method for analyzing crystal orientation-dependent etching interface defects according to claim 1, characterized in that, When performing pulsed CV electrical characteristic tests at room temperature in step 4: the de-trapping pulse time is fixed at 50 μs, the initial width of the trapping pulse time is 150 μs, and the interval between consecutive trapping time periods is 30 μs.

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