A control method of a static memory, a system on chip, and an electronic device

Abstract

The application discloses a control method of a static memory, a system on chip and electronic equipment. The method comprises the following steps: in response to detecting an additional margin adjustment configuration trigger condition, reducing the clock frequency of the static memory from a first frequency to a second frequency, wherein the second frequency is greater than zero; at the second frequency, distributing an additional margin adjustment signal to be configured to the static memory; in response to completing the distribution of the additional margin adjustment signal, restoring the clock frequency of the static memory from the second frequency to the first frequency.

Description

Technical Field

[0001] This application relates to the field of chip technology, and more specifically to a method for controlling static memory, a system-on-a-chip, and an electronic device. Background Technology

[0002] In System-on-Chip (SoC) chip design, the Extra Margin Adjustment (EMA) function of SRAM (Static Random Access Memory) is used to adjust the access speed of SRAM, such as adjusting the clock-to-output time Tcq and clock-to-clock time Tcc. When the chip is in high-performance mode, EMA can speed up the SRAM; in low-power mode, EMA can slow down the speed to save power.

[0003] The EMA signal is provided asynchronously by the system control register and needs to be synchronized to the clock domain of the target subsystem (such as the CPU). However, at high frequencies, the timing path for synchronizing and distributing the EMA signal is very long, making it difficult to meet strict timing requirements, resulting in complex designs and difficult implementation. Summary of the Invention

[0004] In view of the above, this application provides the following technical solution:

[0005] The first aspect of this application provides a method for controlling a static memory, including:

[0006] In response to the detection of an additional margin adjustment configuration trigger condition, the clock frequency of the static memory is reduced from a first frequency to a second frequency, wherein the second frequency is greater than zero;

[0007] At the second frequency, the additional margin adjustment signal to be configured is distributed to the static memory;

[0008] In response to the completion of the additional margin adjustment signal distribution, the clock frequency of the static memory is restored from the second frequency to the first frequency.

[0009] A second aspect of this application provides a system-on-a-chip, comprising:

[0010] The target subsystem includes a static memory;

[0011] Trigger detection circuit, used to detect the trigger conditions for additional margin adjustment configuration;

[0012] A clock control circuit, connected to the trigger detection circuit and the static memory, is used to reduce the clock frequency of the static memory from a first frequency to a second frequency in response to detecting the trigger condition, wherein the second frequency is greater than zero;

[0013] A signal distribution circuit, connected to the clock control circuit and the static memory, is used to distribute the additional margin adjustment signal to be configured to the static memory at the second frequency.

[0014] The clock control circuit is also configured to restore the clock frequency of the static memory from the second frequency to the first frequency in response to completing the distribution of the additional margin adjustment signal.

[0015] A third aspect of this application provides an electronic device, comprising:

[0016] A memory for storing computer programs and the data generated by the execution of said computer programs;

[0017] A processor for executing the application to achieve:

[0018] In response to the detection of an additional margin adjustment configuration trigger condition, the clock frequency of the static memory is reduced from a first frequency to a second frequency, wherein the second frequency is greater than zero;

[0019] At the second frequency, the additional margin adjustment signal to be configured is distributed to the static memory;

[0020] In response to the completion of the additional margin adjustment signal distribution, the clock frequency of the static memory is restored from the second frequency to the first frequency. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0022] Figure 1 A flowchart illustrating a control method for a static memory provided in an embodiment of this application;

[0023] Figure 2 This is a schematic diagram of a static memory control architecture provided in an embodiment of this application;

[0024] Figure 3 A schematic diagram of an EMA change detection circuit provided in an embodiment of this application;

[0025] Figure 4 A schematic diagram of state transitions for a clock-controlled state machine provided in an embodiment of this application;

[0026] Figure 5 A flowchart illustrating a static memory control method in an application scenario provided by an embodiment of this application;

[0027] Figure 6 This is a schematic diagram of a system-on-a-chip provided in an embodiment of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0029] The terms "first" and "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units may include steps or units not listed, but may include steps or units not listed.

[0030] This application discloses a control method, apparatus, and on-chip system for static memory (SRAM), applied to the timing parameter configuration of SRAM in dynamic voltage and frequency adjustment scenarios. When an additional margin adjustment signal is detected, instead of stopping the clock or relying on complex software intervention, the clock frequency of the SRAM is temporarily reduced from the normal operating first frequency to a second frequency greater than zero. The additional margin adjustment signal to be configured is distributed under this relaxed clock environment after frequency reduction. After the signal distribution is complete, the clock frequency is restored to the original first frequency. Throughout the entire process, the clock of the SRAM remains running and never stops. This application extends the timing window through hardware-automatic frequency reduction, reducing the timing convergence difficulty of EMA (Extra Margin Adjustment) signal synchronization and distribution in high-frequency scenarios. It also avoids system interruptions and complex software control caused by stopping the clock, achieving low-overhead, high-reliability timing parameter configuration of the SRAM during continuous system operation.

[0031] See Figure 1 The diagram illustrates a flowchart of a static memory control method provided in an embodiment of this application. The method may include the following steps:

[0032] S101, In response to detecting an additional margin adjustment configuration trigger condition, the clock frequency of the static memory is reduced from a first frequency to a second frequency.

[0033] The additional margin adjustment configuration trigger condition characterizes the trigger signal that requires updating the EMA signal of Static Random-Access Memory (SRAM). This can be determined by comparing the current EMA value with the historical stored EMA value, or by other hardware or software flags indicating a configuration change. The difference can be a difference in monitored values, a data difference, or an indirect manifestation of other flags. For example, the difference could be a status flag signal indicating that the current EMA signal value is inconsistent with the value of the previous detection cycle. The first frequency is the initial operating frequency of the SRAM, i.e., the clock frequency at which the SRAM operates with the target subsystem before the EMA configuration trigger condition is detected. This can be divided into high-frequency (e.g., 1 GHz) and low-frequency (e.g., 500 MHz) modes, determined by the SoC's (System on Chip) DVFS (Dynamic Voltage and Frequency Scaling) strategy. The second frequency is the temporary operating frequency of the SRAM after frequency reduction. It is the clock frequency set to extend the timing window. Its value is a proportion of the first frequency target. This target proportion can be determined according to the frequency division ratio. For example, the second frequency can be 20% to 50% of the first frequency (which can adapt to a 4:1 or 2:1 frequency division ratio design). The second frequency is always greater than zero. That is, the timing window is effectively extended by reasonable frequency reduction, while ensuring the continuous operation of the SRAM and the target subsystem.

[0034] The clock control logic can receive the EMA configuration trigger condition signal in real time. When the trigger condition is detected to be valid, the finite state machine inside the clock control logic switches from the idle state to the decrement state. Based on the current initial frequency mode of the SRAM, the initial clock frequency (first frequency) of the SRAM is divided by the programmable frequency division mode, reducing the clock frequency of the SRAM (CLK_SRAM) to the preset second frequency. The second frequency is always kept greater than zero to ensure that the SRAM clock does not stop.

[0035] After detecting the additional margin adjustment configuration trigger condition, the clock frequency of the static memory is reduced from a first frequency to a second frequency greater than zero. This frequency reduction extends the timing window for EMA signal synchronization and distribution, reducing the difficulty of timing convergence. By reducing the frequency to a second frequency greater than zero, the problem of target subsystem operation interruption caused by clock stop is solved, ensuring the continuous operation of core modules such as the CPU. Furthermore, the frequency reduction operation is automatically triggered by hardware, requiring no software intervention, thus simplifying system design.

[0036] S102, at the second frequency, the additional margin adjustment signal to be configured is distributed to the static memory.

[0037] The additional margin adjustment signal to be configured is a new EMA signal (such as EMA_new [2:0]) synchronized to the target subsystem clock domain. It can be a 3-bit encoded digital signal, which can be adjusted to SRAM's Tcq (Clock to Output Time) and Tcc (Clock to Clock Time) to adapt to different DVFS requirements. Signal distribution at the second frequency refers to the transmission of the EAM signal in the clock domain after the SRAM frequency is reduced. At this time, the timing window is extended, and the synchronization and distribution of the signal can be completed stably without the risk of timing errors.

[0038] Specifically, the signal distribution step can be executed through the EMA output module. After the SRAM clock frequency is stabilized to the second frequency, the finite state machine of the clock control logic switches from the decrement (DECFREQ) state to the output (OUTPUT) state. At this time, the synchronized EMA signal to be configured is received, and the encoded signal is distributed to the EMA pins of all SRAM cells in the target subsystem through the internal buffer register and fan-out network, completing the signal configuration transmission. The encoded signal can be an N-bit encoded signal, where N is flexibly set according to the additional margin adjustment requirements of the static memory and the hardware design specifications. In this application, a 3-bit encoding is preferred. In this step, the signal distribution is completed at the second frequency after decrementing, and the extended timing window ensures the stability of the signal transmission, avoids timing errors at high frequencies, and achieves timing convergence. The signal distribution and decrementing operation are seamlessly connected without additional time delay, ensuring the high efficiency of EMA configuration.

[0039] S103. In response to completing the distribution of the additional margin adjustment signal, the clock frequency of the static memory is restored from the second frequency to the first frequency.

[0040] The completion of the additional margin adjustment signal distribution indicates that the EMA signal to be configured has been stably transmitted to all SRAM cells, and the SRAM has completed internal parameter adjustments to adapt to the new EMA configuration. The SRAM clock frequency is restored from the temporary second frequency after downsampling to the initial first frequency before the trigger condition was detected, ensuring that the SRAM recovers to its original operating performance along with the target subsystem and avoiding performance loss caused by long-term downsampling. For example, after the EMA signal "101" has been stably distributed to all 8 SRAM chips, the clock control module maintains a second frequency of 250MHz for 3 clock cycles, and then restores the SRAM clock frequency from 250MHz to the initial 1GHz (high-frequency mode) or 500MHz (low-frequency mode). After restoration, the SRAM operates at its original frequency in conjunction with the new EMA configuration.

[0041] This application provides a control method for static memory. In response to the detection of an additional margin adjustment configuration trigger condition, the clock frequency of the static memory is temporarily reduced from a first frequency operating normally to a second frequency greater than zero. Under this relaxed clock environment after frequency reduction, the additional margin adjustment signal to be configured is distributed. After the signal distribution is complete, the clock frequency is restored from the second frequency to the first frequency. This method, through automatic hardware-response frequency reduction, extends the timing window without stopping the static memory clock, thereby reducing the timing convergence difficulty of additional margin adjustment signal synchronization and distribution in high-frequency scenarios. Simultaneously, since the clock remains running throughout the process, system interruptions and complex software control overhead caused by clock interruption are avoided. This achieves low-overhead, high-reliability timing parameter configuration of the static memory under continuous system operation, effectively balancing timing stability in high-performance scenarios and energy efficiency optimization requirements in low-power scenarios.

[0042] See Figure 2 The figure illustrates a schematic diagram of a static memory control architecture provided in an embodiment of this application. Taking a mobile phone system-on-a-chip (SoC) CPU subsystem as an example, this system includes SRAM (Static Random Access Memory), which requires dynamic voltage-frequency adjustment (DVFS) according to different operating states of the mobile phone.

[0043] like Figure 2 As shown, the architecture includes a system control register 201, an EMA detection module 202, an EMA output module 203, an SRAM 204, and a clock control module 205. The system control register 201 outputs asynchronous EMA encoded signals according to the phone's operating state. The EMA detection module 202, connected to the system control register 201, receives the asynchronous EMA signal and synchronizes it to the clock domain of the CPU subsystem, while also detecting whether the EMA value has changed. The clock control module 205, connected to the EMA detection module 202 and the SRAM 204, dynamically adjusts the SRAM clock frequency (CLK_SRAM) based on the detection results. The EMA output module 203, connected to the EMA detection module 202 and all SRAMs 204, distributes the updated EMA signal to each SRAM cell.

[0044] In this embodiment, the clock control module is the main module for dynamically adjusting the SRAM clock frequency. It integrates a finite state machine, a programmable frequency divider, a timer / counter, and a logic control unit. These components work together to complete the entire process control of clock frequency reduction, frequency hold, timing wait, and frequency recovery. The finite state machine, as the core control unit, includes working states such as idle, frequency reduction, output, and recovery. It can achieve orderly state switching based on external trigger signals and internal timing results. The programmable frequency divider is used to accurately divide the initial SRAM clock frequency according to the state machine instructions to obtain a second frequency. The timer / counter is used to accurately time various preset clock cycles, ensuring the timing matching of operations at each stage.

[0045] The following example uses a mobile phone running a large game. It should be noted that the data in this scenario is for illustrative purposes only and does not represent actual data from mobile games. Specific data needs to be determined based on the device's application environment and configuration. The CPU subsystem operates at a high frequency of 1GHz and a high voltage of 1.2V. An EMA signal needs to be configured to accelerate the SRAM's Tcq (clock-to-output time) and Tcc (clock-to-clock time), thereby improving performance. At this time, the system control register issues a new EMA-encoded signal "011" (adapting to high-frequency performance requirements). The EMA detection module detects the change in the EMA value, determining that the EMA configuration trigger condition is met, and sends a change signal to the clock control module. Responding to this trigger condition, the clock control module immediately reduces the SRAM clock frequency from the first frequency of 1GHz to a second frequency of 250MHz (the second frequency is greater than zero to ensure continuous clock operation). During this process, the CPU subsystem experiences no interruption. At the second frequency of 250MHz, the EMA output module temporarily stores the EMA signal "011" to be configured in a buffer register and distributes it in parallel to the EMA pins of all 16 SRAM chips through a fan-out network. Because the timing window of the SRAM is extended from 1ns to 4ns after frequency reduction, the signal distribution process has sufficient timing margin and no timing errors. Once it is confirmed that all SRAMs have stably received the "011" signal, the clock control module restores the SRAM clock frequency from 250MHz to the first frequency of 1GHz, and the CPU subsystem resumes operation at the 1GHz high frequency combined with the new EMA configuration. The entire configuration process takes only a few clock cycles, the phone runs smoothly without lag or interruption, and is completed automatically by hardware without software intervention. Similarly, when the phone switches from game mode to social software mode, the CPU subsystem operates at a low frequency of 500MHz and a low voltage of 0.8V, requiring EMA signal configuration to slow down the SRAM's Tcq and Tcc times, thereby reducing power consumption. At this time, the system control register issues the EMA-encoded signal "001" (to adapt to low-frequency power consumption requirements), and the above process of frequency reduction, signal distribution, and frequency restoration is repeated. The clock control module reduces the initial frequency of 500MHz to a second frequency of 250MHz, completes the distribution of the EMA signal "001", and then restores the clock frequency to 500MHz. Similarly, the CPU subsystem runs continuously throughout the configuration process without any interruption, ensuring a smooth user experience for the social software.

[0046] In some embodiments of this application, detecting the additional threshold adjustment configuration trigger condition includes: synchronizing the received asynchronous additional margin adjustment signal to the clock domain of the target subsystem to obtain the synchronized additional margin adjustment signal; comparing the synchronized additional margin adjustment signal with the additional margin adjustment signal stored in the previous detection cycle; and determining the additional margin adjustment configuration trigger condition in response to the comparison result indicating that the two are inconsistent.

[0047] The asynchronous margin adjustment signal is output by the system control register. This adjustment signal can be an N-bit encoded signal, where N can be flexibly set according to the margin adjustment requirements of the static memory and the hardware design specifications. For example, in this embodiment, a 3-bit signal is used, denoted as EMA [2:0], where 2:0 in square brackets represents the bit width range of the encoded signal, corresponding to the sequential arrangement of the 3-bit signal from the high bit to the low bit. The clock domain of this register is not synchronized with the clock domain of the target subsystem such as the CPU subsystem. Direct transmission will result in metastability, timing errors, and other problems, and cannot be directly used for SRAM configuration. The clock domain of the target subsystem is the clock domain that the SRAM and the target subsystem work together. Based on the SRAM clock (CLK_SRAM), it is the clock domain that the EMA signal ultimately needs to adapt to. The synchronized margin adjustment signal refers to the stable EMA signal (EMA_new [2:0]) after converting the asynchronous EMA signal to the clock domain of the target subsystem. It has no metastability risk and can be directly used for subsequent comparison and distribution.

[0048] The extra margin adjustment signal stored in the previous detection cycle is the synchronized EMA signal (e.g., EMA_t-1 [2:0]) stored in the 3-bit flip-flop within the EMA detection module. This signal is the EMA configuration signal currently being used by the SRAM and is updated in real time with each detection cycle. Then, the 3-bit synchronized EMA signal and the 3-bit historical stored signal are compared bit by bit to determine if there is a coding difference. If at least one bit in the output of the 3-bit XOR gate group is 1, it indicates that there is a coding difference between the new synchronized EMA signal and the currently used EMA signal, and the SRAM needs to be updated with EMA configuration. Then, the 3-bit comparison result is converted into a 1-bit valid trigger signal (Change). This signal provides a clear basis for the clock control module to trigger the frequency reduction. Change=1 indicates that the trigger condition is valid, and Change=0 indicates that the trigger condition is invalid.

[0049] In this embodiment, hardware-level trigger condition self-detection is achieved by synchronizing the received asynchronous margin adjustment signal to the clock domain of the target subsystem and comparing it with the stored value of the previous cycle. This method does not require software polling or interrupt intervention, can respond to changes in EMA value in real time and automatically trigger subsequent frequency reduction configuration processes, reducing software complexity and improving the system's real-time response and reliability to EMA parameter changes in DVFS scenarios.

[0050] In some implementations, obtaining the synchronized margin adjustment signal includes: converting the asynchronous margin adjustment signal to the clock domain of the target subsystem via a synchronization circuit, and outputting the synchronized margin adjustment signal. The synchronization circuit includes multiple cascaded flip-flops for sequentially sampling the asynchronous margin adjustment signal to eliminate metastability.

[0051] The synchronization circuit, a hardware circuit for converting the clock signal of the asynchronous EMA signal, is a core component of the EMA detection module. In this embodiment, a three-stage series-connected flip-flop is used as the synchronization circuit. However, it can be adjusted to a two-stage, four-stage, or multi-stage structure depending on the actual SoC process requirements. The main function is step-by-step sampling of the series-connected flip-flops. A multi-stage series-connected flip-flop refers to multiple D-type edge-triggered flip-flops connected in series. The output of the previous stage flip-flop serves as the input of the next stage flip-flop, driven by the clock of the target subsystem, achieving step-by-step sampling of the asynchronous signal. Step-by-step sampling means that the multi-stage flip-flops sequentially capture and resample the asynchronous signal. Each sampling stage reduces the duration of metastability, ultimately outputting a stable digital signal. Metastability is an inherent problem in the transmission of asynchronous signals across clock domains, referring to the unstable state of the flip-flop output between 0 and 1, which can lead to logic errors in subsequent circuits. Multi-stage sampling is an effective hardware method to eliminate metastability.

[0052] In this embodiment of the application, synchronizing the received asynchronous additional margin adjustment signal to the clock domain of the target subsystem includes: sampling the asynchronous additional margin adjustment signal step by step through multiple cascaded flip-flops, wherein the first flip-flop captures the initial signal in the target clock domain, subsequent flip-flops resample the output of the previous stage in sequence, and the last flip-flop outputs the synchronized additional margin adjustment signal.

[0053] Multi-stage cascaded flip-flops can be constructed using three-stage D-type edge-triggered flip-flops, sequentially connected to form a synchronous chain. The output of the previous stage serves as the input of the next stage, forming the hardware foundation for stage-by-stage sampling. The first stage flip-flop is a level-triggered flip-flop without a clock drive, primarily used for initial capture of asynchronous signals, converting external asynchronous EMA signals into internal chip-level signals. Subsequent stages are edge-triggered flip-flops driven by the target subsystem clock (CLK), their core function being resampling, synchronously sampling the signal output from the previous stage to gradually eliminate metastability. The final stage flip-flop is the last stage of the synchronous chain, outputting a completely stable synchronous signal without any metastability risk, and can be directly used for subsequent signal comparison and distribution.

[0054] For example, taking the asynchronous EMA [0] signal as an example, its corresponding three-level synchronization chain is FF1 (first level), FF2 (second level), and FF3 (third level): FF1 is not driven by CLK and captures the asynchronous level of EMA [0] in real time (such as the high level "1"), and the output may have a metastable "1"; FF2 is driven by the target subsystem 1GHz CLK, and resamples the output of FF1 at the rising edge of CLK, and the output tends to be a stable "1", greatly reducing the risk of metastability; FF3 is driven by the same 1GHz CLK, and resamples the output of FF2 again at the rising edge of CLK, and the output is a completely stable "1", and the risk of metastability is completely eliminated; the output of FF3 is the stable signal after EMA [0] synchronization, which, together with the synchronization signals of EMA [1] and EMA [2], forms "101" EMA_new. [2:0]. This embodiment of the application uses a multi-stage series flip-flop to sample the asynchronous extra margin adjustment signal stage by stage. After the first-stage flip-flop captures the initial signal, subsequent flip-flops resample the output of the previous stage in sequence, eliminating the metastability risk that may occur during cross-clock domain transmission, and finally outputting a stable and reliable synchronized signal. This synchronization circuit provides a high-quality input signal for subsequent EMA value change detection, ensuring the accuracy of trigger condition judgment and the stability of system operation.

[0055] See Figure 3Figure 3 illustrates a schematic diagram of an EMA change detection circuit provided in an embodiment of this application. This circuit is used to compare the synchronized extra margin adjustment signal with the extra margin adjustment signal stored in the previous detection cycle. As shown in Figure 3, the detection circuit includes three XOR gates, one OR gate, and a 3-bit register. The 3-bit register stores the EMA signal value (EMA_t-1[2:0]) of the previous detection cycle; the inputs of the three XOR gates are respectively connected to each bit of the synchronized EMA signal (EMA_new[2:0]) of the current cycle and the corresponding bit output by the register (each bit of EMA_t-1[2:0]), used to compare whether the two are consistent bit by bit; the outputs of the three XOR gates are connected to the input of a three-input OR gate, which summarizes the bit-by-bit comparison results into a 1-bit final change signal (Change).

[0056] The circuit operates as follows: when EMA_new[2:0] and EMA_t-1[2:0] are completely identical, all three XOR gates output 0, and the OR gate outputs 0, indicating that the EMA value has not changed; when EMA_new[2:0] and EMA_t-1[2:0] are inconsistent at any bit, the corresponding XOR gate outputs 1, and the OR gate outputs 1, indicating that a change in the EMA value has been detected. This change signal (Change=1) serves as the additional margin adjustment configuration trigger condition, used to trigger subsequent frequency reduction operations. Through this hardware comparison circuit, this embodiment achieves real-time detection of EMA value changes without software intervention, and the response delay is only a single clock cycle, providing a precise and low-latency trigger signal for subsequent dynamic clock frequency adjustment.

[0057] In some embodiments of this application, in response to the completion of the distribution of the additional margin adjustment signal, restoring the clock frequency of the static memory from the second frequency domain to the first frequency includes: in response to the completion of the distribution of the additional margin adjustment signal, waiting for a preset number of clock cycles, and restoring the clock frequency of the static memory from the second frequency to the first frequency.

[0058] In this embodiment, by adding a preset number of clock cycles after the EMA signal distribution is completed, the SRAM is ensured to stably receive and respond to the new EMA configuration signal, avoiding configuration failure or SRAM malfunction due to premature frequency recovery. The preset number of clock cycles is the number of timing cycles preset by the 4-bit counter within the clock control module, preferably three SRAM clock cycles (CLK_SRAM). This can be flexibly adjusted (e.g., two cycles) according to the number of SRAMs, wiring length, process delay, etc., to provide sufficient time for the SRAM to complete the reception of the EMA signal and internal parameter adjustment. The completion of EMA signal distribution can be determined by waiting for the preset number of clock cycles or by detecting the SRAM's internal configuration completion flag. For example, when using the preset cycle waiting method, after determining that the EMA signal distribution is complete, the finite state machine of the clock control module remains in the output (OUTPUT) state, keeping the SRAM's second frequency unchanged until the counter completes the preset cycle of timing. For example, after the EMA output module distributes the EMA signal "100" to 32 SRAM chips, the finite state machine of the clock control module enters the OUTPUT state. A 4-bit counter starts timing based on a second frequency of 250MHz, counting 1, 2, and 3 clock cycles sequentially (totaling 12ns). During the timing period, the SRAM always operates at 250MHz, completing the internal Tcq and Tcc parameter adjustments. When the counter counts to 3, it outputs a timing completion signal, the finite state machine switches to the RESTORE state, and the clock control module restores the SRAM clock frequency from 250MHz to the first frequency of 1GHz. If the number of SRAM chips is small (e.g., 8 chips), the preset period can be adjusted to 2, totaling 8ns, improving the frequency recovery speed while ensuring effective configuration. This embodiment provides sufficient buffer time for the stable operation of the EMA signal within the static memory by waiting for a preset number of clock cycles after completing the distribution of the additional margin adjustment signal before restoring the clock frequency, avoiding signal sampling errors caused by premature frequency recovery. This mechanism employs a simplified design with a fixed-period wait, eliminating the need to detect signal status, thus reducing hardware implementation complexity while ensuring the reliability and consistency of frequency recovery operations.

[0059] In some embodiments of this application, reducing the clock frequency of the static memory from a first frequency to a second frequency includes: determining a target frequency reduction mode based on the current frequency mode of the static memory, wherein the frequency mode includes a first frequency mode and a second frequency mode, the frequency value corresponding to the first frequency mode is higher than the frequency value corresponding to the second frequency mode, the target frequency reduction mode includes a first frequency reduction mode and a second frequency reduction mode, the first frequency reduction mode corresponds to the first frequency mode, and the second frequency reduction mode corresponds to the second frequency mode; performing frequency reduction processing on the first frequency according to the target frequency reduction mode to obtain the second frequency; wherein the frequency reduction amplitude corresponding to the first frequency reduction mode is different from the frequency reduction amplitude corresponding to the second frequency reduction mode.

[0060] The frequency mode is the initial frequency mode of the SRAM as it operates with the target subsystem. It is determined by the SoC's DVFS strategy and is divided into a first frequency mode (high-frequency mode) and a second frequency mode (low-frequency mode). The frequency value of the first frequency mode is significantly higher than that of the second frequency mode. The target frequency reduction mode is the frequency reduction strategy selected by the clock control module based on the initial frequency mode of the SRAM. It is divided into a first frequency reduction mode corresponding to the high-frequency mode and a second frequency reduction mode corresponding to the low-frequency mode. The frequency reduction magnitude refers to the proportion by which the SRAM's first frequency is reduced to the second frequency. The calculation formula is: Frequency Reduction Magnitude = (First Frequency - Second Frequency) / First Frequency × 100%. The larger the frequency reduction magnitude, the lower the second frequency, and the greater the extension of the timing window.

[0061] The clock control module receives a 1-bit frequency mode signal (Freq_Mode) provided by the system configuration in real time. This signal directly represents the current frequency mode of the SRAM. For example, Freq_Mode=1 indicates that the SRAM is in the first frequency mode (high frequency mode, such as 1GHz), and Freq_Mode=0 indicates that the SRAM is in the second frequency mode (low frequency mode, such as 500MHz). When the clock control module detects the EMA configuration trigger condition (Change=1), it immediately determines the target frequency reduction mode based on the current Freq_Mode signal: if Freq_Mode=1, the target frequency reduction mode is determined to be the first frequency reduction mode; if Freq_Mode=0, the target frequency reduction mode is determined to be the second frequency reduction mode. The identification of the frequency mode and the determination of the target frequency reduction mode are both completed within one clock cycle, ensuring the rapid triggering of the frequency reduction operation.

[0062] Once the clock control module determines the target downclocking mode, the finite state machine switches from the IDLE state to the DECFREQ state and outputs a corresponding division factor selection signal (Div_Sel) to the programmable frequency divider according to the target downclocking mode: If it is the first downclocking mode (corresponding to the high-frequency mode), the output Div_Sel=01, controlling the programmable frequency divider to use a 4:1 division ratio to downclock the first high-frequency frequency (e.g., 1GHz) by 75%, resulting in the second frequency (e.g., 250MHz); if it is the second downclocking mode (corresponding to the low-frequency mode), the output Div_Sel=10, controlling the programmable frequency divider to use a 2:1 division ratio to downclock the first low-frequency frequency (e.g., 500MHz) by 50%, resulting in the second frequency (e.g., 250MHz). After the programmable frequency divider completes the division according to the Div_Sel signal, it outputs a stable second frequency as the new clock frequency for the SRAM, and the downclocking magnitudes of the two downclocking modes are different, achieving graded downclocking.

[0063] Further, in this embodiment of the application, the first frequency is down-clocked according to the target down-clocking mode to obtain the second frequency, including: if the target down-clocking mode is a first down-clocking mode, the first frequency is reduced to a first target frequency, and the timing window of the static memory is extended to a first multiple of the initial period, wherein the first target frequency and the first multiple have a first matching relationship; if the target down-clocking mode is a second down-clocking mode, the first frequency is reduced to a second target frequency, and the timing window of the static memory is extended to a second multiple of the initial period, wherein the second target frequency and the second multiple have a second matching relationship.

[0064] The first down-frequency mode corresponds to the first frequency mode of the SRAM (such as high-frequency mode), which is a large down-frequency reduction mode adapted to the timing requirements of high-frequency scenarios. The first target frequency is the second frequency after down-frequency reduction in the first down-frequency mode, which is the result of the high-frequency first frequency after fixed frequency division, for example, 250MHz. The timing window refers to the time window during which the EMA signal can be stably transmitted in the SRAM clock domain, which is equal to the period of the SRAM clock. The lower the clock frequency, the longer the period, and the larger the timing window. The initial period refers to the clock period of the SRAM at the first frequency. The initial period is narrow in high-frequency mode (e.g., 1GHz corresponds to 1ns). The first multiplier is the extension factor of the timing window in the first down-frequency mode, such as being set to 4 times. The first matching relationship refers to the reciprocal matching relationship between the first target frequency and the first multiplier, that is, the extension factor = first frequency / first target frequency = initial period / period after down-frequency reduction. This is the inherent physical relationship between clock frequency and period, ensuring that the timing window extension factor is quantitatively controllable. Correspondingly, the second down-frequency mode can be the second frequency mode of the SRAM, such as low-frequency mode, which is a small down-frequency reduction mode adapted to the timing requirements of low-frequency scenarios.

[0065] For example, taking the CPU subsystem of a server SoC as an application scenario, this subsystem supports dual-frequency modes: a high-frequency mode (first frequency mode) of 1GHz and a low-frequency mode (second frequency mode) of 500MHz. The clock control module configures different down-frequency strategies for the two modes. In high-frequency mode, after detecting the EMA configuration trigger condition, the first down-frequency mode is activated, dividing the frequency by 4:1 to reduce 1GHz to the first target frequency of 250MHz. The initial period is extended from 1ns to 4ns, and the timing window is increased by 4 times, meeting the strict timing constraints of long-path EMA signal distribution at high frequencies. Even if there are delays in signal synchronization and distribution paths, stable transmission can still be achieved. In low-frequency mode, after detecting the EMA configuration trigger condition, the second down-frequency mode is activated, dividing the frequency by 2:1 to reduce 500MHz to the second target frequency of 250MHz. The initial period is extended from 2ns to 4ns, and the timing window is increased by 2 times. This not only meets the timing requirements but also, because the frequency reduction is only small, the CPU subsystem's computing performance is almost unaffected, ensuring the server's operating efficiency under low load.

[0066] In this embodiment, by reducing the first frequency to the corresponding target frequency under different frequency modes and extending the timing window of the static memory to a corresponding multiple of the initial period, a precise match is achieved between the frequency reduction magnitude and the timing window extension factor. This mechanism ensures sufficient timing margin in high-frequency scenarios to guarantee stable signal distribution, and moderate frequency reduction in low-frequency scenarios to account for performance loss. Thus, while meeting the timing requirements of different DVFS scenarios, the overall energy efficiency of the system is optimized.

[0067] See Figure 4 This diagram illustrates the state transitions of a clock control state machine according to an embodiment of this application. The state machine is used to implement a frequency reduction control process and a mechanism for restoring the clock frequency after waiting for a preset period. As shown in Figure 4, the state machine includes four states: Idle, DECFREQ, OUTPUT, and RESTORE. The meanings and transition processes of each state are as follows:

[0068] Idle State (IDLE): The state machine is in its initial state, and the clock frequency of the static memory remains at the first frequency (normal operating frequency). The state machine waits for the EMA change signal in this state.

[0069] When the EMA detection module detects a change in the EMA value, it outputs a change signal Change=1, triggering the state machine to jump from the idle state (IDLE) to the de-frequency state (DECFREQ).

[0070] DECFREQ State: After entering this state, the state machine determines the target frequency reduction mode based on the current frequency mode of the static memory. If it is the first frequency mode (high frequency), the first frequency reduction mode is selected; if it is the second frequency mode (low frequency), the second frequency reduction mode is selected. The state machine controls the programmable frequency divider to reduce the first frequency according to the selected frequency reduction mode, lowering the clock frequency to the second frequency, and correspondingly extending the timing window of the static memory (e.g., extending the timing window by 4 times in high-frequency scenarios and by 2 times in low-frequency scenarios). Simultaneously, the state machine waits for the frequency divider output to stabilize. When the frequency divider feeds back a stability indication signal Clk_Stab=1 (indicating that the down-frequency clock frequency has been stably output), the state machine transitions from the DECFREQ state to the OUTPUT state.

[0071] Output State (OUTPUT): The state machine maintains the second frequency after frequency reduction unchanged, keeps the timing window in an extended state, and waits for the EMA output module to complete the distribution of the additional margin adjustment signal to be configured. According to this embodiment, this waiting time is 3 clock cycles (corresponding to...). Figure 4 The state machine performs a 3-cycle wait to ensure the signal remains stable within the SRAM. After 3 clock cycles, the state machine transitions from the output state (OUTPUT) to the restore state (RESTORE).

[0072] Restore: The state machine controls the programmable divider to restore the clock frequency from the second frequency to the first frequency, and the timing window is synchronously restored to its initial cycle. Simultaneously, the state machine waits for the frequency to stabilize, with a waiting time of one clock cycle (corresponding to...). Figure 4 (Wait 1 cycle). Once the frequency stabilizes, the state machine returns from the RESTORE state to the IDLE state, waiting for the next EMA change.

[0073] Through the finite state machine design of this state machine, this embodiment achieves precise hardware control of the frequency reduction strategy: in the frequency reduction state, different reduction amplitudes are selected according to the frequency mode, reflecting the differentiated frequency reduction strategy of using different reduction amplitudes for high-frequency and low-frequency modes; in the output state, a three-clock-cycle wait ensures signal stability, providing sufficient buffer time for the stable activation of the EMA signal within the static memory; and the matching relationship between the frequency reduction amplitude and the timing window extension (e.g., high-frequency reduction to 25% to obtain a 4x timing window, low-frequency reduction to 50% to obtain a 2x timing window) is specifically implemented by the parameter configuration of the frequency divider in the frequency reduction state, ensuring sufficient timing margin in different frequency modes. The entire state transition process is completed automatically by hardware without software intervention, realizing an efficient hardware implementation of the static memory control method.

[0074] In some embodiments of this application, at a second frequency, distributing the additional margin adjustment signal to be configured to the static memory includes: temporarily storing the additional margin adjustment signal to be configured in a buffer register; transmitting the signal in the buffer register in parallel to all storage units in the static memory through a fan-out network; and updating the output value of the buffer register after a preset clock cycle after frequency reduction.

[0075] The buffer register can be a 3-bit high-drive-capability D-type flip-flop, dedicated to temporarily storing the EMA_new [2:0] signal. Its function is signal buffering and drive enhancement, solving the signal attenuation problem in the fan-out network. Storing the EMA signal in the buffer register before signal distribution keeps the signal at a stable level, avoiding configuration errors caused by signal fluctuations during distribution. The fan-out network is a dedicated wiring network for the EMA output module, employing a tree-shaped equal-length wiring design. Its function is to transmit the 3-bit EMA signal from the buffer register in parallel to all SRAM cells within the target subsystem. Parallel transmission means that each bit of the 3-bit EMA signal is simultaneously transmitted to the corresponding EMA pin of all SRAMs through an independent wiring branch, ensuring that all SRAM cells receive the signal simultaneously. All storage cells refer to each SRAM chip within the target subsystem, including the SRAMs of core modules such as the CPU subsystem and GPU subsystem; the number can be flexibly adjusted according to the SoC design requirements.

[0076] After the clock control module stabilizes the SRAM clock frequency to the second frequency, the EMA_new [2:0] signal synchronized by the EMA detection module is input to the 3-bit buffer register of the EMA output module. The buffer register captures the signal on the rising edge of the second frequency clock and latches it temporarily. The buffer register adopts a high-drive-capability hardware design, which can drive the signal transmission of multiple fan-out networks, avoiding signal attenuation and distortion in long-distance wiring and multi-branch transmission. The fan-out network is designed with a main wiring branch for each of the 3-bit EMA signals output by the buffer register. Each main branch is then connected to the corresponding EMA pin of all SRAM cells through branch wiring of equal length, forming a tree structure of "one tree with multiple branches". The length of all wiring branches is strictly consistent to ensure that each bit of the 3-bit MA signal has the same delay time when transmitted to different SRAM cells, realizing synchronous parallel transmission of signals. During signal transmission, due to the high drive capability of the buffer register, the signal is attenuated and distorted, and the EMA signal received by all SRAM cells is completely consistent with the signal temporarily stored in the buffer register. When the clock control module reduces the SRAM clock from the first frequency to the second frequency, it does not immediately output the EMA signal in the buffer register to the fan-out network. Instead, it waits for one CLK_SRAM cycle of the second frequency until the clock frequency is completely stable and the delay fluctuations in the signal transmission path are eliminated. Then, through the write enable signal of the buffer register, it formally updates the temporarily stored EMA_new [2:0] signal and outputs it to the fan-out network, starting the parallel distribution of the signal. This waiting process is triggered by the finite state machine of the clock control module and is synchronized with the switching from the DECFREQ state to the OUTPUT state to ensure complete timing matching.

[0077] This embodiment of the application solves the signal consistency and drive capability problems under multi-load conditions by temporarily storing the additional margin adjustment signal to be configured in a buffer register and transmitting it in parallel to all static memory units using a fan-out network. Updating the buffer register output value after a preset clock cycle following frequency reduction provides sufficient setup time for signal propagation and ensures that all memory units receive the updated configuration signal at the same time, avoiding configuration errors caused by differences in signal arrival time and improving the system's reliability and robustness.

[0078] See Figure 5 The document illustrates a flowchart of a static memory control method in an application scenario provided by an embodiment of this application. The process is explained using the example of a mobile SoC's CPU subsystem switching from a low-frequency social application to a high-frequency gaming scenario.

[0079] When the phone is running social media apps, the CPU subsystem operates at a low frequency of 500MHz and a low voltage of 0.8V. The EMA code signal currently output by the system control register is "001" to meet the low-frequency power consumption requirements. When the user launches a large game, the system control register updates the EMA code to "011" according to the DVFS strategy to speed up the SRAM's Tcq and Tcc times and meet the high-frequency performance requirements.

[0080] like Figure 5 As shown, the control method first performs the step of receiving the asynchronous EMA signal. The EMA detection module receives the asynchronous 3-bit EMA encoded signal "011" from the system control register. Then, the asynchronous EMA signal is synchronized to the target subsystem clock domain. The three-stage trigger synchronization circuit inside the EMA detection module samples the asynchronous EMA signal "011" step by step, converts it to the 1GHz clock domain of the CPU subsystem, and obtains the synchronized stable signal EMA_new[2:0] = "011".

[0081] The process then proceeds to detect whether the EMA value has changed. The change detection circuit in the EMA detection module compares the synchronized EMA_new[2:0]="011" with the previous cycle value EMA_t-1[2:0]="001" stored in the register. Since they are inconsistent, a change in the EMA value is determined. Upon detecting a change in the EMA value, a change signal Change is generated. The change detection circuit outputs Change=1 as the EMA configuration trigger condition and sends it to the clock control module. Upon receiving Change=1, the clock control module executes step S105: determining the frequency reduction magnitude based on the frequency mode. At this time, the CPU subsystem is in a 1GHz high-frequency mode, corresponding to the first frequency mode. Therefore, the first frequency reduction mode is determined, with a reduction magnitude of 25% (250MHz) from 1GHz.

[0082] Next, the SRAM clock frequency is reduced from the first frequency to the second frequency. The clock control module controls the programmable divider to reduce the SRAM clock frequency from 1GHz to 250MHz, while the SRAM timing window is extended from 1ns to 4ns, and the clock runs continuously without any interruption to the CPU subsystem.

[0083] After frequency reduction is complete, the EMA signal is distributed at the second frequency. The EMA output module temporarily stores the EMA signal "011" to be configured in a buffer register and distributes it in parallel to the EMA pins of all 16 SRAM chips through a fan-out network. Since the timing window has been extended to 4ns, the signal distribution process has sufficient timing margin and no timing errors.

[0084] The system then waits for a preset period to ensure signal stability. It waits for three 250MHz clock cycles (corresponding to 3 cycles in the diagram) to ensure the EMA signal is stably active within all SRAMs. After this wait, the SRAM clock frequency is restored from the second frequency to the first frequency. The clock control module controls the programmable divider to restore the SRAM clock frequency from 250MHz to 1GHz, and the timing window is synchronized back to 1ns. Finally, it returns to an idle state to await the next EMA change. The system returns to its initial state, and the CPU subsystem runs at a high frequency of 1GHz with the new EMA configuration "011," completing the entire EMA configuration process. The entire process is completed automatically by hardware without software intervention, and the SRAM clock runs continuously without any interruption to the CPU subsystem, ensuring a smooth experience when switching between social media apps and demanding games.

[0085] Another embodiment of this application also provides a control device for a static memory, comprising:

[0086] A frequency adjustment unit is configured to reduce the clock frequency of the static memory from a first frequency to a second frequency in response to detecting an additional margin adjustment configuration trigger condition, wherein the second frequency is greater than zero.

[0087] A signal distribution unit is used to distribute the additional margin adjustment signal to be configured to the static memory at the second frequency;

[0088] A frequency recovery unit is configured to restore the clock frequency of the static memory from the second frequency to the first frequency in response to completing the distribution of the additional margin adjustment signal.

[0089] It should be noted that the specific implementation of each unit in this embodiment can be referred to the corresponding content above, and will not be described in detail here.

[0090] In another embodiment of this application, a readable storage medium is provided on which a computer program is stored, which, when executed by a processor, implements the static memory control method described above.

[0091] Another embodiment of this application also provides a system on a single chip, see [link to relevant documentation]. Figure 6 The on-chip system includes:

[0092] The target subsystem 601 includes static memory.

[0093] Trigger detection circuit 602 is used to detect the trigger conditions for additional margin adjustment configuration.

[0094] The clock control circuit 603, connected to the trigger detection circuit 602 and the static memory, is used to reduce the clock frequency of the static memory from a first frequency to a second frequency in response to the detection of the trigger condition, wherein the second frequency is greater than zero.

[0095] The signal distribution circuit 604, connected to the clock control circuit 603 and the static memory, is used to distribute the additional threshold adjustment signal to be configured to the static memory at the second frequency.

[0096] The clock control circuit 603 is also used to restore the clock frequency of the static memory from the second frequency to the first frequency in response to the distribution of the additional margin adjustment signal.

[0097] In some possible implementations, the trigger detection circuit includes:

[0098] A synchronization circuit is used to synchronize the received asynchronous margin adjustment signal to the clock domain of the target subsystem and output the synchronized margin adjustment signal.

[0099] A comparison circuit, connected to the synchronization circuit, is used to compare the synchronized additional margin adjustment signal with the additional margin adjustment signal stored in the previous detection cycle, and output a trigger signal in response to the inconsistency between the two.

[0100] In some possible implementations, the synchronization circuit includes multiple cascaded flip-flops for progressively sampling the asynchronous margin adjustment signal to eliminate metastability.

[0101] In some possible implementations, the clock control circuit includes:

[0102] A state machine is used to determine a target frequency reduction mode based on the current frequency mode of the static memory. The frequency mode includes a first frequency mode and a second frequency mode. The frequency value corresponding to the first frequency mode is higher than the frequency value corresponding to the second frequency mode. The target frequency reduction mode includes a first frequency reduction mode and a second frequency reduction mode. The first frequency reduction mode corresponds to the first frequency mode, and the second frequency reduction mode corresponds to the second frequency mode.

[0103] A programmable frequency divider, connected to the state machine and the static memory, is used to down-clock the first frequency according to the target down-clocking mode and output the second frequency.

[0104] The frequency reduction magnitude corresponding to the first frequency reduction mode is different from that corresponding to the second frequency reduction mode.

[0105] In some possible implementations, if the target frequency reduction mode is a first frequency reduction mode, the programmable frequency divider reduces the first frequency to a first target frequency and extends the timing window of the static memory to a first multiple of the initial period, wherein the first target frequency and the first multiple have a first matching relationship;

[0106] If the target frequency reduction mode is the second frequency reduction mode, the programmable frequency divider reduces the first frequency to the second target frequency and extends the timing window of the static memory to a second multiple of the initial period, wherein the second target frequency and the second multiple have a second matching relationship.

[0107] In some possible implementations, the signal distribution circuit includes:

[0108] A buffer register is used to temporarily store the additional margin adjustment signal to be configured;

[0109] A fan-out network connects the buffer register and all memory cells in the static memory, and is used to transmit the signals in the buffer register to each memory cell in parallel.

[0110] The buffer register updates its output value after a preset clock cycle following the frequency reduction.

[0111] In some possible implementations, the synchronization circuit includes:

[0112] The first-stage trigger is used to capture the initial signal of the asynchronous margin adjustment signal in the target clock domain;

[0113] At least one intermediate stage flip-flop is connected to the first stage flip-flop to resample the output of the previous stage sequentially.

[0114] The final stage trigger is connected to the intermediate stage trigger and is used to output the additional margin adjustment signal after synchronization.

[0115] It should be noted that the specific implementation of the on-chip system and its corresponding circuit in this embodiment can be referred to the relevant content above, and will not be described in detail here.

[0116] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0117] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0118] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0119] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for controlling a static memory, comprising: In response to the detection of an additional margin adjustment configuration trigger condition, the clock frequency of the static memory is reduced from a first frequency to a second frequency, wherein the second frequency is greater than zero; At the second frequency, the additional margin adjustment signal to be configured is distributed to the static memory; In response to the completion of the additional margin adjustment signal distribution, the clock frequency of the static memory is restored from the second frequency to the first frequency.

2. The method according to claim 1, wherein detecting the additional margin adjustment configuration trigger condition includes: The received asynchronous margin adjustment signal is synchronized to the clock domain of the target subsystem to obtain the synchronized margin adjustment signal. The synchronized additional margin adjustment signal is compared with the additional margin adjustment signal stored in the previous detection cycle; In response to the inconsistency between the comparison results, the additional margin adjustment configuration trigger condition is determined.

3. The method according to claim 2, wherein obtaining the synchronized additional margin adjustment signal comprises: The asynchronous margin adjustment signal is converted to the clock domain of the target subsystem by a synchronization circuit, and the synchronized margin adjustment signal is output. The synchronization circuit includes multiple series-connected flip-flops for sampling the asynchronous margin adjustment signal step by step to eliminate metastability.

4. The method of claim 1, wherein restoring the clock frequency of the static memory from the second frequency to the first frequency in response to completing the distribution of the additional margin adjustment signal comprises: In response to the completion of the additional margin adjustment signal distribution, after waiting for a preset number of clock cycles, the clock frequency of the static memory is restored from the second frequency to the first frequency.

5. The method according to claim 1, wherein reducing the clock frequency of the static memory from the first frequency to the second frequency comprises: Based on the current frequency mode of the static memory, a target frequency reduction mode is determined, wherein the frequency mode includes a first frequency mode and a second frequency mode, the frequency value corresponding to the first frequency mode is higher than the frequency value corresponding to the second frequency mode, and the target frequency reduction mode includes a first frequency reduction mode and a second frequency reduction mode, the first frequency reduction mode corresponds to the first frequency mode, and the second frequency reduction mode corresponds to the second frequency mode. The first frequency is down-frequency processed according to the target down-frequency mode to obtain the second frequency; The frequency reduction magnitude corresponding to the first frequency reduction mode is different from that corresponding to the second frequency reduction mode.

6. The method according to claim 5, wherein the step of down-clocking the first frequency according to the target down-clocking mode to obtain the second frequency comprises: If the target frequency reduction mode is the first frequency reduction mode, the first frequency is reduced to the first target frequency, and the timing window of the static memory is extended to the first multiple of the initial period, wherein the first target frequency and the first multiple have a first matching relationship; If the target frequency reduction mode is the second frequency reduction mode, the first frequency is reduced to the second target frequency, and the timing window of the static memory is extended to the second multiple of the initial period, wherein the second target frequency and the second multiple have a second matching relationship.

7. The method according to claim 1, wherein distributing the additional margin adjustment signal to be configured to the static memory at the second frequency comprises: The additional margin adjustment signal to be configured is temporarily stored in a buffer register; The signals in the buffer register are transmitted in parallel to all memory cells in the static memory through a fan-out network; The output value of the buffer register is updated after a preset clock cycle following the frequency reduction.

8. The method according to claim 2, wherein synchronizing the received asynchronous margin adjustment signal to the clock domain of the target subsystem comprises: The asynchronous margin adjustment signal is sampled step by step by multiple cascaded flip-flops. The first flip-flop captures the initial signal in the target clock domain, and subsequent flip-flops resample the output of the previous stage in sequence. The last flip-flop outputs the synchronized margin adjustment signal.

9. A system-on-a-chip, comprising: The target subsystem includes a static memory; Trigger detection circuit, used to detect the trigger conditions for additional margin adjustment configuration; A clock control circuit, connected to the trigger detection circuit and the static memory, is used to reduce the clock frequency of the static memory from a first frequency to a second frequency in response to detecting the trigger condition, wherein the second frequency is greater than zero; A signal distribution circuit, connected to the clock control circuit and the static memory, is used to distribute the additional margin adjustment signal to be configured to the static memory at the second frequency. The clock control circuit is also configured to restore the clock frequency of the static memory from the second frequency to the first frequency in response to completing the distribution of the additional margin adjustment signal.

10. An electronic device, comprising: A memory for storing computer programs and the data generated by the execution of said computer programs; A processor for executing the application to achieve: In response to the detection of an additional margin adjustment configuration trigger condition, the clock frequency of the static memory is reduced from a first frequency to a second frequency, wherein the second frequency is greater than zero; At the second frequency, the additional margin adjustment signal to be configured is distributed to the static memory; In response to the completion of the additional margin adjustment signal distribution, the clock frequency of the static memory is restored from the second frequency to the first frequency.

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