Fail-safe circuit and system on chip

Abstract

The embodiment provides a fault safety circuit and a system on chip, wherein the circuit comprises: a control module adapted to generate a first control signal and a second control signal according to a voltage of a power supply end and a potential of an output node; a gating module adapted to be gated or turned off according to the first control signal and the second control signal and an input signal provided by an input module; and a switch module having a first switch branch and a second switch branch, the switch module being adapted to, when the gating module is gated, gate the first switch branch and turn off the second switch branch according to the voltage of the power supply end, so that the potential of the output node is the potential of the input signal, and being adapted to, when the gating module is turned off, gate the second switch branch and turn off the first switch branch, so that the potential of the second switch branch is the potential of the output node. By using the technical scheme, the reaction time of the fault safety circuit in a power-off state can be reduced, and thus the safety and service life of a system circuit are improved.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a fail-safe circuit and a system-on-a-chip. Background Technology

[0002] With the vigorous development of integrated circuits, electronic products are being used in a wider range of fields, and the requirements for the reliability of integrated circuits are becoming increasingly stringent.

[0003] In some circuit applications, when a power outage occurs at the power supply end—for example, the voltage at the power supply end suddenly disappears, such as becoming 0V—while devices connected to the output nodes or output terminals of the power supply end are in normal working condition, there is a possibility that the current or voltage generated by the devices may flow back to the power supply end through the output nodes or output terminals, potentially damaging the power supply end. To prevent this backflow, a fail-safe circuit is usually installed at the power supply end.

[0004] However, existing fail-safe circuits still have some problems. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a fail-safe circuit and a system-on-a-chip that can reduce the response time of the fail-safe circuit under power failure conditions, thereby improving the safety and service life of the system circuit.

[0006] This invention provides a fail-safe circuit, comprising: an input module, a control module, a gating module, a switching module, and an output node, wherein:

[0007] The control module is coupled to the power supply terminal, the gating module, the switching module and the output node respectively, and is adapted to generate a first control signal and a second control signal according to the voltage of the power supply terminal and the potential of the output node, wherein the potentials of the first control signal and the second control signal are different.

[0008] The gating module is coupled to the switch module and the input module respectively, and is adapted to be selected or turned off according to the first control signal and the second control signal, as well as the input signal provided by the input module;

[0009] The switching module is coupled to the power supply terminal and the output node, respectively. The switching module has a first switching branch and a second switching branch. The switching module is adapted to select the first switching branch and turn off the second switching branch according to the voltage of the power supply terminal when the gating module is selected, so that the potential of the output node is the potential of the input signal. It is also adapted to select the second switching branch and turn off the first switching branch according to the voltage of the power supply terminal when the gating module is turned off, so that the potential of the second switching branch is the potential of the output node.

[0010] This invention provides a system-on-a-chip including the fail-safe circuit described in any of the foregoing embodiments.

[0011] The fail-safe circuit provided in this embodiment of the invention uses a gating module directly coupled to the input module, which reduces the energy consumption of the input signal and enhances the driving capability of the gating module. Upon receiving the first and second control signals generated by the control module, the gating module can quickly turn on or off. When the gating module is off, i.e., when the fail-safe circuit is in a fail-safe state, the switching module can quickly turn on the second switching branch and turn off the first switching branch based on the voltage at the power supply terminal. This allows the potential of the second switching branch to be quickly raised to the potential of the output node. When the potential of the second switching branch and the potential of the output node are the same, it prevents electrical signals generated by external devices from flowing back into the system circuit through the output node. Therefore, the fail-safe circuit of this embodiment of the invention can reduce the response time of the fail-safe circuit in a power-down state, thereby improving the safety and service life of the system circuit. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this specification, the drawings used in the description of the embodiments of this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A schematic diagram of a fail-safe circuit is shown.

[0014] Figure 2 A schematic diagram of a fail-safe circuit according to an embodiment of the present invention is shown;

[0015] Figure 3 A schematic diagram of the structure of a switch module according to an embodiment of the present invention is shown;

[0016] Figure 4A schematic diagram of the specific structure of a switch module in an embodiment of the present invention is shown;

[0017] Figure 5 A schematic diagram of the specific structure of a control module in an embodiment of the present invention is shown;

[0018] Figure 6 A schematic diagram of another fail-safe circuit in an embodiment of the present invention is shown;

[0019] Figure 7 A schematic diagram of the specific structure of another fail-safe circuit in an embodiment of the present invention is shown;

[0020] Figure 8 A schematic diagram of the specific structure of another fail-safe circuit in an embodiment of the present invention is shown;

[0021] Figure 9 A schematic diagram of waveform changes at a critical node in a fail-safe circuit is shown.

[0022] Figure 10 A schematic diagram of waveform changes at a critical node in a fail-safe circuit according to an embodiment of the present invention is shown.

[0023] Figure 11 A schematic diagram of the specific structure of another fail-safe circuit in an embodiment of the present invention is shown. Detailed Implementation

[0024] As described in the background section, existing fail-safe circuits still have some problems when the voltage at the power supply end suddenly disappears.

[0025] To more clearly illustrate the problems with fail-safe circuits, the following detailed explanation is provided with reference to the accompanying drawings and specific examples.

[0026] See Figure 1 The diagram shown is a structural schematic of a fail-safe circuit, as follows: Figure 1 As shown, the fail-safe circuit includes an enable terminal OEN, an input node I, an output node PAD, inverters P1 to P4, a second inverter P2, P-type transistors PM1 to PM4, N-type transistors NM1 to NM3, a NAND gate, a NOR gate, and a control module. The source of the P-type transistor PM1 is connected to the power supply terminal VDDIO, and the gate of the P-type transistor PM2 is connected to the control module.

[0027] In this embodiment, when the level of OEN is 0 (corresponding to a low level), if the voltage of VDDIO is 1 (corresponding to a high level), the potential of the control signal Sc output by the control module to the gate of the P-type transistor PM2 is 0, so that both the P-type transistor PM2 and the N-type transistor NM2 are turned on, the P-type transistor PM3 is turned off, and the P-type transistor PM4 is turned on, thus selecting the path between the input node I and the output node PAD. The potential of PG is the same as the potential of the output node PAD and is related to the input signal of the input node I.

[0028] In this embodiment, when the level of OEN is 0, if the voltage of VDDIO is 0 at this time, the potential of the control signal Sc output by the control module to the gate of the P-type transistor PM2 is 1. Then, both the P-type transistor PM2 and the N-type transistor NM2 are turned off, the P-type transistor PM3 is turned on, and the P-type transistor PM4 is turned off. At this time, the potential of the PG point is the same as the potential of the output node PAD, thereby avoiding backflow to the power supply end through the output node PAD.

[0029] In practical applications, the inventors discovered that when the voltage of VDDIO is 0, due to the presence of P-type transistor PM1 and N-type transistor NM1, the driving capability of the output to P-type transistor PM2 and N-type transistor NM2 is reduced, and P-type transistor PM2 and N-type transistor NM2 cannot be turned off quickly. During this period, the potential of point PG cannot be pulled up to the potential of output node PAD, resulting in the phenomenon that the current or voltage generated by external devices flows back to the power supply terminal through the output node PAD, which will damage the power supply terminal.

[0030] To address the aforementioned technical problems, this invention provides a fail-safe circuit, comprising: an input module, a control module, a gating module, a switching module, and an output node. The control module is coupled to a power supply terminal, the gating module, the switching module, and the output node, respectively, and is adapted to generate a first control signal and a second control signal based on the voltage of the power supply terminal and the potential of the output node, wherein the first control signal and the second control signal have different potentials. The gating module is coupled to the switching module and the input module, respectively, and is adapted to generate a first control signal and a second control signal based on the first control signal, the second control signal, and the output node's voltage. The input signal is selected or turned off; the switching module is coupled to the power supply terminal and the output node respectively, and the switching module has a first switching branch and a second switching branch, wherein the switching module is adapted to select the first switching branch and turn off the second switching branch according to the voltage of the power supply terminal when the selection module is selected, so that the potential of the output node is the potential of the input signal, and is adapted to select the second switching branch and turn off the first switching branch according to the voltage of the power supply terminal when the selection module is turned off, so that the potential of the second switching branch is the potential of the output node.

[0031] The fail-safe circuit provided in this embodiment of the invention uses a gating module directly coupled to the input module, which reduces the energy consumption of the input signal and enhances the driving capability of the gating module. Upon receiving the first and second control signals generated by the control module, the gating module can quickly turn on or off. When the gating module is off, i.e., when the fail-safe circuit is in a fail-safe state, the switching module can quickly turn on the second switching branch and turn off the first switching branch based on the voltage at the power supply terminal. This allows the potential of the second switching branch to be quickly raised to the potential of the output node. When the potential of the second switching branch and the potential of the output node are the same, it prevents electrical signals generated by external devices from flowing back into the system circuit through the output node. Therefore, the fail-safe circuit of this embodiment of the invention can reduce the response time of the fail-safe circuit in a power-down state, thereby improving the safety and service life of the system circuit.

[0032] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be described by way of example below with reference to the accompanying drawings.

[0033] See Figure 2 The diagram shown is a structural schematic of a fail-safe circuit according to an embodiment of the present invention. Figure 2 As shown, the fail-safe circuit may include: an input module 110, a control module 120, a gating module 130, a switching module 140, and an output node PAD, wherein:

[0034] The control module 120 is coupled to the power supply terminal VDD, the gating module 130, the switching module 140 and the output node PAD respectively, and is adapted to generate a first control signal P_FSC and a second control signal P_FSCN according to the voltage of the power supply terminal VDD and the potential of the output node PAD, and the potentials of the first control signal P_FSC and the second control signal P_FSCN are different.

[0035] The gating module 130 is coupled to the switch module 140 and the input module 110 respectively, and is adapted to be selected or turned off according to the first control signal P_FSC and the second control signal P_FSCN, as well as the input signal IN provided by the input module 110.

[0036] The switching module 140 is coupled to the power supply terminal VDD and the output node PAD, respectively. The switching module 140 has a first switching branch SW1 and a second switching branch SW2. The switching module 140 is adapted to select the first switching branch SW1 and turn off the second switching branch SW2 according to the voltage of the power supply terminal VDD when the gating module 130 is selected, so that the potential of the output node PAD is the potential of the input signal IN. The switching module 140 is also adapted to select the second switching branch SW2 and turn off the first switching branch SW1 according to the voltage of the power supply terminal VDD when the gating module 130 is turned off, so that the potential of the second switching branch SW2 is the potential of the output node PAD.

[0037] In this embodiment, the principle of the fail-safe circuit is as follows:

[0038] When the fail-safe circuit is in normal operating condition, the voltage at the power supply terminal VDD is 1. The control module 120 can generate a first control signal P_FSC and a second control signal P_FSCN with different potentials based on the voltage at the power supply terminal VDD and the level of the output node PAD (for example, the potential of the first control signal P_FSC is 0, while the potential of the second control signal P_FSCN is 1). Then, under the action of the first control signal P_FSC, the second control signal P_FSCN, and the input signal IN, the gating module 130 can be gated to output the input signal IN to the first switch branch SW1 and the second switch branch SW2 respectively.

[0039] Under the influence of the voltage at the power supply terminal VDD and the input signal IN, the first switch branch SW1 is turned on, while the second switch branch SW2 is turned off. This opens the path between the input module 110 and the output node PAD, and the potential of the output node PAD is the same as the potential of the input signal IN, enabling the fail-safe circuit to drive external devices normally.

[0040] When the fail-safe circuit is in a fail-safe state, the voltage at the power supply terminal VDD is 0. The control module 120 can generate a first control signal P_FSC and a second control signal P_FSCN with different potentials based on the voltage at the power supply terminal VDD and the level of the output node PAD (for example, the potential of the first control signal P_FSC is 1, while the potential of the second control signal P_FSCN is 0). Then, under the action of the first control signal P_FSC, the second control signal P_FSCN, and the input signal IN, the gating module 130 can be turned off, thereby disconnecting the path between the input module 110 and the output node PAD.

[0041] At the same time, under the action of the power supply VDD, the first switch branch SW1 is turned off, and the second switch branch SW2 is turned on. In this way, the path between the second switch branch SW2 and the output node PAD is opened, so that the potential of the second switch branch SW2 can be raised to the potential of the output node PAD. When the potential of the second switch branch SW2 is the same as the potential of the output node PAD, it can prevent the electrical signals generated by external devices from flowing back into the system circuit through the output node.

[0042] Furthermore, by directly coupling the gating module 130 to the input module 110, the energy consumption of the input signal can be reduced, and the driving capability of the gating module 130 can be enhanced. Thus, when the first control signal P_FSC and the second control signal P_FSCN generated by the control module 120 are received, the gating module 130 can quickly turn on or off. Consequently, when the fault-safe circuit is in a fault-safe state, the potential of the second switch branch SW2 can be quickly raised to the potential of the output node PAD.

[0043] In short, this embodiment, by placing the position of the gating module 130 at the front and using the first control signal P_FSC and the second control signal P_FSCN generated by the control module 120 to control the gating and shutting-off process of the gating module 130, can enable the potential of the second switch branch SW2 to be quickly raised to the potential of the output node PAD when the fault-safe circuit is in a fault-safe state, so as to avoid the backflow phenomenon.

[0044] It is understood that the above examples are illustrated with the power supply voltage VDD being 1, the potential of the first control signal P_FSC being 0, and the potential of the second control signal P_FSCN being 1, and the power supply voltage VDD being 0, the potential of the first control signal P_FSC being 1, and the potential of the second control signal P_FSCN being 0. In some other embodiments, when the power supply voltage VDD is 1, the potential of the first control signal P_FSC is 1, and the potential of the second control signal P_FSCN is 0; and when the power supply voltage VDD is 0, the potential of the first control signal P_FSC is 0, and the potential of the second control signal P_FSCN is 1.

[0045] In this embodiment, combined with Figure 2 See Figure 3 The diagram shown is a structural schematic of a switch module in an embodiment of the present invention. Figure 3 As shown, the switch module 140 may include: a first switch unit 141, a second switch unit 142, and a pull-up unit 143, wherein:

[0046] The first switching unit 141 is located on the first switching branch SW1 and is coupled to the pull-up unit 143, the gating module 130, the power supply terminal VDD and the second switching unit 142 respectively. The first switching unit 141 is adapted to generate a first driving signal when the gating module 130 is selected according to the voltage of the power supply terminal VDD, and is adapted to generate a second driving signal when the gating module 130 is turned off according to the voltage of the power supply terminal VDD.

[0047] The second switching unit 142 is located on the first switching branch SW1 and is coupled to the power supply terminal VDD and the output node PAD respectively. The second switching unit 142 is adapted to select the first switching branch SW1 according to the voltage of the power supply terminal VDD and the first driving signal, and is adapted to turn off the first switching branch SW1 according to the voltage of the power supply terminal VDD and the second driving signal.

[0048] The pull-up unit 143 is located on the second switch branch SW2 and is coupled to the gating module 130, the power supply terminal VDD and the output node PAD respectively. The pull-up unit 143 is adapted to turn off the second switch branch SW2 according to the voltage of the power supply terminal VDD when the gating module 130 is turned on, and is adapted to turn on the second switch branch SW2 according to the voltage of the power supply terminal VDD when the gating module 130 is turned off.

[0049] In this embodiment, when the voltage of the power supply terminal VDD is 1, the gating module 130 can be selected, so that the input signal IN can be output to the first switching unit 141 located on the first switching branch SW1 and the pull-up unit 143 located on the second switching branch SW2 respectively. At this time, since the voltage of the power supply terminal VDD is 1, the first switching unit 141 is turned on, while the pull-up unit 143 is turned off, that is, the second switching branch SW2 is turned off.

[0050] When the first switching unit 141 is turned on, the second switching unit 142 is also turned on under the action of the power supply terminal VDD and the first drive signal, so that the first switching branch SW1 is selected, forming a path between the input module 110, the first switching unit 141, the second switching unit 142, and the output node PAD.

[0051] In this embodiment, when the voltage at the power supply terminal VDD is 0, the gating module 130 can be turned off, and there is no input signal on the first switch branch SW1 and the second switch branch SW2. At this time, since the voltage at the power supply terminal VDD is 1, the pull-up unit 143 and the first switch unit 141 are turned on. When the first switch unit 141 is turned on, the second switch unit 142 is turned off under the action of the power supply terminal VDD and the second drive signal.

[0052] In this way, the second switch branch SW2 is turned on, forming a path between input module 110, pull-up unit 143, and output node PAD.

[0053] In this embodiment, by setting a first switch branch SW1 and a second switch branch SW2, and ensuring that the first switch branch SW1 and the second switch branch SW2 are not turned on at the same time, different switch branches can be selected when the fault-safe circuit is in different states, so as to prevent electrical signals generated by external devices from flowing back into the system circuit through the output node PAD.

[0054] In this embodiment, see Figure 4 The schematic diagram shown in this embodiment of the invention illustrates the specific structure of a switch module. Figure 4 As shown, the first switching unit 141 may include: a first NMOS transistor NM11 and a first PMOS transistor PM11, wherein:

[0055] The control terminals of the first PMOS transistor PM11 and the first NMOS transistor NM11 are both coupled to the gating module 130 and the pull-up unit 143, respectively. The first terminal of the first PMOS transistor PM11 is connected to the power supply terminal VDD. The second terminal of the first PMOS transistor PM11 is connected to the first terminal of the first NMOS transistor NM11 and the second switching unit 142, respectively. The second terminal of the first NMOS transistor NM11 is grounded.

[0056] In this embodiment, when the voltage of the power supply terminal VDD is 1, both the first PMOS transistor PM11 and the first NMOS transistor NM11 are turned on, thereby generating a first drive signal to the second switching unit 142; when the voltage of the power supply terminal VDD is 0, the first PMOS transistor PM11 is turned off, while the first NMOS transistor NM11 is turned on, thereby generating a second drive signal to the second switching unit 142.

[0057] In other words, by employing the first NMOS transistor NM11 and the first PMOS transistor PM11 with the above-mentioned connection relationship, the first switching unit 141 is always in the selected state, thereby generating a first driving signal Tr1 for driving the second switching unit 142 to conduct based on the state of the selection module 130, and outputting a second driving signal Tr2 for driving the second switching unit 142 to conduct, so as to control the on / off state of the first switching branch SW1.

[0058] In this embodiment, the second switching unit 142 may include: a second PMOS transistor PM12, the control terminal of the second PMOS transistor PM12 is connected to the first switching unit 141, the first terminal of the second PMOS transistor PM12 is connected to the power supply terminal VDD, and the second terminal of the second PMOS transistor PM12 is connected to the output node PAD.

[0059] In this embodiment, when the voltage of the power supply terminal VDD is 1, under the action of the first drive signal and the power supply terminal VDD, the second PMOS transistor PM12 is turned on, thereby turning on the first switching branch SW1, and the potential of the output node PAD is the same as the potential of the input signal IN; when the voltage of the power supply terminal VDD is 0, under the action of the second drive signal and the power supply terminal VDD, the second PMOS transistor PM12 is turned off, thereby turning off the first switching branch SW1, so as to disconnect the path between the first switching branch SW1 and the output node PAD, while the second switching branch SW2 is turned on, which can prevent the electrical signals generated by external devices from flowing back to the system circuit through the output node PAD.

[0060] In this embodiment, the first switching unit 141 is coupled to the gating module 130 at the first node IPA, and is coupled to the second switching unit 142 at the second node PG.

[0061] In this case, the second switch branch SW2 may include: a first sub-branch SW21 and a second sub-branch SW22, wherein the first end of the first sub-branch SW21 is coupled to the first node IPA and the second end of the first sub-branch SW21 is coupled to the output node PAD; the first end of the second sub-branch SW22 is coupled to the second node PG and the second end of the second sub-branch SW22 is coupled to the output node PAD.

[0062] In other words, the first sub-branch SW21 and the second sub-branch SW22 share the same input terminal.

[0063] It should be noted that "the first sub-branch SW21 and the second sub-branch SW22 share the same input terminal" means that when the fault-safe circuit is in a fault-safe state, the signal on the output node PAD is simultaneously transmitted to the first sub-branch SW21 and the second sub-branch SW22. Therefore, the output node PAD can be considered as the "signal input terminal", hence the first sub-branch SW21 and the second sub-branch SW22 share the same input terminal.

[0064] Correspondingly, the pull-up unit 143 may include: a fifth PMOS transistor PM13 located on the first sub-branch SW21 and a sixth PMOS transistor PM14 located on the second sub-branch SW2, wherein:

[0065] The control terminal of the fifth PMOS transistor PM13 is connected to the power supply terminal VDD. The first terminal of the fifth PMOS transistor PM13 serves as the first terminal of the first sub-branch SW1, and the second terminal of the fifth PMOS transistor PM13 serves as the second terminal of the first sub-branch SW1.

[0066] The control terminal of the sixth PMOS transistor PM14 is connected to the power supply terminal VDD. The first terminal of the sixth PMOS transistor PM14 serves as the first terminal of the second sub-branch SW2, and the second terminal of the sixth PMOS transistor PM14 serves as the second terminal of the second sub-branch SW2.

[0067] In this embodiment, when the voltage of the power supply terminal VDD is 0, the first switch branch SW1 is turned off, and the fifth PMOS transistor PM13 and the sixth PMOS transistor PM14 are both turned on, thereby forming a path between the first node IPA and the fifth PMOS transistor PM13-PAD, and forming a path between the second node PG and the sixth PMOS transistor PM14-PAD. Thus, the potentials of the first node IPA and the second node PG are both the potentials of the output node PAD. In this way, when the second switch unit 142 is turned off, external devices cannot backfeed their generated electrical signals to the system circuit through the output node PAD.

[0068] In this embodiment, by placing the gating module 130 in front (i.e., before the switch module 140), the demand on the driving capability of the switch module 140 can be greatly reduced, compared to Figure 1 The fault circuit in the circuit can be replaced by a transistor with a smaller size, which can be used as the transistor in the switching module 140, thereby reducing the layout size and reducing the overall power consumption.

[0069] In this embodiment, when the second switch branch SW2 is turned on, the potential of the second node PG is the same as the potential of the output node PAD. Since the second node PG is connected to the control terminal of the second PMOS transistor PM12, there is a risk that the second PMOS transistor PM12 may be mis-turned on when a parasitic diode exists in the second PMOS transistor PM12, which may cause a reverse current phenomenon.

[0070] Based on this, see Figure 4 and Figure 5 ,in, Figure 5 This is a schematic diagram of the specific structure of a control module in an embodiment of the present invention, such as... Figure 4 and Figure 5 As shown, the control module 120 may include a well potential generation unit 121, which is coupled to the substrate NW of the second PMOS transistor PM12, the power supply terminal VDD, and the output node PAD, respectively. It is adapted to conduct the path between the substrate NW of the second PMOS transistor PM12 and the power supply terminal VDD when the selection module 130 is selected, such that the potential of the substrate NW of the second PMOS transistor PM12 is equal to the voltage of the power supply terminal VDD; and to conduct the path between the substrate NW of the second PMOS transistor PM12 and the output node PAD when the selection module 130 is turned off, such that the potential of the substrate NW of the second PMOS transistor PM12 is equal to the potential of the output node PAD.

[0071] Specifically, when the selection module 130 is turned off, the potential of the second node PG is the same as the potential of the output node PAD, and the potential of the substrate NW of the second PMOS transistor PM12 is also the same as that of the output node PAD. This allows the parasitic diode in the second PMOS transistor PM12 to be in a short-circuit state, and the second PMOS transistor PM12 cannot be turned on. Thus, when the selection module 130 is turned off and the fault-safe circuit is in a fault-safe state, external devices cannot backflow the electrical signals they generate to the system circuit through the output node PAD.

[0072] In this embodiment, as Figure 5 As shown, the well potential generation unit 121 may include: a third PMOS transistor PM15 and a fourth PMOS transistor PM16, wherein:

[0073] The control terminal of the third PMOS transistor PM15 is connected to the output node PAD. The first terminal of the third PMOS transistor PM15 is connected to the power supply terminal VDD and the control terminal of the fourth PMOS transistor PM16, respectively. The second terminal of the third PMOS transistor PM15 is connected to the third terminal of the third PMOS transistor PM15, the second terminal and the third terminal of the fourth PMOS transistor PM16, and the substrate NW of the second PMOS transistor PM12, respectively. The first terminal of the fourth PMOS transistor PM16 is connected to the output node PAD.

[0074] In this embodiment, when the voltage of the power supply terminal VDD is 1, the third PMOS transistor PM15 is turned on, thereby forming a path between the power supply terminal VDD, the third PMOS transistor PM15, and the substrate NW, so that the potential of the substrate NW of the second PMOS transistor PM12 is the same as the voltage of the power supply terminal VDD.

[0075] When the voltage at the power supply terminal VDD is 0, the fourth PMOS transistor PM16 is turned on, thus forming a path between the output node PAD, the fourth PMOS transistor PM16, and the substrate NW. This makes the potential of the substrate NW of the second PMOS transistor PM12 the same as the potential of the output node PAD. Thus, when the potential at the control terminal of the second PMOS transistor PM12 is also the potential of the output node PAD, the parasitic diode in the second PMOS transistor PM12 will inevitably be in a short-circuit state, and the second PMOS transistor PM12 cannot be turned on. Therefore, when the fail-safe circuit is in a fail-safe state, external devices cannot backflow the electrical signals they generate to the system circuit through the output node PAD.

[0076] In practical applications, the inventors further discovered that when the fail-safe circuit is in a fail-safe state, there is a chance that the path between the output node PAD and ground will be made open. In this case, the electrical signal of the output node PAD will flow to ground, resulting in leakage.

[0077] In this embodiment, to improve the safety of the fault-safe circuit when it is in a fault-safe state, see [reference needed]. Figure 6 The schematic diagram of another fail-safe circuit in this embodiment of the invention is shown below. Figure 6 As shown, the fail-safe circuit may further include: a pull-down module 150, coupled to the switch module 140, adapted to, in response to the first pull-down signal SLHP and the second pull-down signal OEH, disconnect the path between the switch module 140 and ground VSS when the gating module 130 is turned off, and select the path between the switch module 140 and ground VSS when the gating module 130 is selected.

[0078] Specifically, when the selection module 130 is selected, it indicates that the fault-safe circuit is in normal working condition and the voltage of the power supply terminal VDD is 1. At this time, the path between the power supply terminal VDD, the switch module 140, and the pull-down module 150 is selected. Under the action of the power supply terminal VDD and the first pull-down signal SLHP, as well as the power supply terminal VDD and the second pull-down signal OEH, the pull-down module 150 is turned on, thereby selecting the path between the switch module 140 and the ground VSS.

[0079] When the gating module 130 is turned off, it indicates that the fault-safe circuit is in a fault-safe state, and the voltage of the power supply terminal VDD is 0. At this time, the path between the power supply terminal VDD, the switch module 140, and the pull-down module 150 is turned off. Under the action of the first pull-down signal SLHP and the second pull-down signal OEH, the pull-down module 150 is turned off, thereby disconnecting the path between the switch module 140 and ground VSS. In this way, the path between the output node PAD and ground VSS is disconnected, thus avoiding leakage.

[0080] In this embodiment, the first pull-down signal SLHP and the second pull-down signal OEH can be manually input or obtained from other devices. This embodiment does not impose any restrictions on the source of the first pull-down signal SLHP and the second pull-down signal OEH.

[0081] In this embodiment, the connection and disconnection between the switching module and ground can be achieved by changing the potentials of the first pull-down signal SLHP and the second pull-down signal OEH.

[0082] In this embodiment, to further improve the safety of the fault-safe circuit when it is in a fault-safe state, see below. Figure 6 The fail-safe circuit may further include a logic control module 160, which is coupled to the control module 120 and the pull-down module 150 respectively. It is adapted to perform logical operations on the first initial pull-down signal SLHN and the first control signal P_FSC to generate the first pull-down signal SLHP; and to perform logical operations on the second initial pull-down signal OENH and the first control signal P_FSC to generate the second pull-down signal OEH.

[0083] Specifically, when the selection module 130 is selected, it indicates that the fault-safe circuit is in normal working condition, the voltage of the power supply terminal VDD is 1, and the potential of the first control signal P_FSC is 0. At this time, the path between the power supply terminal VDD, the switch module 140, and the pull-down module 150 is selected. At the same time, the logic control module 160 can perform logical operations on the first control signal P_FSC and the first initial pull-down signal SLHN to generate the first pull-down signal SLHP; and perform logical operations on the first control signal P_FSC and the second initial pull-down signal OENH to generate the second pull-down signal OEH, thereby turning on the pull-down module 150, and thus selecting the path between the switch module 140 and ground VSS.

[0084] When the selection module 130 is turned off, it indicates that the fault-safe circuit is in a fault-safe state, the voltage of the power supply terminal VDD is 0, and the potential of the first control signal P_FSC is 1. At this time, the path between the power supply terminal VDD, the switch module 140, and the pull-down module 150 is turned off. At the same time, the logic control module 160 can perform logical operations on the first control signal P_FSC and the first initial pull-down signal SLHN to generate the first pull-down signal SLHP; and perform logical operations on the first control signal P_FSC and the second initial pull-down signal OENH to generate the second pull-down signal OEH, thereby turning off the pull-down module 150. As a result, the path between the switch module 140 and ground VSS is disconnected, thus disconnecting the path between the output node PAD and ground VSS and preventing leakage.

[0085] In this embodiment, the potential of the first control signal P_FSC can characterize the current operating state of the fail-safe circuit. By using the first control signal P_FSC as the control signal for turning the pull-down module 150 on and off, the pull-down module 150 can only be turned off when the fail-safe circuit is determined to be in a fail-safe state based on the potential of the first control signal P_FSC. This can prevent the pull-down module 150 from being mistakenly turned on or off due to the incorrect input of the first pull-down signal SLHP and the second pull-down signal OEH, thereby improving the reliability of the fail-safe circuit.

[0086] In this embodiment, see Figure 7 The schematic diagram shown in the embodiment of the present invention illustrates the specific structure of another fail-safe circuit, as follows: Figure 7 As shown, the pull-down module 150 includes: a second NMOS transistor NM12 and a third NMOS transistor NM13, wherein:

[0087] The control terminal of the second NMOS transistor NM12 is adapted to input the first initial pull-down signal SLHN. The first terminal of the second NMOS transistor is connected to the first terminal of the switch module 140 (e.g., the first switch unit 141) and the third NMOS transistor NM13, respectively. The second terminal of the second NMOS transistor NM12 is connected to the third terminal and grounded to VSS.

[0088] The control terminal of the third NMOS transistor NM13 is adapted to input a second initial pull-down signal OENH. The second terminal and the third terminal of the third NMOS transistor NM13 are respectively connected to the switching module (e.g., the first switching unit 141) and grounded.

[0089] See next Figure 7 The logic control module 160 may include a first NOR gate NOR1 and a second NOR gate NOR2, wherein:

[0090] The first input terminal of the first NOR gate NOR1 is adapted to input the first initial pull-down signal SLHN, the second input terminal of the first NOR gate NOR1 is adapted to input the first control signal P_FSC, and the output terminal of the first NOR gate NOR1 is connected to the pull-down module 150 (e.g., the control terminal of the second NMOS transistor NM12).

[0091] The first input terminal of the second NOR gate NOR2 is adapted to input the second initial pull-down signal OENH, the second input terminal of the second NOR gate NOR2 is adapted to input the first control signal P_FSC, and the output terminal of the second NOR gate NOR2 is connected to the pull-down module 150 (e.g., the control terminal of the third NMOS transistor NM12).

[0092] Specifically, the potential of the first control signal P_FSC can characterize the current operating state of the fail-safe circuit. By using the first control signal P_FSC as the control signal for turning the pull-down module 150 on and off, the pull-down module 150 can be safely and reliably controlled to be erroneously turned on or off, thereby improving the reliability of the fail-safe circuit.

[0093] As a specific embodiment, if the voltage of the power supply terminal VDD is 1, the potential of the first control signal P_FSC is 0, which makes the potential of the first initial pull-down signal SLHN 0. Then, after passing through the first NOR gate NOR1, the potential of the first pull-down signal SLHP is 1. If the potential of the second initial pull-down signal OENH is 0, then after passing through the first NOR gate NOR1, the potential of the second pull-down signal OEH is 1, thereby making the pull-down module 150 in the on state.

[0094] As another specific embodiment, if the voltage of the power supply terminal VDD is 0, the potential of the first control signal P_FSC is 1, and the potential of the first initial pull-down signal SLHN is 0 or 1, then after passing through the first NOR gate NOR1, the potential of the first pull-down signal SLHP is 0; if the potential of the second initial pull-down signal OENH is 0 or 1, then after passing through the first NOR gate NOR1, the potential of the second pull-down signal OEH is 0, thereby causing the pull-down module 150 to be in the off state.

[0095] Therefore, the first initial pull-down signal SLHN and the second initial pull-down signal OENH can have different potentials based on the potential of the first control signal P_FSC, so as to realize the on / off state of the pull-down module 150.

[0096] It should be noted that, firstly, Figure 7 The illustrated structure of the logic control module 160 is for illustrative purposes only, indicating that logical operations can be performed on the first control signal P_FSC, the first initial pull-down signal SLHN, and the second initial pull-down signal OENH, and should not be construed as a limitation of the present invention. In some other embodiments, other types of logic operation devices can be selected based on the potentials of the first control signal P_FSC, the first initial pull-down signal SLHN, and the second initial pull-down signal OENH; secondly, the potentials of the first control signal P_FSC, the first initial pull-down signal SLHN, and the second initial pull-down signal OENH described in the above example are also for illustrative purposes, indicating that the on / off state of the pull-down module 150 can be changed by changing the potentials of the first control signal P_FSC, the first initial pull-down signal SLHN, and the second initial pull-down signal OENH.

[0097] In this embodiment, see Figure 8 The schematic diagram shown in this embodiment of the invention illustrates a specific structure of another fail-safe circuit, as follows: Figure 8 As shown, the gating module 130 may include: a transmission gate TG, which includes a seventh PMOS transistor PM17 and a fourth NMOS transistor NM14 connected in parallel, wherein:

[0098] The control terminal of the seventh PMOS transistor PM17 serves as the first control terminal of the gating module 130, and is used to receive the first control signal P_FSC; the control terminal of the fourth NMOS transistor NM14 serves as the second control terminal of the gating module 130, and is used to receive the second control signal P_FSCN.

[0099] Specifically, when the voltage at the power supply terminal VDD is 1, the potential of the first control signal P_FSC is 0, while the potential of the second control signal P_FSCN is 1. As a result, both the fourth NMOS transistor NM14 and the seventh PMOS transistor PM17 are turned on, so that the input signal IN can be transmitted to the switch module 140 to select the first switch branch SW1 and disconnect the second switch branch SW2.

[0100] When the voltage at the power supply terminal VDD is 0, the potential of the first control signal P_FSC is 1, while the potential of the second control signal P_FSCN is 0. As a result, the fourth NMOS transistor NM14 and the seventh PMOS transistor PM17 are both turned off, thereby enabling the second switch branch SW2 to be turned on and the first switch branch SW1 to be turned off, preventing backflow.

[0101] In short, the gating module 130 in this embodiment needs to satisfy the following: when the voltage of the power supply terminal VDD is 1, the gating module 130 is in a fully on state, and when the voltage of the power supply terminal VDD is 0, the gating module 130 is in a fully off state.

[0102] In this embodiment, by placing the gating module 130 in front, the waveform of the signal output to the second node PG is corrected by the switching module 140, which can improve the waveform quality of the second node PG.

[0103] For example, see Figure 9 The diagram shows the waveform changes of a critical node in a fail-safe circuit. Figure 10 The diagram shown is a waveform change diagram of a critical node in a fail-safe circuit according to an embodiment of the present invention, wherein... Figure 9 and Figure 10 The horizontal axis represents time t, in ns, and the vertical axis represents voltage, in V.

[0104] like Figure 9 As shown, the rising and falling edges of the waveform at critical nodes (e.g., PG) exhibit significant steps, which can cause signal distortion and aberration, thus affecting signal quality and reliability. Furthermore, the rise and fall speeds are relatively slow. (See also...) Figure 10 The waveform at the critical node PG has no obvious steps on both the rising and falling edges, which can improve the signal quality and reliability. Moreover, the rising and falling speeds are slower, resulting in higher waveform quality.

[0105] In this embodiment, combined with Figure 1 and Figure 5 The control module 120 may include: a first control signal generation unit 122 and a second control signal generation unit 123, wherein:

[0106] The second control signal generation unit 123 is coupled to the power supply terminal VDD, the output node PAD and the gating module 130 respectively, and is adapted to generate the second control signal P_FSCN according to the voltage of the power supply terminal VDD and the potential of the output node PAD;

[0107] The first control signal generation unit 122 is coupled to the power supply terminal VDD, the output node PAD, the second control signal generation unit 123 and the gating module 130 respectively, and is adapted to generate the first control signal P_FSC according to the voltage of the power supply terminal VDD, the potential of the output node PAD and the second control signal P_FSCN.

[0108] Specifically, when the voltage of the power supply terminal VDD is 1, under the action of the power supply terminal VDD and the output node PAD, the second control signal generation unit 123 can generate a second control signal P_FSCN with a potential of 1. Then, based on the voltage of the power supply terminal VDD, the potential of the output node PAD and the potential of the second control signal P_FSCN, the first control signal generation unit 122 can generate a first control signal P_FSC with a potential of 0.

[0109] When the voltage at the power supply terminal VDD is 0, under the action of the power supply terminal VDD and the output node PAD, the second control signal generation unit 123 can generate a second control signal P_FSCN with a potential of 0. Then, based on the voltage at the power supply terminal VDD, the potential of the output node PAD, and the potential of the second control signal P_FSCN, the first control signal generation unit 122 can generate a first control signal P_FSC with a potential of 1.

[0110] In other words, when the fail-safe circuit is in either state (normal operation state and power-off state), the potentials of the first control signal P_FSC and the second control signal P_FSCN are always opposite, which can quickly turn the selection module 130 on or off.

[0111] It should be noted that the above example illustrates the generation process of the first control signal P_FSC and the second control signal P_FSCN by assuming that the potential of the second control signal P_FSCN is the same as the voltage of the power supply terminal VDD. In some other embodiments, the potential of the first control signal P_FSC can be the same as the voltage of the power supply terminal VDD. This invention does not limit this, as long as the potentials of the first control signal P_FSC and the second control signal P_FSCN are opposite.

[0112] In this embodiment, the first control signal generation unit 122 may include: an eighth PMOS transistor PM18 and a fifth NMOS transistor NM15, wherein:

[0113] The control terminal of the eighth PMOS transistor PM18 is connected to the power supply terminal VDD, the first terminal of the eighth PMOS transistor PM18 is connected to the output node PAD, and the second terminal of the eighth PMOS transistor PM18 is connected to the first terminal of the fifth NMOS transistor NM15 and the gating module 130, respectively.

[0114] The control terminal of the fifth NMOS transistor NM15 is connected to the second control signal generation unit 123, and the second terminal of the fifth NMOS transistor NM15 is connected to the third terminal and grounded to VSS.

[0115] In this embodiment, the second control signal generation unit 123 may include: a ninth PMOS transistor PM19 and a sixth NMOS transistor NM16, wherein:

[0116] The control terminal of the ninth PMOS transistor PM19 is connected to the control terminal of the sixth NMOS transistor NM16 and the output node PAD. The first terminal of the ninth PMOS transistor PM19 is connected to the power supply terminal VDD. The second terminal of the ninth PMOS transistor PM19 is connected to the first terminal of the sixth NMOS transistor NM16 and the gating module 130, respectively.

[0117] The second and third terminals of the sixth NMOS transistor are connected and grounded to VSS.

[0118] In this embodiment, as Figure 5 As shown, when the voltage of the power supply terminal VDD is 1, the voltage of the power supply terminal VDD is greater than the potential of the output node PAD, so the ninth PMOS transistor PM19 is turned on. At this time, the power supply terminal VDD is directly connected to one end of the gating module 130, so the potential of the second control signal P_SFCN is 1.

[0119] Furthermore, the ninth PMOS transistor PM19 is turned on, which in turn turns on the fifth NMOS transistor NM15, while the eighth PMOS transistor PM18 is turned off. One end of the selection module 130 is grounded to VSS, so that the potential of the first control signal P_SFC is 0.

[0120] When the voltage at the power supply terminal VDD is 0, the voltage at the power supply terminal VDD is less than the potential of the output node PAD. The ninth PMOS transistor PM19 is turned off, which causes the fifth NMOS transistor NM15 to be turned off, while the eighth PMOS transistor PM18 is turned on. One end of the selection module 130 is connected to the voltage terminal VDD, so the potential of the first control signal P_SFC is 1.

[0121] Furthermore, the sixth NMOS transistor NM16 is turned on, and one end of the gating module 130 is grounded to VSS, thereby the potential of the second control signal P_SFCN is 0.

[0122] That is, by setting up a first control signal generation unit 122 and a second control signal generation unit 123 with the above-mentioned connection relationship and structure, the first control signal P_SFC and the second control signal P_SFCN can have completely opposite potentials by selecting different paths according to the relationship between the voltage of the power supply terminal VDD and the potential of the output node PAD.

[0123] In this embodiment, see next. Figure 5 The control module 120 further includes a potential selection unit 124, which is coupled to the power supply terminal VDD, the output node PAD, and the second control signal generation unit 123, respectively. It is adapted to select the path between the first control unit 122 and the power supply terminal VDD, and the path between the second control unit 123 and the output node PAD, according to the potential of the output node and the voltage of the power supply terminal; or, select the path between the second control unit 123 and the power supply terminal VDD, and the path between the first control unit 122 and the output node PAD.

[0124] In other words, when the fail-safe circuit is in different states, the relative potential between the power supply terminal VDD and the output node PAD is different. By setting the potential selection unit 124, a first control signal and a second control signal with different potentials can be output according to the relative potential between the power supply terminal VDD and the output node PAD.

[0125] As a specific embodiment, when the fail-safe circuit is in normal state, the voltage of the power supply terminal VDD is greater than the potential of the output node PAD. Through the potential selection unit 124, the path between the second control unit 123 and the power supply terminal VDD is turned on, and the potential of the second control signal P_FSCN is 1. Meanwhile, the path between the first control unit 122 and the output node PAD is turned on, and the potential of the first control signal P_FSC is 0.

[0126] When the fail-safe circuit is in a fail-safe state, the voltage at the power supply terminal VDD is less than the potential of the output node PAD (at this time, the potential of the output node PAD is the potential of the external device). Through the potential selection unit 124, the path between the first control unit 122 and the power supply terminal VDD is turned on, and the potential of the first control signal P_FSC is 1. Meanwhile, the path between the second control unit 123 and the output node PAD is turned on, and the potential of the second control signal P_FSCN is 0.

[0127] In this embodiment, the potential selection unit 124 may include: a tenth PMOS transistor PM20, a seventh NMOS transistor NM17, an eighth NMOS transistor NM18, and a ninth NMOS transistor NM19, wherein:

[0128] The control terminal of the tenth PMOS transistor PM20 is connected to the power supply terminal VDD, the first terminal of the tenth PMOS transistor PM20 is connected to the output node PAD, and the second terminal of the tenth PMOS transistor PM20 is connected to the second control signal generation unit 123, the control terminal NM17 of the seventh NMOS transistor, the control terminal of the eighth NMOS transistor NM18, the control terminal of the ninth NMOS transistor, and the first terminal of the seventh NMOS transistor NM17, respectively.

[0129] The second terminal of the seventh NMOS transistor NM17 is connected to the first terminal of the eighth NMOS transistor NM18, and the third terminal of the seventh NMOS transistor NM17 is connected to the third terminal of the eighth NMOS transistor NM18, the third terminal and the second terminal of the ninth NMOS transistor NM19, respectively, and grounded.

[0130] The second terminal of the eighth NMOS transistor NM18 is connected to the first terminal of the ninth NMOS transistor NM19.

[0131] In this embodiment, by Figure 5 It can be seen that when the voltage of the power supply terminal VDD is greater than the potential of the output node PAD, the tenth PMOS transistor PM20 is turned off; while when the voltage of the power supply terminal VDD is less than the potential of the output node PAD, the tenth PMOS transistor PM20 is turned on. Therefore, the state of the fail-safe circuit can be determined by the switching state of the tenth PMOS transistor PM20.

[0132] In this embodiment, the input module 110 may include: an enable control terminal OEN, an input node I, and a first logic unit 111, wherein:

[0133] The enable control terminal OEN is coupled to the first logic unit 111 and is adapted to enable or disable the path between the input node I and the output node PAD based on the input enable signal.

[0134] The input node I is coupled to the first logic unit 111 and is adapted to provide an initial input signal to the first logic unit 111;

[0135] The first logic unit 111 is coupled to the gating module 130 and is adapted to perform logical operations on the initial input signal and the enable signal to output the input signal.

[0136] Specifically, when the enable signal's potential is 0, the enable control terminal OEN is enabled, allowing the path between input node I and output node PAD to be selected; when the enable signal's potential is 1, the enable control terminal OEN is enabled, disconnecting the path between input node I and output node PAD. Therefore, the connection or disconnection of the path between input node I and output node PAD can be controlled by controlling the potential of the input enable signal.

[0137] It is understood that the enable state of the enable control terminal OEN in the above example is only for illustrative purposes. It is used to indicate that by changing the potential of the enable signal input to the enable control terminal OEN, the on / off state of the path between the input node I and the output node PAD can be controlled. It should not be construed as a limitation of the present invention.

[0138] Input node I can provide the required electrical signals and / or clock signals to external devices.

[0139] The first logic unit 111 can perform corresponding logic operations on the initial input signal and the enable signal to provide the gating module 130 with corresponding electrical signals and / or clock signals.

[0140] In this embodiment, the first logic unit 111 may include: a first inverter P11, a NAND gate NAND1, and a second inverter P12, wherein:

[0141] The input terminal of the first inverter P11 is connected to the enable control terminal OEN, the output terminal of the first inverter P11 is connected to the first input terminal of the NAND gate NAND1, the second input terminal of the NAND gate NAND1 is connected to the input node I, the output terminal of the NAND gate NAND1 is connected to the input terminal of the second inverter P12, and the output terminal of the second inverter P12 is connected to the gating module 130.

[0142] That is, the first logic unit 111 first inverts the enable signal through the first inverter P11, then performs a NAND operation on the inverted enable signal and the initial input signal through the NAND gate NAND1, and finally performs another inversion operation through the second inverter P12 to output the input signal IN to the gating module 130.

[0143] It should be noted that, Figure 11 The structure of the first logic unit 111 shown is for illustrative purposes only. Appropriate logic devices can be flexibly selected according to the actual application scenario so that the input signal IN output by the first logic unit 111 can meet the requirements.

[0144] In this embodiment, considering that when the fail-safe circuit is in a fail-safe state, the output node PAD is connected to external devices and the potential of the output node PAD is high, the path between the output node PAD and ground VSS can be disconnected to further reduce the occurrence of backflow.

[0145] See Figure 11 The fail-safe circuit further includes a protection module 170, which is coupled to the enable control terminal OEN, the input node I, and the output node PAD, respectively. It is adapted to disconnect or enable the path between the output node PAD and ground VSS according to the initial input signal and the enable signal when the gating module 130 is enabled; and to disconnect the path between the output node PAD and ground VSS when the gating module 130 is turned off.

[0146] In this embodiment, the protection module 170 may include: a second logic operation unit 171 and a third switching unit 172, wherein:

[0147] The second logic operation unit 171 is coupled to the enable control terminal OEN, the input node I and the third switch unit 172 respectively, and is adapted to perform logic operations on the initial input signal and the enable signal to generate a shutdown signal;

[0148] The third switching unit 172 is coupled to the output node PAD and is adapted to be in a selected state or a disconnected state according to the off signal when the selection module 130 is selected; and to be in a disconnected state when the selection module 130 is turned off.

[0149] Specifically, by performing logical operations on the initial input signal and the enable signal, the second logic operation unit 171 can output a shutdown signal, thereby enabling the third switch unit 172 to be in an open or closed state when the fault-safe circuit is in normal working condition; while when the gating module 130 is turned off, it indicates that the fault-safe circuit is in a fault-safe state, the third switch unit 172 is connected to the output node, and the gating module 130 is in an open state, thus disconnecting the path between the output node PAD and ground, further reducing the occurrence of backflow phenomenon.

[0150] In this embodiment, the second logic operation unit 171 may include: a third NOR gate NOR3, a third inverter P13, and a fourth inverter P14, wherein:

[0151] The first input terminal of the third NOR gate NOR3 is connected to the enable control terminal OEN, the second input terminal of the third NOR gate NOR3 is connected to the input node I, the output terminal of the third NOR gate NOR3 is connected to the input terminal of the third inverter P13, the output terminal of the third inverter P13 is connected to the input terminal of the fourth inverter P14, and the output terminal of the fourth inverter P14 is connected to the third switching unit 172.

[0152] That is, the second logic operation unit 171 first performs a NOR operation on the enable signal and the initial input signal through the third NOR gate NOR3, and then performs two inversion operations through the third inverter P13 and the fourth inverter P14 in sequence, thereby outputting a turn-off signal to make the third switch unit 172 in the off state.

[0153] In one specific embodiment, if the voltage at the power supply terminal VDD is 1, the potential at the enable control terminal OEN is 1, and the potential at the input node is 1 or 0, then after passing through the third NOR gate NOR3, the potential of the signal output to the third inverter P13 is 0. This, in turn, passes through the third inverter P13 and the fourth inverter P14 sequentially, making the potential of the turn-off signal 0, and the third switching unit 172 is in the off state. If the voltage at the power supply terminal VDD is 1, the potential at the enable control terminal OEN is 0, and the potential at the input node is 0, then after passing through the third NOR gate NOR3, the potential of the signal output to the third inverter P13 is 1. This, in turn, passes through the third inverter P13 and the fourth inverter P14 sequentially, making the potential of the turn-off signal 1, and the third switching unit 172 is in the on state.

[0154] That is, when the voltage of the power supply terminal VDD is 1, it means that the fault-safe circuit is in normal condition. By configuring the potential of the enable control terminal OEN and the input node, the third switch unit 172 can be in the on state or in the off state.

[0155] If the voltage at the power supply terminal VDD is 0, it indicates that the fault-safe circuit is in a fault-safe state. Therefore, the third switch unit 172 must be in the open state, thereby disconnecting the path between the output node PAD and ground VSS.

[0156] It should be noted that, Figure 11 The structure of the second logic operation unit 171 shown is for illustrative purposes only. The appropriate logic operation device can be flexibly selected according to the actual application scenario so that the output of the second logic operation unit 171 causes the third switch unit 172 to be in the off state.

[0157] In this embodiment, the third switching unit 172 includes: a tenth NMOS transistor NM20, the control terminal of the tenth NMOS transistor NM20 is connected to the second logic operation unit 171, the first terminal of the tenth NMOS transistor is connected to the output node PAD, and the second and third terminals of the tenth NMOS transistor NM20 are connected and grounded to VSS.

[0158] In summary, by employing the fail-safe circuit in the above embodiments, on the one hand, by placing the gating module 130 at the front, the gating module 130 can be quickly turned off when the fail-safe circuit is in a fail-safe state, thereby rapidly raising the potential of the second switching branch SW2 to the potential of the output node, reducing the response time of the fail-safe circuit in the power-down state, and preventing electrical signals generated by external devices from flowing back into the system circuit through the output node; on the other hand, by placing the gating module 130 at the front, the driving capability requirement of the switching module 140 can be alleviated, thus allowing the use of transistors with smaller sizes to reduce the layout size, reduce overall power consumption, and improve the output waveform quality, thereby improving the driving capability of the output node PAD terminal.

[0159] Furthermore, by coupling the switch module 140 to the control module 120, and by adding the pull-down module 150, the logic operation module 160, and the protection module 170, the backflow phenomenon in the fail-safe circuit under fail-safe conditions can be further reduced.

[0160] It should be noted that in this embodiment, the control terminal of the transistor can refer to the gate of the transistor, the first terminal of the transistor can refer to the source of the transistor, the second terminal of the transistor can refer to the drain of the transistor, and the second terminal of the transistor can refer to the substrate of the transistor.

[0161] In some other embodiments, the control terminal of the transistor may refer to the gate of the transistor, the first terminal of the transistor may refer to the drain of the transistor, the second terminal of the transistor may refer to the source of the transistor, and the third terminal of the transistor may refer to the substrate of the transistor.

[0162] This embodiment also provides a system-on-a-chip, which may include the fail-safe circuit described in any of the foregoing embodiments.

[0163] While this embodiment has been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A fail-safe circuit, characterized in that, include: The system consists of an input module, a control module, a gating module, a switch module, and an output node, among which: The control module is coupled to the power supply terminal, the gating module, the switching module and the output node respectively, and is adapted to generate a first control signal and a second control signal according to the voltage of the power supply terminal and the potential of the output node, wherein the potentials of the first control signal and the second control signal are different. The gating module is coupled to the switch module and the input module respectively, and is adapted to be selected or turned off according to the first control signal and the second control signal, as well as the input signal provided by the input module; The switching module is coupled to the power supply terminal and the output node, respectively. The switching module has a first switching branch and a second switching branch. The switching module is adapted to select the first switching branch and turn off the second switching branch according to the voltage of the power supply terminal when the gating module is selected, so that the potential of the output node is the potential of the input signal. It is also adapted to select the second switching branch and turn off the first switching branch according to the voltage of the power supply terminal when the gating module is turned off, so that the potential of the second switching branch is the potential of the output node.

2. The fail-safe circuit according to claim 1, characterized in that, The switching module includes: a first switching unit, a second switching unit, and a pull-up unit, wherein: The first switching unit is located on the first switching branch and is coupled to the pull-up unit, the gating module, the power supply terminal and the second switching unit respectively. The first switching unit is adapted to generate a first driving signal when the gating module is selected according to the voltage of the power supply terminal, and is adapted to generate a second driving signal when the gating module is turned off according to the voltage of the power supply terminal. The second switching unit is located on the first switching branch and is coupled to the power supply terminal and the output node respectively. The second switching unit is adapted to select the first switching branch according to the voltage of the power supply terminal and the first driving signal, and is adapted to turn off the first switching branch according to the voltage of the power supply terminal and the second driving signal. The pull-up unit is located on the second switch branch and is coupled to the gating module, the power supply terminal and the output node respectively. The pull-up unit is adapted to turn off the second switch branch according to the voltage of the power supply terminal when the gating module is selected, and is adapted to turn on the second switch branch according to the voltage of the power supply terminal when the gating module is turned off.

3. The fail-safe circuit according to claim 2, characterized in that, The first switching unit includes: a first NMOS transistor and a first PMOS transistor, wherein: The control terminal of the first PMOS transistor and the control terminal of the first NMOS transistor are both coupled to the gating module and the pull-up unit, respectively. The first terminal of the first PMOS transistor is connected to the power supply terminal, and the second terminal of the first PMOS transistor is connected to the first terminal of the first NMOS transistor and the second switching unit, respectively. The second terminal of the first NMOS transistor is grounded.

4. The fail-safe circuit according to claim 2, characterized in that, The second switching unit includes: a second PMOS transistor, the control terminal of the second PMOS transistor being connected to the first switching unit, the first terminal of the second PMOS transistor being connected to the power supply terminal, and the second terminal of the second PMOS transistor being connected to the output node.

5. The fail-safe circuit according to claim 4, characterized in that, The control module includes: a well potential generation unit, which is coupled to the substrate of the second PMOS transistor, the power supply terminal, and the output node, respectively. When the gating module is selected, the well potential generation unit is configured to conduct a path between the substrate of the second PMOS transistor and the power supply terminal, such that the potential of the substrate of the second PMOS transistor is equal to the voltage of the power supply terminal; and when the gating module is turned off, the well potential generation unit is configured to conduct a path between the substrate of the second PMOS transistor and the output node, such that the potential of the substrate of the second PMOS transistor is equal to the potential of the output node.

6. The fail-safe circuit according to claim 5, characterized in that, The well potential generation unit includes: a third PMOS transistor and a fourth PMOS transistor, wherein: The control terminal of the third PMOS transistor is connected to the output node, the first terminal of the third PMOS transistor is connected to the power supply terminal and the control terminal of the fourth PMOS transistor respectively, and the second terminal of the third PMOS transistor is connected to the third terminal of the third PMOS transistor, the second terminal and the third terminal of the fourth PMOS transistor, and the substrate of the second PMOS transistor respectively. The first terminal of the fourth PMOS transistor is connected to the output node.

7. The fail-safe circuit according to claim 2, characterized in that, The first switching unit is coupled to the gating module at the first node and to the second switching unit at the second node; The second switch branch includes: a first sub-branch and a second sub-branch, wherein a first end of the first sub-branch is coupled to the first node, and a second end of the first sub-branch is coupled to the output node; a first end of the second sub-branch is coupled to the second node, and a second end of the second sub-branch is coupled to the output node. The pull-up unit includes: a fifth PMOS transistor located on the first sub-branch and a sixth PMOS transistor located on the second sub-branch, wherein: The control terminal of the fifth PMOS transistor is connected to the power supply terminal, the first terminal of the fifth PMOS transistor serves as the first terminal of the first sub-branch, and the second terminal of the fifth PMOS transistor serves as the second terminal of the first sub-branch. The control terminal of the sixth PMOS transistor is connected to the power supply terminal. The first terminal of the sixth PMOS transistor serves as the first terminal of the second sub-branch, and the second terminal of the sixth PMOS transistor serves as the second terminal of the second sub-branch.

8. The fail-safe circuit according to claim 1, characterized in that, The fail-safe circuit further includes: a pull-down module coupled to the switch module, adapted to, in response to a first pull-down signal and a second pull-down signal, disconnect the path between the switch module and ground when the gating module is turned off, and enable the path between the switch module and ground when the gating module is turned on.

9. The fail-safe circuit according to claim 8, characterized in that, The pull-down module includes: a second NMOS transistor and a third NMOS transistor, wherein: The control terminal of the second NMOS transistor is adapted to input a first pull-down signal. The first terminal of the second NMOS transistor is connected to the first terminal of the switching module and the first terminal of the third NMOS transistor, respectively. The second terminal of the second NMOS transistor is connected to the third terminal and grounded. The control terminal of the third NMOS transistor is adapted to input a second pull-down signal. The second terminal of the third NMOS transistor is connected to the third terminal and the switching module respectively, and is grounded.

10. The fail-safe circuit according to claim 8, characterized in that, The fail-safe circuit also includes: A logic control module, coupled to the control module and the pull-down module respectively, is adapted to perform logical operations on a first initial pull-down signal and a first control signal to generate a first pull-down signal; and to perform logical operations on a second initial pull-down signal and the first control signal to generate a second pull-down signal.

11. The fail-safe circuit according to claim 10, characterized in that, The logic control module includes a first NOR gate and a second NOR gate, wherein: The first input terminal of the first NOR gate is adapted to input the first initial pull-down signal, the second input terminal of the first NOR gate is adapted to input the first control signal, and the output terminal of the first NOR gate is connected to the pull-down module. The first input terminal of the second NOR gate is adapted to input the second initial pull-down signal, the second input terminal of the second NOR gate is adapted to input the first control signal, and the output terminal of the second NOR gate is connected to the pull-down module.

12. The fail-safe circuit according to claim 1, characterized in that, The gating module includes a transmission gate, which comprises a seventh PMOS transistor and a fourth NMOS transistor connected in parallel, wherein: The control terminal of the seventh PMOS transistor serves as the first control terminal of the gating module, and is used to receive the first control signal; the control terminal of the fourth NMOS transistor serves as the second control terminal of the gating module, and is used to receive the second control signal.

13. The fail-safe circuit according to claim 1, characterized in that, The control module includes: a first control signal generation unit and a second control signal generation unit, wherein: The second control signal generation unit is coupled to the power supply terminal, the output node and the gating module respectively, and is adapted to generate the second control signal according to the voltage of the power supply terminal and the potential of the output node; The first control signal generation unit is coupled to the power supply terminal, the output node, the second control signal generation unit, and the gating module, respectively, and is adapted to generate the first control signal based on the voltage of the power supply terminal, the potential of the output node, and the second control signal.

14. The fail-safe circuit according to claim 13, characterized in that, The first control signal generation unit includes: an eighth PMOS transistor and a fifth NMOS transistor, wherein: The control terminal of the eighth PMOS transistor is connected to the power supply terminal, the first terminal of the eighth PMOS transistor is connected to the output node, and the second terminal of the eighth PMOS transistor is connected to the first terminal of the fifth NMOS transistor and the gating module, respectively. The control terminal of the fifth NMOS transistor is connected to the second control signal generation unit, and the second terminal of the fifth NMOS transistor is connected to the third terminal and grounded.

15. The fail-safe circuit according to claim 13, characterized in that, The first control signal generation unit includes: a ninth PMOS transistor and a sixth NMOS transistor, wherein: The control terminal of the ninth PMOS transistor is connected to the control terminal of the sixth NMOS transistor and the output node; the first terminal of the ninth PMOS transistor is connected to the power supply terminal; and the second terminal of the ninth PMOS transistor is connected to the first terminal of the sixth NMOS transistor and the gating module, respectively. The second and third terminals of the sixth NMOS transistor are connected and grounded.

16. The fail-safe circuit according to claim 13, characterized in that, The control module further includes a potential selection unit, which is coupled to the power supply terminal, the output node, and the second control signal generation unit, respectively. It is adapted to select the path between the first control unit and the power supply terminal, and the path between the second control unit and the output node, based on the potential of the output node and the voltage of the power supply terminal; or to select the path between the second control unit and the power supply terminal, and the path between the first control unit and the output node.

17. The fail-safe circuit according to claim 16, characterized in that, The potential selection unit includes: a tenth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor, wherein: The control terminal of the tenth PMOS transistor is connected to the power supply terminal, the first terminal of the tenth PMOS transistor is connected to the output node, and the second terminal of the tenth PMOS transistor is connected to the second control signal generation unit, the control terminal of the seventh NMOS transistor, the control terminal of the eighth NMOS transistor, the control terminal of the ninth NMOS transistor, and the first terminal of the seventh NMOS transistor, respectively. The second terminal of the seventh NMOS transistor is connected to the first terminal of the eighth NMOS transistor, and the third terminal of the seventh NMOS transistor is connected to the third terminal of the eighth NMOS transistor, the third terminal of the ninth NMOS transistor, and the second terminal, respectively, and is grounded. The second terminal of the eighth NMOS transistor is connected to the first terminal of the ninth NMOS transistor.

18. The fail-safe circuit according to claim 1, characterized in that, The input module includes: an enable control terminal, an input node, and a first logic unit, wherein: The enable control terminal is coupled to the first logic unit and is adapted to enable or disable the path between the input node and the output node based on the input enable signal. The input node is coupled to the first logic unit and is adapted to provide an initial input signal to the first logic unit; The first logic unit, coupled to the gating module, is adapted to perform logical operations on the initial input signal and the enable signal to output the input signal.

19. The fail-safe circuit according to claim 18, characterized in that, The first logic unit includes: a first inverter, a NAND gate, and a second inverter, wherein: The input terminal of the first inverter is connected to the enable control terminal, the output terminal of the first inverter is connected to the first input terminal of the NAND gate, the second input terminal of the NAND gate is connected to the input node, the output terminal of the NAND gate is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the gating module.

20. The fail-safe circuit according to claim 18, characterized in that, The fail-safe circuit further includes: a protection module, coupled to the enable control terminal, the input node and the output node respectively, adapted to disconnect or enable the path between the output node and ground according to the initial input signal and the enable signal when the gating module is enabled; and to disconnect the path between the output node and ground when the gating module is turned off.

21. The fail-safe circuit according to claim 20, characterized in that, The protection module includes: a second logic operation unit and a third switching unit, wherein: The second logic operation unit is coupled to the enable control terminal, the input node and the third switch unit respectively, and is adapted to perform logic operations on the initial input signal and the enable signal to generate a shutdown signal; The third switching unit, coupled to the output node, is adapted to be in a selected state or a disconnected state according to the shutdown signal when the selection module is selected; and to be in a disconnected state when the selection module is shut down.

22. The fail-safe circuit according to claim 21, characterized in that, The second logic operation unit includes: a third NOR gate, a third inverter, and a fourth inverter, wherein: The first input terminal of the third NOR gate is connected to the enable control terminal, the second input terminal of the third NOR gate is connected to the input node, the output terminal of the third NOR gate is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the third switching unit.

23. The fail-safe circuit according to claim 21, characterized in that, The third switching unit includes a tenth NMOS transistor, the control terminal of which is connected to the second logic operation unit, the first terminal of which is connected to the output node, and the second and third terminals of which are connected and grounded.

24. A system-on-a-chip, characterized in that, include: The fail-safe circuit as described in any one of claims 1 to 23.

Images