A column-level latch module, an analog-to-digital converter, and an image sensor

Abstract

The application discloses a column-level latch module, an analog-to-digital converter and an image sensor, and belongs to the field of integrated circuit design. A first latch of a first stage, a second and third latch of a second stage and an output latch unit of a third stage are sequentially arranged. The first latch can sequentially latch four level quantization values, the second latch can latch a low conversion gain reset level quantization value from the first stage and timely transmit the low conversion gain reset level quantization value to the third stage, and the third latch can time-sharing transmit the other three level quantization values in the first latch to the third stage. Finally, the third stage can time-sharing output a high conversion gain reset level quantization value and a signal level quantization value and a low conversion gain reset level quantization value and a signal level quantization value. The column-level latch module can be constructed by a small number of latch combinations, the time-sharing output of a pair of level quantization values of high and low conversion gains can be realized, and the column-level latch module has a small circuit area and a low cost.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to a column-level latch module, an analog-to-digital converter, and an image sensor. Background Technology

[0002] CMOS Image Sensor (CIS) has been widely used in many fields. The combination of pixel units based on DCG (Dual Conversion Gain) technology and analog-to-digital converters is a mainstream architecture for high dynamic range CIS. The analog-to-digital converter needs to quantize multiple analog voltages output by the pixel circuit in sequence, and then process them through CDS (Correlated Double Sampling) to form two noise-suppressed digital results with high gain and low gain, so as to finally obtain a high dynamic range image. However, the analog-to-digital converters in related technologies are not mature enough, and the global counter circuit in the analog-to-digital converter usually has the problems of many components and large circuit area.

[0003] Therefore, how to provide a solution to the above-mentioned technical problems is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a column-level latch module, an analog-to-digital converter, and an image sensor. This invention sequentially comprises a first-stage latch, second and third-stage latches, and a third-stage output latch unit. The first latch can sequentially latch four level quantization values. The second latch can latch a low-conversion-gain reset level quantization value from the first stage and transmit it to the third stage for output at an appropriate time. The third latch can transmit the high-conversion-gain reset level quantization value, the high-conversion-gain signal level quantization value, and the low-conversion-gain signal level quantization value from the first latch to the third stage in a time-division manner. Ultimately, the third stage can output "high-conversion-gain reset level quantization value and signal level quantization value" and "low-conversion-gain reset level quantization value and signal level quantization value" in a time-division manner. A column-level latch module can be constructed using a small number of latch combinations, achieving time-division output of a pair of level quantization values ​​for both high and low conversion gains, with a small circuit area and low cost.

[0005] To address the aforementioned technical problems, this invention provides a column-level latch module applied to an analog-to-digital converter in an image sensor. The image sensor employs a dual-conversion-gain mode, and after a single exposure, the pixel circuit of the image sensor sequentially outputs a low conversion gain reset level, a high conversion gain reset level, a high conversion gain signal level, and a low conversion gain signal level. The column-level latch module includes:

[0006] The first latch is used in conjunction with the main counter and column comparator module of the analog-to-digital converter to sequentially latch: the quantized value of the low conversion gain reset level, the quantized value of the high conversion gain reset level, the quantized value of the high conversion gain signal level, and the quantized value of the low conversion gain signal level.

[0007] The second latch is used to latch the low conversion gain reset level quantization value in the first latch;

[0008] The third latch latches the high conversion gain reset level quantized value, the high conversion gain signal level quantized value, and the low conversion gain signal level quantized value from the first latch.

[0009] The output latch unit is used to latch the high conversion gain reset level quantized value and the high conversion gain signal level quantized value from the third latch and output them in parallel; it also latches the low conversion gain reset level quantized value from the second latch and the low conversion gain signal level quantized value from the third latch and outputs them in parallel.

[0010] On the other hand, the output latch unit includes:

[0011] The fourth latch, whose output is connected to the first data transmission channel via a column selector switch, is used to latch the low conversion gain reset level quantization value in the second latch, and also to latch one of the high conversion gain reset level quantization value and the high conversion gain signal level quantization value in the third latch.

[0012] The fifth latch, whose output is connected to the second data transmission channel via a column selector switch, is used to latch the low conversion gain signal level quantization value in the third latch, and also to latch the other of the high conversion gain reset level quantization value and the high conversion gain signal level quantization value in the third latch.

[0013] The column selection switch is used to switch on and off under the control of the column selection signal of the image sensor.

[0014] On the other hand, at least one of the first latch, the second latch, the third latch, the fourth latch, and the fifth latch has a differential clock terminal and an input terminal.

[0015] On the other hand, the fourth latch includes a first inverter, a second inverter, a first input switch, a second input switch, and a sampling switch;

[0016] The first terminal of the first input switch is connected to the output terminal of the second latch, the first terminal of the second input switch is connected to the output terminal of the third latch, the input terminal of the first inverter is connected to the second terminal of the first input switch, the second terminal of the second input switch and the first terminal of the sampling switch, respectively, the second terminal of the sampling switch is connected to the output terminal of the second inverter, and the output terminal of the first inverter and the input terminal of the second inverter together serve as the inverted output terminal of the fourth latch.

[0017] On the other hand, the control signal of the sampling switch is obtained by performing a OR NOT operation on the control signal of the first input switch and the control signal of the second input switch.

[0018] On the other hand, the column-level latch module also includes:

[0019] The input terminal is connected to the output terminal of the column-level comparator module in the same column of the analog-to-digital converter, and the output terminal is connected to the clock terminal of the first latch. The pulse generator is used to convert the step signal output by the column-level comparator module into a pulse signal.

[0020] On the other hand, the pulse generator includes:

[0021] An initial sampling module, whose input is connected to the output of the column-level comparator module in the same column as the analog-to-digital converter, is used to sample the output signal of the column-level comparator module under the control of a clock signal.

[0022] The phase alignment module, whose input is connected to the output of the initial sampling module, is used to sample the sampling signal of the initial sampling module so as to lock the flip event of the column comparator to the stable phase of the clock signal, thereby achieving phase alignment between the sampled signal and the clock signal.

[0023] The input terminal is connected to the output terminal of the phase alignment module, and the output terminal is connected to the clock terminal of the first latch. The pulse generation module is used to generate a single-cycle pulse signal based on the phase-aligned sampled signal.

[0024] On the other hand, the initial sampling module is a first D flip-flop; the phase alignment module is a second D flip-flop;

[0025] The input of the first D flip-flop is connected to the output of the column comparator module in the same column of the analog-to-digital converter. The inverted output of the first D flip-flop is connected to the input of the second D flip-flop. The inverted output of the second D flip-flop is connected to the input of the pulse generation module.

[0026] The pulse generation module includes:

[0027] The third D flip-flop, whose input terminal and the first input terminal of the logic NOR gate are used together as the input terminal of the pulse generation module, is used to sample the output signal of the phase alignment module so as to delay the output signal of the phase alignment module;

[0028] The logic NOR gate, whose second input is connected to the output of the third D flip-flop, is used to perform NOR logic operation on the output signal of the phase alignment module and the output signal of the third D flip-flop, so as to convert the step signal output by the column comparator module into a pulse signal.

[0029] To address the aforementioned technical problems, the present invention also provides an analog-to-digital converter, including a master counter, multiple column-level comparator modules, and multiple column-level latch modules as described above;

[0030] The main counter is used to count the ramp signals corresponding to each level output by the pixel circuit of the image sensor;

[0031] The column-level comparator module is used to flip its own output when the level value output by the pixel circuit of the corresponding pixel column is equal to the level value of the ramp signal, so that the column-level latch module latches the current count value of the main counter.

[0032] To address the aforementioned technical problems, the present invention also provides an image sensor, including a pixel circuit and an analog-to-digital converter as described above connected to the pixel circuit.

[0033] Beneficial Effects: This invention provides a column-level latch module. Considering that by combining latches in series, the output latch unit connected to the data transmission channel can output a pair of level quantized values ​​for high and low conversion gains in a time-division manner, thereby avoiding the need for a multiplexer, this invention sequentially sets up a first latch in the first stage, second and third latches in the second stage, and an output latch unit in the third stage. The first latch can sequentially latch four level quantized values, while the second latch can latch the low conversion gain reset level quantized value from the first stage and transmit it to the third stage for output at an appropriate time. The third latch can transmit the high conversion gain reset level quantized value, the high conversion gain signal level quantized value, and the low conversion gain signal level quantized value from the first latch to the third stage in a time-division manner. Ultimately, the third stage can output "the high conversion gain reset level quantized value and the signal level quantized value" and "the low conversion gain reset level quantized value and the signal level quantized value" in a time-division manner. A column-level latch module can be constructed with a small number of latches, and the time-division output of a pair of level quantized values ​​for high and low conversion gains can be achieved, with a small circuit area and low cost.

[0034] The present invention also provides an analog-to-digital converter and an image sensor, which have the same beneficial effects as the above-mentioned multi-level latch module. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the relevant technologies and the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A schematic diagram of the structure of the first column-level latch module provided by the present invention;

[0037] Figure 2 A schematic diagram of the pixel circuit for dual-conversion gain technology;

[0038] Figure 3 The timing diagram for the pixel circuitry of the dual-conversion gain technology;

[0039] Figure 4 A schematic diagram of the structure of the first analog-to-digital converter provided by the present invention;

[0040] Figure 5 This is a schematic diagram of the structure of the second analog-to-digital converter provided by the present invention;

[0041] Figure 6 This is a schematic diagram of the structure of the second column-level latch module provided by the present invention;

[0042] Figure 7 This is a schematic diagram of the structure of the third-level latch module provided by the present invention;

[0043] Figure 8 Here are schematic diagrams of the two latches provided by the present invention;

[0044] Figure 9 A schematic diagram of a fourth latch provided by the present invention;

[0045] Figure 10 A waveform diagram of the control signal for the fourth latch provided by the present invention;

[0046] Figure 11 A schematic diagram of a pulse generator provided by the present invention;

[0047] Figure 12 A timing diagram of the column-level latch module in an analog-to-digital converter provided by the present invention;

[0048] Figure 13 The timing diagram of the column-level latch module provided by the present invention under linear readout timing;

[0049] Figure 14The timing diagram for the column-level latch module provided by this invention in the synthesis of high dynamic applications in three or four frames. Detailed Implementation

[0050] The core of this invention is to provide a column-level latch module, an analog-to-digital converter, and an image sensor. This invention sequentially sets up a first-stage first latch, second and third-stage second latches, and a third-stage output latch unit. The first latch can sequentially latch four level quantization values, while the second latch can latch a low conversion gain reset level quantization value from the first stage and transmit it to the third stage for output at an appropriate time. The third latch can transmit the high conversion gain reset level quantization value, the high conversion gain signal level quantization value, and the low conversion gain signal level quantization value from the first latch to the third stage in a time-division manner. Ultimately, the third stage can output "high conversion gain reset level quantization value and signal level quantization value" and "low conversion gain reset level quantization value and signal level quantization value" in a time-division manner. A column-level latch module can be constructed using a small number of latch combinations, achieving time-division output of a pair of level quantization values ​​for both high and low conversion gains, with a small circuit area and low cost.

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] Specifically, firstly, the core of pixel dual conversion gain technology in improving dynamic range lies in acquiring two images with different conversion gains and then combining them into a single high dynamic range image. Therefore, dual conversion gain technology requires specific exposure and readout timing. A typical example is the DOL2 (Digital Overlap 2) exposure timing, which is a dual-exposure parallel mode, where long exposure + high conversion gain and short exposure + low conversion gain are acquired alternately in parallel. This not only improves dynamic range but also greatly alleviates the problem of "ghosting" of moving objects caused by time-division exposure intervals. For example, a 1 / 30 second long exposure + a 1 / 1000 second short exposure, with the interval between the long and short exposure frames being only 1 / 1000 second, instead of the traditional 1 / 30 second. However, in recent years, with the further improvement of image quality requirements, an exposure and readout timing that can completely eliminate "ghosting" has been proposed, namely the DCG readout timing. The difference between it and the DOL2 timing is that only one exposure is performed, and then two readouts are performed using high and low conversion gains respectively to obtain two images. DOL2 always involves two exposures and two readouts. DCG timing, with its single exposure, completely eliminates the "ghosting" problem. The trade-off is that it cannot be combined with long and short exposures to increase dynamic range; instead, it can only be extended through different gains. Naturally, readout circuits supporting DCG timing must be compatible with DOL2, or a three-frame combination of DCG+VS (Very Short exposure) to achieve a wider dynamic range. Therefore, readout circuits supporting DCG timing have become the technical path for mid-to-high-end CIS products to achieve full dynamic range, low noise, and high real-time imaging.

[0053] The DCG timing sequence is characterized by one exposure and two readouts. Furthermore, due to low-noise design requirements, CDS (Correlated Double Sample) technology must be used to eliminate KT / C noise and offset voltage. Therefore, the quantization sequence in DCG timing is typically LCG_V1 (low conversion gain reset level), HCG_V1 (high conversion gain reset level), HCG_V2 (high conversion gain signal level), and LCG_V2 (low conversion gain signal level). However, a mature analog-to-digital converter (ADC) is lacking in related technologies, resulting in a larger number of counter circuit components and a larger circuit area in the ADC.

[0054] Specifically, for a better explanation of the embodiments of the present invention, please refer to... Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of the pixel circuit structure for dual-conversion gain technology. Figure 3This is a timing diagram of the pixel circuit for dual-conversion-gain technology. The pixel circuit includes a photodiode, a charge transfer switch (TX), a reset switch (RX), a gain switching switch (FDG), a source follower (SF), and a row selection switch (SEL). The conversion gain of the pixel circuit is defined as the magnitude of the voltage converted from photogenerated electrons, measured in µV / e-. The conversion gain typically depends on the parasitic capacitance of the FD (Floating Diffusio) node; the higher the parasitic capacitance, the lower the conversion gain (CG), and vice versa. Here, the FD node capacitance is controlled by whether the FDG is on or off. When FDG is high, the C_FDG capacitor is connected to the FD node, significantly reducing the conversion gain and thus achieving dual-conversion-gain switching. The operating states will be described sequentially below.

[0055] (1) Reset: RX=1, FDG=1, TX=0; Reset the FD node.

[0056] (2) Row selection enable: SEL=1, PIXOUT output voltage.

[0057] (3) LCG_V1 quantization: RX=0, output LCG_V1 voltage value, which is quantized by the first segment RAMP.

[0058] (4) HCG_V1 quantization: FDG=0, FD node is high conversion gain, output HCG_V1 voltage, which is quantized by the second RAMP stage.

[0059] (5) HCG_V2 quantization: Turn on TX to transfer photogenerated electrons to the FD node and output HCG_V2 voltage, which is then quantized via the third RAMP stage.

[0060] (6) LCG_V2 quantization: FDG=1, FD node has low conversion gain, output LCG_V2 voltage, which is quantized by the fourth segment RAMP.

[0061] (7) Standby: SEL=0, RX=1, FDG=1, TX=0, Pixel enters standby mode, waiting for the next exposure and readout.

[0062] It can be seen that the DCG timing is significantly different from the conventional linear timing, requiring two reset signals to be read before reading the photoelectric signal. The HCG (High Conversion Gain) timing is sandwiched between the LCG (Low Conversion Gain) timing, and the two are interleaved.

[0063] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of the first column-level latch module provided by the present invention. This column-level latch module is applied to the analog-to-digital converter of an image sensor. The image sensor adopts a dual-conversion-gain mode. After a single exposure, the pixel circuit of the image sensor sequentially outputs a low conversion gain reset level, a high conversion gain reset level, a high conversion gain signal level, and a low conversion gain signal level. The column-level latch module includes:

[0064] The first latch is used in conjunction with the main counter and column comparator module of the analog-to-digital converter to sequentially latch: the quantized value of the low conversion gain reset level, the quantized value of the high conversion gain reset level, the quantized value of the high conversion gain signal level, and the quantized value of the low conversion gain signal level.

[0065] The second latch is used to latch the low conversion gain reset level quantization value in the first latch;

[0066] The third latch latches the high conversion gain reset level quantized value, the high conversion gain signal level quantized value, and the low conversion gain signal level quantized value from the first latch.

[0067] The output latch unit is used to latch the high conversion gain reset level quantized value and the high conversion gain signal level quantized value from the third latch and output them in parallel; it also latches the low conversion gain reset level quantized value from the second latch and the low conversion gain signal level quantized value from the third latch and outputs them in parallel.

[0068] Specifically, considering the technical problems mentioned above, and taking into account that the output latch unit connected to the data transmission channel can "time-division" output a pair of level quantization values ​​for each of the high and low conversion gains, thereby avoiding the need for a multiplexer, a three-stage serial latch architecture is set in this embodiment of the invention. The first latch, as the first stage, can cooperate with the main counter and column comparator module to sequentially latch the quantization values ​​of the four levels (LCG reset level, HCG reset level, HCG signal level, and LCG signal level) output by the pixel unit. The output latch unit, as the third stage, can output the quantization values ​​of the HCG reset level and HCG signal level in parallel, and output the quantization values ​​of the LCG reset level and LCG signal level in parallel, that is, output a pair of level quantization values ​​twice, each time, avoiding the use of a multiplexer.

[0069] The second and third latches can serve as an intermediate second stage. Since the quantized value of the LCG reset level and the quantized value of the LCG signal level are the first and fourth generated level quantized values, respectively, the quantized value of the first generated LCG reset level can be temporarily stored in the second latch. The third latch can transfer the remaining three level quantized values ​​to the output latch unit, so that the output latch unit first latches and outputs a pair of level quantized values ​​of HCG, and then latches and outputs a pair of level quantized values ​​of LCG.

[0070] Specifically, the present invention uses a three-level latch architecture. The column-level latch module can be implemented by using latch combination, without the need for multiplexers, which can simplify the structure, reduce costs and reduce circuit area.

[0071] Specifically, for a better explanation of the relationship between the master counter, the column-level comparator module, and the column-level latch module, please refer to [link / reference needed]. Figure 4 and Figure 5 , Figure 4 This is a schematic diagram of the structure of the first analog-to-digital converter provided by the present invention. Figure 5 This is a schematic diagram of the structure of the second analog-to-digital converter provided by the present invention. Figure 4 In this architecture, the pixel array is driven by row selection logic circuits. Each column-level comparator module and column-level latch module corresponds one-to-one with a pixel column. A pulse generator can be configured within the column-level latch module, as will be explained later. A single master counter is used globally. The pixel circuit output voltage signal (VPIX) enters the positive input of the column-level comparator module of the analog-to-digital converter. The ramp generator drives the negative input of the column-level comparator module array through the ramp signal VRAMP. When VPIX and VRAMP cross, the output of the column-level comparator module (which can be simply called the comparator) flips. The master counter (which can be a Gray code counter, Gray CNT) provides the count value for the global column-level latch modules. Each column of the ADC_1X contains several sets of latches. When the comparator output flips, the column-level latch module captures the current master counter count value and stores it temporarily. A pulse generator can be inserted between the comparator and the column-level latch module to convert the step signal output by the comparator into a pulse signal. This prevents the column-level latch module from continuously following the main counter's count value before the comparator flips, thus reducing power consumption. The column-level latch module can be connected to the data transmission channel, where the column selector transmits data sequentially according to the designed order.

[0072] Among them, Figure 5 In this context, the master counter can be of various types, for example, it can be... Figure 5The system includes a binary counter and a Gray code counter for the binary-to-Gray code decoder. Furthermore, due to the large size of the column-level latch module array, to improve the transmission rate, the output of the main counter can be passed step-by-step by a chain of D flip-flops (DFFs) or directly driven step-by-step by a buffer circuit. Step-by-step driving requires grouping. Figure 5 The document describes a grouping example of column-level latch modules in K columns, where the number of drive (unit) levels can be M, which can be determined based on the actual number of columns and the value of K.

[0073] This invention provides a column-level latch module. Considering that by combining latches in series, the output latch unit connected to the data transmission channel can output a pair of level quantized values ​​for high and low conversion gains in a time-division manner, thereby avoiding the need for a multiplexer, this invention sequentially sets up a first latch in the first stage, second and third latches in the second stage, and an output latch unit in the third stage. The first latch can latch four level quantized values ​​in sequence, while the second latch can latch the low conversion gain reset level quantized value from the first stage and transmit it to the third stage for output at an appropriate time. The third latch can transmit the high conversion gain reset level quantized value, the high conversion gain signal level quantized value, and the low conversion gain signal level quantized value from the first latch to the third stage in a time-division manner. Ultimately, the third stage can output "the high conversion gain reset level quantized value and the signal level quantized value" and "the low conversion gain reset level quantized value and the signal level quantized value" in a time-division manner. A column-level latch module can be constructed with a small number of latches, and the time-division output of a pair of level quantized values ​​for high and low conversion gains can be achieved, with a small circuit area and low cost.

[0074] Based on the above embodiments:

[0075] As an optional embodiment, the output latch unit includes:

[0076] The fourth latch, whose output is connected to the first data transmission channel via a column selector switch, is used to latch the low conversion gain reset level quantization value in the second latch, and also to latch one of the high conversion gain reset level quantization value and the high conversion gain signal level quantization value in the third latch.

[0077] The fifth latch, whose output is connected to the second data transmission channel via a column selector switch, is used to latch the low conversion gain signal level quantization value in the third latch, and also to latch the other of the high conversion gain reset level quantization value and the high conversion gain signal level quantization value in the third latch.

[0078] A column selector switch is used to turn the image sensor on and off under the control of the column selector signal.

[0079] Specifically, for a better explanation of the embodiments of the present invention, please refer to... Figure 6 , Figure 6 This is a schematic diagram of the structure of the second column-level latch module provided by the present invention. Considering that the operation of the output latch unit can be realized by a pair of latches, that is, the output of two pairs of level quantization values ​​is time-division and parallel, the output latch unit in this embodiment of the present invention is composed of a fourth latch, a fifth latch, and a column selection switch. The column selection switch is a device that satisfies the column selection logic and is theoretically indispensable. Since the third latch is required to transmit data to the fourth latch and the fifth latch respectively, and the second latch also needs to transmit data to the fourth latch, the fourth latch has two input terminals, which are respectively connected to the output terminals of the second latch and the third latch. Figure 6 In this array, LAT0 is the first latch, LAT1-1 is the second latch, LAT1-2 is the third latch, LAT1-3 is the fifth latch, LAT2 is the fourth latch, DATE is the output data of the main counter, and Vcomp is the output of the comparator.

[0080] Specifically, Figure 6 Each latch output is labeled Q / QN. As long as the final output polarity meets expectations, either Q (output terminal) or QN (inverting output terminal) can be used for the latch.

[0081] The output latch unit in this embodiment of the invention has the advantages of simple structure, low cost and small circuit area.

[0082] Of course, in addition to this specific construction, the output latch unit can also have other constructions, and the embodiments of the present invention are not limited here.

[0083] As an optional embodiment, at least one of the first latch, second latch, third latch, fourth latch, and fifth latch has a differential clock input and an differential input.

[0084] Specifically, for a better explanation of the embodiments of the present invention, please refer to... Figure 7 , Figure 7 This is a schematic diagram of the third-level latch module provided by the present invention. Considering that designing the clock and input terminals of the latches as two-port differential configurations can save array components, in this embodiment of the invention, at least one of the first, second, third, fourth, and fifth latches has a differential configuration for both its clock and input terminals. Figure 7Some ports of the middle latches use differential configurations. The input of the first latch uses DP and DN differential configurations, and the bus is N bits. WEN0 is the clock control signal for LAT1-1. To save array components, it is used as a differential signal throughout the entire column-level latch module array. For simplicity, WEN0 is represented by a single line. Similar latches, WEN1 and WEN3, will not be elaborated further. LAT2 is a dual-input latch that can receive data from both LAT1-1 and LAT1-2. Therefore, its control signal differs from the other latches, and the control logic will be explained further below. LAT2 is connected to the data transmission channel's transmission bus (DT BUS Line) via a column select switch, which is controlled by a column select signal (from the column selector).

[0085] Specifically, for a better explanation of the embodiments of the present invention, please refer to... Figure 8 , Figure 8 The diagrams provided by this invention show the structures of two latches, with the left side showing the structure of the first latch LAT0 and the right side showing the structure of LAT1 (the second latch LAT1-1, the third latch LAT1-2, and the fifth latch LAT1-3). LAT0 consists of two inverters and two switches, and LAT1 also consists of two inverters and two switches. Of course, in addition to this specific form, the first latch, the second latch, the third latch, and the fifth latch can also be in other forms, and this embodiment of the invention does not limit them.

[0086] As an optional embodiment, the fourth latch includes a first inverter, a second inverter, a first input switch, a second input switch, and a sampling switch;

[0087] The first terminal of the first input switch is connected to the output terminal of the second latch, the first terminal of the second input switch is connected to the output terminal of the third latch, the input terminal of the first inverter is connected to the second terminal of the first input switch, the second terminal of the second input switch and the first terminal of the sampling switch, respectively, the second terminal of the sampling switch is connected to the output terminal of the second inverter, and the output terminal of the first inverter and the input terminal of the second inverter together serve as the inverted output terminal of the fourth latch.

[0088] Specifically, for a better explanation of the embodiments of the present invention, please refer to... Figure 9 and Figure 10 , Figure 9 This is a schematic diagram of a fourth latch provided by the present invention. Figure 10This is a waveform diagram of the control signal for the fourth latch provided by the present invention. Port D1 is the first terminal of the first input switch, connected to the output terminal of the second latch. Port D2 is the first terminal of the second input switch, connected to the output terminal of the third latch. The switch controlled by the SC signal is a sampling switch. The SC signal is derived from SHIFT (switching signal) and CK (clock signal). See [link to relevant documentation]. Figure 10 It can be seen that when either SHIFT or CK is high (representing that the corresponding switch is in the on state), SC is low. Since the dual-input latch (i.e. the fourth latch) implemented in this embodiment of the invention uses only a few simple components (two inverters and three switches), the fourth latch in this embodiment of the invention has the advantages of simple structure and small circuit area.

[0089] The fourth latch can selectively latch data from either the second or third latch: when it is necessary to latch data from the second latch, the first input switch can be closed by a clock signal, the second input switch can be closed by a SHIFT signal, and the sampling switch can be closed by an SC signal; when it is necessary to latch data from the third latch, the first input switch can be closed by a clock signal, the second input switch can be closed by a SHIFT signal, and the sampling switch can be closed by an SC signal.

[0090] Of course, in addition to this specific form, the fourth latch can also take other forms, and the embodiments of the present invention are not limited here.

[0091] As an optional embodiment, the control signal of the sampling switch is obtained by performing a OR NOT logic operation on the control signals of the first input switch and the second input switch.

[0092] Specifically, considering that the control signal of the sampling switch conforms to the OR-NOT logic with the control signals of the first input switch and the second input switch; that is, when either the control signal of the first input switch or the control signal of the second input switch is high, the control signal of the sampling switch is low, and when both the control signals of the first input switch and the second input switch are low, the control signal of the sampling switch is high. Therefore, in order to save computing resources, the embodiment of the present invention can use a simple OR-NOT logic operation to efficiently obtain the control signal of the sampling switch based on the control signals of the first input switch and the control signals of the second input switch.

[0093] The waveform diagram of the OR / NOT logical operation process is as follows: Figure 10 , Figure 10 In this context, CK is the control signal for the first input switch, SHIFT is the control signal for the second input switch, and SC is the control signal for the sampling switch.

[0094] As an optional embodiment, the column-level latch module further includes:

[0095] The input terminal is connected to the output terminal of the column-level comparator module in the same column of the analog-to-digital converter, and the output terminal is connected to the clock terminal of the first latch. The pulse generator is used to convert the step signal output by the column-level comparator module into a pulse signal.

[0096] Specifically, considering that converting the step signal output by the column-level comparator module into a pulse signal can prevent the column-level latch module from continuously following the main counter's count value before the comparator flips, thus reducing power consumption, a pulse generator is also provided between the column-level latch module and the comparator in this embodiment of the invention. This pulse generator can be used to convert the step signal output by the column-level comparator module into a pulse signal.

[0097] As an optional embodiment, the pulse generator includes:

[0098] An initial sampling module, whose input is connected to the output of the column-level comparator module in the same column as the analog-to-digital converter, is used to sample the output signal of the column-level comparator module under the control of a clock signal.

[0099] The phase alignment module, whose input is connected to the output of the initial sampling module, is used to sample the sampling signal of the initial sampling module so as to lock the flip event of the column comparator to the stable phase of the clock signal, thereby achieving phase alignment between the sampled signal and the clock signal.

[0100] The input terminal is connected to the output terminal of the phase alignment module, and the output terminal is connected to the clock terminal of the first latch. The pulse generation module is used to generate a single-cycle pulse signal based on the phase-aligned sampled signal.

[0101] Specifically, in CMOS image sensors, analog-to-digital converters typically employ a column-parallel architecture, with each column equipped with an independent column-level comparator module. However, due to factors such as process variations, power supply noise, or signal propagation delays, the flip-off times of the column-level comparator modules in different columns may vary slightly, leading to inconsistent timing of latching operations across columns. This inter-column timing offset manifests as visible vertical stripes in the image, severely impacting image quality. To address this issue, this embodiment of the invention includes a pulse generator comprising an initial sampling module, a phase alignment module, and a pulse generation module. This structure, through a two-stage synchronous sampling mechanism, forces the originally asynchronous column-level comparator flip-off events to be locked to a stable phase of the global clock signal, and generates a precise single-cycle pulse signal based on this to drive the clock input of the first latch. This ensures that all pixel columns complete data latching under a unified timing reference, suppressing inter-column mismatch caused by dispersed sampling times, thereby eliminating vertical stripe defects in the image sensor imaging process.

[0102] Of course, in addition to this specific form, the pulse generator can also take other forms, and the embodiments of the present invention are not limited here.

[0103] As an optional embodiment, the initial sampling module is a first D flip-flop; the phase alignment module is a second D flip-flop;

[0104] The input of the first D flip-flop is connected to the output of the column comparator module in the same column of the analog-to-digital converter. The inverted output of the first D flip-flop is connected to the input of the second D flip-flop. The inverted output of the second D flip-flop is connected to the input of the pulse generation module.

[0105] Specifically, for a better explanation of the embodiments of the present invention, please refer to... Figure 11 , Figure 11 The diagram shows a pulse generator according to the present invention. DFF1 is the first D flip-flop and DFF2 is the second D flip-flop. This type of initial sampling module and phase alignment module has the advantages of simple structure and small circuit area.

[0106] Of course, in addition to this specific form, the initial sampling module and the phase alignment module can also be in other forms, and the embodiments of the present invention are not limited here.

[0107] As an optional embodiment, the pulse generation module includes:

[0108] The third D flip-flop, whose input terminal and the first input terminal of the logic NOR gate are used together as the input terminal of the pulse generation module, is used to sample the output signal of the phase alignment module so as to delay the output signal of the phase alignment module;

[0109] The logic NOR gate, whose second input is connected to the output of the third D flip-flop, is used to perform NOR logic operation on the output signal of the phase alignment module and the output signal of the third D flip-flop, so as to convert the step signal output by the column comparator module into a pulse signal.

[0110] Specifically, through the third D flip-flop in this embodiment of the invention ( Figure 11 By combining DFF3 (a logic gate) with a logic OR gate, a pulse generation module can be realized, which has the advantages of simple structure and small circuit area.

[0111] Of course, in addition to this specific form, the pulse generation module can also take other forms, and the embodiments of the present invention are not limited here.

[0112] Specifically, for a better explanation of the embodiments of the present invention, please refer to... Figure 12 and combined Figure 7 , Figure 12This is the working timing diagram of the column-level latch module in an analog-to-digital converter provided by the present invention. The operation signals SEL, RX, FDG, and TX of the pixel circuit are marked in the figure for comparison to facilitate understanding. EN_RAMP is aligned with the VRAMP ramp interval. The main counter counts within the enabling interval when EN_RAMP is pulled high. RSTN is the reset signal for the main counter and is reset once before the start of each RAMP wave segment. Vcomp is the comparator output signal. When VRAMP crosses VPIX, Vcomp changes from low to high. The pulse generator (PulseGen) converts this into a pulse signal and uses it as the CK input signal for LAT0. The data flow process will be described below in the order of the four RAMP segments.

[0113] In the first RAMP wave segment, LAT0 captures the data D1_LCG (low conversion gain reset level quantization value) when the comparator flips. Subsequently, under the action of the WEN0 pulse P3, D1_LCG is transferred from LAT0 to LAT1-1. Timing requirement: t2 < p3 < t4, that is, the data transfer is completed within the two enabling intervals of EN_RAMP.

[0114] In the second RAMP wave segment, LAT0 captures the data D1_HCG (high conversion gain reset level quantization value) when the comparator flips. Subsequently, under the action of the WEN1 pulse P4, D1_HCG is transferred from LAT0 to LAT1-2. Timing requirement: t5 < p4 < t6.

[0115] In the third RAMP wave segment, LAT0 captures the data D2_HCG (high conversion gain signal level quantization value) when the comparator flips. However, at this time, both LAT1-1 and LAT1-2 are occupied. It is not until the LCG data transmission of the previous row period is completed at time t7 that LAT2 and LAT1-3 can write data. First, transfer the D1_HCG stored in LAT1-2 to LAT2 through the P5 pulse of EN_SHIFT, then use the P5 pulse of WEN1 to transfer D2_HCG from LAT0 to LAT1-2, and then use the P7 pulse of WEN3 to transfer D2_HCG from LAT1-2 to LAT1-3. By the time t9, LAT2 has obtained D1_HCG and LAT1-3 has obtained D2_HCG, forming a complete HCG data together, and the HCG data transmission can start.

[0116] Among them, the timing requirements are t7 < p5 < p6 < p7 < t9, and t8 < p6 < t10. It can be seen that D1_HCG reaches LAT2 "by borrowing the path" of LAT1-2, bypassing LAT1-1 and also obtaining a temporary storage time, thus achieving the purpose of saving a set of latches.

[0117] In the fourth - segment RAMP - wave interval, LAT0 captures the data D2_LCG (low - conversion - gain signal - level quantization value) when the comparator flips. Subsequently, under the action of the WEN1 pulse P8, D2_LCG is transferred from LAT0 to LAT1 - 2. Timing requirement: t11 < p8 < t1 (the next cycle), which can be achieved after the end of EN_RAMP and before t1 of the next line cycle.

[0118] Since the HCG data starts to be transmitted at t9, only the fourth - segment RAMP time length may not be sufficient for all column data to complete transmission. Especially in high - resolution and high - frame - rate CIS chips, the line cycle is becoming increasingly tight. Therefore, the HCG data transmission may need to be extended to the next line cycle.

[0119] In the first - segment RAMP - wave interval of the next line cycle, operations on WEN2 and WEN3 can only be performed after the HCG data transmission is completed. P1 transfers the D1_LCG stored temporarily in LAT1 - 1 to LAT2 before P3, and P2 must transfer the D2_LCG stored temporarily in LAT1 - 2 to LAT1 - 3 before P3 to avoid data overwriting and loss. Timing requirement: t1 < (P1 & P2) < P3, and it is required that (P1 & P2) < t3, where P1 and P2 do not necessarily occur simultaneously. At t3, LAT2 has obtained D1_LCG and LAT1 - 3 has obtained D2_LCG, forming a complete LCG data together before data transmission can start.

[0120] So far, a complete timing scheme for data latching and transmission in the DCG read - out timing has been described.

[0121] In addition, for a better illustration of the embodiments of the present invention, please refer to Figure 13 And Figure 14 , Figure 13 is the working timing diagram of the column - level latch module provided by the present invention under the linear read - out timing, Figure 14 is the working timing diagram of the column - level latch module provided by the present invention in the three - frame or four - frame synthesis high - dynamic application. In Figure 13 , compared with the DCG timing, the linear timing is much simpler. Here, only a few key timing requirements are described, and the rest are the same as Figure 12 The similar process will not be elaborated. Those skilled in the art can easily infer it. Among them: in the first - segment RAMP - wave interval, the timing requirement is t1 < p1 < t2; in the second - segment RAMP - wave interval, the timing requirement is t3 < p2 < t5, and t3 < p2 < (p3 & p4) < t4. In Figure 14In this context, VS stands for Very Short. To achieve higher dynamic range, the industry goes beyond two-frame DCG synthesis; it often uses three-frame or even four-frame synthesis schemes. This involves using a very short exposure (one frame) or combining it with LOFIC (Lateral Overflow Integration Capacitor) technology to significantly improve dynamic range. The column-level latch module solution proposed in this invention is applicable to both DCG timing and linear timing; therefore, the proposed solution is also well-suited for three-frame and four-frame synthesis timing that combines these two methods.

[0122] Additionally, it is worth mentioning that although the RAMP waveforms shown in the embodiments of the present invention are all slopes from high to low, they can also be slopes from low to high. The embodiments of the present invention do not limit this.

[0123] The present invention also provides an analog-to-digital converter, including a master counter, multiple column-level comparator modules, and multiple column-level latch modules as described in the foregoing embodiments;

[0124] The master counter is used to count the ramp signals corresponding to each level output by the pixel circuit of the image sensor;

[0125] The column-level comparator module is used to flip its own output when the level value of the output of the pixel circuit of the corresponding pixel column is equal to the level value of the ramp signal, so that the column-level latch module latches the current count value of the main counter.

[0126] For an introduction to the analog-to-digital converter provided in the embodiments of the present invention, please refer to the aforementioned embodiments of the column-level latch module; the embodiments of the present invention will not be repeated here.

[0127] The present invention also provides an image sensor, including a pixel circuit and an analog-to-digital converter as described in the foregoing embodiments connected to the pixel circuit.

[0128] For a description of the image sensor provided in the embodiments of the present invention, please refer to the aforementioned embodiments of the column-level latch module; the embodiments of the present invention will not be repeated here.

[0129] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should also be noted that in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0130] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A column-level latch module applied to an analog-to-digital converter of an image sensor, wherein the pixel circuit of the image sensor sequentially outputs a low conversion gain reset level, a high conversion gain reset level, a high conversion gain signal level, and a low conversion gain signal level after a single exposure, characterized in that, The column-level latch module includes: The first latch is used in conjunction with the main counter and column comparator module of the analog-to-digital converter to sequentially latch the quantized value of the low conversion gain reset level, the quantized value of the high conversion gain reset level, the quantized value of the high conversion gain signal level, and the quantized value of the low conversion gain signal level. The second latch is used to latch the low conversion gain reset level quantization value in the first latch; The third latch is used to latch the high conversion gain reset level quantized value, the high conversion gain signal level quantized value, and the low conversion gain signal level quantized value in the first latch. The output latch unit is used to latch the high conversion gain reset level quantized value and the high conversion gain signal level quantized value from the third latch and output them in parallel; and to output the low conversion gain reset level quantized value latched from the second latch and the low conversion gain signal level quantized value latched from the third latch in parallel.

2. The column-level latch module according to claim 1, characterized in that, The output latch unit includes: The fourth latch, whose output is connected to the first data transmission channel via a column selector switch, is used to latch the low conversion gain reset level quantization value in the second latch, and also to latch one of the high conversion gain reset level quantization value and the high conversion gain signal level quantization value in the third latch. The fifth latch, whose output is connected to the second data transmission channel via a column selector switch, is used to latch the low conversion gain signal level quantization value in the third latch, and also to latch the other of the high conversion gain reset level quantization value and the high conversion gain signal level quantization value in the third latch. The column selection switch is used to switch on and off under the control of the column selection signal of the image sensor.

3. The column-level latch module according to claim 2, characterized in that, In the first latch, the second latch, the third latch, the fourth latch, and the fifth latch, at least one of them has a differential clock terminal and an input terminal.

4. The column-level latch module according to claim 2, characterized in that, The fourth latch includes a first inverter, a second inverter, a first input switch, a second input switch, and a sampling switch; The first terminal of the first input switch is connected to the output terminal of the second latch, the first terminal of the second input switch is connected to the output terminal of the third latch, the input terminal of the first inverter is connected to the second terminal of the first input switch, the second terminal of the second input switch and the first terminal of the sampling switch, the second terminal of the sampling switch is connected to the output terminal of the second inverter, and the output terminal of the first inverter and the input terminal of the second inverter together serve as the inverted output terminal of the fourth latch.

5. The column-level latch module according to claim 4, characterized in that, The control signal of the sampling switch is obtained by performing a OR NOT operation on the control signals of the first input switch and the second input switch.

6. The column-level latch module according to any one of claims 1 to 5, characterized in that, The column-level latch module also includes: The input terminal is connected to the output terminal of the column-level comparator module in the same column of the analog-to-digital converter, and the output terminal is connected to the clock terminal of the first latch. The pulse generator is used to convert the step signal output by the column-level comparator module into a pulse signal.

7. The column-level latch module according to claim 6, characterized in that, The pulse generator includes: An initial sampling module, whose input is connected to the output of the column-level comparator module in the same column as the analog-to-digital converter, is used to sample the output signal of the column-level comparator module under the control of a clock signal. The phase alignment module, whose input is connected to the output of the initial sampling module, is used to sample the sampling signal of the initial sampling module so as to lock the flip event of the column comparator to the stable phase of the clock signal, thereby achieving phase alignment between the sampled signal and the clock signal. The input terminal is connected to the output terminal of the phase alignment module, and the output terminal is connected to the clock terminal of the first latch. The pulse generation module is used to generate a single-cycle pulse signal based on the phase-aligned sampled signal.

8. The column-level latch module according to claim 7, characterized in that, The initial sampling module is a first D flip-flop; the phase alignment module is a second D flip-flop; The input of the first D flip-flop is connected to the output of the column comparator module in the same column of the analog-to-digital converter. The inverted output of the first D flip-flop is connected to the input of the second D flip-flop. The inverted output of the second D flip-flop is connected to the input of the pulse generation module. The pulse generation module includes: The third D flip-flop, whose input terminal and the first input terminal of the logic NOR gate are used together as the input terminal of the pulse generation module, is used to sample the output signal of the phase alignment module so as to delay the output signal of the phase alignment module; The logic NOR gate, whose second input is connected to the output of the third D flip-flop, is used to perform NOR logic operation on the output signal of the phase alignment module and the output signal of the third D flip-flop, so as to convert the step signal output by the column comparator module into a pulse signal.

9. An analog-to-digital converter, characterized in that, It includes a master counter, multiple column-level comparator modules, and multiple column-level latch modules as described in any one of claims 1 to 8; The main counter is used to count the ramp signals corresponding to each level output by the pixel circuit of the image sensor; The column-level comparator module is used to flip its own output when the level value output by the pixel circuit of the corresponding pixel column is equal to the level value of the ramp signal, so that the column-level latch module latches the current count value of the main counter.

10. An image sensor, characterized in that, It includes a pixel circuit and an analog-to-digital converter as described in claim 9 connected to the pixel circuit.

Images