A three-dimensional chip wafer level packaging structure of diamond integrated glass substrate and a packaging method thereof

Abstract

The application discloses a three-dimensional chip wafer level packaging structure of a diamond integrated glass substrate and a packaging method thereof, and aims at solving the problem of low thermal conductivity of the glass as a switching board at present.The glass substrate and the diamond substrate in the three-dimensional chip wafer level packaging structure of the application are connected through a bonding layer to form a composite switching board, glass through holes TGV are formed on the glass substrate, the glass through holes TGV are in an array structure, diamond through holes TDV are formed on the diamond substrate, the diamond through holes TDV are in an array structure, the diamond through holes TDV and the glass through holes TGV are aligned to form a through hole structure, the through hole structure is filled with conductive metal, and the chip is bonded to the chip bonding surface of the diamond substrate through a mixed bonding layer.The composite switching board is formed by bonding the glass substrate and the diamond substrate, the process is simplified by adopting the mode of bonding first and punching later, and the stacking and packaging process of the three-dimensional structure of the "chip-diamond heat plate-glass switching board" is realized.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging, specifically relating to the packaging structure and preparation method of a composite heat dissipation adapter plate between a glass substrate and a diamond substrate (heat spreader). Background Technology

[0002] Existing wafer-level packaging technologies mainly include flip-chip packaging, wafer-level ball grid array packaging, and wafer-level system packaging. These technologies have addressed the density issue in chip packaging to some extent. As transistor sizes approach physical limits, semiconductor development has entered the "post-Moore's Law era," and advanced processes have reached a bottleneck. Problem-solving is gradually shifting from advanced processes to advanced integration and packaging. Based on advanced packaging technologies, integration density is improved and chip size is reduced through 2.5D / 3D stacking and heterogeneous material interconnection. Currently, through-silicon vias (TSVs) are a key technology for vertical interconnection in 3D integrated circuits (3D ICs), while short-circuit defects in the insulating layer and open-circuit defects in the bumps are two common failure modes of TSVs.

[0003] Glass substrates, with their inherent insulation and excellent high-frequency electrical properties, have become the preferred choice for next-generation substrates. Compared to traditional organic PCB substrates, glass substrates are less expensive, exhibit lower warpage and are less prone to deformation in large-size applications, and also have higher thermal conductivity and better heat dissipation. As glass interposers, compared to silicon interposers, the ultra-thin glass substrates allow for the integration of more cores. Furthermore, as a key technology in 3D vertical interconnects such as TSV and TGV, the glass interposer's good insulation properties eliminate the need for sputtering insulating layers when achieving 3D vertical interconnects. It also possesses high-frequency electrical characteristics, along with good dimensional stability and flexibility.

[0004] The existing wafer-level packaging technology and the integrated application of glass substrate and diamond heat dissipation mainly have the following problems:

[0005] 1) Complex manufacturing process and high processing difficulty: In terms of high-density two-dimensional and three-dimensional interconnects, multi-layer structures and heterogeneous material connection and stacking, the traditional approach usually adopts the process of drilling holes first and then connecting them. This method has extremely high requirements for the alignment accuracy after drilling, resulting in low processing difficulty and low product yield. At the same time, the material connection process may cause damage and contamination of the through-hole structure, thereby affecting the subsequent electrothermal interconnection process.

[0006] 2) Increased thermal management and high-frequency / high-power issues: Traditional organic substrates and silicon interposers have significant defects in thermal conductivity and coefficient of thermal expansion. They also have high warpage, making it difficult to achieve efficient heat conduction and uniform heat dissipation. This leads to hot spots and junction problems in the chip, resulting in decreased reliability during chip application and affecting the mechanical stability and lifespan of the package.

[0007] 3) Manufacturing difficulty: Existing packaging technologies and structures struggle to simultaneously achieve conductivity, thermal conductivity, and mechanical strength, making it difficult to solve and overcome hotspot issues in chip integration. Mismatches in the coefficients of thermal expansion between materials and the substrate can easily lead to mechanical stress and microcracks within the package, affecting its reliability and lifespan.

[0008] 4) Problems such as parasitic capacitance and parasitic effects caused by silicon interposers. Silicon, as a semiconductor material, has poor conductivity and insulation, which affects the reliability of chip packaging.

[0009] 5) Insufficient bonding strength at the interface of heterogeneous materials: The surface energies of glass and diamond are significantly different, and direct bonding is prone to interface cracking. Summary of the Invention

[0010] Based on the advantages of glass as an interposer or substrate compared to silicon interposers or organic substrates, this invention provides a three-dimensional chip wafer-level packaging structure and packaging method for diamond integrated glass substrates to solve the problem of low thermal conductivity of glass materials.

[0011] The three-dimensional chip wafer-level packaging structure of the diamond integrated glass substrate of the present invention includes a glass substrate, a diamond substrate, diamond through-holes (TDVs), glass through-holes (TGVs), and conductive metal. The glass substrate and the diamond substrate are connected by a bonding layer to form a composite adapter plate. Glass through-holes (TGVs) are formed on the glass substrate in an array structure. Diamond through-holes (TDVs) are formed on the diamond substrate in an array structure. The diamond through-holes (TDVs) and glass through-holes (TGVs) are aligned to form a through-hole structure. The through-hole structure is filled with conductive metal. The chip bonding surface of the diamond substrate is bonded to the chip through a hybrid bonding layer.

[0012] This invention forms a composite adapter board by bonding a glass substrate and a diamond substrate (heat spreader). In the geometry of the composite adapter board, a TGV / TDV through-hole structure is prepared on the composite adapter board using a laser etching process. The through-hole structure is then filled with conductive metals such as copper by electroplating or chemical plating to create a 3D interconnect package structure for the chip and the composite adapter board, thereby realizing a three-dimensional electrical and thermal interconnect package structure.

[0013] The packaging method of the three-dimensional chip wafer-level packaging structure of the diamond integrated glass substrate of the present invention is implemented according to the following steps:

[0014] Step 1: First, perform plasma activation treatment on the bonding surfaces of the glass substrate and the diamond substrate. Then, bond the glass substrate and the diamond substrate together through a bonding layer, which is an Al2O3 dielectric layer, to obtain a composite adapter board.

[0015] Step 2: First, the composite adapter board is thinned and then annealed. Then, a diamond through-hole (TDV) is etched on the diamond substrate of the composite adapter board using ultraviolet nanosecond laser etching, and a glass through-hole (TGV) is etched on the glass substrate of the composite adapter board. After etching, the recast layer on the sidewall of the through-hole is removed by CF4 / O2 plasma treatment. Then, the composite adapter board is placed in a mixed solution of HNO3 / H2SO4 and cleaned at a temperature of 230~350℃. The diamond through-hole (TDV) and the glass through-hole (TGV) are aligned to form a through-hole structure (alignment deviation ≤ 5μm).

[0016] Step 3: Fill the through holes of the composite adapter plate with conductive metal by electroplating or chemical plating to obtain the filled composite adapter plate.

[0017] Step 4: Pre-treat the chip bonding surface (diamond substrate surface) of the filled composite adapter board. Deposit a SiO2 dielectric layer on the chip bonding surface using plasma-enhanced chemical vapor deposition (PECVD) and expose the through-hole structure. Prepare metal sites on the through-holes using photolithography. Then, perform oxygen plasma activation treatment on the chip bonding surface. Subsequently, place the chip on the chip bonding surface and form a hybrid bonding layer by hot-press bonding to obtain the chip-diamond / glass substrate composite structure.

[0018] Step 5: Bond the substrate bonding surface of the chip-diamond / glass substrate composite structure to the substrate using solder to complete the packaging of the three-dimensional chip wafer-level packaging structure of the diamond integrated glass substrate.

[0019] This invention provides a wafer-level chip integrated diamond heat dissipation substrate packaging method. Insulation bonding is achieved by bonding a glass adapter plate and a diamond heat sink. The substrate is then thinned to the target size using a combination of rough grinding and CMP. A combination of laser etching and wet etching is used to drill holes in the diamond / glass composite adapter plate. Electroplating and other methods are used to fill the vias. After hole filling, the surface is polished using CMP, ion beam polishing, and other methods. Copper pads are sputtered and bonded to a large number of chips using photolithography and sputtering. This method simplifies the secondary polishing problem before bonding the passive substrate (glass substrate) and diamond substrate by employing a bonding-then-drilling approach, thus achieving the stacking and packaging process of a three-dimensional structure of "chip-diamond heat sink-glass adapter plate". Attached Figure Description

[0020] Figure 1 This is a flowchart of the packaging method for the three-dimensional chip wafer-level packaging structure of the diamond integrated glass substrate of the present invention.

[0021] Figure 2 This is a flowchart illustrating the fabrication of a three-dimensional chip wafer-level packaging structure for a diamond integrated glass substrate, as shown in the example. Detailed Implementation

[0022] Specific Implementation Method 1: The three-dimensional chip wafer-level packaging structure of the diamond integrated glass substrate in this implementation method includes a glass substrate 101, a diamond substrate 100, diamond through-holes TDV103, glass through-holes TGV104, and conductive metal 105. The glass substrate 101 and the diamond substrate 100 are connected by a bonding layer 102 to form a composite adapter plate. Glass through-holes TGV104 are formed on the glass substrate 101 in an array structure. Diamond through-holes TDV103 are formed on the diamond substrate 100 in an array structure. Diamond through-holes TDV103 and glass through-holes TGV104 are aligned to form a through-hole structure. Conductive metal 105 is filled in the through-hole structure. The chip bonding surface of the diamond substrate 100 is bonded to the chip 106 through a hybrid bonding layer 107.

[0023] Specific Implementation Method Two: The difference between this implementation method and Specific Implementation Method One is that the thickness of the glass substrate 101 is 50μm~1000μm, and the material of the glass substrate 101 is high borosilicate glass, alkali glass, alkali-free glass, or quartz glass.

[0024] This embodiment preferably uses quartz glass, which has a lower dielectric constant (3.8-4.0@1MHz) and better high-frequency performance.

[0025] Specific Implementation Method 3: This implementation method differs from Specific Implementation Method 1 or 2 in that the thickness of the diamond substrate 100 is 100μm~500μm.

[0026] In this embodiment, the thickness of the diamond substrate is preferably 100-300μm to balance heat dissipation efficiency and mechanical support performance.

[0027] Specific Implementation Method Four: This implementation method differs from Specific Implementation Methods One to Three in that the diameter of the diamond through-hole TDV103 is 20~300μm, and the diameter of the glass through-hole TGV104 is 20~300μm.

[0028] In this embodiment, the depth-to-diameter ratio of diamond through-hole (TDV) and glass through-hole (TGV) is in the range of 5:1 to 10:1.

[0029] Specific Implementation Method 5: This implementation method differs from Specific Implementation Methods 1 to 4 in that it uses an electroplating process to fill the through-hole structure with conductive metal 105.

[0030] In this embodiment, conductive material is used to fill the through-hole structure with metal. The conductive material filling needs to achieve uniform filling in order to achieve low resistance and high heat dissipation requirements. The conductive metal 105 serves both heat dissipation and electrical interconnection between upper and lower circuit boards.

[0031] Specific Implementation Method Six: This implementation method differs from one of Specific Implementation Methods One to Five in that the conductive metal 105 is made of copper.

[0032] Specific Implementation Method Seven: The packaging method for the three-dimensional chip wafer-level packaging structure of the diamond integrated glass substrate in this implementation method is carried out according to the following steps:

[0033] Step 1: First, perform plasma activation treatment on the bonding surfaces of the glass substrate 101 and the diamond substrate 100. Then, bond the glass substrate 101 and the diamond substrate 100 together through the bonding layer 102, which is an Al2O3 dielectric layer, to obtain the composite adapter plate.

[0034] Step 2: First, the composite adapter board is thinned, followed by annealing. Then, a diamond through-hole TDV103 is etched on the diamond substrate 100 of the composite adapter board using ultraviolet nanosecond laser etching, and a glass through-hole TGV104 is etched on the glass substrate 101 of the composite adapter board. After etching, the recast layer on the sidewall of the through-hole is removed by CF4 / O2 plasma treatment. Then, the composite adapter board is placed in a mixed solution of HNO3 / H2SO4 and cleaned at a temperature of 230~350℃. The diamond through-hole TDV103 and the glass through-hole TGV104 are aligned to form a through-hole structure (alignment deviation ≤5μm).

[0035] Step 3: Fill the through holes of the composite adapter plate with conductive metal 105 by electroplating or chemical plating to obtain the filled composite adapter plate.

[0036] Step 4: Pre-treat the chip bonding surface (diamond substrate surface) of the filled composite adapter board. Deposit a SiO2 dielectric layer on the chip bonding surface using plasma-enhanced chemical vapor deposition (PECVD) and expose the through-hole structure. Prepare metal sites on the through-holes using photolithography. Then, perform oxygen plasma activation treatment on the chip bonding surface. Subsequently, place the chip 106 on the chip bonding surface and form a hybrid bonding layer 107 by hot-press bonding to obtain the chip-diamond / glass substrate composite structure.

[0037] Step 5: Bond the substrate bonding surface of the chip-diamond / glass substrate composite structure to the substrate 108 using solder to complete the packaging of the three-dimensional chip wafer-level packaging structure of the diamond integrated glass substrate.

[0038] In step four of this embodiment, the bonding surface with deposited dielectric layer and metal sites is activated by oxygen plasma (activation power 120-150W, treatment time 30-40s) to generate hydroxyl groups (-OH) on the SiO2 surface and an oxide layer (Cu2O / CuO) on the Cu surface. Then, the chip and the composite adapter are hot-pressed to achieve Cu / SiO2 mixed bonding. During the bonding process, Si-O-Si covalent bonds are formed between the SiO2 dielectric layers through hydroxyl condensation reaction, and the surface oxide layer is removed and metal bonds are formed between the Cu metal sites through hot-press diffusion. The dual bonding effect constructs a high-strength and highly reliable mixed bonding layer 107, and finally realizes the bonding process between the chip and the filled composite adapter, resulting in a chip-diamond / glass substrate composite structure.

[0039] Specific Implementation Method Eight: This implementation method differs from Specific Implementation Method Seven in that the plasma activation treatment in step one uses an Ar / O2 mixed gas as the activation gas, controls the volume ratio of Ar to O2 to be 3:1, the activation power to be 200W, and the treatment time to be 30~60s.

[0040] Specific Implementation Method Nine: This implementation method differs from Specific Implementation Method Seven or Eight in that the bonding layer 102 described in step one is prepared using atomic layer deposition (ALD) technology.

[0041] The bonding layer 102 prepared in this embodiment can regulate the surface energy of the interface, enhance the physical adsorption capacity, strengthen the chemical stability of the interface, and inhibit the interface diffusion and reaction.

[0042] Specific Implementation Method 10: This implementation method differs from Specific Implementation Methods 7 to 9 in that step 2 uses a grinding + chemical mechanical polishing (CMP) composite process to thin the composite adapter board, reducing the thickness of the composite adapter board to 50~500μm. After the adapter board is thinned, the packaging thickness can be reduced, effectively improving heat dissipation and electrical performance, and optimizing the distribution of mechanical stress.

[0043] Specific Implementation Method Eleven: This implementation method differs from Specific Implementation Methods Seven to Ten in that, in step two, the ultraviolet nanosecond laser etching process uses a laser wavelength of 355 nm, a controlled pulse width of 12 ns, and an energy density of 15 J / cm². 2 The repetition frequency is 40 kHz.

[0044] Specific Implementation Method Twelve: This implementation method differs from Specific Implementation Methods Seven to Eleven in that the temperature for hot pressing bonding in step four is controlled at 260~280℃, the pressure at 8~10MPa, the holding time at temperature and pressure at 40~80min, and the bonding atmosphere is nitrogen.

[0045] Specific Implementation Method Thirteen: This implementation method differs from Specific Implementation Methods Seven to Twelve in that the pretreatment described in step four is a plasma polishing process or a chemical mechanical polishing (CMP) process.

[0046] Specific Implementation Method Fourteen: This implementation method differs from Specific Implementation Methods Seven to Thirteen in that the substrate 108 in step five is a glass substrate or a circuit board, and the bonding method is solder flip bonding with a solder melting point of 183~220℃.

[0047] This embodiment preferably adopts a solder ball array (BGA) with solder ball diameters of 50~100μm and spacing of 100~200μm.

[0048] Example: The packaging method of the three-dimensional chip wafer-level packaging structure of diamond integrated glass substrate in this example is implemented according to the following steps:

[0049] Step 1: Bond the glass substrate 101 and the diamond substrate 100 together using bonding layer 102. The bonding process is as follows: Pre-treat the surfaces of the glass substrate and the diamond substrate to be bonded, ensuring a surface roughness Ra ≤ 0.5 nm and the absence of organic contaminants and oxide layers. Then, deposit an Al2O3 interlayer with a thickness of 40 nm on both the pre-treated glass substrate and diamond substrate surfaces to be bonded using atomic layer deposition (ALD). The interlayer has a dielectric constant of 9-10 (1MHz) and a breakdown electric field strength ≥ 1.5 × 10⁻⁶. 6 V / cm; Plasma surface activation treatment was performed on glass substrates and diamond substrates with deposited Al2O3 interlayers. The activation gas was an Ar / O2 mixed gas, the activation power was 200W, and the treatment time was 40s. Then, in a clean environment, the Al2O3 interlayer surfaces of the glass substrate and the diamond substrate were precisely aligned and bonded. Hot pressing bonding was performed using surface activated bonding (SAB) process. The bonding temperature was 200℃, the bonding pressure was 6MPa, the holding time was 50min, and the bonding atmosphere was a nitrogen environment, forming a transparent high-strength bonding structure, thus obtaining a composite adapter board.

[0050] Step 2: Thinning treatment of the composite adapter plate using a combination of grinding and chemical mechanical polishing (CMP) to reduce the thickness of the composite adapter plate to 200 mm. After thinning to μm, the plate is annealed (annealing temperature 250℃, holding time 2h, nitrogen atmosphere). Then, a 40μm diameter diamond through-hole TDV103 is etched along the thickness of the diamond substrate 100 of the composite adapter plate using ultraviolet nanosecond laser etching. A 40μm diameter glass through-hole TGV104 is etched along the thickness of the glass substrate 101 of the composite adapter plate. After etching, the plate is treated with CF4 / O2 plasma (volume ratio 4:1~10:1, power 200W, time 3min) to remove the recast layer on the sidewall of the through-hole. The treated composite adapter plate is placed in a mixed solution of HNO3 / H2SO4 (volume ratio 3:1) and cleaned at 300℃ for 2h to remove the graphitization introduced by the laser ablation process. The diamond through-hole TDV103 and the glass through-hole TGV104 are aligned to form a through-hole structure, resulting in a composite adapter plate with through-holes.

[0051] Step 3: Pre-treatment of the composite adapter plate with through holes. The pre-treatment process is as follows: First, alkaline degreasing (NaOH 50g / L + Na2CO3 30g / L + surfactant 2g / L, 50℃), followed by ultrasonic-assisted degreasing, then acid activation (hydrochloric acid 100mL / L + sulfuric acid 50mL / L, room temperature 6min) to remove the oxide layer and roughen the hole walls; ultrasonic cleaning with deionized water, followed by nitrogen drying to ensure no residue in the holes and a water contact angle ≤15°; electroplating process, firstly, magnetron sputtering to deposit a copper seed layer (purity ≥99.99%, thickness 120nm) to ensure conductivity of the hole walls, then acidic copper sulfate plating solution (CuSO4•5H2O 220g / L + H2SO4 50g / L + Cl) is used. - 50mg / L + additives), the electroplating process uses a stepped current density: 1A / dm² (60min) → 2.5A / dm² (130min) → 0.8A / dm² (30min), with air stirring + cathode movement, and finally cleaning and drying (vacuum drying at 60℃ for 30min), and annealing at 300℃ in an inert or reducing atmosphere to eliminate electroplating stress, recrystallize copper, improve conductivity and stability, and use chemical mechanical polishing (CMP) to remove excess copper and seed layer on the surface, so that the copper pillar and the surface of the adapter board are flattened and coplanar, and the filled composite adapter board is obtained, which creates conditions for subsequent photolithography, wiring or bonding processes;

[0052] Step 4: Pre-treat the bonding surfaces of the filled composite adapter board. Chemical mechanical polishing (CMP) is used to ensure the bonding surface roughness Ra ≤ 1 nm and that the surface is free of organic contaminants and oxide layers. Photolithography is then used to locate and deposit dielectric layers and metal sites on the through-hole structure. Specifically, plasma-enhanced chemical vapor deposition (PECVD) is used to deposit a SiO2 dielectric layer on the pre-treated chip bonding surface. The dielectric layer thickness is 80 nm. Copper metal sites are prepared by magnetron sputtering and electroplating. The metal sites are precisely aligned with the diamond through-hole (TDV) of the composite adapter and the silicon through-hole (TSV) of the chip (alignment deviation ≤ 5 μm). The chip bonding surface is activated by oxygen plasma (activation power 120-150W, treatment time 30-40s). Then the chip is placed on the chip bonding surface and hot-pressed to form a hybrid bonding layer 107. The hot-pressing bonding temperature is 260℃, the pressure is 8MPa, the holding time is 60min, and the bonding atmosphere is nitrogen. The chip and the filled composite adapter are bonded through the hybrid bonding layer 107 to obtain a chip-diamond / glass substrate composite structure.

[0053] Step 5: The lower surface of the chip-diamond / glass substrate composite structure is bonded to the circuit board 108. The bonding is achieved by metal wire bonding or by contacting the PCB trace pads with the pads. Then, solder is used to connect the components, completing the packaging of the three-dimensional chip wafer-level packaging structure of the diamond integrated glass substrate.

[0054] This embodiment provides a three-dimensional wafer-level chip packaging structure and method for diamond integrated glass substrate. First, insulation, heat dissipation, and high-strength interconnection between the glass transition plate and the diamond heat sink are achieved to prepare a glass substrate / diamond composite transition plate, and then through-hole preparation is performed. This process reduces the alignment accuracy problem of the connecting holes of heterogeneous materials in the subsequent packaging, solves the bonding yield problem of drilling holes before connecting in the prior art, and achieves high-cost stacking.

[0055] Secondly, the use of a glass-diamond composite material leverages the low difference in their coefficients of thermal expansion to improve the reliability and stability of the packaging process, achieving efficient thermal management. Compared to a standalone glass adapter, the composite adapter not only conducts heat more efficiently, reducing temperature differences between the chip and the substrate and preventing warping caused by thermal stress mismatch, but also provides a robust mechanical connection, enhancing the overall stability of the packaging structure. This eliminates the need for complex thermal interface materials and multi-layer heat dissipation structures in the packaging process, further simplifying the manufacturing process. It is compatible with existing CMOS technologies, low-temperature processes, and supports advanced W2W / C2W packaging flows.

[0056] This embodiment employs a glass substrate and diamond composite adapter plate packaging structure and method. Diamond is composited onto the surface of the glass substrate. Leveraging the high thermal conductivity of diamond, excellent electrothermal interconnection is achieved between the glass adapter plate and the diamond heat spreader, enabling heat conduction in both two-dimensional and three-dimensional directions through the heat spreader's heat-spreading effect. Furthermore, the supporting role of diamond, combined with the thinning of both the glass adapter plate and the diamond, reduces the risk of breakage. Bonding and connection are achieved before etching TGV / TDV vias, effectively reducing warpage during packaging. Due to the low difference in thermal expansion coefficients between the glass substrate and diamond, mechanical stability issues caused by thermal stress during heat transfer are effectively mitigated. Simultaneously, as a next-generation substrate, the glass substrate is expected to drive the development of packaging substrates and adapter plates.

Claims

1. A three-dimensional chip wafer-level packaging structure for a diamond integrated glass substrate, characterized in that... The three-dimensional chip wafer-level packaging structure of the diamond integrated glass substrate includes a glass substrate (101), a diamond substrate (100), diamond through-hole TDV (103), glass through-hole TGV (104), and conductive metal (105). The glass substrate (101) and the diamond substrate (100) are connected by a bonding layer (102) to form a composite adapter. Glass through-hole TGV (104) is opened on the glass substrate (101) and the glass through-hole TGV (104) is arranged in an array structure. Diamond through-hole TDV (103) is opened on the diamond substrate (100) and the diamond through-hole TDV (103) is arranged in an array structure. The diamond through-hole TDV (103) and the glass through-hole TGV (104) are aligned to form a through-hole structure. The through-hole structure is filled with conductive metal (105). The chip bonding surface of the diamond substrate (100) is bonded to the chip (106) through a hybrid bonding layer (107).

2. The three-dimensional chip wafer-level packaging structure of diamond integrated glass substrate according to claim 1, characterized in that... The thickness of the glass substrate (101) is 50μm~1000μm, and the material of the glass substrate (101) is high borosilicate glass, alkali glass, alkali-free glass or quartz glass; the thickness of the diamond substrate (100) is 100μm~500μm.

3. The three-dimensional chip wafer-level packaging structure of diamond integrated glass substrate according to claim 1, characterized in that... The diameter of the diamond through-hole TDV (103) is 20~300μm, and the diameter of the glass through-hole TGV (104) is 20~300μm.

4. The three-dimensional chip wafer-level packaging structure of diamond integrated glass substrate according to claim 1, characterized in that... Electroplating is used to fill the through-hole structure with conductive metal (105).

5. The packaging method for the three-dimensional chip wafer-level packaging structure of the diamond integrated glass substrate as described in claim 1. Its features The encapsulation method is implemented according to the following steps: Step 1: First, perform plasma activation treatment on the bonding surfaces of the glass substrate (101) and the diamond substrate (100), and then bond the glass substrate (101) and the diamond substrate (100) together through the bonding layer (102). The bonding layer (102) is an Al2O3 dielectric layer, and a composite adapter board is obtained. Step 2: First, the composite adapter plate is thinned and then annealed. Then, a diamond through-hole TDV (103) is etched on the diamond substrate (100) of the composite adapter plate using ultraviolet nanosecond laser etching process, and a glass through-hole TGV (104) is etched on the glass substrate (101) of the composite adapter plate. After etching, the recast layer on the sidewall of the through-hole is removed by CF4 / O2 plasma treatment. Then, the composite adapter plate is placed in a mixed solution of HNO3 / H2SO4 and cleaned at a temperature of 230~350℃. The diamond through-hole TDV (103) and the glass through-hole TGV (104) are aligned to form a through-hole structure. Step 3: Fill the through holes of the composite adapter plate with conductive metal (105) by electroplating or chemical plating to obtain the filled composite adapter plate. Step 4: Pre-treat the chip bonding surface of the filled composite adapter board. Deposit a SiO2 dielectric layer on the chip bonding surface using plasma-enhanced chemical vapor deposition and expose the through-hole structure. Prepare metal sites on the through-hole using photolithography. Then, perform oxygen plasma activation treatment on the chip bonding surface. Subsequently, place the chip (106) on the chip bonding surface and form a hybrid bonding layer (107) by hot-press bonding to obtain the chip-diamond / glass substrate composite structure. Step 5: Bond the substrate bonding surface of the chip-diamond / glass substrate composite structure to the substrate (108) using solder to complete the packaging of the three-dimensional chip wafer-level packaging structure of the diamond integrated glass substrate.

6. The packaging method for the three-dimensional chip wafer-level packaging structure of diamond integrated glass substrate according to claim 5, characterized in that... In step one, plasma activation treatment uses an Ar / O2 mixed gas as the activation gas, with the volume ratio of Ar to O2 controlled at 3:1, the activation power at 200W, and the treatment time at 30~60s.

7. The packaging method for the three-dimensional chip wafer-level packaging structure of diamond integrated glass substrate according to claim 5, characterized in that... The bonding layer (102) mentioned in step one is prepared by atomic layer deposition process.

8. The packaging method for the three-dimensional chip wafer-level packaging structure of diamond integrated glass substrate according to claim 5, characterized in that... In step four, the temperature for hot pressing bonding is controlled at 260~280℃, the pressure at 8~10MPa, the holding time at temperature and pressure at 40~80min, and the bonding atmosphere is nitrogen.

9. The packaging method for the three-dimensional chip wafer-level packaging structure of diamond integrated glass substrate according to claim 5, characterized in that... The pretreatment described in step four is either plasma polishing or chemical mechanical polishing.

10. The packaging method for the three-dimensional chip wafer-level packaging structure of diamond integrated glass substrate according to claim 5, characterized in that... The substrate (108) in step five is a glass substrate or a circuit board, and the bonding method is solder flip bonding.

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