Stacked electronic device

Abstract

The embodiment of the present disclosure relates to the technical field of chip packaging, in particular to a stacked electronic device, comprising: a first packaging substrate having a first surface and a second surface arranged oppositely; at least one first chip in the first packaging substrate; wherein a heat dissipation surface of the first chip faces the first surface of the first packaging substrate; a signal surface of the first chip faces the second surface of the first packaging substrate; a first shielding structure grounded in the first packaging substrate, comprising at least one first conductive layer and a plurality of first conductive vias located at the peripheral side of the first chip; and at least one second chip arranged on the side where the second surface of the first packaging substrate is located and electrically connected with the first packaging substrate.

Description

Technical Field

[0001] This disclosure relates to the field of chip packaging technology, and particularly to stacked electronic devices. Background Technology

[0002] In radio frequency communication systems such as phased array antennas, beamforming control chips and power amplifier chips typically work together. A common approach is to package the beamforming control chip and power amplifier chip separately and mount them on a circuit board (PCB) in a planar "lay-flat" manner. This approach presents the following technical problems:

[0003] First, there's the issue of electromagnetic interference. Power amplifier chips radiate strong radio frequency signals during operation. These signals can easily crosstalk into adjacent channels, causing signal leakage and coupling between channels. This can lead to link oscillations, rendering the entire system malfunction. Due to the requirements of miniaturization and high-density deployment, it's difficult to solve this problem at the system level by simply adding metal shielding.

[0004] Second, there is a structural conflict between heat dissipation and signal routing. For high-power applications, power amplifier chips generate a significant amount of heat, requiring efficient heat dissipation. In traditional packaging, the signal and heat dissipation surfaces are typically on the same side of the package. This structure contradicts the architectural requirements of "tile-type" antenna arrays: tile-type antenna arrays require the beamforming control chip's heat dissipation surface to face the heat sink, and the signal surface to face the antenna elements. However, in traditional packaging, with the heat dissipation and signal surfaces on the same side, it's impossible to simultaneously meet these two opposing connection requirements: if the signal surface faces the heat sink, the signal cannot be routed to the PCB, thus preventing it from reaching the antenna elements connected to the PCB; if the heat dissipation surface faces the PCB for signal connection, heat will accumulate on the PCB, failing to dissipate effectively, leading to system heat dissipation difficulties and performance degradation.

[0005] Third, arranging multiple chips in a planar layout will occupy a large PCB area, which will become a bottleneck in the system design for high-frequency phased array systems with higher frequencies and smaller requirements for antenna element spacing. Summary of the Invention

[0006] The purpose of this disclosure is to provide a stacked electronic device that solves the technical problems of severe signal crosstalk, heat dissipation and signal wiring conflicts, and large system area occupation caused by the chip planar layout in the prior art.

[0007] This disclosure provides an embodiment of a stacked electronic device, comprising:

[0008] The first packaging substrate has a first surface and a second surface disposed opposite to each other;

[0009] At least one first chip is contained within the first packaging substrate; wherein the heat dissipation surface of the first chip faces the first surface of the first packaging substrate; and the signal surface of the first chip faces the second surface of the first packaging substrate.

[0010] The first shielding structure grounded within the first packaging substrate includes at least one first conductive layer and a plurality of first conductive vias located on the periphery of the first chip.

[0011] At least one second chip is disposed on one side of the second surface of the first packaging substrate and is electrically connected to the first packaging substrate.

[0012] In this embodiment, the heat dissipation surface of the first chip faces the first surface of the first packaging substrate, and the signal surface faces the second surface. This "inverted" layout separates the chip's thermal path and electrical signal path, allowing heat to be directly conducted upwards from the first surface to the external heat sink, achieving efficient heat dissipation. Simultaneously, the electrical signal is transmitted downwards from the second surface, resolving the structural conflict between heat dissipation and signal wiring. This is particularly suitable for "tile-type" array structures, improving the system's heat dissipation efficiency and overall performance.

[0013] In this embodiment, the second chip is disposed on one side of the second surface of the first packaging substrate, forming a vertically stacked structure with the first packaging substrate. Since the signal surface of the first chip faces the second surface, the second chip can achieve convenient electrical interconnection with the first chip through the second surface of the first packaging substrate. On the one hand, this reduces the size of the device in the planar direction; on the other hand, it allows for a shorter RF signal transmission path between the first and second chips, thereby effectively reducing signal loss and improving channel efficiency.

[0014] In this embodiment, to suppress the increased risk of electromagnetic interference caused by the vertical stacking of the first and second chips and the shortened physical distance, a first shielding structure, including a first conductive via and a first conductive layer, is provided within the first packaging substrate to surround the first chip. This built-in shielding structure forms an electromagnetic shielding cavity, effectively isolating the first chip in place, reducing electromagnetic interference and signal crosstalk between the first chip and other circuits, and between different first chips, thus avoiding link oscillation. This achieves high stability and high reliability in a small size without the need for an additional external metal shield. Attached Figure Description

[0015] Figure 1 A schematic diagram of the overall structure of a stacked electronic device according to Embodiment 1 of this application is shown;

[0016] Figure 2A A three-dimensional structural schematic diagram of a stacked electronic device according to Embodiment 1 of this application is shown;

[0017] Figure 2B A top view of a stacked electronic device according to Embodiment 1 of this application is shown;

[0018] Figure 3A A top view of a first packaging substrate according to Embodiment 1 of this application is shown;

[0019] Figure 3B This is a schematic diagram showing the projection of the first chip and the first conductive via on the plane of the second packaging substrate.

[0020] Figure 3C A three-dimensional structural diagram of the first chip located within a first packaging substrate according to Embodiment 1 of this application is shown.

[0021] Figure 3D A cross-sectional schematic diagram of a first chip located within a first packaging substrate according to Embodiment 1 of this application is shown.

[0022] Figure 4A The position of the conductive connection structure according to Embodiment 1 of this application is shown in a top view;

[0023] Figure 4B A three-dimensional schematic diagram showing the arrangement of conductive connection structures according to Embodiment 1 of this application is shown.

[0024] Figure 4C This diagram shows a layout where the signal connection structure is partially surrounded by the grounding connection structure in a conductive connection structure according to Embodiment 1 of this application.

[0025] Figure 5 A cross-sectional schematic diagram showing the radio frequency channel connection between the first packaging substrate and the second packaging substrate according to Embodiment 1 of this application is shown.

[0026] Figure 6 A top view showing the radio frequency channel connection between the first packaging substrate and the second packaging substrate according to Embodiment 1 of this application;

[0027] Figure 7 A three-dimensional structural schematic diagram of the second chip and its underlying conductive layer in the second packaging substrate according to Embodiment 1 of this application is shown.

[0028] Figure 8 This diagram illustrates the structure of a second chip mounted on the surface of a first packaging substrate according to Embodiment 2 of this application. Detailed Implementation

[0029] To address the challenges of heat dissipation difficulties, large system size, and severe signal crosstalk between chips in multi-chip package structures, embodiments of this application provide a stacked electronic device.

[0030] The following combination Figure 1This application describes the stacked electronic device in Embodiment 1.

[0031] Figure 1 A schematic diagram of the overall structure of the stacked electronic device in Embodiment 1 is shown. The structure in the diagram has been simplified to better illustrate the overall structure. Figure 1 As shown, the device 10 includes a first packaging substrate 101, and the first packaging substrate 101 includes at least one first chip 104.

[0032] The first packaging substrate 101 has a first surface 102 and a second surface 103 disposed opposite to each other. In one example, a first chip 104 is embedded within the dielectric layer of the first packaging substrate 101 through a packaging process. The first packaging substrate 101 contains a redistribution layer (RDL). The redistribution layer is a conductive layer formed by a redistribution process during the packaging substrate manufacturing process, enabling signals from the first chip 104 to be electrically discharged through the redistribution layer. Figure 1 In the illustrated embodiment, the redistribution layer includes conductive layers 132a-132d. The redistribution layer of the first package substrate 101 is not limited to four conductive layers, but may include fewer (e.g., two) or more (e.g., five or more) conductive layers.

[0033] The first surface 102 serves as a heat dissipation surface for mounting a heat sink 106. The heat sink 106 is a heat dissipation component disposed on the outer side of the first surface 102. It can be a metal heat sink or a liquid cooling plate and can be thermally coupled to the first surface 102 through a thermally conductive interface material (such as thermal paste, phase change material, or thermal pad). This heat sink is used to transfer the heat generated by the first chip 104 to the ambient air or coolant. The second surface 103 is the surface facing away from the first surface 102.

[0034] The first chip 104 has two opposing sides. One side is used for heat conduction and heat dissipation, and can be called the "heat dissipation side". The other side contains pads for signal input and output, through which signals are input and output, and can be called the "signal side". The pads on the signal side can be connected to the redistribution layer inside the first package substrate.

[0035] The device 10 also includes at least one second chip 108, which is disposed on the side of the second surface 103 of the first packaging substrate 101 and is electrically connected to the first packaging substrate 101. Figure 1 In the illustrated embodiment, device 10 further includes a second packaging substrate 105, which is disposed on the side where the second surface 103 of the first packaging substrate 101 is located, and the second chip 108 is located within the second packaging substrate 105. The second packaging substrate 105 is electrically connected to the first packaging substrate 101, and the second packaging substrate 105 and the first packaging substrate 101 form a vertically stacked structure. Figure 1In this process, the second surface 103 and the second packaging substrate 105 can be electrically connected through the conductive connection structure 107.

[0036] The second chip 108 is embedded in the second packaging substrate 105 through a packaging process. With this design, the first chip 104 and the second chip 108 are stacked vertically. Compared with the planar layout of the first chip 104 and the second chip 108, the device of this solution has a smaller size in the horizontal direction, which is conducive to realizing the miniaturization design of the device.

[0037] To suppress the increased electromagnetic interference risk caused by the vertical stacking of the first and second chips and the shortened physical distance, a first shielding structure 130 is provided within the first packaging substrate 101 for electromagnetic shielding of the first chip 104. The first shielding structure includes multiple first conductive vias 131 located around the periphery of the first chip 104 and at least one first conductive layer. The first conductive layer can be any one or more conductive layers in the redistribution layers within the first packaging substrate 101. The first conductive vias 131 and at least one first conductive layer are grounded. The first conductive vias 131 extend vertically and are electrically connected to the horizontally arranged first conductive layer. The first shielding structure 130, built into the first packaging substrate 101, effectively isolates the electromagnetic radiation generated by different first chips 104 during operation, prevents interference between different first chips 104, and reduces electromagnetic interference from the first chip to other circuits (such as the second chip). This eliminates the need for an additional independent shielding structure outside the first packaging substrate 101, reducing system complexity and weight.

[0038] In this embodiment, the first chip 104 is embedded in the first packaging substrate 101 in an inverted manner, with its heat dissipation surface facing the first surface 102 to facilitate heat conduction upwards to the external heat sink 106, reducing thermal resistance and improving heat dissipation efficiency; its signal surface faces the second surface 103 for electrical connection with the lower second packaging substrate 105. This layout achieves "thermoelectric separation," that is, heat is conducted upwards and electrical signals are transmitted downwards, avoiding wiring conflicts and heat accumulation problems caused by the heat dissipation surface and signal surface being on the same side.

[0039] Meanwhile, since the signal surface of the first chip faces the second surface, the second chip can achieve convenient electrical interconnection with the first chip through the second surface of the first packaging substrate. This reduces the size of the device in the planar direction and shortens the signal transmission path between the first chip 104 and the second packaging substrate 105, which helps to reduce signal transmission loss and improve transmission efficiency.

[0040] This embodiment employs a dual-package substrate stacking architecture: the upper layer is a first package substrate 101 integrating a first chip 104, and the lower layer is a second package substrate 105 integrating a second chip 108. Before the final substrate-to-substrate stacking assembly, the first package substrate 101 and the second package substrate 105 can be subjected to independent electrical performance tests and RF function verifications (e.g., S-parameters, gain, isolation, etc.). Through testing and screening, only qualified first package substrates and qualified second package substrates are subsequently integrated, thereby achieving assembly of known good products. This solution effectively avoids the problem of scrapping the entire module due to the failure of a single chip or local process defects (such as short circuits, open circuits, or substandard RF performance), thereby reducing the final scrap rate of stacked electronic devices, improving manufacturing yield, and effectively controlling mass production costs.

[0041] Figure 2A A three-dimensional structural schematic diagram of a stacked electronic device according to Embodiment 1 of this application is shown; Figure 2B A top view of a stacked electronic device according to Embodiment 1 of this application is shown.

[0042] In this embodiment, the first chip 104 is a radio frequency power amplifier (PA) chip (PA chips generate a large amount of heat when operating), and the second chip 108 is a beamforming control chip. This stacked electronic device can be used in phased array radar or communication applications. The beamforming control chip (also known as a phased array chip) can include multiple radio frequency channels, where each channel is a transmission channel for radio frequency signals, including a transmit channel and a receive channel. Each radio frequency channel is connected to a radio frequency power amplifier chip. Each radio frequency channel includes a corresponding phase shifter and / or amplitude modulator. The phase shifter is used to shift the phase of the signal, and the amplitude modulator is used to adjust the amplitude of the signal. The amplitude modulator can be an attenuator or an amplifier. When a specific direction needs to be pointed to achieve a specific beam, the corresponding radio frequency signal can be phase-shifted using the phase shifter in the phased array, and / or the corresponding radio frequency signal can be amplitude-adjusted using the amplitude modulator, thereby obtaining a specific directional radiation pattern and a corresponding beam. The beamforming control chip controls the beam direction by adjusting the amplitude and phase of the signal. The processed signal is transmitted to the power amplifier chip for power amplification, and then radiated out through the antenna.

[0043] The beamforming control chip includes multiple radio frequency channels (e.g., 4, 8, or 16 radio frequency channels), therefore, a corresponding number of first chips 104 (e.g., 4, 8, or 16 PA chips) can be integrated within the first packaging substrate 101, and the multiple first chips 104 are electrically connected to the same second chip 108. For example... Figure 2BAs shown in the example, the first packaging substrate 101 includes four first chips 104, and the four first chips 104 are electrically connected to the same second chip 108. That is, one beamforming control chip corresponds to four PA chips.

[0044] Figure 3A A top view of a first packaging substrate according to Embodiment 1 of this application is shown; Figure 3B This is a schematic diagram showing the projection of the first chip and the first conductive via on the plane of the second packaging substrate. Figure 3C A three-dimensional structural diagram of the first chip located within a first packaging substrate according to Embodiment 1 of this application is shown. Figure 3D This diagram shows a cross-sectional view of a first chip located within a first packaging substrate according to Embodiment 1 of this application. For clarity, Figure 3C and Figure 3D Only one first chip within the first packaging substrate is shown.

[0045] like Figure 3A As shown, in this embodiment, each first chip 104 is surrounded by a plurality of first conductive vias 131, and first conductive vias 131 are also provided between adjacent first chips 104, which can prevent crosstalk between different first chips 104.

[0046] like Figure 3B As shown, the projections of multiple first chips 104 onto the plane where the second chip 108 is located (e.g., the plane of the second packaging substrate 105) are arranged around the second chip 108, and each first chip 104 at least partially overlaps with the second chip 108. Through this vertical stacking layout, the physical transmission distance of the radio frequency signal from the first chip 104 to the second chip 108 is shortened, reducing the loss of high-frequency radio frequency signals during transmission and improving channel efficiency. Furthermore, this layout also ensures that each of the multiple first chips 104 can maintain a short connection distance with the second chip 108.

[0047] According to some embodiments of this application, such as Figure 1 , Figure 3A and Figure 3D As shown, the first packaging substrate 101 includes a plurality of heat dissipation vias 202, which are located between the heat dissipation surface of the first chip 104 and the first surface 102 of the first packaging substrate 101. These heat dissipation vias 202 establish a vertical heat dissipation channel from the heat dissipation surface of the first chip to the top layer of the first packaging substrate, so that the heat of the first chip can be quickly conducted to the external heat sink 106 that is thermally connected to the first surface 102.

[0048] In one specific embodiment, the heat dissipation via 202 is a via filled with a thermally conductive metal (e.g., copper). To maximize heat dissipation efficiency within a limited layout space, the diameter of the heat dissipation via 202 can be set between 50 micrometers and 150 micrometers, for example, 100 micrometers, and the spacing between adjacent heat dissipation vias (distance between the edges of the vias) can be set between 20 micrometers and 50 micrometers, for example, 30 micrometers or 40 micrometers. The smaller diameter and tighter spacing allow for a high-density via array arrangement in the heat dissipation surface area of ​​the first chip 104, thereby increasing the effective thermal conductivity cross-sectional area and reducing the vertical thermal resistance. The smaller diameter and tighter spacing can meet the production requirements of high yield and mass production while ensuring excellent heat dissipation performance.

[0049] like Figure 3D As shown, in this embodiment, the conductive layer directly connected to the first conductive via 131 is the first conductive layer. Specifically, the first conductive layer includes: an upper first conductive layer, such as conductive layer 132b, disposed on the side of the first chip 104 facing the first surface 102; and a lower first conductive layer, such as conductive layer 132c, disposed on the side of the first chip 104 facing the second surface 103. Multiple first conductive vias 131 connect the upper first conductive layer (conductive layer 132b) and the lower first conductive layer (conductive layer 132c), and the three work together to form a shielding structure enclosing the first chip 104 in three-dimensional space, thereby achieving effective electromagnetic isolation. Simulation verification shows that this structure can provide approximately 6dB to 10dB of shielding effectiveness in the millimeter-wave band (e.g., X, Ku, or Ka bands), effectively suppressing the leakage of RF energy generated by the PA chip and blocking external interference, thereby avoiding the risk of oscillation caused by signal crosstalk in the RF link and ensuring stable operation of multiple channels.

[0050] In other embodiments, the number and position of the first conductive layers can be flexibly adjusted. For example, the upper first conductive layer can also be conductive layer 132a, and the lower first conductive layer can also be conductive layer 132c. If multiple first conductive vias 131 are electrically connected to the upper and lower first conductive layers, the three can also work together to form a shielding structure that encloses the first chip 104 in three-dimensional space, thereby achieving effective electromagnetic isolation.

[0051] In another alternative embodiment, the first conductive layer may consist of only a single layer. For example, the first conductive layer may include a lower first conductive layer (e.g., conductive layer 132c) but not an upper first conductive layer; or, the first conductive layer may also include an upper first conductive layer but not a lower first conductive layer. In this configuration, the first shielding structure is a semi-open shielding structure, but the first conductive via can still form an electromagnetic barrier around the periphery of the first chip, providing electromagnetic isolation and forming isolation within the first packaging substrate.

[0052] In another alternative embodiment, the first conductive layer may include multiple conductive layers located above and / or below the chip. For example, the upper first conductive layer may include conductive layer 132a and conductive layer 132b, both of which are grounded and connected through vias, thereby increasing the equivalent thickness of the upper first conductive layer and further enhancing the shielding effectiveness; and / or, the lower first conductive layer may include conductive layer 132c and conductive layer 132d, both of which are grounded and connected through vias, thereby increasing the equivalent thickness of the lower first conductive layer and further enhancing the shielding effectiveness.

[0053] like Figure 3D As shown, the pads 201 of the first chip 104 can be electrically connected to the conductive layer on the second surface 103 side through the redistribution layer in the first packaging substrate, thereby transmitting electrical signals downward.

[0054] like Figure 3A As shown, the gap between two adjacent first conductive vias 131 is the first gap a, as... Figure 3D As shown, the gap between the upper first conductive layer (conductive layer 132b) and the lower first conductive layer (conductive layer 132c) is the second gap h. The width of the smaller of the first gap a and the second gap h is between 150 micrometers (um) and 300 micrometers, for example, 200um. This size range can ensure that the first shielding structure provides sufficient shielding effectiveness for the millimeter-wave frequency band while taking into account the feasibility and economy of the multilayer packaging substrate manufacturing process, and avoid increasing manufacturing costs or processing difficulties due to excessively small size.

[0055] Figure 4A The position of the conductive connection structure according to Embodiment 1 of this application is shown in a top view; Figure 4B A three-dimensional schematic diagram showing the arrangement of conductive connection structures according to Embodiment 1 of this application is shown. Figure 4C This diagram shows a layout in which the signal connection structure is partially surrounded by the ground connection structure in a conductive connection structure according to Embodiment 1 of this application.

[0056] like Figure 4A and Figure 4B As shown, in this embodiment, the conductive connection structure 107 includes a signal connection structure 107b and a first ground connection structure 107a. The conductive connection structure 107 is a functional interface connecting the upper and lower layers. The signal connection structure 107b is responsible for transmitting signals (e.g., signals output from the second chip to the first chip, or signals output from the first chip to the second chip), and the first ground connection structure 107a is responsible for providing a common ground potential and serving as a shielding and isolation function.

[0057] The conductive connection structure 107 is a conductive element used to achieve electrical connection and physical fixation between the first packaging substrate 101 and the second packaging substrate 105. The conductive connection structure 107 can be a conductive pillar, such as a copper pillar; the conductive connection structure 107 can also be a conductive bump, etc.

[0058] To ensure signal integrity during vertical transmission, such as Figure 4C As shown, a first grounding connection structure 107a is disposed on the outer periphery of the signal connection structure 107b, providing electromagnetic shielding for the signal connection structure 107b. For example, a first grounding connection structure 107a is arranged around each signal connection structure 107b responsible for transmitting radio frequency signals. This layout is similar to the structure of a coaxial cable, providing good impedance matching for vertical signal transmission while preventing signal radiation outward. According to some embodiments of this application, the signal connection structure 107b is partially surrounded by a plurality of first grounding connection structures 107a on its periphery, such as... Figure 4C As shown, the signal connection structure 107b is partially surrounded by five first ground connection structures 107a on its periphery; in other embodiments, the number of first ground connection structures 107a on the periphery can be three to eight, or can be adaptively adjusted according to the signal integrity simulation results. The first ground connection structures 107a are distributed in a semi-enclosed manner around the signal connection structure 107b, which can achieve better impedance control and shielding effect while saving space and reducing coupling between the package substrates.

[0059] like Figure 4A As shown, the projections of the first ground connection structure 107a and the signal connection structure 107b onto the first packaging substrate 101 along the vertical direction are located at the edge of the first packaging substrate 101. This layout helps to simplify the wiring design of the packaging substrate components and at the same time provides mechanical support for the edge of the packaging substrate.

[0060] The conductive connection structure 107 also includes a second ground connection structure 107c. The projection of the second ground connection structure 107c onto the first packaging substrate 101 along the vertical direction is located in the gap between adjacent first chips 104. The first transmission lines 501 of different radio frequency channels are isolated by the second ground connection structure 107c, thereby further improving the isolation between different radio frequency channels and suppressing signal leakage and crosstalk between channels. The second ground connection structure 107c also plays a mechanical support role, which can effectively prevent the first packaging substrate 101 and the second packaging substrate from warping or deforming during manufacturing or operation.

[0061] exist Figure 4AFor clarity, each first chip 104 is shown with a corresponding first transmission line 501 and a corresponding first ground connection structure 107a. In actual implementation, each first chip 104 may correspond to multiple first transmission lines 501 (e.g., RF signal input lines, RF signal output lines, etc.), and each first transmission line 501 may correspond to a first ground connection structure 107a. The specific number can be configured according to requirements such as the number of pads 201 of the first chip 104. For example, when a first chip 104 has N pads 201, N first transmission lines 501 and N first ground connection structures 107a can be correspondingly set, where N is a positive integer greater than 1.

[0062] Figure 5 A cross-sectional schematic diagram showing the radio frequency channel connection between the first packaging substrate and the second packaging substrate according to Embodiment 1 of this application is shown. Figure 6 A top view showing the radio frequency channel connection between the first packaging substrate and the second packaging substrate according to Embodiment 1 of this application.

[0063] like Figure 5 As shown, one end of each signal connection structure 107b is electrically connected to the first transmission line 501 in the first packaging substrate 101, and the other end is electrically connected to the second transmission line 703 in the second packaging substrate 105. The first transmission line 501 is further connected to the pad 201 of the first chip 104, and the second transmission line 703 is further connected to the pad 503 of the second chip 108. Figure 5 The dashed lines in the diagram schematically illustrate the transmission path of the radio frequency signal: the radio frequency signal starts from the pad 201 of the first chip 104, is transmitted to the signal connection structure 107b via the first transmission line 501, is then transmitted vertically via the signal connection structure 107b, and finally reaches the pad 503 of the second chip 108 via the second transmission line 703.

[0064] like Figure 5 and Figure 6 As shown, since the first chip 104 and the second chip 108 are stacked vertically, the pads 201 of the first chip 104 and the pads 503 of the second chip 108 are adjacent in the horizontal projection direction. The radio frequency signal does not need to make a long horizontal detour, the transmission path length of the radio frequency signal is greatly reduced, the loss of the radio frequency signal is reduced, and the signal transmission efficiency is effectively improved.

[0065] According to some embodiments of this application, the size of the conductive connection structure 107 is 150 micrometers to 300 micrometers, for example, 200 micrometers or 250 micrometers, and the spacing between adjacent conductive connection structures 107 is 180 micrometers to 300 micrometers, for example, 200 micrometers. Here, "size" refers to the side length or diameter of the cross-section of the conductive connection structure 107. This size range (150 micrometers to 300 micrometers) and spacing (180 micrometers to 300 micrometers) are designed to accommodate the process capabilities of the packaging substrate-level packaging while meeting the requirements for impedance matching and shielding.

[0066] The following combination Figure 1 and Figure 7 The second packaging substrate 105 of this solution is described. Figure 7 This diagram shows a three-dimensional structural schematic of a second chip and its underlying conductive layer in a second packaging substrate according to Embodiment 1 of this application.

[0067] like Figure 1 As shown, the second chip 108 is embedded within the dielectric layer of the second packaging substrate 105 through a packaging process. The second packaging substrate 105 contains a redistribution layer (RDL), allowing the signals of the second chip 108 to be electrically connected to the first packaging substrate via the redistribution layer. Figure 1 In the illustrated embodiment, the redistribution layer includes conductive layers 904a-904d. The redistribution layer of the second packaging substrate 105 is not limited to four conductive layers, but may include fewer (e.g., two) or more (e.g., five or more) conductive layers.

[0068] like Figure 1 As shown, according to some embodiments of this application, the second packaging substrate 105 has a grounded second shielding structure 930 for electromagnetic shielding of the second chip 108. The second shielding structure 930 includes a plurality of grounded second conductive vias 902 located on the periphery of the second chip 108 and at least one second conductive layer. The second conductive layer can be any one or more conductive layers in the redistribution layers within the second packaging substrate 105. The second conductive vias 902 and at least one second conductive layer are grounded. The second conductive vias 902 extend vertically and are electrically connected to the horizontally arranged second conductive layer. The second shielding structure can shield the second chip 108, further avoiding interference between the first chip 104 and the second chip 108, without requiring additional shielding outside the second packaging substrate 105.

[0069] In this embodiment, the conductive layer directly connected to the second conductive via 902 is the second conductive layer. Specifically, the second conductive layer includes: an upper second conductive layer, such as conductive layer 904b, disposed on the side of the second chip 108 facing the first chip 104; and a lower second conductive layer, such as conductive layer 904c, disposed on the side of the second chip 108 away from the first chip 104. Multiple second conductive vias 902 are electrically connected to the upper second conductive layer (conductive layer 904b) and the lower second conductive layer (conductive layer 904c), and the three layers work together to form a shielding structure enclosing the second chip 108 in three-dimensional space, thereby achieving effective electromagnetic isolation. This effectively suppresses the leakage of radio frequency energy generated by the second chip and blocks external interference, thereby reducing the risk of oscillation caused by signal crosstalk in the radio frequency link and ensuring stable operation of multiple channels.

[0070] In other embodiments, the number and position of the second conductive layer can be flexibly adjusted. For example, the upper second conductive layer can also be conductive layer 904a, and the lower second conductive layer can also be conductive layer 904c. If multiple second conductive vias 902 are electrically connected to the upper and lower second conductive layers, the three can also work together to form a shielding structure that encloses the second chip 108 in three-dimensional space, thereby achieving effective electromagnetic isolation.

[0071] In another alternative embodiment, the second conductive layer may consist of only a single layer, for example, the second conductive layer may include a lower second conductive layer (e.g., 904c) but not an upper second conductive layer; or, the second conductive layer may also include an upper second conductive layer but not a lower second conductive layer. In this configuration, the second shielding structure is a semi-open shielding structure, but the second conductive via can still form an electromagnetic barrier around the second chip, providing electromagnetic isolation and forming isolation within the second packaging substrate.

[0072] In another alternative embodiment, the second conductive layer may include multiple conductive layers located above and / or below the chip. For example, the upper second conductive layer may include conductive layers 904a and 904b, both of which are grounded and connected via vias, thereby increasing the equivalent thickness of the upper second conductive layer and further enhancing the shielding effectiveness; and / or, the lower second conductive layer may include conductive layers 904c and 904d, both of which are grounded and connected via vias, thereby increasing the equivalent thickness of the lower second conductive layer and further enhancing the shielding effectiveness.

[0073] like Figure 7As shown, according to some embodiments of this application, the second packaging substrate 105 further includes a signal via 903. The signal via 903 is located on the periphery of the second chip 108 and within the second shielding structure 930, that is, the signal via 903 is located within the area enclosed by the second conductive via 902. The signal via 903 is electrically connected to the pads of the second chip 108 for leading the signals of the second chip 108 to the bottom surface (for connection with an external PCB). Figure 7 In the example shown, two layers of conductive vias are arranged inside the second packaging substrate 105. The outer conductive via is the second conductive via 902, and at least part of the inner conductive via is the signal via 903. The second conductive via 902 can form a shield outside the signal via 903 to prevent the signal of the signal via 903 from being interfered with.

[0074] According to some embodiments of this application, such as Figure 1 As shown, the second packaging substrate 105 has a third surface 908 and a fourth surface 909 disposed opposite to each other. The third surface 908 is the top surface of the second packaging substrate and is used to connect to the first packaging substrate 101. The fourth surface 909 has a plurality of signal pads 907 for connecting to an external PCB, for surface mounting (SMT) of the entire stacked device onto the external PCB.

[0075] Figure 8 This illustration shows a stacked electronic device according to Embodiment 2 of this application. The difference between Embodiment 2 and Embodiment 1 is that the second chip is mounted on the second surface of the first packaging substrate. Figure 8 As shown, the second chip 108 is attached to the second surface 103 of the first packaging substrate 101 via multiple conductive bumps or conductive pillars 1003.

[0076] In this embodiment, the second chip 108 is directly flip-chip bonded to the bottom of the first package substrate 101. High-density electrical interconnects are achieved using micro-bumps or micro-pillars. This approach further reduces the overall height and interconnect parasitic parameters.

[0077] According to some embodiments of this application, the second surface of the first packaging substrate 101 also has a plurality of electrical connection structures 1002, which are located on the periphery of the second chip 108 and are used for signal fan-out.

[0078] like Figure 8As shown, since the second chip 108 is directly mounted on the central region of the second surface 103 of the first packaging substrate 101, bumps or solder balls (electrical connection structure 1002) are provided on the edge of the second chip 108 in order to transmit the signal to the external PCB. These bumps or solder balls serve as signal fan-out pads, and also support the entire device and connect it to the PCB, allowing the device to be used directly as a wafer-level fan-out package component.

[0079] It is understood that the specific embodiments described herein are merely for illustrative purposes and not for limiting the scope of this application. Furthermore, for ease of description, the accompanying drawings show only the parts relevant to this application, and not all of the structures or processes. It should be noted that similar reference numerals and letters in this specification denote similar items in the accompanying drawings.

[0080] It should be understood that although the terms "first," "second," etc., may be used herein to describe various features, these features should not be limited by these terms. The use of these terms is merely for distinction and should not be construed as indicating or implying relative importance. For example, without departing from the scope of the exemplary embodiments, a first feature may be referred to as a second feature, and similarly, a second feature may be referred to as a first feature.

[0081] In the description of this application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this embodiment based on the specific circumstances.

[0082] Various aspects of the illustrative embodiments will be described using terminology commonly employed by those skilled in the art to convey the essence of their work to others skilled in the art. However, it will be apparent to those skilled in the art that some alternative embodiments may be practiced using some of the features described herein. Specific figures and configurations are set forth for purposes of explanation in order to provide a more thorough understanding of the illustrative embodiments. However, it will be apparent to those skilled in the art that alternative embodiments may be practiced without specific details. In some other instances, well-known features have been omitted or simplified herein to avoid obscuring the illustrative embodiments of this application.

[0083] References to "an embodiment," "embodiment," "illustrative embodiment," etc., in this specification indicate that the described embodiment may include specific features, structures, or properties; however, each embodiment may or may not necessarily include specific features, structures, or properties. Furthermore, these phrases are not necessarily directed to the same embodiment. Additionally, when specific features are described in conjunction with specific embodiments, the knowledge of those skilled in the art can influence the combination of these features with other embodiments, whether or not those embodiments are explicitly described.

[0084] Unless the context otherwise specifies, the terms “comprising,” “having,” and “including” are synonyms. The phrase “A and / or B” means “(A), (B), or (A and B).”

[0085] As used herein, the term "module" may refer to, as part of, or include: a memory (shared, dedicated, or grouped), an application-specific integrated circuit (ASIC), electronic circuitry and / or a processor (shared, dedicated, or grouped), combinational logic circuitry, and / or other suitable components that provide the said functionality for running one or more software or firmware programs.

[0086] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order is not necessary. Rather, in some embodiments, these features may be illustrated in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular drawing does not mean that all embodiments need to include such features; in some embodiments, these features may be omitted or may be combined with other features.

[0087] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, the use of the technical solutions of this application is not limited to the various applications mentioned in the embodiments of this application. Various structures and modifications can be easily implemented with reference to the technical solutions of this application to achieve the various beneficial effects mentioned herein. Within the scope of knowledge possessed by those skilled in the art, all changes made without departing from the spirit of this application should be considered within the scope of this patent application.

Claims

1. A stacked electronic device, characterized in that, include: The first packaging substrate has a first surface and a second surface disposed opposite to each other; At least one first chip is contained within the first packaging substrate; wherein the heat dissipation surface of the first chip faces the first surface of the first packaging substrate; and the signal surface of the first chip faces the second surface of the first packaging substrate. The first shielding structure grounded within the first packaging substrate includes at least one first conductive layer and a plurality of first conductive vias located on the periphery of the first chip. At least one second chip is disposed on one side of the second surface of the first packaging substrate and is electrically connected to the first packaging substrate.

2. The stacked electronic device according to claim 1, characterized in that, The first chip is a power amplifier chip, and the second chip is a beamforming control chip.

3. The stacked electronic device according to claim 1, characterized in that, The first packaging substrate further includes a plurality of heat dissipation through holes, which are located between the heat dissipation surface of the first chip and the first surface of the first packaging substrate.

4. The stacked electronic device according to claim 3, characterized in that, The diameter of the heat dissipation holes is 50 micrometers to 150 micrometers, and the spacing between adjacent heat dissipation holes is 20 micrometers to 50 micrometers.

5. The stacked electronic device according to claim 1, characterized in that, The at least one first conductive layer includes: A first conductive layer disposed on the side of the first chip facing the first surface; and The lower first conductive layer is disposed on the side of the first chip facing the second surface; The plurality of first conductive vias are electrically connected to the upper first conductive layer and the lower first conductive layer.

6. The stacked electronic device according to claim 5, characterized in that, The gap between two adjacent first conductive vias is the first gap, and the gap between the upper first conductive layer and the lower first conductive layer is the second gap. The smaller of the first gap and the second gap has a size between 150 micrometers and 300 micrometers.

7. The stacked electronic device according to claim 1, characterized in that, There are multiple first chips, and the first conductive vias are provided between adjacent first chips.

8. The stacked electronic device according to claim 1, characterized in that, There are multiple first chips, and multiple first chips are electrically connected to the same second chip.

9. The stacked electronic device according to claim 8, characterized in that, The projections of multiple first chips onto the plane where the second chip is located are arranged around the second chip, and each first chip and the second chip at least partially overlap.

10. The stacked electronic device according to claim 1, characterized in that, It also includes a second packaging substrate disposed on one side of the second surface of the first packaging substrate, and the second chip is located inside the second packaging substrate.

11. The stacked electronic device according to claim 10, characterized in that, It also includes multiple conductive connection structures located between the first packaging substrate and the second packaging substrate; the multiple conductive connection structures include signal connection structures and a first ground connection structure.

12. The stacked electronic device according to claim 11, characterized in that, The first grounding connection structure is disposed on the outer periphery of the signal connection structure.

13. The stacked electronic device according to claim 11, characterized in that, The conductive connection structure has a size of 150 micrometers to 300 micrometers, and the spacing between adjacent conductive connection structures is 180 micrometers to 300 micrometers.

14. The stacked electronic device according to claim 11, characterized in that, The projections of the signal connection structure and the first ground connection structure onto the first packaging substrate in the vertical direction are located at the edge of the first packaging substrate.

15. The stacked electronic device according to claim 11, characterized in that, The conductive connection structure further includes a second grounding connection structure; The projection of the second grounding connection structure onto the first packaging substrate in the vertical direction is located in the gap between adjacent first chips.

16. The stacked electronic device according to claim 10, characterized in that, The second packaging substrate has a grounded second shielding structure, which includes at least one second conductive layer and a plurality of second conductive vias located on the periphery of the second chip, to provide electromagnetic shielding for the second chip.

17. The stacked electronic device according to claim 16, characterized in that, The at least one second conductive layer includes: The upper second conductive layer disposed on the side of the second chip facing the first chip; and The lower second conductive layer is disposed on the side of the second chip opposite to the first chip; The plurality of second conductive vias are electrically connected to the upper second conductive layer and the lower second conductive layer, together forming a shielding cavity in which the second chip is located.

18. The stacked electronic device according to claim 10, characterized in that, The second packaging substrate has a third surface and a fourth surface disposed opposite to each other, the third surface being connected to the first packaging substrate; the fourth surface has a plurality of signal pads for external connection.

19. The stacked electronic device according to claim 1, characterized in that, The second chip is mounted on the second surface of the first packaging substrate.

20. The stacked electronic device according to claim 19, characterized in that, The second surface of the first packaging substrate also has a plurality of electrical connection structures, which are located on the periphery of the second chip.

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