Memory management unit and memory management method

Abstract

The application provides a memory management method and a memory management unit. The memory management unit comprises an address conversion and control module and a translation lookaside buffer (TLB) structure. The TLB structure comprises an L2 TLB and a local buffer. The local buffer adopts a full-connected structure and comprises a plurality of entries. Each entry stores a group of related page table entries. The method comprises the following steps: the address conversion and control module sends a received first virtual address to the local buffer and the L2 TLB; the local buffer queries a first target page table entry corresponding to the first virtual address from the plurality of entries based on the first virtual address, and determines a first query result based on whether the first target page table entry is queried from the plurality of entries; the first query result comprises a physical address corresponding to the first virtual address or a query miss; the L2 TLB queries the first target page table entry corresponding to the first virtual address based on the first virtual address; and the L2 TLB and the local buffer query in parallel. According to the application, the address conversion efficiency can be improved.

Description

Technical Field

[0001] This application relates to memory management technology, and more particularly to a memory management unit and a memory management method. Background Technology

[0002] In related technologies, processors typically use a TLB structure to store recently used page table entries, thereby accelerating address translation efficiency. However, in scenarios such as sequential access, linear scan, stack / heap expansion, and access to adjacent data structures within a page, adjacent page table entries in the same cache line are often accessed consecutively, causing L2TLB misses when adjacent PTEs are accessed again in subsequent steps, thus reducing hit efficiency. Summary of the Invention

[0003] This application provides a memory management unit, a memory management method, and a processor.

[0004] The technical solution of this application embodiment is implemented as follows:

[0005] This application provides a memory management unit, which includes an address translation and control module and a translation back buffer (TLB) structure. The TLB structure includes a two-level translation back buffer (L2 TLB) and a local buffer. The local buffer adopts a fully associative structure and includes multiple entries. Each entry stores a set of related page table entries. The address translation and control module is used to send the first virtual address corresponding to the received memory access request to the local buffer and the L2 TLB. The local buffer is used to query the first target page table entry corresponding to the first virtual address from the multiple entries based on the first virtual address, and determine the first query result corresponding to the memory access request based on whether the first target page table entry is found from the multiple entries. The first query result includes the physical address corresponding to the first virtual address or a query miss. The L2 TLB is used to query the first target page table entry corresponding to the first virtual address based on the first virtual address. The L2 TLB and the local buffer perform the query in parallel.

[0006] This application provides a memory management method applied to a memory management unit. The memory management unit includes an address translation and control module and a translation back buffer (TLB) structure. The TLB structure includes a two-level translation back buffer (L2 TLB) and a local buffer. The local buffer adopts a fully associative structure and includes multiple entries. Each entry stores a set of related page table entries. The method includes: the address translation and control module sending a first virtual address corresponding to a received memory access request to the local buffer and the L2 TLB; the local buffer querying the first target page table entry corresponding to the first virtual address from the multiple entries based on the first virtual address, and determining a first query result corresponding to the memory access request based on whether the first target page table entry is found from the multiple entries; the first query result includes the physical address corresponding to the first virtual address or a query miss; the L2 TLB querying the first target page table entry corresponding to the first virtual address based on the first virtual address, with the L2 TLB and the local buffer performing the query in parallel.

[0007] This application provides a processor, which includes the memory management unit and execution unit described above. The execution unit is used to generate a memory access request and send the memory access request to the address translation and control module in the memory management unit.

[0008] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0009] A local buffer is added to the TLB structure, and the local buffer adopts a fully associative structure. Each entry in the local buffer is used to store related page table entries aggregated into a group. In this way, when accessing related page table entries multiple times, the corresponding target page table entry can be directly queried in the local buffer, thereby significantly reducing page table traversal operations and significantly compressing the average address translation latency. The local buffer and the L2 TLB in the TLB structure are queried in parallel. This fully combines the advantages of the large storage capacity of the L2 TLB and the fast query efficiency of the local buffer, further improving the address translation efficiency.

[0010] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0012] Figure 1 This is a schematic diagram of the composition structure of a memory management unit provided in an embodiment of this application. Figure 1 .

[0013] Figure 2This is a schematic diagram illustrating the implementation process of a memory management method provided in this application embodiment.

[0014] Figure 3 This is a schematic diagram of the composition structure of a memory management unit provided in an embodiment of this application. Figure 2 .

[0015] Figure 4 This is a schematic diagram of the instruction stream address for a discrete event system scenario provided in an embodiment of this application.

[0016] Figure 5 This is a schematic diagram of sequential access to page table entries provided in an embodiment of this application.

[0017] Figure 6 This is a two-level address translation cache structure provided in the embodiments of this application.

[0018] Figure 7 This is a schematic diagram of a parallel query L2 TLB and a local special buffer provided in an embodiment of this application.

[0019] Figure 8 This is a schematic diagram of a query L2 TLB and local special buffer pipeline and hit selection process provided in an embodiment of this application.

[0020] Figure 9 This is a schematic diagram of backfilling L2 TLB and local special cache provided in an embodiment of this application.

[0021] Figure 10 This is a schematic diagram of the average access latency of a memory management unit provided in an embodiment of this application.

[0022] Figure 11 This is a schematic diagram illustrating the speedup ratio of the average access latency of a memory management unit provided in an embodiment of this application.

[0023] Figure 12 This is a schematic diagram of the missing rate corresponding to a TLB structure provided in an embodiment of this application.

[0024] Figure 13 This is a schematic diagram illustrating the speedup of the missing rate corresponding to a TLB structure provided in an embodiment of this application;

[0025] Figure 14 This is a schematic diagram of the composition structure of a processor provided in an embodiment of this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0029] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0030] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0031] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0032] 1) Memory Management Unit: This is a hardware component used to translate logical addresses (virtual addresses) into physical addresses (actual memory addresses), and can be a hardware circuit.

[0033] 2) Translate Lookaside Buffer (TLB): This is a high-speed cache used to accelerate the translation of virtual addresses to physical addresses;

[0034] 3) Fully associative structure: This is a structural design method of TLB, which means that memory blocks (or virtual pages) can be freely mapped to any location in the cache (or TLB) without fixed mapping rules;

[0035] 4) Set-associative architecture: This is a TLB architecture design where the TLB is divided into multiple sets, each containing multiple ways. Memory blocks (or virtual pages) are first mapped to a specific set, and then any free way within that set is selected for storage.

[0036] 5) Page table: A data structure used to map virtual memory to physical memory.

[0037] In processor architectures of related technologies, the memory management unit (MMU) is responsible for translating virtual addresses issued by programs into physical addresses. This translation process is typically accomplished by querying page tables, and page table entries (PTEs) are stored in system memory. To accelerate this process, the processor uses a TLB (TLB) to cache recently used PTEs. Related technologies often employ multiple levels of TLBs, such as L1 / L2. L1 TLBs prioritize extremely low hit latency and have relatively small capacity, while L2 TLBs have higher latency but larger capacity and higher set associativity, allowing for a wider range of memory accesses.

[0038] Page table organization inherently exhibits spatial locality: in common architectures, such as x86, Advanced RISC Machine (ARM), and Reduced Instruction Set Computer – Five (RISC-V), the final-level page table stores multiple consecutive virtual page steps (PTEs) (e.g., 8 or more PTEs per line) within a fixed-size cache line (e.g., 64 bytes). In application scenarios involving sequential access, linear scans, stack / heap expansion, and access to adjacent data structures within a page, adjacent page table entries within the same cache line are often accessed consecutively. Since the L2 TLB only stores page table entries, subsequent accesses to adjacent page table entries trigger L2 TLB misses, thus reducing hit efficiency.

[0039] Based on the above description, embodiments of this application provide a memory management unit. Figure 1 This is a schematic diagram of the composition structure of a memory management unit provided in an embodiment of this application. Figure 1 ,like Figure 1As shown, the memory management unit 100 includes an address translation and control module 101 and a translation lookup buffer (TLB) structure 102; the TLB structure 102 includes a secondary translation lookup buffer (L2 TLB) 121 and a local buffer 122; the local buffer adopts a fully associative structure, and the local buffer includes multiple entries, each entry storing a set of related page table entries, wherein:

[0040] The memory management unit 100 is a core hardware component used to respond to the processor's memory access requests. Its core functions are virtual address to physical address translation, memory protection, and cache management. In some implementations, the memory management unit can be embedded in the processor or it can be a hardware component independent of the processor.

[0041] In some implementations, the memory management unit 100 can convert virtual addresses to physical addresses by traversing the page table or by querying the TLB structure.

[0042] Address translation and control module 101 is a hardware component in the memory management unit used to receive and parse memory access requests. In some embodiments, the address translation and control module may include address translation control circuitry.

[0043] TLB structure 102 is a hardware component in the memory management unit used to store page table entries. In some implementations, the TLB structure typically consists of multiple entries, each storing a mapping between virtual page numbers (VPNs) and physical page frame numbers (PFNs), i.e., a mapping between virtual addresses and physical addresses.

[0044] In some implementations, the TLB hierarchy typically employs a multi-level TLB structure, for example, it may include L1 TLB and L2 TLB 121. L1 TLB is the first-level TLB in the TLB structure, with a small capacity but very fast access speed, often referred to as a fast TLB. L2 TLB is the second-level TLB in the TLB structure, located between L1 TLB and main memory, with a larger capacity but slightly slower access speed. When L1 TLB is missed, L2 TLB is accessed.

[0045] In some implementations, the L1 TLB may be a fully connected structure, and the L2 TLB may be a group connected structure.

[0046] The local buffer 122 is a new hardware component added to the TLB structure in this embodiment of the application, used to store multiple sets of related or adjacent page table entries. In some implementations, the local buffer may adopt a fully associative structure.

[0047] This application provides a memory management method applied to the aforementioned memory management unit. Figure 2This is a schematic diagram illustrating the implementation flow of a memory management method provided in an embodiment of this application, as shown below. Figure 2 As shown, the steps include S201 to S203 as follows:

[0048] Step S201: The address translation and control module sends the first virtual address corresponding to the received memory access request to the local buffer and L2 TLB;

[0049] Here, a memory access request is generated by the execution unit in the processor when executing a load or store instruction, and is used to request the physical address required to execute that instruction.

[0050] In some implementations, the execution unit in the processor sends the generated memory access request to the address translation and control module in the memory management unit. The memory access request may include a virtual address. The first virtual address is the virtual address included in the current memory access request.

[0051] In some implementations, the address translation and control module receives a memory access request, parses out the first virtual address included in the memory access request, sends the first virtual address to the TLB structure, queries the TLB structure, and obtains the physical address corresponding to the first virtual address.

[0052] In some implementations, the TLB structure may further include a Level 1 Translation Backup Buffer (L1 TLB). The address translation and control module first sends the first virtual address to the L1 TLB. If the physical address corresponding to the first virtual address is found in the L1 TLB, the physical address corresponding to the first virtual address is sent to the execution unit in the processor. If the physical address corresponding to the first virtual address is not found in the L1 TLB, the first virtual address is sent to the local buffer and the L2 TLB to retrieve the physical address corresponding to the first virtual address from the local buffer and / or the L2 TLB.

[0053] In some implementations, the address translation and control module can simultaneously send the first virtual address to the local buffer and the L2 TLB, respectively, and the local buffer and the L2 TLB can query the physical address corresponding to the first virtual address in parallel based on the first virtual address.

[0054] In some implementations, the address translation and control module may first send the first virtual address to the local buffer. In response to the local buffer not finding a physical address corresponding to the first virtual address, the first virtual address is sent to the L2 TLB, and the L2 TLB queries the physical address corresponding to the first virtual address based on the first virtual address.

[0055] In some implementations, if the address translation and control module does not find a match for the physical address corresponding to the first virtual address in the L1 TLB, it can send the first virtual address to the L2 TLB and obtain the physical address corresponding to the first virtual address by querying the L2 TLB.

[0056] Step S202: The local buffer queries the first target page table entry corresponding to the first virtual address from multiple entries based on the first virtual address, and determines the first query result corresponding to the memory access request based on whether the first target page table entry is found from the multiple entries; the first query result includes the physical address corresponding to the first virtual address or a query miss;

[0057] Here, the first query result is the query result obtained by querying the local buffer based on the current memory access request.

[0058] In some implementations, the local buffer receives a first virtual address sent by the address translation and control module, and based on the first virtual address, sequentially queries multiple entries included in the local buffer, and sequentially determines whether there is a first target page table entry corresponding to the first virtual address among the multiple page table entries stored in each entry, thereby determining the first query result corresponding to the memory access request.

[0059] In some implementations, if a first target page table entry corresponding to the first virtual address is found from multiple entries, the first query result is determined to be the physical address corresponding to the first virtual address; if no first target page table entry corresponding to the first virtual address is found from multiple entries, the first query result is determined to be a query miss.

[0060] In some implementations, each page table entry can describe a mapping relationship between a set of virtual addresses and physical addresses. After determining the first target page table entry, the local buffer can determine the physical address corresponding to the first virtual address based on the mapping relationship between the virtual address and physical address described by the first target page table entry, thereby determining that the first query result is the physical address corresponding to the first virtual address.

[0061] In some implementations, since the local buffer uses a fully associative structure and has a small capacity, when the first target page table entry is found in the local buffer, the physical address corresponding to the first virtual address is directly returned to the execution unit in the processor, thereby improving the efficiency of address translation.

[0062] Step S203: The L2 TLB queries the first target page table entry corresponding to the first virtual address based on the first virtual address. The L2 TLB and the local buffer perform the query in parallel.

[0063] In some implementations, the L2 TLB receives a first virtual address sent by the address translation and control module, and queries the physical address corresponding to the first virtual address based on the first virtual address.

[0064] In some implementations, the L2 TLB can adopt a group-associative structure. The L2 TLB can include multiple groups, and each group includes multiple page table entries. The L2 TLB first determines the target group index based on the first virtual address, determines the target group from the multiple groups based on the target group index, then determines the entry identifier based on the first virtual address, and determines the first target page table entry corresponding to the first virtual address from the target group based on the entry identifier.

[0065] In some implementations, the L2 TLB and the local buffer are independent structures, but they can communicate with each other. For example, if a query to the L2 TLB fails but a query to the local buffer succeeds, the L2 TLB sends a fail signal to the local buffer, causing the local buffer to update the L2 TLB with the first target page table entry found in the query. Here, a fail means that the target page table entry corresponding to the virtual address was found.

[0066] In this embodiment, a local buffer is added to the TLB structure, and the local buffer adopts a fully connected structure. Each entry in the local buffer is used to store related page table entries aggregated into a group. In this way, when accessing related page table entries multiple times, the corresponding target page table entry can be directly queried in the local buffer, thereby significantly reducing page table traversal operations and significantly compressing the average address translation latency. The local buffer and the L2 TLB in the TLB structure are queried in parallel. This fully combines the advantages of the large storage capacity of L2TLB and the fast query efficiency of the local buffer, further improving the address translation efficiency.

[0067] In some embodiments, the first virtual address includes an entry identifier and an offset, and step S202 above may include the following step S211:

[0068] Step S211: The local buffer determines the target entry from multiple entries based on the entry identifier; and determines the first target page table entry corresponding to the first virtual address from a set of related page table entries stored in the target entry based on the offset.

[0069] Here, the entry tag is part of the virtual address used to uniquely identify an entry in a page table or TLB.

[0070] Offset is the portion of a virtual address that specifies the exact byte position within a physical page frame.

[0071] In some implementations, each entry in the local buffer consists of an entry identifier bit and multiple page table entry slots. For example, an entry includes an entry identifier bit and eight page table entry slots.

[0072] In some implementations, based on the entry identifier included in the first virtual address, the entry identifiers are sequentially compared with the entry identifiers stored in the entry identifier bits of multiple entries in the local buffer, and the entry corresponding to the entry identifier that is the same as the entry identifier included in the first virtual address among the entry identifiers stored in the entry identifier bits of the multiple entries is determined as the target entry.

[0073] In some implementations, a first target page table entry corresponding to the first virtual address is determined from a plurality of page table entries stored in the target entry, based on the offset included in the first virtual address.

[0074] In some implementations, a set of related page table entries are aggregated in each entry of the local buffer. By leveraging the local associativity of allocation, the probability of misses can be reduced when accessing related or adjacent page table entries multiple times, thereby reducing the operation of traversing the page table.

[0075] In some implementations, a set of related page table entries may refer to multiple page table entries located in the same cache line and / or in adjacent cache lines within the page table.

[0076] In this embodiment, the first virtual address includes an entry identifier and an offset. The local buffer determines the target entry from multiple entries based on the entry identifier; and determines the first target page table entry corresponding to the first virtual address from a set of related page table entries stored in the target entry based on the offset. In this way, the target entry and its corresponding offset position of the first target page table entry can be accurately and quickly located in the local buffer using the entry identifier and the offset, thereby improving the efficiency of accessing the first target page table entry.

[0077] In some embodiments, the above method may further include the following steps S221 to S222:

[0078] Step S221: In response to the first query result including the physical address corresponding to the first virtual address and the second virtual address sent by the address translation and control module, the local buffer queries the second target page table entry corresponding to the second virtual address from multiple entries;

[0079] Here, the second virtual address is the virtual address included in the next memory access request corresponding to the current memory access request.

[0080] In some implementations, the page table entries corresponding to the first virtual address and the second virtual address are adjacent page table entries in the page table.

[0081] In some implementations, when the local buffer finds a corresponding first target page table entry based on the first virtual address, it can determine that the local buffer includes a target entry storing the first target page table entry. This target entry also includes other page table entries related to the first target page table entry. Since the page table entries corresponding to the first and second virtual addresses are adjacent in the page table, it is known that the page table entry corresponding to the second virtual address is also stored in this target entry. Therefore, based on the second virtual address, the second target page table entry corresponding to the second virtual address can be determined from the target entries in the local buffer. The second target page table entry is a page table entry related to the first target page table entry within the same entry; it can also be understood as the second target page table entry being adjacent to the first target page table entry and located in the same cache line or adjacent cache lines in the page table.

[0082] Step S222: The local buffer determines the second query result corresponding to the second virtual address as the physical address corresponding to the second virtual address based on the second target page table entry; the second target page table entry is a page table entry related to the first page table entry in the same entry.

[0083] Here, the second query result is the query result obtained by querying the local buffer based on the next memory access request corresponding to the current memory access request.

[0084] In some implementations, the local buffer determines the physical address corresponding to the second virtual address based on the mapping relationship between virtual addresses and physical addresses included in the second target page table entry, thereby determining the second query result as the physical address corresponding to the second virtual address.

[0085] In some implementations, if the first query result includes a query miss, it is determined that the local buffer does not store the first target page table entry corresponding to the first virtual address, nor does it store other page table entries related to the first target page table entry. Therefore, when the second virtual address is received, the query for the second target page table entry corresponding to the second virtual address will also fail to find the second target page table entry corresponding to the second virtual address, thus determining that the second query result is a query miss.

[0086] In this embodiment, in response to the first query result including the physical address corresponding to the first virtual address, the local buffer queries a second target page table entry corresponding to the second virtual address from multiple entries based on the second virtual address sent by the address translation and control module. Based on the second target page table entry, the second query result corresponding to the second virtual address is determined to be the physical address corresponding to the second virtual address. The second target page table entry is a page table entry related to the first page table entry within the same entry. Thus, since each entry in the local buffer stores multiple related page table entries, in the case of multiple accesses to related page table entries, multiple accessed related page table entries can be hit consecutively, thereby improving the hit probability.

[0087] In some embodiments, step S203 above may include the following step S231:

[0088] Step S231: If the L2 TLB finds the first target page table entry corresponding to the first virtual address based on the first virtual address, it determines that the third query result corresponding to the memory access request includes the physical address corresponding to the first virtual address; if the L2 TLB does not find the first target page table entry corresponding to the first virtual address based on the first virtual address, it determines that the third query result includes a query miss.

[0089] Here, the third query result is the query result obtained by querying the L2 TLB based on the current memory access request.

[0090] In some implementations, the L2 TLB receives a first virtual address sent by the address translation and control module, and based on the first virtual address, queries multiple page table entries stored in the L2 TLB to determine whether the first target page table entry corresponding to the first virtual address can be found.

[0091] In some implementations, when the L2 TLB finds a first target page table entry corresponding to the first virtual address, it is determined that one of the multiple entries in the L2 TLB stores the first target page table entry. Therefore, the physical address corresponding to the first virtual address can be determined based on the mapping relationship between the virtual address and the physical address included in the first target page table entry, thereby determining that the third query result is the physical address corresponding to the first virtual address.

[0092] In some implementations, if the L2 TLB does not find the first target page table entry corresponding to the first virtual address, it can be determined that the first target page table entry is not stored in multiple entries in the L2 TLB, thereby determining that the third query result is a query miss.

[0093] In some embodiments, the above method may further include the following step S241:

[0094] Step S241: The local buffer is also used to backfill the first target page table entry into the L2 TLB if the first query result includes the physical address corresponding to the first virtual address and the third query result includes a query miss.

[0095] In some implementations, if the local buffer obtains a first query result based on the current memory access request, which includes the physical address corresponding to the first virtual address, and a third query result, which includes a query miss, the local buffer returns the first query result to the execution unit in the processor and sends the first target page table entry to the L2 TLB, so that the L2 TLB stores the first target page table entry into the entry in the L2 TLB.

[0096] In some implementations, the L2 TLB receives a first target page table entry sent by the local buffer and stores the first target page table entry into an entry in the L2 TLB.

[0097] In some implementations, if the local buffer returns the first query result directly to the execution unit in the processor when the first query result includes the physical address corresponding to the first virtual address and the third query result includes the physical address corresponding to the first virtual address.

[0098] In some implementations, the local buffer backfills the first target page table entry into the L1 TLB.

[0099] In this embodiment, if the first query result includes the physical address corresponding to the first virtual address, and the third query result includes a query miss, the local buffer backfills the first target page table entry into the L2 TLB. In this way, by backfilling the first target page table entry into the L2 TLB, the local buffer can improve the L2 TLB hit probability.

[0100] In some embodiments, the memory management unit further includes a page table traverser, and the above method may further include the following steps S251 and S252:

[0101] Step S251: In response to a first query result including a query miss and a third query result including a query miss, the page table traverser queries the page table for a first target page table entry corresponding to the first virtual address, and at least one page table entry related to the first target page table entry in the same cache line and adjacent cache lines.

[0102] Here, the page table traverser is a hardware component in the memory management unit used to traverse page tables. It searches for the mapping relationship between virtual addresses and physical addresses by traversing page table levels (such as multi-level page tables) or caches.

[0103] In some implementations, if the page table traverser determines that the query TLB structure has not been hit when the first query result includes a query miss and the third query result includes a query miss, then the page table traverser needs to traverse the page table to query the first target page table entry corresponding to the first virtual address.

[0104] In some implementations, the page table traverser can retrieve a first target page table entry and multiple page table entries associated with the first target page table entry from the page table.

[0105] In some implementations, the page table can be a multi-level page table. The page table traverser traverses the multi-level page tables level by level until it finds the first target page table entry. It then identifies at least one page table entry in the page table that is adjacent to the first target page table entry as at least one page table entry that is related to the first target page table entry in the same cache line and adjacent cache lines.

[0106] In some implementations, the page table entry associated with the first target page table entry may be at least one page table entry located in the same cache line and adjacent cache line as the first target page table entry in the page table.

[0107] Step S252: The page table traverser sends the first target page table entry to the L2 TLB, and sends the first target page table entry, as well as at least one related page table entry located in the same cache line and adjacent cache lines as the first target page table entry, to the local buffer.

[0108] In some implementations, the page table traverser sends a first target page table entry to the L2 TLB so that the L2 TLB stores the first target page table entry into the corresponding entry.

[0109] In some implementations, the page table traverser aggregates a first target page table entry and at least one page table entry associated with the first target page table entry into a set of related page table entries, and sends the set of related page table entries to a local buffer so that the local buffer stores the set of related page table entries in the local buffer.

[0110] In some implementations, the page table traverser sends a first target page table entry to the L1 TLB, causing the L1 TLB to store the first target page table entry in the corresponding entry.

[0111] In this embodiment, the memory management unit further includes a page table traverser. In response to a first query result including a query miss and a third query result including a query miss, the page table traverser, based on a first virtual address, queries the page table for a first target page table entry corresponding to the first virtual address, and at least one page table entry related to the first target page table entry located in the same cache line and adjacent cache lines. The page table traverser then sends the first target page table entry to the L2 TLB and sends the first target page table entry, along with at least one page table entry related to the first target page table entry, to the local buffer. Thus, in the event that both the L2 TLB and local buffer queries fail, the page table traverser obtains the first target page table entry by traversing the page table and sends it to the L2 TLB, thereby improving the hit efficiency of subsequent L2 TLB queries. Sending the first target page table entry, along with at least one page table entry related to the first target page table entry located in the same cache line and adjacent cache lines, to the local buffer further improves the hit efficiency of subsequent local buffer queries.

[0112] In some embodiments, the above method further includes the following steps S261 and S262:

[0113] Step S261: The L2 TLB updates the first target page table entry to the L2 TLB;

[0114] In some implementations, the L2 TLB receives the first target page table entry and writes it to an entry in the L2 TLB.

[0115] In some implementations, when all entries in the L2 TLB have stored page table entries, the first target page table entry is updated in the L2 TLB based on the access time corresponding to the page table entries stored in each entry. For example, the entry in the L2 TLB with the longest access time corresponding to the stored page table entries is determined, and the page table entries in that entry are replaced with the first target page table entry.

[0116] In some implementations, a pseudo-least recently used (PLRU) replacement strategy is employed to update page table entries stored in the local buffer.

[0117] Step S262: The local buffer updates the first target page table entry, as well as at least one page table entry related to the first target page table entry in the same cache line and adjacent cache lines, to the same entry in the local buffer.

[0118] In some implementations, the local buffer receives a first target page table entry and at least one page table entry associated with the first target page table entry, and writes the page table entries of the entire cache line consisting of the first target page table entry and at least one page table entry associated with the first target page table entry into the same entry in the local buffer.

[0119] In some implementations, when all entries in the local buffer already store page table entries, the first target page table entry, along with at least one page table entry associated with the first target page table entry located in the same cache line or adjacent cache line, is updated in the local buffer based on the access time corresponding to the page table entries stored in each entry. For example, the entry in the local buffer with the longest access time corresponding to the page table entries is determined, and the page table entries in that entry are replaced with the first target page table entry and at least one page table entry associated with the first target page table entry.

[0120] In some implementations, after the page table traverser finds the first target page table entry, a complete cache line is returned on the bus. This cache line is the cache line containing the first target page table entry. The first target page table entry in the cache line is written into the L2 TLB. The cache line, along with the cache line adjacent to it in the page table, is written into the local buffer.

[0121] In some implementations, since the local buffer caches the entire cache line as well as the page table entries stored in adjacent cache lines, subsequent accesses can hit consecutively after backfilling.

[0122] In some implementations, a pseudo-least recently used replacement strategy is employed to update page table entries stored in the local buffer.

[0123] In some embodiments, the local buffer includes a first number of entries, each entry including a flag bit and a second number of page table entry slots; each page table entry slot is used to store a page table entry; the entry identifier bit is used to store an entry identifier.

[0124] Here, the first number is the number of entries included in the local buffer. For example, the first number can be 16, which means that the local buffer includes 16 entries.

[0125] The second quantity is the number of page table entry slots included in each entry in the local buffer. For example, the second quantity can be 8, which means that each entry includes 8 page table entry slots and each entry can store 8 page table entries.

[0126] In some implementations, a local buffer can aggregate multiple related page table entries into the same entry storage.

[0127] In some implementations, the local buffer stores page table entries located in the same cache line in the same entry.

[0128] In some implementations, the second number can be the same as the number of page table entries located in the same cache line in the page table.

[0129] In this embodiment of the application, each entry in the local buffer stores multiple related page table entries, so that subsequent queries of related page table entries can be hit, thereby improving the hit rate.

[0130] This application provides a memory management unit, such as... Figure 1 As shown, the memory management unit includes an address translation and control module and a translation lookup buffer (TLB) structure. The TLB structure includes a two-level translation lookup buffer (L2 TLB) and a local buffer. The local buffer adopts a fully associative structure and includes multiple entries. Each entry stores a set of related page table entries. Specifically: the address translation and control module is used to send the first virtual address corresponding to the received memory access request to the local buffer and the L2 TLB; the local buffer is used to query the first target page table entry corresponding to the first virtual address from the multiple entries based on the first virtual address, and determine the first query result corresponding to the memory access request based on whether the first target page table entry is found from the multiple entries; the first query result includes the physical address corresponding to the first virtual address or a query miss; the L2 TLB is used to query the first target page table entry corresponding to the first virtual address based on the first virtual address; the L2 TLB and the local buffer perform parallel queries.

[0131] In this embodiment, a local buffer is added to the TLB structure, and the local buffer adopts a fully connected structure. Each entry in the local buffer is used to store related page table entries aggregated into a group. In this way, when accessing related page table entries multiple times, the corresponding target page table entry can be directly queried in the local buffer, thereby significantly reducing page table traversal operations and significantly compressing the average address translation latency. The local buffer and the L2 TLB in the TLB structure are queried in parallel. This fully combines the advantages of the large storage capacity of L2TLB and the fast query efficiency of the local buffer, further improving the address translation efficiency.

[0132] In some embodiments, the first virtual address includes an entry identifier and an offset; a local buffer is further configured to determine a target entry from a plurality of entries based on the entry identifier; and to determine a first target page table entry corresponding to the first virtual address from a set of related page table entries stored in the target entry based on the offset.

[0133] In this embodiment, the first virtual address includes an entry identifier and an offset. The local buffer determines the target entry from multiple entries based on the entry identifier; and determines the first target page table entry corresponding to the first virtual address from a set of related page table entries stored in the target entry based on the offset. In this way, the target entry and its corresponding offset position of the first target page table entry can be accurately and quickly located in the local buffer using the entry identifier and the offset, thereby improving the efficiency of accessing the first target page table entry.

[0134] In some embodiments, the local buffer is further configured to, in response to the first query result including the physical address corresponding to the first virtual address, query a second target page table entry corresponding to the second virtual address from multiple entries based on the second virtual address sent by the address translation and control module; the local buffer is further configured to, based on the second target page table entry, determine that the second query result corresponding to the second virtual address is the physical address corresponding to the second virtual address; the second target page table entry is a page table entry related to the first page table entry in the same entry.

[0135] In this embodiment, in response to the first query result including the physical address corresponding to the first virtual address, the local buffer queries a second target page table entry corresponding to the second virtual address from multiple entries based on the second virtual address sent by the address translation and control module. Based on the second target page table entry, the second query result corresponding to the second virtual address is determined to be the physical address corresponding to the second virtual address. The second target page table entry is a page table entry related to the first page table entry within the same entry. Thus, since each entry in the local buffer stores multiple related page table entries, in the case of multiple accesses to related page table entries, multiple accessed related page table entries can be hit consecutively, thereby improving the hit probability.

[0136] In some embodiments, the L2 TLB is further configured to, when a first target page table entry corresponding to the first virtual address is found based on the first virtual address, determine that the third query result corresponding to the memory access request includes the physical address corresponding to the first virtual address; and when a first target page table entry corresponding to the first virtual address is not found based on the first virtual address, determine that the third query result includes a query miss.

[0137] In some embodiments, the local buffer is further configured to backfill the first target page table entry into the L2 TLB if the first query result includes the physical address corresponding to the first virtual address and the third query result includes a query miss.

[0138] In this embodiment, if the first query result includes the physical address corresponding to the first virtual address, and the third query result includes a query miss, the local buffer backfills the first target page table entry into the L2 TLB. In this way, by backfilling the first target page table entry into the L2 TLB, the local buffer can improve the L2 TLB hit probability.

[0139] In some embodiments, such as Figure 3 As shown, the memory management unit 100 further includes a page table traverser 103. The page table traverser 103 is configured to, in response to a first query result including a query miss and a third query result including a query miss, query from the page table based on the first virtual address a first target page table entry corresponding to the first virtual address, and at least one page table entry related to the first target page table entry located in the same cache line and adjacent cache lines. The page table traverser 103 is also configured to send the first target page table entry to the L2 TLB, and send the first target page table entry, and at least one page table entry related to the first target page table entry located in the same cache line and adjacent cache lines to the local buffer.

[0140] In this embodiment, the memory management unit further includes a page table traverser. In response to a first query result including a query miss and a third query result including a query miss, the page table traverser, based on a first virtual address, queries the page table for a first target page table entry corresponding to the first virtual address, and at least one page table entry related to the first target page table entry located in the same cache line and adjacent cache lines. The page table traverser then sends the first target page table entry to the L2 TLB and sends the first target page table entry, along with at least one page table entry related to the first target page table entry, to the local buffer. Thus, in the event that both the L2 TLB and local buffer queries fail, the page table traverser obtains the first target page table entry by traversing the page table and sends it to the L2 TLB, thereby improving the hit efficiency of subsequent L2 TLB queries. Sending the first target page table entry, along with at least one page table entry related to the first target page table entry located in the same cache line and adjacent cache lines, to the local buffer further improves the hit efficiency of subsequent local buffer queries.

[0141] In some embodiments, the L2 TLB is further configured to update the first target page table entry to the L2 TLB; the local buffer is further configured to update the first target page table entry, as well as at least one page table entry associated with the first target page table entry in the same cache line and adjacent cache lines, to the same entry in the local buffer.

[0142] In some embodiments, the local buffer includes a first number of entries, each entry including an entry identifier bit and a second number of page table entry slots; each page table entry slot is used to store a page table entry; the entry identifier bit is used to store an entry identifier.

[0143] In this embodiment of the application, each entry in the local buffer stores multiple related page table entries, so that subsequent queries of related page table entries can be hit, thereby improving the hit rate.

[0144] The following will describe an exemplary application of the embodiments of this application in a real-world application scenario.

[0145] In processor architectures of related technologies, the memory management unit (MMU) is responsible for translating virtual addresses issued by programs into physical addresses. This translation process is typically accomplished by querying page tables, and page table entries (PTEs) are stored in system memory. To accelerate this process, the processor uses a TLB (TLB) to cache recently used PTEs. Related technologies often employ multiple levels of TLBs, such as L1 / L2. L1 TLBs prioritize extremely low hit latency and have relatively small capacity, while L2 TLBs have higher latency but larger capacity and higher set associativity, allowing for a wider range of memory accesses.

[0146] Page table organization inherently exhibits spatial locality: in common architectures (such as x86 / ARM / RISC-V), the last-level page table stores multiple consecutive virtual page steps (PTEs) in a fixed-size cache line (e.g., 64B) (e.g., 8 or more PTEs per line). In application scenarios involving sequential access, linear scans, stack / heap expansion, and access to adjacent data structures within a page, adjacent PTEs in the same cache line are often accessed consecutively. Since the L2 TLB only stores page table entries, subsequent accesses to adjacent PTEs can trigger L2TLB misses, thus reducing hit efficiency.

[0147] In practical implementation, the TLB structure in related technologies has the following drawbacks: Under processor performance loads, such as discrete events, the instruction stream addresses exhibit strong regularity, such as... Figure 4 As shown, sequential access to page table entries is as follows: Figure 5 As shown, this describes the page table entry accessed corresponding to the address of the instruction. Figure 4 and Figure 5 Squares of the same color indicate that page table entries accessed by different instructions are located in the same or adjacent cache lines. For example... Figure 4 As shown, the page table entries corresponding to ae6, ae7, and ae8 are located in the same or adjacent cache lines, while the page table entries corresponding to ade, adf, and ae0 are located in the same or adjacent cache lines. Figure 5As shown, page table entries corresponding to ae0, ae1, ae2, ae3, ae4, ae5, ae6, and ae7 are accessed sequentially, and multiple page table entries are located in the same or adjacent cache lines. It is evident that page table entries accessed multiple times consecutively are concentrated in the same or adjacent cache lines, indicating significant spatial correlation. Observation shows that the lower address bits [2:0] of the instructions are mostly different, indicating weak temporal correlation and few completely identical addresses. Due to spatial correlation, there is a high probability that different page table entries stored in the same cache line will be accessed subsequently.

[0148] Based on the above description, this application provides a heterogeneous parallel L2 TLB circuit structure. This structure deploys a 16-entry fully associative register array that can be queried in parallel on a conventional single-page PTE cache architecture (related to L2 TLB in other technologies), called a local special buffer (corresponding to the local buffer in the aforementioned embodiments). This allows each entry to fully cache page table cache lines containing multiple 4K leaf PTEs and cache prefetched adjacent page table lines to expand physical address coverage. Combined with a pseudo-Least Recently Used (PLRU) replacement strategy, it reduces the L2TLB miss rate in the above scenarios, significantly reduces page table traversal operations, and significantly compresses the average address translation latency, achieving considerable performance improvement. Simultaneously, it is completely transparent to existing RISC-V page table mechanisms and failure processes, allowing for seamless integration and implementation.

[0149] Figure 6 This application provides a two-level address translation cache structure, such as... Figure 6 As shown, the two-level address translation cache structure includes an L2 TLB 121 and a local special buffer 601. The L2 TLB adopts a multi-way set-associative structure, comprising multiple sets. Each set may include four L2 TLB entries 602. Each L2 TLB entry 602 consists of a tag (identifier, corresponding to the entry identifier in the previous embodiment) and a PTE slot (corresponding to the page table entry slot in the previous embodiment), serving as the main translation cache, catering to general access patterns and larger capacity requirements. The local special buffer 601 includes 16 local special buffer entries 603, employing a fully associative structure. Each local special buffer entry 603 consists of a tag and eight PTE slots. The local special buffer 601 aggregates multiple PTEs located in the same cache line from a group of related or adjacent pages into the same entry. Utilizing allocation local associativity, the target page table entry can be directly selected from the entry upon hit, reducing latency for L2 TLB access.

[0150] Figure 7 This is a schematic diagram of a parallel query L2 TLB and a local special buffer provided in an embodiment of this application, as shown below. Figure 7As shown, in the Dc0 stage, the L2 TLB and local special buffer are queried in parallel based on the Virtual Page Number (VPN) parsed from the memory access request; in the Dc1 stage, it is determined whether the L2 TLB and local special buffer are hit; in the Dc2 stage, it is determined whether page table traversal is required based on the query results corresponding to the L2 TLB and local special buffer respectively.

[0151] Figure 8 This is a schematic diagram of a query L2 TLB and local special buffer pipeline and a hit selection process provided in an embodiment of this application, such as... Figure 8 As shown, the process may include the following steps S801 to S805:

[0152] Step S801: Parallel query of L2 TLB and local special buffer;

[0153] Step S802: Determine whether the query results of L2 TLB and local special buffer are both hits; if yes, proceed to step S803; if no, proceed to step S804.

[0154] Step S803: Backfill L1 TLB or perform page table traversal operation and end the current query;

[0155] If both the L2 TLB and the local special buffer are hit, the shortest path is taken, and the query results are returned directly from the local special buffer. The retrieved page table entries are then backfilled into the L1 TLB.

[0156] If both the L2 TLB and the local special buffer are not hit, perform a page table traversal operation, and backfill the traversed page table entries to the L1 I / D TLB and L2 TLB respectively, and update the page table entries stored in the cache line where the traversed page table entries are located to the local special buffer.

[0157] Step S804: Determine whether the local special buffer query result is a hit; if yes, proceed to step S805; if no, proceed to step S803.

[0158] Step S805: Backfill the page table entries that were hit in the local special buffer to L2 TLB.

[0159] If the query result in the local special buffer is a hit, but the query result in the corresponding L2 TLB is a miss, the local special buffer successfully returns the query result to the execution unit in the processor and fills the L2 TLB with the retrieved page table entries. At the same time, the local special buffer fills the L1 TLB with the retrieved page table entries to smooth out subsequent regular hits on the same or adjacent pages.

[0160] Figure 9This is a schematic diagram of backfilling an L2 TLB and a local special cache provided in an embodiment of this application, as shown below. Figure 9 As shown, after the page table variable completes the query for page table entries, a complete cache line containing all page table entries is returned via the bus. The retrieved page table entries are then populated into the L2 TLB in the current cycle. Simultaneously, the entire cache line and the prefetched adjacent cache lines are populated into a local special cache. This populated data can be read in the next cycle for use by query requests. Because the local special cache stores the page table entries of the entire cache line and adjacent cache lines, it can achieve consecutive hits after the first backfill. Furthermore, under the PLRU replacement algorithm, the entire cache line remains active and is not accidentally evicted because different PTE entries are hit, effectively mitigating the frequent misses of the L2 TLB in the aforementioned access scenarios.

[0161] Figure 10 This is a schematic diagram illustrating the average access latency of a memory management unit provided in an embodiment of this application, as shown below. Figure 10 As shown, in scenarios such as astar, bzip2, gcc, gobmk, h264ref, hmmer, libquantum, mcf, omnetpp, perlbench, sjeng, xalancbmk, and average, the memory management unit performs address translation using both the TLB structure in related technologies and the TLB structure in this application. The average access latency of the memory management unit is statistically analyzed. The results show that, in various scenarios, the TLB structure in this application reduces the average access latency of the memory management unit compared to the TLB structure in related technologies.

[0162] Figure 11 This is a schematic diagram illustrating the speedup ratio of the average access latency of a memory management unit provided in an embodiment of this application, as shown below. Figure 11 As shown, the speedup ratio between the average access latency of memory management units using the TLB structure in related technologies and those using the TLB structure in this application is calculated in various scenarios, including astar, bzip2, gcc, gobmk, h264ref, hmmer, libquantum, mcf, omnetpp, perlbench, sjeng, xalancbmk, and average. It can be seen that the memory management unit using the TLB structure in this application has less latency in various scenarios.

[0163] Figure 12 This is a schematic diagram of the missing rate corresponding to a TLB structure provided in an embodiment of this application, such as... Figure 12As shown, the missing rates of TLB structures using related technologies and those using the TLB structure in this application are calculated in scenarios such as astar, bzip2, gcc, gobmk, h264ref, hmmer, libquantum, mcf, omnetpp, perlbench, sjeng, xalancbmk, and average. It can be seen that the TLB structure in this application reduces the missing rate of TLB structures compared to the TLB structures in related technologies.

[0164] Figure 13 This is a schematic diagram illustrating the speedup of the missing data rate corresponding to a TLB structure provided in an embodiment of this application, as shown below. Figure 14 As shown, the speedup ratio between the missing rate of the TLB structure using related technologies and the missing rate of the TLB structure using this application is calculated in scenarios such as astar, bzip2, gcc, gobmk, h264ref, hmmer, libquantum, mcf, omnetpp, perlbench, sjeng, xalancbmk, and average. It can be seen that the TLB structure in this application reduces the missing rate of the TLB structure compared with the TLB structure in related technologies.

[0165] In this embodiment, the TLB structure provided in this application is used to query page table entries. The missing rate decreases in most benchmark tests, with the most significant reduction observed in high-missing-rate scenarios such as libquantum (a quantum computing simulator) and omnetpp (a discrete event network simulator). The average missing rate decreases, indicating that the optimization is universally applicable across different workloads, rather than being effective only in individual cases. This further reduces the overall end-to-end latency of the memory management unit. The latency of the memory management unit in most benchmark tests decreases after optimization, resulting in a decrease in average latency, reflected in a reduction of TLB-related overhead in the memory access path. Furthermore, the decrease in missing rate means fewer page table traversals and L2C / DRAM accesses, reducing memory access power consumption and bus usage. Due to the reduction in TLB-related retries or rollbacks, the idle and invalid work of backend units is also correspondingly reduced.

[0166] This application provides a processor, such as... Figure 14 As shown, the processor 1400 includes the memory management unit 100 and the execution unit 1401 described above. The execution unit 1401 is used to generate memory access requests and send the memory access requests to the address translation and control module in the memory management unit.

[0167] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0168] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0169] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0170] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this application may all be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the integrated unit may be implemented in hardware or in a combination of hardware and software functional units.

[0171] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0172] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0173] The above are merely embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A memory management unit, characterized in that, The memory management unit includes an address translation and control module and a translation lookup buffer (TLB) structure; the TLB structure includes a two-level translation lookup buffer (L2 TLB) and a local buffer; the local buffer adopts a fully associative structure, and the local buffer includes multiple entries, each of which stores a set of related page table entries, wherein: The address translation and control module is used to send the first virtual address corresponding to the received memory access request to the local buffer and the L2 TLB; The local buffer is used to query a first target page table entry corresponding to the first virtual address from a plurality of entries based on the first virtual address, and to determine a first query result corresponding to the memory access request based on whether the first target page table entry is found from the plurality of entries; the first query result includes the physical address corresponding to the first virtual address or a query miss; The L2 TLB is used to query the first target page table entry corresponding to the first virtual address based on the first virtual address; the L2 TLB and the local buffer are queried in parallel.

2. The memory management unit according to claim 1, characterized in that, The first virtual address includes an entry identifier and an offset; The local buffer is further configured to determine a target entry from a plurality of entries based on the entry identifier; and to determine a first target page table entry corresponding to the first virtual address from a set of related page table entries stored in the target entry based on the offset.

3. The memory management unit according to claim 1, characterized in that, The local buffer is also used to query a second target page table entry corresponding to the second virtual address from multiple entries in response to a first query result including the physical address corresponding to the first virtual address, based on the second virtual address sent by the address translation and control module; The local buffer is further configured to determine, based on the second target page table entry, that the second query result corresponding to the second virtual address is the physical address corresponding to the second virtual address; the second target page table entry is a page table entry related to the first page table entry in the same entry.

4. The memory management unit according to claim 1, characterized in that, The L2 TLB is further configured to determine, when a first target page table entry corresponding to the first virtual address is found based on the first virtual address, that the third query result corresponding to the memory access request includes the physical address corresponding to the first virtual address; If no first target page table entry corresponding to the first virtual address is found based on the first virtual address, the third query result is determined to include a query miss.

5. The memory management unit according to claim 4, characterized in that, The local buffer is further configured to backfill the first target page table entry into the L2 TLB when the first query result includes the physical address corresponding to the first virtual address and the third query result includes a query miss.

6. The memory management unit according to claim 4, characterized in that, The memory management unit further includes a page table traverser, wherein: The page table traverser is configured to, in response to the first query result including a query miss and the third query result including a query miss, query from the page table based on the first virtual address a first target page table entry corresponding to the first virtual address, and at least one page table entry related to the first target page table entry located in the same cache line and adjacent cache lines. The page table traverser is further configured to send the first target page table entry to the L2 TLB, and send the first target page table entry, as well as at least one related page table entry located in the same cache line and adjacent cache lines as the first target page table entry, to the local buffer.

7. The memory management unit according to claim 6, characterized in that, The L2 TLB is also used to update the first target page table entry to the L2 TLB; The local buffer is further configured to update the first target page table entry, as well as at least one page table entry related to the first target page table entry in the same cache line and adjacent cache lines, to the same entry in the local buffer.

8. The memory management unit according to any one of claims 1 to 7, characterized in that, The local buffer includes a first number of entries, each entry including an entry identifier bit and a second number of page table entry slots; each page table entry slot is used to store a page table entry; the entry identifier bit is used to store an entry identifier.

9. A memory management method, characterized in that, This is applied to a memory management unit, which includes an address translation and control module and a translation lookup buffer (TLB) structure. The TLB structure includes a second-level translation lookup buffer (L2 TLB) and a local buffer. The local buffer adopts a fully associative structure and includes multiple entries, each of which stores a set of related page table entries, including: The address translation and control module sends the first virtual address corresponding to the received memory access request to the local buffer and the L2 TLB; The local buffer queries a first target page table entry corresponding to the first virtual address from a plurality of entries based on the first virtual address, and determines a first query result corresponding to the memory access request based on whether the first target page table entry is found from the plurality of entries; the first query result includes the physical address corresponding to the first virtual address or a query miss; The L2 TLB queries the first target page table entry corresponding to the first virtual address based on the first virtual address, and the L2 TLB and the local buffer perform the query in parallel.

10. The method according to claim 9, characterized in that, The first virtual address includes an entry identifier and an offset. The local buffer, based on the first virtual address, queries a first target page table entry corresponding to the first virtual address from a plurality of entries, including: The local buffer determines a target entry from a plurality of entries based on the entry identifier; and determines a first target page table entry corresponding to the first virtual address from a set of related page table entries stored in the target entry based on the offset.

11. The method according to claim 9, characterized in that, The method further includes: The local buffer responds to the first query result, which includes the physical address corresponding to the first virtual address, and queries the second target page table entry corresponding to the second virtual address from the multiple entries based on the second virtual address sent by the address translation and control module. The local buffer determines the second query result corresponding to the second virtual address as the physical address corresponding to the second virtual address based on the second target page table entry; the second target page table entry is a page table entry related to the first page table entry in the same entry.

12. The method according to claim 9, characterized in that, The L2 TLB queries the first target page table entry corresponding to the first virtual address based on the first virtual address, including: If the L2 TLB finds a first target page table entry corresponding to the first virtual address based on the first virtual address, it determines that the third query result corresponding to the memory access request includes the physical address corresponding to the first virtual address; if it does not find a first target page table entry corresponding to the first virtual address based on the first virtual address, it determines that the third query result includes a query miss.

13. The method according to claim 12, characterized in that, The method further includes: If the first query result includes the physical address corresponding to the first virtual address, and the third query result includes a query miss, the local buffer will backfill the first target page table entry into the L2 TLB.

14. The method according to claim 12, characterized in that, The memory management unit further includes a page table traverser, and the method further includes: In response to the first query result including a query miss and the third query result including a query miss, the page table traverser queries the page table for a first target page table entry corresponding to the first virtual address, and at least one page table entry related to the first target page table entry located in the same cache line and adjacent cache lines. The page table traverser sends the first target page table entry to the L2 TLB, and sends the first target page table entry, as well as at least one related page table entry located in the same cache line and adjacent cache lines as the first target page table entry, to the local buffer.

15. The method according to claim 14, characterized in that, The method further includes: The L2 TLB updates the first target page table entry to the L2 TLB; The local buffer updates the first target page table entry, as well as at least one page table entry related to the first target page table entry in the same cache line and adjacent cache lines, to the same entry in the local buffer.

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