In-memory differential computing method and architecture based on ferroelectric random access memory
By implementing parallel differential computation within FeRAM memory cells and using polarization reversal charge as the result, the problems of high latency and energy consumption in traditional differential operations are solved, improving computational efficiency and system integration, and simplifying hardware design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- EAST CHINA NORMAL UNIV
- Filing Date
- 2026-02-12
- Publication Date
- 2026-06-09
Smart Images
Figure CN122177175A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of in-memory computing technology, and in particular to an in-memory differential computing method and architecture based on ferroelectric random access memory (FeRAM). Background Technology
[0002] In-memory computing technology, as a core direction for breaking through the performance bottleneck of the traditional von Neumann architecture, has become a research hotspot in the semiconductor and computer fields. By directly integrating computing functions into storage units, it fundamentally reduces the latency and energy consumption of data transfer between memory and processor, giving it irreplaceable advantages in high-performance computing, artificial intelligence, embedded devices, and other scenarios. Differential operations, as the core fundamental operation of differential calculus, are the core support for many key applications such as function gradient solving, image edge extraction, signal rate of change analysis, and neural network gradient descent training. Its computational efficiency directly determines the overall performance of the related system.
[0003] In existing technologies, differential computation primarily relies on a separate "storage-transfer-computation" architecture: the data to be computed is first stored in a separate memory; during computation, a microcontroller unit or central processing unit reads the data from the memory, performs differential computation through dedicated circuitry, and the result is written back to memory. This architecture has three inherent drawbacks: first, frequent data transfer between memory and processor generates significant invalid transmission delays, especially in differential scenarios with high-frequency weight updates, where accumulated delays severely impact system real-time performance; second, data transmission is accompanied by significant energy consumption, becoming a major bottleneck for low-power device applications; and third, the separate storage and computation modules require more hardware resources, leading to low system integration and increased costs. Therefore, developing a simple, low-power in-memory computing solution adapted to differential computation has become a pressing technical challenge in this field. Summary of the Invention
[0004] To address the aforementioned technical problems, this invention provides an in-memory differential computation method and architecture based on ferroelectric random access memory (FeRAM). Utilizing the physical characteristics of FeRAM, parallel differential computation is performed directly within the memory cell, while also possessing advantages such as low power consumption, high speed, and high integration, thus breaking through the performance bottleneck of traditional differential operation architectures.
[0005] The technical solution adopted by this invention to solve its technical problem is: an in-memory differential calculation method based on ferroelectric random access memory, comprising the following steps: Pre-defined correspondence between binary logic and pulse polarity; Convert the subtrahend and minuend in the difference operation into their corresponding pulse sequences; Apply the pulse sequence corresponding to the subtraction to the storage cell of the ferroelectric random access memory to complete the subtraction storage and initial polarization; A pulse sequence corresponding to the minuend is applied to the storage cell of the same ferroelectric random access memory to trigger ferroelectric domain reversal; The polarization reversal charge generated by the ferroelectric domain reversal in the storage cell of the ferroelectric random access memory is read, and the polarization reversal charge is directly used as the result of the difference calculation between the subtrahend and the minuend.
[0006] As a further improvement of the present invention, the correspondence between the binary logic and the pulse polarity (1) is as follows: The binary representation of positive numbers: a negative pulse corresponds to writing logic "1", and a positive pulse corresponds to writing logic "0". When a logic "1" is written to the memory cell of the same ferroelectric random access memory to represent the subtrahend using a negative pulse, and then a logic "0" is written to represent the minuend using a positive pulse, a positive polarization reversal current will be obtained, which is "1-0=1". The binary representation of negative numbers: a negative pulse corresponds to writing logic "0", and a positive pulse corresponds to writing logic "-1". When a positive pulse is first used to write logic "-1" to represent the subtrahend in the same ferroelectric random access memory cell, and then a negative pulse is used to write logic "0" to represent the minuend, a negative polarization reversal current is obtained, which is "-1-0=-1".
[0007] As a further improvement of the present invention, the correspondence between the binary logic and the pulse polarity (2) is as follows: The binary representation of positive numbers: a positive pulse corresponds to logic "1", and a negative pulse corresponds to logic "0"; When a logic "1" is first written to the storage cell of the same ferroelectric random access memory to represent the minuend using a positive pulse, and then a logic "0" is written to represent the subtrahend using a negative pulse, a negative polarization reversal current will be obtained, which is "0-1=-1". The binary representation of negative numbers: a negative pulse corresponds to writing logic "-1", and a positive pulse corresponds to writing logic "0". When a negative pulse is first used to write logic "-1" to represent the minuend in the same ferroelectric random access memory cell, and then a positive pulse is used to write logic "0" to represent the subtrahend, a positive polarization reversal current will be obtained, which is "0-(-1)=1".
[0008] As a further improvement of the present invention, when two pulses with the same polarity are applied to the same storage cell of the ferroelectric random access memory, the storage cell of the ferroelectric random access memory does not undergo polarization reversal, and the current is "0".
[0009] As a further improvement of the present invention, the steps of subtraction storage and initial polarization include: selecting a target storage cell in the ferroelectric random access memory through a word line, applying a pulse sequence corresponding to the subtraction to the target storage cell, thereby completing the subtraction storage and initial polarization; The step of triggering ferroelectric domain inversion includes: maintaining the word line strobe state, applying a pulse sequence corresponding to the minuend to the same target memory cell, thereby triggering ferroelectric domain inversion.
[0010] As a further improvement of the present invention, the in-memory differential calculation method supports parallel differential calculation: by selecting the target row in the ferroelectric random access memory through word lines, a pulse sequence is applied to all memory cells of the target row in parallel, and the polarization reversal charge of all memory cells is read synchronously to realize synchronous differential calculation of multiple columns of data.
[0011] As a further improvement of the present invention, the step of reading the polarization reversal charge includes: performing an integral operation on the polarization reversal current output by the storage cell of the ferroelectric random access memory through an analog-to-digital converter, thereby obtaining the polarization reversal charge.
[0012] This invention also provides an in-memory differential architecture based on ferroelectric random access memory, wherein the in-memory differential architecture is used to implement the in-memory differential calculation method based on ferroelectric random access memory as described above, including: A ferroelectric random access memory array, wherein the ferroelectric random access memory array is composed of multiple memory cells; Bit line group, used to apply pulse sequence corresponding to data to the storage unit; Source line group, used to output the polarization reversal current of the memory cell; Word lines are storage units used to select the target row; The in-memory differential architecture achieves parallel in-memory differential computation through the ferroelectric domain inversion of the memory cell, and the polarization inversion charge generated during the ferroelectric domain inversion process is directly used as the differential computation result.
[0013] As a further improvement of the present invention, the bit line group and the source line group are parallel, and the word line group is perpendicular to the source line group; Alternatively, the bit line group may be perpendicular to the source line group, and the word line group may be perpendicular to or parallel to the source line group.
[0014] As a further improvement of the present invention, the ferroelectric layer of the memory cell adopts at least one of the following ferroelectric materials: HZO, AlScN, PZT, BFO, PMNPT, BTO; the gating transistor of the memory cell adopts at least one of the following: silicon-based complementary metal-oxide transistor and oxide thin film transistor.
[0015] The beneficial effects of this invention are as follows: This invention provides an in-memory differential calculation method and architecture based on ferroelectric random access memory. By pre-setting the correspondence between binary logic and pulse polarity, the subtrahend and minuend are converted into pulse sequences and applied sequentially to the FeRAM storage cells. The polarization reversal charge is directly used as the differential result, fundamentally eliminating the separate process of "data storage-transfer-computation" in traditional differential operations. This avoids the additional latency and energy consumption caused by frequent data transfer between memory and processor, significantly improving the efficiency of differential calculation and energy utilization. At the same time, the physical characteristics of FeRAM are used to achieve the integration of storage and computation, eliminating the need to build additional dedicated computing circuits, simplifying the system structure, reducing hardware complexity, and ensuring the simplicity of the calculation process and the accuracy of the results through the direct correlation between the polarization reversal charge and the differential result. This provides core methodological support for the efficient implementation of scenarios such as gradient solving and image edge extraction. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a flowchart of the in-memory differential calculation method based on ferroelectric random access memory of the present invention; Figure 2 This is a schematic diagram of the analog current output calculated by in-memory differential calculation based on ferroelectric random access memory according to the present invention; Figure 3 This is a schematic diagram of the in-memory differential architecture based on ferroelectric random access memory of the present invention; Figure 4 This is a computational example diagram of the in-memory differential architecture based on ferroelectric random access memory of the present invention; Figure 5 These are three digital representations of the differential computation within a ferroelectric random access memory (RAM) according to the present invention. Figure 6 In the diagram, 'a' is an example of in-memory differential computation mentioned in Application Example 1, and 'be' is a schematic diagram of the gradient of the in-memory differential architecture computation function z=sin(2πx)cos(2πy) based on ferroelectric random access memory. Figure 7 This is a schematic diagram illustrating the image edge extraction method based on the in-memory differential calculation method of ferroelectric random access memory according to the present invention. Detailed Implementation
[0018] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0019] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.
[0020] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0021] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.
[0022] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.
[0023] Example 1
[0024] See Figure 1 and Figure 2 This invention provides an in-memory differential calculation method based on ferroelectric random access memory, comprising the following steps: S1, pre-defined correspondence between binary logic and pulse polarity; S2 converts the subtrahend and minuend in the difference operation into corresponding pulse sequences; S3, apply the pulse sequence corresponding to the subtraction to the storage cell of the ferroelectric random access memory to complete the subtraction storage and initial polarization; S4, apply the pulse sequence corresponding to the minuend to the memory cell of the same ferroelectric random access memory to trigger ferroelectric domain reversal; S5 reads the polarization reversal charge generated by the ferroelectric domain reversal in the storage cell of the ferroelectric random access memory. The polarization reversal charge is directly used as the result of the difference calculation between the subtrahend and the minuend.
[0025] This invention, by pre-setting the correspondence between binary logic and pulse polarity, converts the subtrahend and minuend into pulse sequences and applies them sequentially to FeRAM storage cells. It directly uses the polarization-inverted charge as the difference result, fundamentally eliminating the traditional separate process of "data storage-transfer-computation" in differential operations. This avoids the additional latency and energy consumption caused by frequent data transfer between memory and processor, significantly improving the efficiency and energy utilization of differential computation. Simultaneously, it utilizes the physical characteristics of FeRAM to achieve integrated storage and computation, eliminating the need for dedicated computation circuits, simplifying the system structure, reducing hardware complexity, and ensuring the simplicity of the computation process and the accuracy of the results through the direct correlation between the polarization-inverted charge and the difference result. This provides core methodological support for the efficient implementation of subsequent gradient solving, image edge extraction, and other scenarios.
[0026] In step S1, the correspondence between binary logic and pulse polarity is as follows: a negative pulse corresponds to writing logic "1", and a positive pulse corresponds to writing logic "0".
[0027] like Figure 2 As shown, when a logic "1" is first written to a memory cell of the same ferroelectric random access memory using a negative pulse, and then a logic "0" is written to it using a positive pulse, i.e. P up to P down This indicates that the polarization direction of the ferroelectric domains is from "upward" ( P up Switch to "Down" P down Therefore, a positive polarization reversal current is obtained, which is "1-0=1". Similarly, when a logic "0" is written to a memory cell of the same ferroelectric random access memory with a positive pulse and then a logic "1" is written with a negative pulse, i.e. P down to P up This indicates that the polarization direction of the ferroelectric domains is from "downward" ( P down Switch to "Up" P upWhen the polarity of two pulses input to the same ferroelectric random access memory cell is in the same direction, a negative polarization reversal current is obtained, i.e., "0-1=-1". P down to P down or P up to P up When the ferroelectric domains undergo polarization reversal, the current is "0".
[0028] Of course, in other embodiments of the present invention, the correspondence between binary logic and pulse polarity can also be: a positive pulse corresponds to logic "1", and a negative pulse corresponds to logic "0". In this case, the pulse for the minuend needs to be input first, followed by the pulse for the subtrahend. When a negative pulse is first used to write logic "0" to represent the minuend in the same ferroelectric random access memory (RAM) cell to represent logic "1", and then a positive pulse is used to write logic "1" to represent logic "subtrahend", a negative polarization reversal current is obtained, i.e., "1-0=1"; when a positive pulse is first used to write logic "1" to represent the minuend in the same ferroelectric RAM cell to represent logic "0", and then a negative pulse is used to write logic "0" to represent logic "subtrahend", a positive polarization reversal current is obtained, i.e., "0-1=-1". Furthermore, when the polarities of the two input pulses in the same ferroelectric RAM cell are in the same direction, i.e. P down to P down or P up to P up When the ferroelectric domains are unpolarized and reversed, the current is "0". It is evident that the pulse input order for the minuend and subtrahend is exactly reversed in both logic modes.
[0029] This invention clarifies the specific correspondence between "negative pulses correspond to logic '1' and positive pulses correspond to logic '0'" or "positive pulses correspond to logic '1' and negative pulses correspond to logic '0'", and refines the correlation between polarization reversal current and differential results under different writing orders. This enables a precise mapping between binary logic and the physical polarization response of FeRAM. Positive and negative polarization reversal currents can directly correspond to the positive and negative values of the differential results without additional signal conversion or decoding steps, significantly improving the intuitiveness and recognizability of the differential results and reducing the difficulty of result reading and quantization. At the same time, the clarification of this specific correspondence significantly enhances the controllability of the calculation process, effectively avoiding calculation errors caused by ambiguity in logic definitions, ensuring high precision of differential operations, and providing a clear and reliable operational basis for the engineering implementation of the method.
[0030] Further, in step S3, the subtraction storage and initial polarization steps include: selecting the target memory cell in the ferroelectric random access memory through word lines, applying the pulse sequence corresponding to the subtrahend to the target memory cell, thereby completing the subtraction storage and initial polarization. In step S4, the step of triggering ferroelectric domain reversal includes: maintaining the word line selection state, applying the pulse sequence corresponding to the minuend to the same target memory cell, thereby triggering ferroelectric domain reversal. By selecting the target memory cell through word lines and maintaining the selection state to complete two pulse applications, the memory cell to be computed can be accurately located, ensuring that the pulse sequences of the subtrahend and minuend are accurately applied to the same memory cell, providing a key guarantee for the effective occurrence of polarization reversal and the accuracy of the difference result; at the same time, the introduction of the word line selection mechanism makes the operation of the memory cell highly controllable, laying the foundation for the subsequent implementation of parallel computing.
[0031] This invention provides an in-memory differential computation method that supports parallel differential computation: by using word lines to select the target row in the ferroelectric random access memory, a pulse sequence is applied in parallel to all memory cells in that target row, and the polarization inversion charge of all memory cells is read synchronously, thus achieving synchronous differential computation of multiple columns of data. This invention achieves parallel differential computation of multiple columns of data based on the word line-selected target row mechanism. It can synchronously apply pulse sequences to all memory cells in the same row and read the polarization inversion charge, significantly improving the processing throughput of large-scale data differential operations. Compared with the serial computation mode, the computational efficiency increases linearly with the number of columns. It is particularly suitable for scenarios requiring batch processing of data, such as solving the gradient of two-dimensional elliptic equations and differencing image pixel matrices, providing an efficient solution for high-performance, low-power differential computation requirements.
[0032] Furthermore, the step of reading the polarization reversal charge in this invention includes: performing an integral operation on the polarization reversal current output by the storage unit of the ferroelectric random access memory through an analog-to-digital converter to obtain the polarization reversal charge. This can convert the instantaneous polarization reversal current into stable and quantifiable charge data, effectively avoiding noise interference and numerical fluctuations that may occur during the direct current reading process, and significantly improving the measurement accuracy and stability of the differential results.
[0033] Example 2
[0034] See Figure 3 The present invention also provides an in-memory differential architecture based on ferroelectric random access memory. The in-memory differential architecture is used to implement the in-memory differential calculation method based on ferroelectric random access memory as described in Embodiment 1, including: ferroelectric random access memory array, bit line group (BL), source line group (SL) and word line group (WL).
[0035] The ferroelectric random access memory array consists of multiple memory cells, and each memory cell includes a gating transistor.
[0036] The bit line group consists of multiple parallel wires connected to the drain of the select transistor, used to apply pulse sequences corresponding to the data (i.e., subtrahend and minuend) to the memory cells. The source line group consists of multiple parallel wires connected to the source of the select transistor, used to output the polarization reversal current of the memory cells. The word line group is used to select the memory cells of the target row. It consists of multiple parallel wires connected to the gate of the select transistor. Each wire corresponds to a row of memory cells in the FeRAM array. Its core function is to "select" all FeRAM memory cells in the target row by applying voltage pulses, enabling them to perform data writing, reading, or differential calculations. Rows that are not selected remain dormant and do not respond to signals from the bit lines / source lines.
[0037] Preferably, in this embodiment, the bit line group and the source line group are parallel, and the word line group is perpendicular to the source line group. This optimized and efficient layout can maximize the efficiency of parallel computing.
[0038] Of course, the in-memory differential architecture of this invention can also adopt the traditional FeRAM layout architecture, for example, the bit line group is perpendicular to the source line group, and the word line group is perpendicular to or parallel to the source line group. Adaptation can be achieved without making major modifications to the existing FeRAM production line or hardware design, which significantly reduces the application threshold and R&D conversion cost of the architecture.
[0039] In this invention, the ferroelectric layer of the storage cell adopts at least one of the following ferroelectric materials: HZO (hafnium zirconium oxide), AlScN (aluminum scandium nitrogen), PZT (lead zirconate titanate), BFO (bismuth ferrite), PMNPT (lead magnesium niobate-lead titanate), and BTO (barium titanate).
[0040] Preferably, in this embodiment, the ferroelectric layer of the memory cell is made of HZO, which has a fatigue performance of up to 10. 12 The subpolarity reversal is far superior to traditional storage materials. At the same time, after each polarity reversal, it can automatically read the weights stored in the previous storage and synchronously store the weights corresponding to the new read pulses, without the need for additional storage control logic, providing an ideal hardware foundation for achieving efficient differential operations.
[0041] Alternatively, the gating transistor of the memory cell can be a silicon-based complementary metal-oxide transistor or an oxide thin-film transistor, etc.
[0042] The in-memory differential architecture achieves parallel in-memory differential computation through the ferroelectric domain inversion of the storage cells. The polarization inversion charge generated during the ferroelectric domain inversion process is directly used as the differential computation result.
[0043] like Figure 4As shown, for example, when calculating the result of X2-X5+X4-X5+X6-X5+X8-X5, first, the value of X is represented entirely in binary. At time t0, WL0 is turned on, and the pulse corresponding to X2 is input in parallel to the corresponding binary bit in BL, writing X2. A similar operation is performed, writing the states of X4, X6, and X8 in BL1 to BL3. Then, WL is turned on simultaneously, and the pulse corresponding to X5 is input to the corresponding binary bit in BL, obtaining the calculation result of X2-X5+X4-X5+X6-X5+X8-X5 on SL.
[0044] Example 3
[0045] This embodiment specifies three digital representations of the in-memory differential calculation method based on ferroelectric random access memory.
[0046] Number representation method 1: To verify the feasibility of the proposed in-memory differential computation method based on ferroelectric random access memory, a 16-bit differential computation unit was first constructed based on 32 HZO FeRAM memory cells, of which 16 represent positive weights (Positive 16-bit). -16 Up to 2 -1 Represents a decimal between 0 and 1, 2 0 Up to 2 15 Represents numbers between 0 and 65535; 16 represent negative weights (Negative 16 bits), -2 -16 to -2 -1 -2 represents a decimal between 0 and -1. 0 to -2 15 It represents a number between 0 and -65535.
[0047] like Figure 5 As shown in diagram a, when using 16 HZO FeRAM memory cells to represent positive and negative 16-bit binary numbers for differential operations, the 8 HZO FeRAM memory cells in the positive (and negative) half-regions are written with "0" using positive (and negative) pulses and "1" using negative (and positive) pulses. The operation process consists of two steps: first, a 16-bit pulse sequence is input to represent the subtrahend (and this value is stored); then, another pulse sequence is input to represent the minuend. The polarization reversal current is read as the result of the differential operation; a positive polarization reversal current is counted as 1, a negative polarization reversal current as -1, and a current without polarization reversal as 0.
[0048] Number representation method two: like Figure 5 As shown in b, the FP16-bit representation is used:
[0049] Where b 10-iIt represents the binary value (0 or 1) of the mantissa bits (Bits 10 to 0), where e = 1 to 30 is the value of the exponent. The entire number representation differs from FP16, which divides the number into positive and negative parts, with the negative part having the opposite sign.
[0050] Number representation method three: like Figure 5 As shown in c, the FP32-bit representation is used:
[0051] Where b 23-i It represents the binary value (0 or 1) of the mantissa bits (Bits 23 to 0), where e = 1 to 254 is the value of the exponent. The entire number representation differs from FP32, which uses two parts, positive and negative, with the negative part having the opposite sign.
[0052] The in-memory differential calculation method and in-memory differential architecture described in this invention can be used in scenarios such as mathematical function gradient solving, image edge extraction, neural network gradient descent calculation, and sensor data change rate analysis.
[0053] Application Example 1 This application example is based on a 16-bit binary representation. Using 0.6443125 - (-0.3515625) as an example, differential calculations are performed. The pulse voltage sequence of 0.6443125 is represented as a positive half-region of 2. -8 2 -6 2 -3 2 -1 A negative pulse (representing "1") and all positive pulses (representing "0") represent the entire negative half of the signal; a pulse voltage sequence of -0.3515625 pulses has all positive pulses in the positive half of the signal (representing "0") and all positive pulses in the negative half of the signal (representing "0"). -2 2 -4 2 -5 2 -7 A positive pulse represents "-1", and all other pulses are negative pulses, representing "0".
[0054] like Figure 6 As shown in Figure a, when performing the differential operation, first input a pulse voltage sequence of 0.6443125, then input a pulse voltage sequence of -0.3515625. This means that 0.6443125 minus -0.3515625 results in a positive half-zone weighting of 2. -8 2 -6 2 -3 2 -1 The positive polarization reversal current output by the HZO FeRAM indicates that these bits are all "1", and the weighted average of the negative half-region is 2. -2 2 -4 2 -5 2-7 The positive polarization reversal current output by the HZO FeRAM indicates that these bits are all "1". Therefore, the result of subtracting -0.3515625 from 0.6443125 is 1×2. -8 1×2 -6 1×2 -3 1×2 -1 1×2 -2 1×2 -4 1×2 -5 and 1×2 -7 The weighted sum of these values equals 0.99609375.
[0055] The gradient of the two-dimensional elliptic equation was calculated using the 32-bit differential strategy described above. Figure 6 b is the function z = sin(2πx)cos(2πy) that needs to be differentiated, with the calculation interval x, y ∈ (0.01, 0.99) and a step size Δx = Δy = 0.01. Using the forward difference method, the values of Z at corresponding coordinates (x, y) are input sequentially to obtain the difference between two adjacent coordinates Z. Then, the first derivative in the x-direction is equal to:
[0056] Figure 6 c is the first-order partial derivative in the x-direction measured by HZO FeRAM, and the range of the derivative is x,y∈[0.015,0.985]. The expression for the first-order partial derivative in the y-direction is:
[0057] Figure 6 d is the first-order partial derivative in the y-direction measured by HZO FeRAM, with the derivative ranging from x,y ∈ [0.015, 0.985]. The magnitude of the gradient ( Figure 6 e) Calculated by the following formula for x:
[0058] The modulus of the gradient quantizes the degree of change of a function at a certain point. Figure 6 The corresponding streamline diagram is also drawn in e, with arrows pointing from the direction of small gradient to the direction of large gradient.
[0059] Application Example 2 This application example is based on an 8-bit binary number representation. Figure 7 Edge extraction was performed, and the essence of edge extraction is computation. Figure 7 The gradient of a, and the extracted edge structure are as follows: Figure 7 As shown in b.
[0060] The same or similar parts between the various embodiments in this specification can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments.
[0061] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A method for in-memory differential computation based on ferroelectric random access memory, characterized in that, Includes the following steps: Pre-defined correspondence between binary logic and pulse polarity; Convert the subtrahend and minuend in the difference operation into their corresponding pulse sequences; Apply the pulse sequence corresponding to the subtraction to the storage cell of the ferroelectric random access memory to complete the subtraction storage and initial polarization; A pulse sequence corresponding to the minuend is applied to the storage cell of the same ferroelectric random access memory to trigger ferroelectric domain reversal; The polarization reversal charge generated by the ferroelectric domain reversal in the storage cell of the ferroelectric random access memory is read, and the polarization reversal charge is directly used as the result of the difference calculation between the subtrahend and the minuend.
2. The memory differential calculation method based on ferroelectric random access memory according to claim 1, characterized in that, The correspondence between the binary logic and the pulse polarity is as follows: The binary representation of positive numbers: a negative pulse corresponds to writing logic "1", and a positive pulse corresponds to writing logic "0". When a logic "1" is first written with a negative pulse to represent the subtrahend in the same ferroelectric random access memory cell, and then a logic "0" is written with a positive pulse to represent the minuend, a positive polarization reversal current is obtained, which is "1-0=1". The binary representation of the negative number region: a negative pulse corresponds to writing logic "0", and a positive pulse corresponds to writing logic "-1"; When a positive pulse is used to write logic "-1" to represent the subtrahend in the same ferroelectric random access memory cell, and then a negative pulse is used to write logic "0" to represent the minuend, a negative polarization reversal current is obtained, which is "-1-0=-1".
3. The memory differential calculation method based on ferroelectric random access memory according to claim 1, characterized in that, The correspondence between the binary logic and the pulse polarity is as follows: The binary representation of positive numbers: a positive pulse corresponds to logic "1", and a negative pulse corresponds to logic "0". When a logic "1" is first written to the storage cell of the same ferroelectric random access memory to represent the minuend using a positive pulse, and then a logic "0" is written to represent the subtrahend using a negative pulse, a negative polarization reversal current will be obtained, which is "0-1=-1". The binary representation of negative numbers: a negative pulse corresponds to writing logic "-1", and a positive pulse corresponds to writing logic "0". When a negative pulse is first used to write logic "-1" to represent the minuend in the same ferroelectric random access memory cell, and then a positive pulse is used to write logic "0" to represent the subtrahend, a positive polarization reversal current will be obtained, which is "0-(-1)=1".
4. The in-memory differential calculation method based on ferroelectric random access memory according to claim 2 or 3, characterized in that, When two pulses with the same polarity are applied to the same memory cell of the ferroelectric random access memory, the memory cell does not undergo polarization reversal, and the current is "0".
5. The memory differential calculation method based on ferroelectric random access memory according to claim 1, characterized in that, The steps of subtraction storage and initial polarization include: selecting a target storage cell in the ferroelectric random access memory through a word line, applying a pulse sequence corresponding to the subtraction to the target storage cell, thereby completing the subtraction storage and initial polarization; The step of triggering ferroelectric domain inversion includes: maintaining the word line strobe state, applying a pulse sequence corresponding to the minuend to the same target memory cell, thereby triggering ferroelectric domain inversion.
6. The memory differential calculation method based on ferroelectric random access memory according to claim 5, characterized in that, The in-memory differential calculation method supports parallel differential calculation: by selecting the target row in the ferroelectric random access memory through word lines, a pulse sequence is applied to all memory cells of the target row in parallel, and the polarization reversal charge of all memory cells is read synchronously to realize synchronous differential calculation of multiple columns of data.
7. The memory differential calculation method based on ferroelectric random access memory according to claim 1, characterized in that, The steps for reading the polarization reversal charge include: integrating the polarization reversal current output from the storage cell of the ferroelectric random access memory using an analog-to-digital converter to obtain the polarization reversal charge.
8. A differential architecture based on ferroelectric random access memory, characterized in that, The in-memory differential architecture is used to implement the in-memory differential computation method based on ferroelectric random access memory as described in claim 1, including: A ferroelectric random access memory array, wherein the ferroelectric random access memory array is composed of multiple memory cells; Bit line group, used to apply pulse sequence corresponding to data to the storage unit; Source line group, used to output the polarization reversal current of the memory cell; Word lines are storage units used to select the target row; The in-memory differential architecture achieves parallel in-memory differential computation through the ferroelectric domain inversion of the memory cell, and the polarization inversion charge generated during the ferroelectric domain inversion process is directly used as the differential computation result.
9. The in-memory differential architecture based on ferroelectric random access memory according to claim 8, characterized in that, The bit line group and the source line group are parallel, and the word line group is perpendicular to the source line group; Alternatively, the bit line group may be perpendicular to the source line group, and the word line group may be perpendicular to or parallel to the source line group.
10. The in-memory differential architecture based on ferroelectric random access memory according to claim 8, characterized in that, The ferroelectric layer of the memory cell uses at least one of the following ferroelectric materials: HZO, AlScN, PZT, BFO, PMNPT, BTO; the gate transistor of the memory cell uses at least one of the following: silicon-based complementary metal-oxide transistor and oxide thin film transistor.