Memory device and programming operations thereof

Abstract

In certain aspects, a memory device includes an array of memory cells, word lines respectively coupled to rows of the array of memory cells, and a peripheral circuit coupled to the array of memory cells through the word lines. The peripheral circuit is configured to, in a first cycle of a program operation, after applying a verify voltage on a selected word line of the word lines, apply a post pulse voltage on the selected word line, ramp down a voltage on the selected word line from the post pulse voltage to a first supply voltage (Vdd), and subsequently ramp up the voltage on the selected word line from the first supply voltage to a first bias voltage.

Description

Technical Field

[0001] This disclosure relates to storage devices and their operating methods. Background Technology

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Flash memory can perform various operations, such as reading, programming (writing), and erasing. For NAND flash memory, erasure operations can be performed at the block level, and programming or reading operations can be performed at the page level. Summary of the Invention

[0003] In one aspect, a storage device includes: a memory cell array; word lines respectively coupled to rows of the memory cell array; and peripheral circuitry coupled to the memory cell array via the word lines. The peripheral circuitry is configured to: in a first cycle of a programming operation, after applying a verification voltage to a select word line in the word lines, apply a post-pulse voltage to the select word line, slope the voltage on the select word line down from the post-pulse voltage to a first supply voltage (Vdd), and then slope the voltage on the select word line up from the first supply voltage to a first bias voltage.

[0004] In some implementations, in order to immediately ramp up the voltage on the select word line, the peripheral circuitry is configured to ramp up the voltage on the select word line once the voltage on the select word line reaches the first supply voltage.

[0005] In some implementations, the peripheral circuitry is further configured to apply a programming voltage to the select word line after the first bias voltage in a second cycle immediately following the first cycle of the programming operation.

[0006] In some embodiments, the peripheral circuitry is further configured to: in the first cycle of the programming operation, reduce the voltage on the unselected word line from the pass voltage to the first supply voltage, and then immediately increase the voltage on the unselected word line from the first supply voltage to a second bias voltage not greater than the first bias voltage.

[0007] In some implementations, the voltage on the selected word line and the voltage on the unselected word line are ramped down from the same first time and ramped up from the same second time.

[0008] In some embodiments, the unselected word line includes a first unselected word line, a second unselected word line, and a third unselected word line. The first unselected word line is closer to the selected word line than the second unselected word line, and the second unselected word line is closer to the selected word line than the third unselected word line. The second bias voltage on the first unselected word line is the same as the first bias voltage on the selected word line. The second bias voltage on the second unselected word line is less than the first bias voltage. The third bias voltage on the third unselected word line is less than the second bias voltage on the second unselected word line.

[0009] In some embodiments, the memory device further includes source lines coupled to the memory cell array, drain-select-gate (DSG) transistors coupled to columns of the memory cell array, and DSG lines coupled to the DSG transistors. The peripheral circuitry is coupled to the memory cell array via the source lines and the DSG lines and is configured to: during the first cycle of the programming operation, ramp down the voltage on the DSG lines from a selection voltage to a second supply voltage (Vss) lower than the first supply voltage, and ramp up the voltage on the source lines to a fourth bias voltage.

[0010] In some implementations, the voltage on the select word line and the voltage on the DSG line are ramped down from the same first time until the same second time.

[0011] In some embodiments, the memory device further includes bit lines coupled to the memory cell array, source-select-gate (SSG) transistors coupled to columns of the memory cell array, and SSG lines coupled to the SSG transistors. The peripheral circuitry is coupled to the memory cell array via the bit lines and the SSG lines and is configured to: during the first cycle of the programming operation, ramp down the voltage on the SSG lines from a selection voltage to a second supply voltage (Vss) lower than the first supply voltage, and ramp up the voltage on the bit lines to a fourth bias voltage.

[0012] In some implementations, the voltage on the select word line and the voltage on the SSG line are ramped down from the same first time until the same second time.

[0013] In some embodiments, the peripheral circuitry is further configured to: in the third cycle of the programming operation, reduce the voltage on the select word line from the post-pulse voltage to the first supply voltage, and maintain the voltage on the select word line at the first supply voltage.

[0014] In another aspect, a method for operating a memory device is provided. The memory device includes a memory cell array and word lines respectively coupled to rows of the memory cell array. In a first cycle of programming operation, after applying a verification voltage to a select word line in the word lines, a post-pulse voltage is applied to the select word line. The voltage on the select word line is then ramped down from the post-pulse voltage to a first supply voltage (Vdd). Immediately afterwards, the voltage on the select word line is ramped up from the first supply voltage to a first bias voltage.

[0015] In some implementations, in order to immediately ramp up the voltage on the select word line, the voltage on the select word line is ramped up once the voltage on the select word line reaches the first supply voltage.

[0016] In some implementations, in a second cycle immediately following the first cycle of the programming operation, a programming voltage is applied to the select word line after the first bias voltage.

[0017] In some implementations, during the first cycle of the programming operation, the voltage on the unselected word lines is ramped down from the pass voltage to the first supply voltage. Immediately afterwards, the voltage on the unselected word lines is ramped up from the first supply voltage to a second bias voltage no greater than the first bias voltage.

[0018] In some implementations, the electricity on the selected word line and the voltage on the unselected word line are ramped down from the same first time and ramped up from the same second time.

[0019] In some embodiments, the unselected word line includes a first unselected word line, a second unselected word line, and a third unselected word line. The first unselected word line is closer to the selected word line than the second unselected word line, and the second unselected word line is closer to the selected word line than the third unselected word line. The second bias voltage on the first unselected word line is the same as the first bias voltage on the selected word line. The second bias voltage on the second unselected word line is less than the first bias voltage. The third bias voltage on the third unselected word line is less than the second bias voltage on the second unselected word line.

[0020] In some embodiments, the memory device further includes source lines coupled to the memory cell array, DSG transistors coupled to columns of the memory cell array, and DSG lines coupled to the DSG transistors. In the first cycle of the programming operation, the voltage on the DSG lines is ramped down from the selection voltage to a second supply voltage (Vss) lower than the first supply voltage, and the voltage on the source lines is ramped up to a fourth bias voltage.

[0021] In some implementations, the voltages on the select word line and the DSG line slope down from the same first time until the same second time.

[0022] In some embodiments, the memory device further includes bit lines coupled to the memory cell array, SSG transistors coupled to columns of the memory cell array, and SSG lines coupled to the SSG transistors. In the first loop of the programming operation, the voltage on the SSG lines is ramped down from the selection voltage to a second supply voltage (Vss) lower than the first supply voltage, and the voltage on the bit lines is ramped up to a fourth bias voltage.

[0023] In some implementations, the voltage on the select word line and the voltage on the SSG line are ramped down from the same first time until the same second time.

[0024] In some implementations, during the third cycle of the programming operation, the voltage on the select word line is gradually reduced from the post-pulse voltage to the first supply voltage. The voltage on the select word line is then maintained at the first supply voltage.

[0025] In another aspect, a system includes: a storage device configured to store data; and a memory controller coupled to the storage device and configured to control the storage device. The storage device includes a memory cell array, word lines respectively coupled to rows of the memory cell array, and peripheral circuitry coupled to the memory cell array via the word lines. The peripheral circuitry is configured to: in a first cycle of a programming operation, after applying a verification voltage to a select word line in the word lines, apply a post-pulse voltage to the select word line, slope the voltage on the select word line down from the post-pulse voltage to a first supply voltage (Vdd), and then slope the voltage on the select word line up from the first supply voltage to a first bias voltage. Attached Figure Description

[0026] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0027] Figure 1 A schematic diagram of a storage device including peripheral circuitry is shown, according to some aspects of this disclosure.

[0028] Figure 2 A side view of a cross-section of a memory cell array including NAND memory strings is shown, according to some aspects of this disclosure.

[0029] Figure 3 A block diagram of a memory device including a memory cell array and peripheral circuitry, according to some aspects of this disclosure, is shown.

[0030] Figure 4A and Figure 4B The waveform of the word line voltage applied to the select word line during programming operations is shown according to some aspects of this disclosure.

[0031] Figure 5 A timing diagram of a programming operation with multiple loops is shown.

[0032] Figure 6 A timing diagram of another programming operation with multiple loops is shown.

[0033] Figure 7 A timing diagram of programming operations with multiple loops according to some aspects of this disclosure is shown.

[0034] Figure 8 A timing diagram of another programming operation with multiple loops, based on some aspects of this disclosure, is shown.

[0035] Figure 9 The timing diagram and channel potential of another programmed operation with multiple loops according to some aspects of this disclosure are shown.

[0036] Figure 10 A timing diagram of a further programming operation with multiple loops according to some aspects of this disclosure is shown.

[0037] Figure 11 A flowchart illustrating a method for programming a storage device according to some aspects of this disclosure is shown.

[0038] Figure 12 A flowchart is shown of another method for programming a storage device according to some aspects of this disclosure.

[0039] Figure 13 A block diagram of a system having storage devices according to some aspects of this disclosure is shown.

[0040] Figure 14A A diagram of a memory card having storage devices according to some aspects of this disclosure is shown.

[0041] Figure 14B A diagram of a solid-state drive (SSD) with storage devices is shown, according to some aspects of this disclosure.

[0042] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0043] Generally, terms can be understood at least partly from their use in context. For example, the term "one or more," as used herein, can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "described" can be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but can also, at least partly depending on the context, allow for the presence of other factors that are not necessarily explicitly described.

[0044] Memory devices (such as NAND flash memory devices) can store more than a single bit of information into each memory cell with multiple states to increase storage capacity bit by bit and reduce cost. Programming operations for NAND flash memory devices involve multiple programming cycles and verification cycles. At the end of each verification cycle, all word lines are restored to the drain supply voltage Vdd, and the drain select gate (DSG) line and source select gate (SSG) line are restored to the source supply voltage Vss, which can downcouple the channel potential (particularly in the memory cell region near the select word line where the NAND string is programmed). However, due to the hot carrier injection (HCI) effect, the downcoupled channel potential can cause programming interference in subsequent programming cycles. To mitigate these problems, a bias voltage can be applied to the word lines near the select word line at the beginning of the affected programming cycle to clean up accumulated electrons in the channel during a so-called "pre-pulse period" in the programming cycle. However, the additional pre-pulse period prolongs the duration of the programming cycle, thus becoming a time-saving programming (t) period. PROG The bottleneck.

[0045] On the other hand, at the end of the verification cycle, when all word lines are restored to Vdd, a failure bit count (FBC) needs to be performed during the hold period. Some efforts have been made to combine the pre-pulse period in the programming cycle with the FBC period in the previous verification cycle to reduce total programming time and power consumption due to word line voltage ramp-up / ramp-down. However, due to the different voltage drive capabilities between unselected word lines with different bias voltages (e.g., Vss and positive bias voltage), HCI effects can still occur between those unselected word lines due to voltage stress.

[0046] To address one or more of the aforementioned problems, this disclosure provides an improved recovery / pre-pulse scheme that avoids voltage stress between different adjacent unselected word lines, thereby reducing the HCI effect. After applying a verification voltage, all word lines can be ramped down to the same supply voltage (e.g., Vdd) and then immediately ramped up from that same supply voltage to their respective bias voltages for channel cleaning. Since all word lines are restored to the same supply voltage using the same voltage drive capability, voltage stress between adjacent unselected word lines can be significantly reduced. Charge sharing between the far-end and near-end word lines can also accelerate the far-end word line to reach its target voltage. Once the supply voltage is reached, the voltage on the word lines can begin to ramp up without significantly affecting programming time. In some embodiments, the voltage on the DSG and / or SSG lines is ramped down to another supply voltage (e.g., Vss) at the same time as the word lines to avoid threshold voltage shift due to the HCI effect in certain programming modes. The recovery / pre-pulse scheme is a "per-cycle" recovery / pre-pulse scheme that can be enabled and disabled in different cycles of programming operation to balance performance and programming time.

[0047] Figure 1 A schematic circuit diagram of a memory device 100 including peripheral circuitry according to some aspects of this disclosure is shown. The memory device 100 may include a memory cell array 101 and peripheral circuitry 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array, wherein memory cells 106 are provided in the form of an array of NAND memory strings 108, each extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value (such as voltage or charge) depending on the number of electrons trapped in the region of the memory cell 106. Each memory cell 106 may be a floating-gate type memory cell including a floating-gate transistor or a charge-trapping type memory cell including a charge-trapping transistor.

[0048] In some implementations, each storage cell 106 is an SLC with two possible levels (storage states) and thus capable of storing one bit of data. For example, a first level "0" may correspond to a first threshold voltage range, and a second level "1" may correspond to a second threshold voltage range. In some implementations, each storage cell 106 is an xLC capable of storing more than a single bit of data in more than four levels. For example, an xLC may store two bits per cell (MLC), three bits per cell (TLC), or four bits per cell (QLC). Each xLC can be programmed to assume a series of possible nominal storage values ​​(i.e., 2^N corresponding to N bits of data).N (pieces). In some embodiments, at least one of the storage units 106 is set to 2. N One of the levels corresponds to an N-bit data segment, where N is an integer greater than 1.

[0049] like Figure 1 As shown, each NAND memory string 108 may further include a source select gate (SSG) transistor 110 (also referred to as a bottom select gate (BSG) transistor) at its source end and a drain select gate (DSG) transistor 112 (also referred to as a top select gate (TSG) transistor) at its drain end. The SSG transistor 110 and the DSG transistor 112 may be configured to activate and select the NAND memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 108 in the same block 104 are coupled via a common source line (SL) 114 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 108 in the same block 104 have an array common source (ACS). According to some embodiments, the drain of each NAND memory string 108 is coupled to a corresponding bit line 116 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 108 is configured to be selected or deselected by applying a selection voltage (e.g., a positive voltage greater than the threshold voltage of the DSG transistor 112) or a deselection voltage (e.g., a ground voltage) to the gate of the corresponding DSG transistor 112 via one or more DSG lines 113 and / or by applying a selection voltage (e.g., a positive voltage greater than the threshold voltage of the SSG transistor 110) or a deselection voltage (e.g., a ground voltage) to the gate of the corresponding SSG transistor 110 via one or more SSG lines 115.

[0050] like Figure 1As shown, NAND memory strings 108 can be organized into multiple blocks 104, each block 104 may have a common source line 114, for example, coupled to an ACS. In some embodiments, each block 104 is the basic data unit for erase operations, i.e., all memory cells 106 on the same block 104 are erased simultaneously. To erase memory cells 106 in a selected block 104, the source lines 114 coupled to the selected block 104 and unselected blocks 104 in the same plane as the selected block 104 can be biased with an erase voltage (Vers), such as a high positive bias voltage (e.g., 20V or greater). Memory cells 106 of adjacent NAND memory strings 108 can be coupled via word lines 118, which select which row of memory cells 106 is affected by read and program operations. In some embodiments, each word line 118 is coupled to multiple memory cells 106. Each word line 118 may include multiple control gates (gate electrodes) and gate lines coupled to the control gates at each memory cell 106.

[0051] like Figure 1 As shown, the memory cell array 101 may include an array of memory cells 106 in multiple rows and multiple columns within each block 104. According to some embodiments, one column of memory cells corresponds to one NAND memory string 108. Multiple rows of memory cells 106 may be coupled to word lines 118, and multiple columns of memory cells 106 may be coupled to bit lines 116. Peripheral circuitry 102 may be coupled to the memory cell array 101 via bit lines 116 and word lines 118.

[0052] Figure 2 A side view of a cross-section of a memory cell array 101 including NAND memory strings 108 is shown, according to some aspects of this disclosure. (See also:) Figure 2 As shown, the NAND memory string 108 can extend vertically through the memory stack 204 above the substrate 202. The substrate 202 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0053] The memory stack 204 may include staggered gate conductive layers 206 and gate-gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate-gate dielectric layers 208 in the memory stack 204 determines the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding the gate of the memory cell 106, the gate of the DSG transistor 112, or the gate of the SSG transistor 110, and may extend laterally as a DSG line 113 at the top of the memory stack 204, an SSG line 115 at the bottom of the memory stack 204, or a word line 118 between DSG lines 113 and SSG lines 115.

[0054] like Figure 2 As shown, the NAND memory string 108 includes a channel structure extending vertically through the memory stack 204. In some embodiments, the channel structure includes channel holes filled with a semiconductor material (one or more) (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). It should be understood that, although Figure 2 Additional components, not shown but which may form the memory cell array 101, include, but are not limited to, gate line slits / source contacts, local contacts, interconnect layers, etc.

[0055] Return to reference Figure 1 Peripheral circuitry 102 can be coupled to memory cell array 101 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113. Peripheral circuitry 102 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 101 by applying voltage and / or current signals to each selected memory cell 106 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113 and sensing voltage and / or current signals from each selected memory cell 106. Peripheral circuitry 102 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 Some example peripheral circuitry is shown, including a page buffer / sensor amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, a register 314, an interface (I / F) 316, and a data bus 318. It should be understood that in some examples, additional peripheral circuitry may also be included. Figure 3Additional peripheral circuitry not shown.

[0056] Page buffer / sensor amplifier 304 can be configured to sense (read) data from memory cell array 101 and program (write) data to memory cell array 101 according to control signals from control logic 312. In one example, page buffer / sensor amplifier 304 can store one or more pages of programming data to be programmed (written data, referred to herein as "data pages"). In another example, page buffer / sensor amplifier 304 can verify the programmed selected memory cell 106 in each programming / verification cycle of a programming operation to ensure that data has been correctly programmed into the memory cell 106 coupled to select word line 118. In yet another example, page buffer / sensor amplifier 304 can also sense a low-power signal from bit line 116 representing data bits stored in memory cell 106 and amplify small voltage swings to a recognizable logic level during read operations.

[0057] The column decoder / bit line driver 306 can be configured to be controlled by control logic 312 and configured to select one or more NAND memory strings 108 by applying bit line voltages generated from voltage generator 310. The row decoder / word line driver 308 can be configured to be controlled by control logic 312 and configured to select / deselect block 104 of memory cell array 101 and select / deselect word lines of block 104. The row decoder / word line driver 308 can also be configured to drive word lines 118 using word line voltages generated from voltage generator 310. In some embodiments, the row decoder / word line driver 118 can also select / deselect and also drive SSG lines 115 and DSG lines 113. Voltage generator 310 can be configured to be controlled by control logic 122 and generate word line voltages (e.g., read voltage, programming voltage, channel pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 101.

[0058] Control logic 312 can be coupled to each of the aforementioned peripheral circuits and configured to control the operation of each peripheral circuit. Register 314 can be coupled to control logic 312 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 316 can be coupled to control logic 312 and acts as a control buffer to buffer and relay control commands received from the memory controller (not shown) and / or the host (not shown) to control logic 312, and to buffer and relay status information received from control logic 312 to the memory controller and / or the host. Interface 316 can also be coupled to column decoder / bitline driver 306 via data bus 318 and acts as a data input / output (I / O) interface and data buffer to buffer and relay data to and from memory cell array 101.

[0059] To perform the programming operation, in addition to the page buffer / sensor amplifier 304 providing a corresponding data segment to each selected memory cell 106, the row decoder / word line driver 308 can be configured to apply programming and verification voltages to the select word line 118 coupled to the selected row of memory cells 106 in one or more programming / verification cycles, so as to raise the threshold voltage of each selected memory cell 106 to a desired level (within the desired threshold voltage range) based on the corresponding data segment. For example, Figure 4A and Figure 4B The waveform of the word line voltage applied to the select word line during programming operations is shown according to some aspects of this disclosure.

[0060] like Figure 4A and 4B As shown, according to some embodiments, the programming operation includes one or more loops 402, each loop 402 including a programming cycle 404 and a verification cycle 406. Figure 4BAs shown, in each cycle 402, the row decoder / word line driver 308 can be configured to apply a programming voltage (Vpgm) on the select word line 118 in programming cycle 404 to select a row of memory cell 106, and sequentially apply one or more verification voltages (Vvfy) with increasing voltage levels in verification cycle 406 to verify the selected row of memory cell 106. That is, in each cycle 402, the peripheral circuitry 102 can perform verification of the selected row of memory cell 106 at one or more levels in verification cycle 406 after applying the programming voltage in programming cycle 404. According to some embodiments, the number of verification voltages applied in verification cycle 406 depends on the level programmed by a particular cycle 402. Therefore, at the end of the programming operation, for example, the selected memory cell 106 can be programmed to 2 based on the corresponding N bits of data to be stored in the selected memory cell 106. N In one of the levels, where N is a positive integer. In some implementations, the programming operation is incremental step pulse programming (ISPP), in which the programming voltage is gradually increased based on a step voltage in different cycles 402. The magnitude of this "step" (e.g., the increase in the magnitude of the programming voltage in each cycle 402 relative to the programming voltage in the immediately preceding cycle 402) is referred to as the "pulse step height".

[0061] Figure 5 A timing diagram of a programming operation with multiple loops is shown. The programming operation includes multiple loops (e.g., N loops). As mentioned above... Figure 4A and Figure 4B Each cycle of the programming operation includes a programming cycle and a verification cycle. Figure 5 The diagram illustrates a verification cycle 406 (VFY) within a loop and a programming cycle 404 (PGM) immediately following the verification cycle 406 in the previous loop. Verification cycle 406 includes a verification period (phase) in which a verification voltage (Vvfy) with one or more verification voltage pulses is applied to the select word line (sel WLn) to verify the selected memory cell coupled to the select word line at one or more levels. During the verification period, a pass voltage (Vpass) is applied to each unselected word line. At the end of the verification period, a post-pulse voltage (Vpost) is applied to the select word line. Verification cycle 406 also includes a post-pulse period (phase, also known as a recovery period) following the verification period. During the post-pulse period, the voltage on each unselected word line is ramped down from the pass voltage to a first supply voltage (Vdd), and the voltage on the select word line is ramped down from the post-pulse voltage to the first supply voltage. During the post-pulse period, the voltage on each of the DSG line (DSGL) and SSG line (SSGL) is ramped down to a second supply voltage (Vss), such as ground voltage (0V).

[0062] like Figure 5 As shown, programming cycle 404 includes a pre-pulse period (phase) following the post-pulse period of verification cycle 406. During the pre-pulse period, the voltage on each of the unselected word lines and selected word lines is ramped up or ramped down from the first supply voltage to the corresponding bias voltage. For example, the voltage on each of the selected word lines and the first group of unselected word lines (WLn-4–sel WLn) is ramped up to the first bias voltage (V1), the voltage on each of the second group of unselected word lines (WLb+1–WLn-5 and WLn+1–WLx) is ramped up to the second bias voltage (V2), the voltage on each of the third group of unselected word lines (WL0+1–WLb) is ramped up to the third bias voltage (V3), and the voltage on each of the fourth group of unselected word lines (WL0–WLa and WLx+1–WLz) is ramped down to the second supply voltage (Vss). Programming cycle 404 also includes a programming period (phase) following the pre-pulse period, in which a programming voltage (Vpgm) with one or more programming voltage pulses is applied to the select word line to program the selected memory cell to one or more levels. During the programming period, a pass voltage is applied to each unselected word line.

[0063] During the post-pulse period of verification cycle 406, the programmed memory cell near the select word line (e.g., coupled to) Figure 5 The memory cells whose unselected word lines WLn-4–WLn-1 are erased are turned off prematurely due to their relatively high threshold voltage, thereby coupling the channel potential in this region from 0V downwards to a negative voltage (e.g., -3V). This is because the channel potential in the region where the memory cell is erased (e.g., coupled to...) Figure 5 The memory cells (WLn+1–WLz) of the unselected word lines are at a positive voltage, therefore the HCI effect may occur due to the large channel potential difference and cause programming interference. During the pre-charge period of the programming cycle 404 immediately following the verification cycle 406, such as... Figure 5 As shown, biasing each word line at the corresponding bias voltage creates a channel potential distribution that removes electrons accumulated in the selected word line region of the channel, thereby mitigating the HCI effect and potential programming interference before the programming period. However, the introduction of a post-pulse period in verification cycle 406 and a pre-pulse period in programming cycle 404 results in a significant overhead to the total programming time.

[0064] Since a portion of the post-pulse period in verification cycle 406 is reserved only for logic operations of the FBC and not for voltage operations on word lines, the post-pulse period in verification cycle 406 and the pre-pulse period in programming cycle 404 can be "merged" to reduce time overhead. Figure 6 A timing diagram for another programming operation with multiple loops is shown. (e.g.) Figure 6 As shown, after the verification period of verification cycle 406, the voltage on each word line is directly ramped down to the corresponding bias voltage, instead of as... Figure 5 The voltage on each word line is ramped down to a first supply voltage (Vdd). For example, a first bias voltage regulator is used to ramp down the voltage on each of the selected word lines and the first group of unselected word lines (WLn-4–sel WLn) directly from the post-pulse voltage (Vpost) or the pass voltage (Vpass) to the first bias voltage (V1). A second bias voltage regulator is used to ramp down the voltage on each of the second group of unselected word lines (WLb+1–WLn-5 and WLn+1–WLx) directly from the pass voltage to the second bias voltage (V2). A third bias voltage regulator is used to ramp down the voltage on each of the third group of unselected word lines (WLa+1–WLb) directly from the pass voltage to the third bias voltage (V3). A second voltage source is used to ramp down the voltage on each of the fourth group of unselected word lines (WL0–WLa and WLx+1–WLz) directly from the pass voltage to the second supply voltage (Vss).

[0065] It should be understood that Figure 6 The solid lines in the diagram represent the ideal timing diagram of the voltage signals on the word lines. However, in reality, due to limited voltage drive capability, Figure 6 The dashed lines in the diagram illustrate the actual timing of the voltage signals on the word lines. Furthermore, because the supply voltage source has a higher voltage drive capability (e.g., faster drive) than the bias voltage regulator, such as... Figure 6 As shown, voltage stress occurs between the fourth group of unselected word lines (WL0–WLa) and the adjacent third group of unselected word lines (WLa+1–WLb) (i.e., between WLa+1 and WLa), and between the fourth group of unselected word lines (WLx+1–WLz) and the adjacent second group of unselected word lines (WLn+1–WLx) (i.e., between WLx+1 and WLx). This voltage stress may repeat whenever a word line is switched between different word lines. Therefore, the HCI effect may still occur between WLa+1 and WLa, and between WLx+1 and WLx, as... Figure 6 As shown.

[0066] To mitigate the HC effect between adjacent word lines due to differing voltage drive capabilities, the improved recovery / pre-pulse scheme disclosed herein uses a common supply voltage source to restore all word lines to the same supply voltage (e.g., Vdd) and then ramps them up to their respective bias voltages. For example, Figure 7 and 8A timing diagram of a programming operation with multiple loops according to some aspects of this disclosure is shown. The programming operation may include multiple loops (e.g., N loops). Each loop of the programming operation may include a programming cycle and a verification cycle, as described above. Figure 4A and 4B As described in [the text]. Figure 7 and 8 The diagram illustrates the verification cycle 406 (VFY) in the first loop and the programming cycle 404 (PGM) in the second loop that immediately follows the first loop. It should be understood that the "first loop" need not be the first loop in the programming operation, as long as there is another loop that immediately follows it (e.g., the "second loop").

[0067] In some embodiments, the verification cycle 406 includes a verification period (phase) in which the word line driver 308 of the peripheral circuitry 102 is configured to apply a verification voltage (Vvfy) having one or more verification voltage pulses on the select word line (selWLn) to verify the selected memory cell coupled to the select word line at one or more levels. According to some embodiments, at the end of the verification period, for example, at... Figure 7 and 8 At the first time t1, the word line driver 308 of the peripheral circuit 102 is configured to apply a post-pulse voltage (Vpost) to the selected word line. For example, the voltage on the selected word line can be ramped up from the verification voltage to the post-pulse voltage. In some embodiments, during the verification period, the word line driver 308 of the peripheral circuit 102 is also configured to apply a pass voltage (Vpass) to each unselected word line. The pass voltage can be greater than the threshold voltage of the unselected memory cell, causing the channel of the selected NAND memory string to become conductive during the verification period. In some embodiments, the pass voltage is greater than the verification voltage, causing the channel of the selected NAND memory string to become conductive at the end of the verification period, for example, at... Figure 7 and 8 At the first time t1, the voltage on the select word line is upwardly coupled / boosted to the same post-pulse voltage as the pass voltage.

[0068] In some implementations, the verification cycle 406 further includes a post-pulse period (phase, also known as a recovery period) following the verification period. During the post-pulse period, the word line driver 308 of the peripheral circuitry 102 may also be configured to: starting at a first time t1, ramp down the voltage on the select word line from the post-pulse voltage to a first supply voltage (Vdd), and then immediately at a second time t2 following the first time t1, ramp up the voltage on the select word line from the first supply voltage to a first bias voltage (V1). That is, a first voltage source (e.g., a drain voltage source) may be used, for example, to ramp down the voltage on the select word line from the post-pulse voltage to the first supply voltage between the first time t1 and the second time t2. For example, the time period between the first time t1 and the second time t2 (where the voltage on the select word line is driven by the first voltage source) may be less than 0.5 μs, such as about 0.2 μs. In order to immediately ramp up the voltage on the select word line at time t2, the word line driver 308 of the peripheral circuit 102 can be configured to ramp up the voltage on the select word line once the voltage on the select word line reaches the first supply voltage.

[0069] Similarly, during the post-pulse period, the word line driver 308 of the peripheral circuit 102 can also be configured to: starting from the same first time t1, ramp down the voltage on each unselected word line from the pass voltage to the same first supply voltage (Vdd), and then, at the same second time t2, immediately ramp up the voltage on the unselected word lines from the first supply voltage to the corresponding bias voltage (e.g., V1, V2, or V3) or a second supply voltage (Vss) not greater than the first bias voltage (V1). That is, the same first voltage source (e.g., a drain voltage source) can be used, for example, to ramp down the voltage on the unselected word lines from the pass voltage to the first supply voltage between the first time t1 and the second time t2. For example, the time period between the first time t1 and the second time t2 (where the voltage on the unselected word lines is driven by the first voltage source) can be less than 0.5 μs, such as about 0.2 μs. In order to immediately ramp up the voltage on the unselected word line at time t2, the word line driver 308 of the peripheral circuit 102 can be configured to ramp up the voltage on the unselected word line once the voltage on the unselected word line reaches a first supply voltage. In some embodiments, the voltages on the selected and unselected word lines ramp down from the same first time t1 and ramp up from the same second time t2.

[0070] Since all word lines (including the selected word line and each unselected word line) can be driven by the same voltage source between the same first time t1 and the second time t2 (when they are ramped down to the same voltage), it is possible to suppress the above-mentioned... Figure 6The voltage stress between adjacent unselected word lines is thus mitigated to avoid the HCI effect. Furthermore, it should be understood that word lines with different distances to the word line driver 308 of the peripheral circuitry 102 can be driven at different rates due to the resistance and capacitance of the memory cell array. Figure 7 and 8 As shown, between the first time t1 and the second time t2, the solid line represents the voltage change of the near-end word line (closest to word line driver 308), while the dashed line represents the voltage change of the far-end word line (farthest to word line driver 308). When the near-end word line slopes down to the first supply voltage (Vdd, e.g., about 2V), the far-end word line is at a voltage higher than the first supply voltage (Vdd + ΔV, e.g., about 4V), which is sufficient to avoid the HCI effect at the second time t2. On the other hand, charge sharing between the near-end and far-end word lines also reduces the time to reach the bias voltage.

[0071] Unselected word lines can be grouped into different groups based on their distance from the selected word lines and the programming direction of the word lines. Different bias voltages (e.g., V1, V2, and V3) can be assigned to different groups of unselected word lines to form a bias voltage distribution for better channel cleaning before the next programming cycle. In some implementations, a first bias voltage is greater than a second bias voltage, a second bias voltage is greater than a third bias voltage, and a third bias voltage is greater than a second supply voltage (Vss), i.e., V1>V2>V3>Vss. For example, the first bias voltage may be approximately 4.5V, the second bias voltage may be approximately 3.5V, the third bias voltage may be approximately 2.5V, and the second supply voltage may be 0V. In other words, according to some implementations, the closer the unselected word line group is to the selected word line, the larger the bias voltage assigned to the unselected word line group.

[0072] In such Figure 7In some of the embodiments shown (where the programming direction is from the bit line (BL) to the source line (SL), e.g., from top to bottom), a first bias voltage regulator is used to ramp up the voltage on each of the select word line and the first set of unselected word lines (WLn-4–selWLn) from the first supply voltage (Vdd) to the first bias voltage (V1), and a second bias voltage regulator is used to ramp up the voltage on each of the second set of unselected word lines (WLb+1–WLn-5 and WLn+1–WLx) from the first supply voltage (Vdd) to the first bias voltage (V1). A supply voltage (Vdd) is ramped up to a second bias voltage (V2). A third bias voltage regulator is used to ramp up the voltage on each of the third set of unselected word lines (WLa+1–WLb) from the first supply voltage (Vdd) to the third bias voltage (V3). A second voltage source (e.g., a source voltage source) is used to ramp down the voltage on each of the fourth set of unselected word lines (WL0–WLa and WLx+1–WLz) from the first supply voltage (Vdd) to the second supply voltage (Vss). Figure 8 In some implementations shown (where the programming direction is from the source line (SL) to the bit line (BL), e.g., from bottom to top), a first bias voltage regulator is used to select the word line and the first set of unselected word lines (sel). The voltage on each of the first supply voltage (Vdd) is ramped up to the first bias voltage (V1) using a second bias voltage regulator, the voltage on each of the second set of unselected word lines (WLa+1–WLn-1 and WLn+5–WLx) is ramped up to the second bias voltage (V2) using a second bias voltage regulator, the voltage on each of the third set of unselected word lines (WLx+1–WLy) is ramped up to the third bias voltage (V3) using a third bias voltage regulator, and the voltage on each of the fourth set of unselected word lines (WL0–WLa and WLy+1–WLz) is ramped down to the second supply voltage (Vss) using a second voltage source (e.g., a source voltage source).

[0073] like Figure 7 and 8 As shown, the word line driver 308 of the peripheral circuit 102 can also be configured to maintain the voltage on each of the selected and unselected word lines at a corresponding bias voltage (e.g., V1, V2, or V3) or a second supply voltage (Vss) from a second time t2 in the verification cycle 406 of the first cycle to a third time t3 in the programming cycle 404 of the second cycle immediately following the first cycle. The time period between the second time t2 and the third time t3 is as described above regarding... Figure 6The combined post-pulse / recovery period of the verification cycle 406 and the pre-pulse period of the subsequent programming cycle 404 are thus considered as the combined recovery / pre-pulse period of the verification cycle 406 and the subsequent programming cycle. In other words, a bias voltage or a second supply voltage can be maintained on the word line during the combined recovery / pre-pulse period of the verification cycle 406 and the subsequent programming cycle.

[0074] like Figure 7 and 8 As shown, the programming cycle 404 in the second loop may include a programming period (phase) following the merged recovery / pre-pulse period, wherein the word line driver 308 of the peripheral circuitry 102 may also be configured to apply a programming voltage (Vpgm) with one or more programming voltage pulses on the selected word line to program the selected memory cell to one or more levels. During the programming period, the word line driver 308 of the peripheral circuitry 102 may also be configured to apply a pass voltage (Vpass) on each unselected word line to conduct the channel for programming.

[0075] Figure 9 Timing diagrams and channel potentials for another programming operation with multiple cycles, according to some aspects of this disclosure, are shown. Under certain programming modes (threshold voltage distributions), for example, as... Figure 9 As shown, when a memory cell coupled to word line 7 (WL7) is programmed to a lower level (e.g., erase state L0), and memory cells coupled to adjacent word lines 8 and 9 (WL8 and WL9) are programmed to the highest level (e.g., L15 for a QLC), Figure 6 The merging of the post-pulse and pre-pulse periods can reduce the channel potential in the corresponding region, resulting in a large channel potential drop (indicated by the dashed line in the channel potential diagram). The resulting HCI effect causes the threshold voltage of the memory cell coupled to word line 7 to increase. One solution to mitigate this is to reduce the channel potential of the programmed memory cell (indicated by the solid line in the channel potential diagram) by turning off the DSG transistor earlier (from the second time t2 to the first time t1). In other words, during the merged recovery / pre-pulse period, instead of the voltage on the word line being slopped down, the voltage on the DSG line is slopped down (e.g., ...). Figure 6 As shown), during the merged recovery / pre-pulse period, the voltage on the DSG line and / or SSG line (depending on the programming direction) can be ramped down simultaneously with the voltage on the word line (e.g. Figure 7 and 8 (As shown).

[0076] In some implementations, such as Figure 7As shown, during the combined recovery / pre-pulse period, the word line driver 308 of the peripheral circuit 102 is further configured to: ramp down the voltage on the DSG line (DSGL) from the selection voltage to a second supply voltage (Vss) less than the first supply voltage (Vdd) to turn off the DSG transistor coupled to the DSG line. The selection voltage can be higher than the threshold voltage of the DSG transistor, allowing the DSG transistor to switch from being on to being off between a first time t1 and a second time t2. The voltages on the selection word line and the DSG line can be ramped down from the same first time t1 to the same second time t2 to reduce the channel potential between the DSG line and the selection word line, thereby mitigating the HCI effect, as described above regarding... Figure 9 As described above. In some embodiments, during the combined recovery / pre-pulse period, the word line driver 308 of the peripheral circuit 102 is also configured to ramp up the voltage on the source line to a fourth bias voltage (V4), because... Figure 7 The programming direction in the code is from the bit line to the source line.

[0077] In some implementations, such as Figure 8 As shown, during the combined recovery / pre-pulse period, the word line driver 308 of the peripheral circuit 102 is further configured to: ramp down the voltage on the SSG line (SSGL) from the selection voltage to a second supply voltage (Vss) less than the first supply voltage (Vdd) to turn off the SSG transistor coupled to the SSG line. The selection voltage can be higher than the threshold voltage of the SSG transistor, allowing the SSG transistor to switch from being on to being off between a first time t1 and a second time t2. The voltages on the selection word line and the SSG line can be ramped down from the same first time t1 to the same second time t2 to reduce the channel potential between the SSG line and the selection word line, thereby mitigating the HCI effect, as described above regarding... Figure 9 As described above. In some embodiments, during the combined recovery / pre-pulse period, the word line driver 308 of the peripheral circuit 102 is also configured to ramp up the voltage on the bit line to a fourth bias voltage (V4), because... Figure 8 The programming direction in the code is from the source line to the destination line.

[0078] It should be understood that in multi-loop programming operations, it is not necessary to execute the above instructions in every loop. Figures 7 to 9 The operation described herein. In other words, the recovery / pre-pulse scheme disclosed herein is a "per-cycle" recovery / pre-pulse scheme that can be enabled and disabled in different cycles of the programming operation to balance performance and programming time. For example, Figure 10 A timing diagram of another programming operation with multiple loops, based on some aspects of this disclosure, is shown. For example... Figure 10 As shown, in relation to the above text Figure 7 and 8In the post-pulse period of the verification cycle 406 in the third cycle, which differs from the first and second cycles described in the diagram, the word line driver 308 of the peripheral circuit 102 can also be configured to: ramp down the voltage on the selected word line from the post-pulse voltage (Vpost) to the first supply voltage (Vdd), and then maintain the voltage on the selected word line at the first supply voltage. Similarly, the word line driver 308 of the peripheral circuit 102 can also be configured to: ramp down the voltage on each unselected word line from the pass voltage (Vpass) to the first supply voltage, and then maintain the voltage on the selected word line at the first supply voltage. In some embodiments, in Figure 10 The third loop described is the final loop of the programming operation, and the programming operation ends after verification cycle 406. In some implementations, in Figure 10 The third loop described is one of the first few loops of the programming operation, and the programming operation continues programming cycle 404 after verification cycle 406 (e.g., as...). Figure 5 (As shown). That is to say, regarding Figure 10 The described operations can be applied to the first few loops and / or the last loop of a programming operation, while regarding Figure 7-9 The described operations can be applied to the remainder of the programming operation. Furthermore, unlike... Figure 7-9 (While the voltage on the word line is ramped down to the first supply voltage, the voltage on the DSG / SSG line is ramped down from the selection voltage to the second supply voltage.) Figure 10 As shown, after the voltage on the select word line is ramped down to the first supply voltage, the voltage on the DSG line (DSGL) / SSG line (SSGL) is ramped down from the select voltage to the second supply voltage (Vss).

[0079] Figure 11 A flowchart of a method 1100 for programming a memory device according to some aspects of this disclosure is shown. The memory device can be any suitable memory device disclosed herein, such as memory device 100. Method 1100 can be implemented by peripheral circuitry 102, such as line decoder / word line driver 308, page buffer / sensor amplifier 304, and control logic 312. It should be understood that the operations shown in method 1100 are not exhaustive, and other operations can be performed before, after, or between any of the shown operations. Furthermore, some operations can be performed simultaneously or in conjunction with... Figure 11 The different sequences shown are executed.

[0080] refer to Figure 11Method 1100 begins at operation 1101, in which, during the first loop of the programming operation, a verification voltage is applied to the select word line in the word lines, followed by a post-pulse voltage. Method 1100 proceeds to operation 1102, as follows... Figure 11 As shown, in operation 1102, the voltage on the select word line is ramped down from the post-pulse voltage to the first supply voltage (Vdd). For example, as... Figure 7 and 8 As shown, during the verification period of verification cycle 406 in the first loop, a verification voltage (Vvfy) is applied to the select word line (sel WLn), and at time t1, a post-pulse voltage (Vpost) is applied to the select word line. Then, the voltage on the select word line is gradually reduced from the post-pulse voltage at the first time t1 to the first supply voltage (Vdd) at the second time t2.

[0081] Method 1100 proceeds to operation 1104, such as... Figure 11 As shown, in operation 1104, the voltage on the unselected word line is ramped down from the through voltage to a first supply voltage. In some embodiments, the voltage on both the selected and unselected word lines is ramped down from the same first time and ramped up from the same second time. For example, as... Figure 7 and 8 As shown, the voltage on each unselected word line is sloping down from the pass voltage (Vpass) at the first time t1 to the first supply voltage at the second time t2.

[0082] Method 1100 proceeds to operation 1106, such as... Figure 11 As shown, in operation 1106, the voltage on the DSG / SSG line is ramped down from the selection voltage to a second supply voltage (Vss) that is less than the first supply voltage. In some embodiments, the voltages on the selection word line and the DSG / SSG line are ramped down from the same first time until the same second time. For example, as... Figure 7 As shown, the voltage on the DSG line (DSGL) is sloped down from the selection voltage at the first time t1 to the second supply voltage (Vss) at the second time t2. For example, as Figure 8 As shown, the voltage on the SSG line (SSGL) is sloped down from the selected voltage at the first time t1 to the second supply voltage (Vss) at the second time t2.

[0083] Method 1100 proceeds to operation 1108, such as... Figure 11 As shown, in operation 1108, the voltage on the select word line is then ramped up from the first supply voltage to the first bias voltage. In some embodiments, to ramp up the voltage on the select word line immediately after it reaches the first supply voltage, the voltage on the select word line is ramped up once it reaches the first supply voltage. For example, as... Figure 7 and Figure 8 As shown, at the second time t2 (once the voltage on the select word line reaches the first power supply), the voltage on the select word line is then ramped up from the first power supply voltage to the first bias voltage (V1).

[0084] Method 1100 proceeds to operation 1110, such as Figure 11 As shown, at operation 1110, the voltage on the unselected word line is then ramped up from the first supply voltage to a second bias voltage no greater than the first bias voltage. In some embodiments, the unselected word line includes a first unselected word line, a second unselected word line, and a third unselected word line. In some embodiments, the first unselected word line is closer to the selected word line than the second unselected word line, and the second unselected word line is closer to the selected word line than the third unselected word line. In some embodiments, the second bias voltage on the first unselected word line is the same as the first bias voltage on the selected word line, the second bias voltage on the second unselected word line is less than the first bias voltage, and the third bias voltage on the third unselected word line is less than the second bias voltage on the second unselected word line. For example, as... Figure 7 and 8 As shown, at the second time t2 (once the voltage on the selected word line reaches the first power supply), the voltage on each unselected word line is then ramped up from the first supply voltage to the corresponding bias voltage (V1, V2, or V3). The first group ( Figure 7 The first bias voltage (V1) on each unselected word line in WLn-4–WLn-1 or WLn+1–WLn+4 is the same as the first bias voltage (V1) on the unselected word line; the second group ( Figure 7 WLb+1–WLn-5 and WLn+1–WLx and Figure 8 The second bias voltage (V2) on each unselected word line in WLa+1–WLn-1 and WLn+5–WLx is less than the first bias voltage; the third group ( Figure 7 WLa+1–WLb and Figure 8 The third bias voltage (V3) on each unselected word line in WLx+1–WLy is less than the second bias voltage. The first group of unselected word lines is closer to the selected word line than the second group of unselected word lines, and the second group of unselected word lines is closer to the selected word line than the third group of unselected word lines.

[0085] Method 1100 proceeds to operation 1112, such as Figure 11 As shown, in operation 1112, the voltage on the source line / bit line is ramped up to the fourth bias voltage. For example, as... Figure 7 As shown, the voltage on the source line (SL) is ramped up at the first time t1 to the fourth bias voltage (V4) at the second time t2. For example, as Figure 7As shown, the voltage on the bit line (BL) is ramped up at the first time t1 to the fourth bias voltage (V4) at the second time t2.

[0086] Method 1100 proceeds to operation 1114, such as Figure 11 As shown, in operation 1114, a programming voltage is applied to the select word line after the first bias voltage in the second cycle immediately following the first cycle of the programming operation. For example, as... Figure 7 and 8 As shown, in programming cycle 404 of the second loop, a programming voltage (Vpgm) is applied to the select word line after the first bias voltage (V1).

[0087] Figure 12 A flowchart of another method 1200 for programming a memory device according to some aspects of this disclosure is shown. The memory device can be any suitable memory device disclosed herein, such as memory device 100. Method 1200 can be implemented by peripheral circuitry 102, such as line decoder / word line driver 308, page buffer / sensor amplifier 304, and control logic 312. It should be understood that the operations shown in method 1200 are not exhaustive, and other operations can be performed before, after, or between any of the shown operations. Furthermore, some operations can be performed simultaneously or in conjunction with... Figure 12 The different sequences shown are executed.

[0088] refer to Figure 12 Method 1200 begins at operation 1202, in which, in the third loop of the programming operation, the voltage on the select word line is ramped down from the post-pulse voltage to the first supply voltage. Method 1200 proceeds to operation 1204, as follows... Figure 12 As shown, in operation 1204, the voltage on the select word line is maintained at the first supply voltage. For example, as... Figure 10 As shown, in the verification cycle 406 of the third cycle, the voltage on the select word line is ramped down from the pulse post voltage (Vppost) to the first supply voltage (Vdd) and then maintained at the first supply voltage.

[0089] Method 1200 proceeds to operation 1206, such as... Figure 12 As shown, in operation 1206, the voltage on the unselected word line is ramped down from the through voltage to the first supply voltage. Method 1200 proceeds to operation 1208, as follows: Figure 12 As shown, in operation 1208, the voltage on the unselected word line is maintained at the first supply voltage. For example, as... Figure 10 As shown, in the verification cycle 406 of the third cycle, the voltage on each unselected word line is ramped down from the pass voltage (Vpass) to the first supply voltage (Vdd) and then maintained at the first supply voltage.

[0090] Method 1200 proceeds to operation 1210, such as... Figure 12 As shown, in operation 1210, after the voltage on the select word line is ramped down to the first supply voltage, the voltage on the DSG / SSG line is ramped down from the select voltage to the second supply voltage. For example, as Figure 10 As shown, after the voltage on the select word line is ramped down to the first supply voltage, the voltage on the DSG line (DSGL) / SSG line (SSGL) is ramped down from the select voltage to the second supply voltage (Vss).

[0091] Figure 13 A block diagram of a system 1300 having storage devices according to some aspects of this disclosure is shown. System 1300 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 13 As shown, system 1300 may include host 1308 and having one or more storage devices 100 (in Figure 1 The memory system 1302 (shown in the diagram) and memory controller 1306. The host 1308 may be a processor (such as a central processing unit (CPU)) or a system-on-a-chip (SoC) (such as an application processor (AP)). The host 1308 may be configured to send data to or receive data from the memory device 100.

[0092] Storage device 100 can be any storage device disclosed herein. According to some embodiments, memory controller 1306 is coupled to storage device 100 and host 1308 and configured to control storage device 100. Memory controller 1306 can manage data stored in storage device 100 and communicate with host 1308. In some embodiments, memory controller 1306 is designed to operate in a low duty cycle environment (e.g., a Secure Digital Signature (SD) card, Compact Flash Memory (CF) card, Universal Serial Bus (USB) flash drive, or other media for electronic devices (such as personal computers, digital cameras, mobile phones, etc.). In some embodiments, memory controller 1306 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), used for data storage in mobile devices (such as smartphones, tablets, laptops, etc.) and enterprise storage arrays. Memory controller 1306 can be configured to control the operation of storage device 100, such as read, erase, and program operations. The memory controller 1306 can also be configured to manage various functions relating to data stored or to be stored in the storage device 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1306 is also configured to process error correction codes (ECC) relating to data read from or written to the storage device 100. Any other suitable functions may also be performed by the memory controller 1306, such as formatting the storage device 100. The memory controller 1306 may communicate with external devices (e.g., host 1308) according to specific communication protocols. For example, the memory controller 1306 can communicate with external devices through at least one of various interface protocols, such as USB protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0093] The memory controller 1306 and one or more memory devices 100 can be integrated into various types of storage devices, for example, included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 1302 can be implemented and packaged into different types of end electronic products. Figure 14AIn one example shown, the memory controller 1306 and a single storage device 100 can be integrated into a memory card 1402. The memory card 1402 may include a PC card (PCMCIA (Personal Computer Memory Card International Association)), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1402 may also include a connection between the memory card 1401 and a host (e.g., Figure 13 The memory card connector 1404 is coupled to the host 1308. In such a... Figure 14B In another example shown, the memory controller 1306 and multiple storage devices 100 can be integrated into the SSD 1406. The SSD 1406 may also include an SSD connector 1408 that connects the SSD 1406 to a host computer (e.g., Figure 13 The SSD 1406 is coupled to the host 1308 in some implementations. In some implementations, the storage capacity and / or operating speed of the SSD 1406 is greater than the storage capacity and / or operating speed of the memory card 1402.

[0094] The foregoing description can be easily modified and / or adapted for various applications to suit specific implementations. Therefore, based on the teachings and guidance provided herein, these adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementation.

[0095] The scope and extent of this disclosure should not be limited to any of the embodiments described in the above example implementations, but should be defined solely by the appended claims and their equivalents.

[0096] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the subject matter described in this disclosure can also be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, modified, and rearranged with each other in a manner consistent with the scope of this disclosure.

Claims

1. A storage device, comprising: Storage cell array; Word lines, which are respectively coupled to rows of the memory cell array; as well as Peripheral circuitry, coupled to the memory cell array via the word lines, is configured such that, in the first loop of the programming operation: After applying a verification voltage to the select word line in the word line, a post-pulse voltage is applied to the select word line. The voltage on the select word line is gradually reduced from the post-pulse voltage to the first supply voltage (Vdd); as well as Then, the voltage on the select word line is increased from the first supply voltage to the first bias voltage.

2. The storage device according to claim 1, wherein, In order to immediately ramp up the voltage on the select word line, the peripheral circuit is configured to ramp up the voltage on the select word line once the voltage on the select word line reaches the first supply voltage.

3. The storage device according to claim 1 or 2, wherein, The peripheral circuitry is also configured to apply a programming voltage to the select word line after the first bias voltage in a second cycle immediately following the first cycle of the programming operation.

4. The storage device according to any one of claims 1-3, wherein, The peripheral circuit is also configured to: in the first loop of the programming operation: The voltage on the unselected word line in the word line is reduced from the through voltage to the first supply voltage; as well as Then, the voltage on the unselected word line is increased from the first supply voltage to a second bias voltage that is no greater than the first bias voltage.

5. The storage device according to claim 4, wherein, The voltage on the selected word line and the voltage on the unselected word line are sloping down from the same first time and sloping up from the same second time.

6. The storage device according to claim 4 or 5, wherein, The unselected word line includes a first unselected word line, a second unselected word line, and a third unselected word line, wherein the first unselected word line is closer to the selected word line than the second unselected word line, and the second unselected word line is closer to the selected word line than the third unselected word line; The second bias voltage on the first unselected word line is the same as the first bias voltage on the selected word line; The second bias voltage on the second unselected word line is less than the first bias voltage; as well as The third bias voltage on the third unselected word line is less than the second bias voltage on the second unselected word line.

7. The storage device according to any one of claims 1-6, further comprising: The source line coupled to the memory cell array; Drain-select-gate (DSG) transistors are respectively coupled to columns of the memory cell array; as well as The DSG line is coupled to the DSG transistor. The peripheral circuitry is coupled to the memory cell array via the source line and the DSG line and is configured such that, in the first loop of the programming operation: The voltage on the DSG line is ramped down from the selected voltage to a second supply voltage (Vss) that is lower than the first supply voltage; and The voltage on the source line is ramped up to the third bias voltage.

8. The storage device according to claim 7, wherein, The voltage on the select word line and the voltage on the DSG line are ramped down from the same first time until the same second time.

9. The storage device according to any one of claims 1-6, further comprising: Bit lines coupled to the memory cell array; Source-select-gate (SSG) transistors are respectively coupled to columns of the memory cell array; as well as The SSG line coupled to the SSG transistor, The peripheral circuitry is coupled to the memory cell array via the bit line and the SSG line and is configured such that, in the first loop of the programming operation: The voltage on the SSG line is ramped down from the selected voltage to a second supply voltage (Vss) that is lower than the first supply voltage; and The voltage on the bit line is ramped up to the third bias voltage.

10. The storage device according to claim 9, wherein, The voltage on the select word line and the voltage on the SSG line are ramped down from the same first time until the same second time.

11. The storage device according to any one of claims 1-10, wherein, The peripheral circuit is also configured to: in the third loop of the programming operation: The voltage on the select word line is gradually reduced from the post-pulse voltage to the first supply voltage; as well as The voltage on the select word line is maintained at the first supply voltage.

12. A method for operating a storage device, the storage device including a memory cell array and word lines respectively coupled to rows of the memory cell array, the method comprising: In the first loop of the programming operation: After applying a verification voltage to the select word line in the word line, a post-pulse voltage is applied to the select word line. The voltage on the select word line is gradually reduced from the post-pulse voltage to the first supply voltage (Vdd); as well as Then, the voltage on the select word line is increased from the first supply voltage to the first bias voltage.

13. The method according to claim 12, wherein, The subsequent ramping up of the voltage on the select word line includes: ramping up the voltage on the select word line once the voltage on the select word line reaches the first supply voltage.

14. The method according to claim 12 or 13, further comprising: In the second cycle immediately following the first cycle of the programming operation, a programming voltage is applied to the select word line after the first bias voltage.

15. The method according to any one of claims 12-14, further comprising: In the first loop of the programming operation: The voltage on the unselected word line in the word line is reduced from the through voltage to the first supply voltage; as well as Then, the voltage on the unselected word line is increased from the first supply voltage to a second bias voltage that is no greater than the first bias voltage.

16. The method according to claim 15, wherein, The electricity on the selected word line and the voltage on the unselected word line are sloping down from the same first time and sloping up from the same second time.

17. The method according to claim 15 or 16, wherein, The unselected word line includes a first unselected word line, a second unselected word line, and a third unselected word line, wherein the first unselected word line is closer to the selected word line than the second unselected word line, and the second unselected word line is closer to the selected word line than the third unselected word line; The second bias voltage on the first unselected word line is the same as the first bias voltage on the selected word line; The second bias voltage on the second unselected word line is less than the first bias voltage; as well as The third bias voltage on the third unselected word line is less than the second bias voltage on the second unselected word line.

18. The method according to any one of claims 12-17, wherein, The memory device further includes a source line coupled to the memory cell array, drain-select-gate (DSG) transistors coupled to columns of the memory cell array, and DSG lines coupled to the DSG transistors. and The method further includes: in the first loop of the programming operation: The voltage on the DSG line is gradually reduced from the selected voltage to a second supply voltage (Vss) that is lower than the first supply voltage; as well as The voltage on the source line is ramped up to the fourth bias voltage.

19. The method according to claim 18, wherein, The voltages on the select word line and the DSG line decrease at the same first time until the same second time.

20. The method according to any one of claims 12-17, wherein, The memory device further includes bit lines coupled to the memory cell array, source-select-gate (SSG) transistors coupled to columns of the memory cell array, and SSG lines coupled to the SSG transistors. and The method further includes: in the first loop of the programming operation: The voltage on the SSG line is ramped down from the selected voltage to a second supply voltage (Vss) that is lower than the first supply voltage; and The voltage on the bit line is ramped up to the fourth bias voltage.

21. The method according to claim 20, wherein, The voltage on the select word line and the SSG line decreases at the same first time until the same second time.

22. The method according to any one of claims 12-21, further comprising: In the third loop of the programming operation: The voltage on the select word line is gradually reduced from the post-pulse voltage to the first supply voltage; as well as Maintain the voltage on the select word line at the first supply voltage.

23. A system comprising: Storage device, configured to store data and comprising: Storage cell array; Word lines respectively coupled to rows of the memory cell array; and Peripheral circuitry, coupled to the memory cell array via the word lines, is configured such that, in the first loop of the programming operation: After applying a verification voltage to the select word line in the word line, a post-pulse voltage is applied to the select word line. The voltage on the select word line is ramped down from the post-pulse voltage to the first supply voltage (Vdd); and Then, the voltage on the select word line is ramped up from the first supply voltage to the first bias voltage; and A memory controller, which is coupled to the memory device and configured to control the memory device.

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