Overcurrent protection circuit and intelligent high-side switch chip

Abstract

This invention discloses an overcurrent protection circuit and an intelligent high-side switching chip. The circuit includes a resistanceless sampling unit, a reference voltage generation unit, a comparator, a fast turn-off unit, a level conversion and latching unit, and a digital control unit. It samples the output current through a current mirror without resistance and compares it with an adjustable reference voltage to achieve high-precision detection. After the comparator output, the fast turn-off unit directly pulls down the gate of the power transistor to instantaneously limit the current; secondly, after level conversion and latching, the digital control unit controls the driver stage to completely turn off, achieving dual protection. The digital control unit integrates a programmable register, supporting flexible configuration of overcurrent threshold, shielding time, and retry count, and has fault counting and diagnostic functions. This invention solves the problems of contradictory response speed and power consumption, easy false triggering, and inflexible adjustment in the prior art, and has the advantages of fast response, high accuracy, low power consumption, strong configurability, and meeting functional safety requirements.

Description

Technical Field

[0001] This invention relates to the field of protection circuits, and particularly to overcurrent protection circuits and intelligent high-side switch chips. Background Technology

[0002] A high-side switch is an intelligent power device that integrates power MOSFETs, drive circuits, and various protection and diagnostic functions. It is widely used in automotive electronics, industrial control, and other fields to control the connection and disconnection of power supplies with various loads (such as car seat motors, lights, wiper motors, solenoid valves, etc.).

[0003] During system operation, load failures may occur, the most common and most dangerous being a short circuit to ground at the output terminal (i.e., a load short circuit) or an abnormal increase in current. Without an effective overcurrent protection mechanism, the enormous short-circuit current will far exceed the withstand capacity of the chip's internal power MOSFETs, bonding wires, and PCB traces, causing the devices to burn out due to instantaneous overheating, leading to system failure and even safety hazards. Therefore, overcurrent protection circuitry is an indispensable key module in intelligent high-side switching chips.

[0004] In existing technologies, overcurrent protection schemes can be mainly classified into the following categories: (1) Discrete component solution: Use overcurrent protection components such as PTC resettable fuses, or build a detection circuit using transistors, resistors, etc. This solution is low in cost but has low accuracy, slow response, large board area, and the protection threshold is easily affected by temperature.

[0005] (2) Integrated chip solution: This is currently the mainstream solution. Its overcurrent detection methods can be further divided into: (2.1) Direct detection (resistance sampling): A high-precision sampling resistor is connected in series in the power circuit, and the current magnitude is reflected by detecting the voltage drop across its terminals. This scheme has high accuracy, but it introduces additional power loss and voltage drop, reducing system efficiency. At the same time, the temperature drift of the sampling resistor and the parasitic parameters introduced by the PCB layout will affect the detection accuracy, and it requires circuits such as differential amplifiers, increasing cost and design complexity.

[0006] (2.2) Indirect detection (resistorless sampling): The current is estimated by using the current mirror integrated inside the chip or by sensing the on-state voltage drop VDS of the power MOSFET. This method requires no external components, has high integration, and low power consumption. However, the detection accuracy is limited by the chip process and temperature, and is usually low.

[0007] There are two main modes for overcurrent response strategies: Immediate shutdown type: The output is quickly shut down upon detecting overcurrent. It has a fast response speed, but is prone to false triggering in transient surge scenarios such as when capacitive loads are powered on.

[0008] Current-limiting non-shutdown type: When there is an overcurrent, the current is limited to a safe value and the chip is not immediately shut off. However, this will lead to increased chip power consumption and aggravated temperature rise, requiring MCU intervention or thermal shutdown for secondary protection.

[0009] However, the aforementioned existing technologies still have the following significant drawbacks: (1) The contradiction between overcurrent protection response speed and the safety of switching devices (2) Risk of inconsistent protection thresholds and false triggering (3) The dilemma of balancing overcurrent protection power consumption and system efficiency (4) Insufficient integration and the complexity of peripheral circuits (5) The flexibility of overcurrent fault handling is limited. Therefore, the present invention provides an overcurrent protection circuit and an intelligent high-side switch chip. Summary of the Invention

[0010] In view of the problems in the prior art, the purpose of this invention is to provide an overcurrent protection circuit and an intelligent high-side switch chip, which overcomes the difficulties of the prior art and can take into account response speed, detection accuracy, low power consumption, high flexibility, high integration and meet functional safety requirements.

[0011] An embodiment of the present invention provides an overcurrent protection circuit, comprising: A resistanceless sampling unit is provided, the input of which is connected to the output power transistor of the intelligent high-side switching chip. The unit is used to sample the output current of the output power transistor to generate a sampling current proportional to the output current and convert the sampling current into a sampling voltage. A reference voltage generation unit is used to generate an adjustable reference voltage; A comparator unit, wherein a first input terminal of the comparator unit is connected to the sampled voltage and a second input terminal is connected to the reference voltage, is used to compare the sampled voltage with the reference voltage, and outputs an overcurrent trigger signal when the sampled voltage exceeds the reference voltage; A fast shutdown unit, the input of which is connected to the output of the comparator unit and the output of which is connected to the control electrode of the output power transistor, is used to directly and quickly pull down the control electrode potential of the output power transistor after receiving the overcurrent trigger signal, so as to clamp or limit the output current. A level conversion and latching unit, wherein the input terminal of the level conversion and latching unit is connected to the output terminal of the comparator unit, is used to convert the high-voltage domain overcurrent trigger signal output by the comparator unit into a low-voltage domain signal, and latch the signal; A digital control unit, the input terminal of which is connected to the output terminal of the level conversion and latching unit, and its output terminal is connected to the driver stage of the intelligent high-side switch chip, for controlling the driver stage to turn off the output power transistor after receiving the latched overcurrent signal; Furthermore, the digital control unit is equipped with a programmable register for receiving external control commands to adjust at least one of the following parameters: overcurrent threshold, overcurrent shielding time, and overcurrent retry count.

[0012] Preferably, the resistorless sampling unit adopts a current mirror structure, and its sampling ratio is related to the size ratio of the output power transistor.

[0013] Preferably, the reference voltage generating unit includes a reference current source with zero temperature coefficient that provides a reference current and a set of programmable resistor divider networks. The digital control unit adjusts the reference voltage by configuring the tap positions of the resistor divider networks, thereby adjusting the overcurrent threshold.

[0014] Preferably, the fast shutdown unit includes an NMOS transistor, the drain of which is connected to the gate of the output power transistor, the source of which is connected to the source of the output power transistor, and the gate of which is connected to the output terminal of the comparator unit.

[0015] Preferably, the level conversion and latching unit includes an AND gate, a level conversion circuit, and an SR flip-flop; the two inputs of the AND gate are respectively connected to the output of the comparator unit and an enable signal, the output of the AND gate is connected to the input of the level conversion circuit, the output of the level conversion circuit is connected to the set input of the SR flip-flop, and the level conversion circuit converts the overcurrent trigger signal in the high-voltage domain into a low-voltage domain signal; the set input of the SR flip-flop is connected to the output of the level conversion circuit, and the reset input of the SR flip-flop is connected to the reset signal output of the digital control unit, used to clear the latching state according to the reset signal.

[0016] Preferably, the digital control unit further includes a fault counter for recording the number of overcurrent signals received within a preset time. When the number of overcurrent retry attempts reaches the overcurrent retry count, the digital control unit outputs a shutdown signal to shut down the output power transistor.

[0017] Preferably, the digital control unit sets the overcurrent shielding time by configuring the comparator unit or the level conversion and latching unit; during the overcurrent shielding time after the output power transistor is turned on, it does not respond to the overcurrent trigger signal.

[0018] Preferably, the digital control unit further includes a fault diagnosis and reporting interface for reporting the occurrence of overcurrent events, fault count status, and permanent shutdown information to the system main control unit.

[0019] Preferably, the digital control unit is connected to the driver stage via a high-level delay and a first inverter, and the fast shutdown unit responds to the overcurrent trigger signal faster than the digital control unit shuts down the output power transistor via the driver stage.

[0020] Embodiments of the present invention also provide an intelligent high-side switch chip, including: the overcurrent protection circuit as described above.

[0021] In summary, this invention provides an overcurrent protection circuit and an intelligent high-side switch chip that integrate fast response, high precision, low power consumption, flexible configuration, and functional safety, which are significantly superior to the prior art.

[0022] To further understand the features and technical content of this application, please refer to the following detailed description and drawings. However, the detailed description and drawings are only for illustrating this application and are not intended to limit the scope of the claims in any way. Attached Figure Description

[0023] The above and other features and advantages of this application will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0024] Figure 1 This is a circuit diagram of the overcurrent protection circuit of the present invention.

[0025] Figure 2 This is a schematic diagram of the intelligent high-side switch control process using the overcurrent protection circuit of the present invention.

[0026] Figure Labels Detailed Implementation

[0027] The following specific examples illustrate the implementation methods of this application. Those skilled in the art can easily understand the other advantages and effects of this application from the content disclosed herein. This application can also be implemented or applied through other different specific embodiments, and various details in this application can be modified or changed according to different viewpoints and application systems without departing from the spirit of this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0028] The embodiments of this application will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily implement the application. This application may be embodied in many different forms and is not limited to the embodiments described herein.

[0029] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate different embodiments or examples represented in this application, as well as features of different embodiments or examples.

[0030] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0031] For the purpose of clearly describing this application, devices that are not relevant to the description are omitted, and the same or similar components throughout the specification are given the same reference numerals.

[0032] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0033] When we say that a device is "above" another device, this can mean that it is directly above the other device, or it can mean that other devices are present in between. Conversely, when we say that a device is "directly" "above" another device, there are no other devices present in between.

[0034] While the terms first, second, etc., are used in some instances herein to refer to various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, first interface and second interface, etc., are used. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of a feature, step, operation, component, element, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, components, elements, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition occur only when combinations of components, functions, steps, or operations are inherently mutually exclusive in some way.

[0035] The technical terms used herein are for reference only to specific embodiments and are not intended to limit the scope of this application. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. The word "comprising" as used in the specification means to specify a particular characteristic, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.

[0036] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the content of this present application, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0037] The technical problem to be solved by this invention is to provide an overcurrent protection circuit architecture for intelligent high-side switch chips, addressing the aforementioned deficiencies in the existing technology, and aiming to solve or at least alleviate the following technical problems: (1) reducing the probability of false triggering of overcurrent protection under external electromagnetic interference and transient load changes. (2) improving the overcurrent detection accuracy of intelligent high-side switches and realizing flexible adjustment of the number of overcurrent retry attempts and the current limiting threshold. (3) optimizing the contradictory relationship between the response speed and power consumption of the overcurrent protection circuit. (4) meeting the functional safety requirements of automotive-grade intelligent high-side chips for overcurrent detection and providing comprehensive fault diagnosis capabilities.

[0038] Figure 1 This is a circuit diagram of the overcurrent protection circuit of the present invention.Figure 1 As shown, an embodiment of the present invention provides an overcurrent protection circuit, including: a resistorless sampling unit, a reference voltage generation unit, a comparator unit 1, a fast shutdown unit 2, a level conversion and latching unit, and a digital control unit. The input terminal of the resistorless sampling unit is connected to the output power transistor of an intelligent high-side switching chip, used to sample the output current of the output power transistor to generate a sampling current Is proportional to the output current, and converting the sampling current Is into a sampling voltage.

[0039] The reference voltage generation unit is used to generate an adjustable reference voltage.

[0040] The first input terminal of comparator unit 1 is connected to the sampling voltage, and the second input terminal is connected to the reference voltage. It is used to compare the sampling voltage with the reference voltage and output an overcurrent trigger signal when the sampling voltage exceeds the reference voltage.

[0041] The input terminal of the fast shutdown unit 2 is connected to the output terminal of the comparator unit 1, and the output terminal is connected to the control electrode of the output power transistor. It is used to directly and quickly pull down the control electrode potential of the output power transistor after receiving an overcurrent trigger signal, so as to clamp or limit the output current.

[0042] The input terminal of the level conversion and latching unit is connected to the output terminal of comparator unit 1, which is used to convert the high voltage domain overcurrent trigger signal output by comparator unit 1 into a low voltage domain signal and latch the signal.

[0043] The digital control unit has its input connected to the output of the level conversion and latching unit, and its output connected to the driver stage 10 of the intelligent high-side switch chip. After receiving the latched overcurrent signal, the driver stage 10 is controlled to turn off the output power transistor.

[0044] Furthermore, the digital control unit is equipped with a programmable register for receiving external control commands to adjust at least one of the following parameters: overcurrent threshold, overcurrent shielding time, and overcurrent retry count.

[0045] In a preferred embodiment, the resistorless sampling unit employs a current mirror structure, the sampling ratio of which is related to the size ratio of the output power transistor. In a specific implementation of the invention, the resistorless sampling unit is implemented using a precision current mirror structure. Specifically, the current mirror consists of an output power transistor (M1) and a proportionally sized sampling transistor (M2), with a width-to-length ratio of K:1. When the output power transistor M1 is turned on and carries the load current I... OUT At that time, the current I flowing through the sampling tube M2 SENSE ≈ I OUT / K. This ratio K can be made very large (e.g., 1000:1 to 10000:1), making the sampling current I... SENSEExtremely small, thus generating almost no additional power consumption in the sampling branch. Sampling current I SENSE The current then flows through an internal high-precision resistor R4 and is converted into a sampling voltage V. SENSE = I SENSE R4. By using a current mirror replication instead of a direct series resistor, this solution completely avoids introducing any additional voltage drop and power consumption in the main power path, significantly improving the overall efficiency of the system. It is especially suitable for scenarios where large currents are continuously flowing, but is not limited to this.

[0046] In a preferred embodiment, the reference voltage generation unit includes a reference current source with zero temperature coefficient providing a reference current and a set of programmable resistor divider networks. The digital control unit adjusts the reference voltage by configuring the tap positions of the resistor divider networks, thereby adjusting the overcurrent threshold. The reference voltage generation unit does not simply provide a fixed voltage, but is composed of a bandgap reference source, a current mirror, and a programmable resistor string. The bandgap reference source generates a reference voltage V that is independent of power supply and temperature. REF This voltage is passed through a precision resistor R. BIAS This is converted to a reference current with a zero temperature coefficient. In this embodiment, this I... BIAS As a core bias, it not only provides bias for the resistor network (R1, R2, R3) before the comparator, but also ensures the IB in the entire threshold formula. LIM The term is highly stable. The programmable resistor divider network is actually implemented by digitally segmenting R2 (or a combination of R2 and R4). For example, R2 can consist of multiple precision resistor units connected in series and a bypass switch controlled by a register. The digital control unit changes the equivalent resistance of R2 by changing the on / off state of the switch, thereby precisely controlling the (R2-R4) / R4 term in the formula to achieve the overcurrent threshold IOUT. MAX The chip features fine-grained step adjustment. This design offers several advantages: First, the threshold is almost completely decoupled from temperature, power supply voltage, and process angle, ensuring consistency of the protection point throughout its lifecycle and under extreme operating conditions. Second, the digital programming interface allows the chip to dynamically adjust the protection threshold based on different load characteristics after leaving the factory and even during system operation, greatly enhancing the chip's versatility and application flexibility, but without limiting it.

[0047] In a preferred embodiment, the fast shutdown unit 2 includes an NMOS transistor, the drain of which is connected to the gate of the output power transistor, the source of which is connected to the source of the output power transistor, and the gate of which is connected to the output terminal of the comparator unit 1. The fast shutdown unit 2 consists of a high-voltage NMOS transistor (MN). FAST Its structure is composed of components, and its design has undergone special consideration. MN FASTThe dimensions need to be carefully optimized to strike a balance between gate drive capability (provided by the comparator output) and pull-down speed. Its drain is directly connected to the gate of the output power transistor M1, and its source is connected to the source of M1 (i.e., the power bus VBB). When comparator unit 1 detects an overcurrent and momentarily outputs a high level, this high level directly drives MN. FAST The gate of M1 is rapidly switched on, causing it to quickly enter a low-resistance on state. This action is equivalent to connecting an extremely low-resistance switch in parallel across the gate and source of M1, instantly removing the gate charge from M1 and forcing the gate-source voltage Vgs of M1 to drop rapidly below the threshold voltage. From the occurrence of the overcurrent to the start of M1's turn-off, the entire path delay is only the comparator's toggling delay plus MN. FAST The turn-on delay is typically on the order of tens of nanoseconds. This speed is unmatched by traditional turn-off methods using digital logic and driver stages. Its technical advantage lies in its ability to intervene in the early stages of current spike formation, clamping the peak current within a safe range and significantly reducing the short-circuit energy (E = I²) that the power transistor needs to withstand. Rds (on) This approach (t) fundamentally avoids the risk of localized overheating and secondary breakdown of the power transistor. This analog fast path buys valuable processing time for subsequent digital logic shutdown, forming a dual protection mechanism of "clamping first, then shutdown," achieving the most timely and effective protection for power devices, but it is not limited to this.

[0048] In a preferred embodiment, the level conversion and latching unit includes an AND gate 5, a level conversion circuit 6, and an SR flip-flop 7. The two inputs of the AND gate 5 are connected to the output of the comparator unit 1 and an enable signal I1, respectively. The output of the AND gate 5 is connected to the input of the level conversion circuit 6, and the output of the level conversion circuit 6 is connected to the set input of the SR flip-flop 7. The level conversion circuit 6 converts the high-voltage overcurrent trigger signal into a low-voltage signal. The set input of the SR flip-flop 7 is connected to the output of the level conversion circuit 6, and the reset input of the SR flip-flop 7 is connected to the reset signal output 9 of the digital control unit, used to clear the latched state according to the reset signal. To precisely control the recording timing of the overcurrent signal, the AND gate 5 is introduced. Its two inputs are connected to the comparator output and the enable signal I1, respectively. The I1 signal directly originates from the input control logic of the high-side switch, accurately reflecting the conduction period of the power transistor. Only when I1 is high (indicating that the power transistor is on) can the overcurrent signal output by the comparator pass through the AND gate. This effectively prevents false triggering signals caused by output node voltage disturbances or system noise coupled to the comparator input during power transistor turn-off from being transmitted to the back end, significantly improving the circuit's anti-interference capability. The overcurrent pulse (if any) following the AND gate then enters the level shifting circuit 6. Since the comparator and pre-amplifier circuits operate in a high-voltage domain (potentially above 40V), while the digital control unit operates in a low-voltage domain (e.g., 1.8V or 3.3V), the level shifting circuit is an essential interface. It employs a differential structure or gate voltage bootstrapping technology to reliably convert high-voltage pulse signals to low-voltage logic levels. The converted low-voltage pulse is sent to the set input S of the SR flip-flop 7. The SR flip-flop is a basic digital storage unit. Its key feature is that even if the input overcurrent pulse is very short (e.g., due to a rapid turn-off unit action causing the current drop and the comparator to quickly flip back to low), once a high-level pulse is received at the S input, its output immediately jumps to high and latches. This characteristic perfectly solves the problem that analog pulse widths are insufficient for reliable sampling by the back-end digital circuitry. Regardless of the duration of the overcurrent event, the SR flip-flop "freezes" it into a continuous logic high state, ensuring that the digital control unit (DCU) will capture the event. Only after the fault is cleared, and the DCU sends a high-level pulse to the reset terminal of the SR flip-flop via the restart signal output 9, will the flip-flop be reset, its output going low, preparing for the next overcurrent detection. This latching mechanism forms the basis for subsequent overcurrent retry counting and state machine management, but is not limited to it.

[0049] In a preferred embodiment, the digital control unit further includes a fault counter for recording the number of overcurrent signals received within a preset time. When the number reaches the overcurrent retry count, the digital control unit outputs a shutdown signal to turn off the output power transistor. The digital control unit is the brain of the entire protection circuit. Its internal fault counter is a key module. The fault counter increments once whenever the SR flip-flop 7 latches an overcurrent event and sends a signal to the digital control unit. The state machine inside the digital control unit simultaneously starts a timing window (e.g., 100ms). Within this timing window, if the value of the fault counter reaches the "overcurrent retry count" preset by the user through a register (e.g., set to 3 times), the state machine will determine it as a permanent fault and issue an instruction to latch the shutdown state of the driver stage 10, no longer attempting to restart. Simultaneously, it writes a "permanent fault" flag to the diagnostic register, but this is not a limitation.

[0050] In a preferred embodiment, the digital control unit sets the overcurrent shielding time by configuring comparator unit 1 or level shifting and latching unit; during the overcurrent shielding time after the output power transistor is turned on, it does not respond to the overcurrent trigger signal. The overcurrent shielding time is implemented by another timer. This timer starts after each power transistor is turned on (I1 goes high) or after each restart attempt (restart signal is issued). Before the shielding timer overflows, the digital control unit can shield the overcurrent signal in two ways: one is to internally shield the signal from the SR flip-flop; the other, more preferred way, is to use the shielding signal to control another input of AND gate 5 (e.g., to force the I1 signal low during the shielding period), thereby blocking the transmission of the overcurrent signal at the source of the signal chain. This method ensures that during load start-up surges (such as when the bulb filament resistance is low or the motor starting current is high), the protection circuit completely "ignores" these non-faulty, short-term overcurrents, perfectly avoiding false shutdown, but is not limited to this.

[0051] In a preferred embodiment, the digital control unit (MCU) further includes a fault diagnosis and reporting interface for reporting overcurrent events, fault count status, and permanent shutdown information to the system master control unit (MCU). The fault diagnosis and reporting interface is typically a standard SPI slave interface. The MCU can read the chip's status register at any time via the SPI bus to obtain real-time fault information, including: whether an overcurrent has occurred, the current fault count, whether it is in a permanent shutdown state, and the chip temperature. This enables the system to achieve closed-loop intelligent control. For example, when the MCU reads a "permanent overheat shutdown" report from a high-side switch, it can record the fault code and prompt the driver to check it via the human-machine interface. This fully meets the requirements of high-standard functional safety specifications such as ISO 26262 for system diagnostic coverage and fault response capabilities, but is not limited to them.

[0052] In a preferred embodiment, the digital control unit is connected to the driver stage 10 via a high-level delay 3 and a first inverter 4. The speed at which the fast shutdown unit 2 responds to the overcurrent trigger signal is faster than the speed at which the digital control unit turns off the output power transistor via the driver stage 10.

[0053] The connection between the high-level delay unit 3 and the first inverter 4 clearly demonstrates the dual-path protection strategy of this invention. The fast shutdown unit 2 is directly controlled by the comparator, resulting in an extremely short path and achieving nanosecond-level instantaneous current limiting (clamping). After being latched by the SR flip-flop, widened by the high-level delay unit (ensuring reliable sampling by the digital logic), and processed by the inverter logic, the final path to turn off the power transistor via the driver stage 10 typically has a delay in the hundreds of nanoseconds to microseconds. Although this delay is relatively long, its function is not to limit spikes, but to perform a thorough, state-machine-controlled shutdown. The fast shutdown path comes first, ensuring the safety of the power transistor; the digital shutdown path follows, ensuring the correctness of the system logic and the reliability of fault handling. The two complement each other, jointly constructing a fast and intelligent overcurrent protection system, but this is not its limitation.

[0054] The specific embodiments of the present invention are as follows: This embodiment provides an overcurrent protection circuit applied to a smart high-side switch chip. For example... Figure 1 As shown, the circuit mainly includes: a resistorless sampling unit composed of a current mirror, a reference voltage generation unit composed of a reference current source and a resistor network, a comparator unit 1, a fast turn-off unit 2 composed of NMOS transistors, a level conversion and latching unit including an AND gate 5, a level conversion circuit 6 and an SR flip-flop 7, and a digital control unit (shown in conjunction with the driver stage 10 in the figure).

[0055] The core of this invention lies in resistance-free sampling and flexible threshold comparison. For example... Figure 1 As shown, the resistorless sampling unit adopts a current mirror structure, and is connected to the output power transistor (high-side power transistor). Figure 1 (Not fully shown) A sampled current Is is replicated proportionally. This sampled current Is is strictly proportional to the load current IOUT flowing through the power transistor, let the ratio be K. LIM That is, Is = IOUT / K LIM The sampling current Is flows through resistor R4, generating a sampling voltage component proportional to IOUT at the upper end of R4 (i.e., the V+ node). Simultaneously, a reference current generated by a zero-temperature-coefficient reference current source flows through resistors R1, R2, and R3 in series. Resistors R1 and R3 are designed to have the same resistance value. Therefore, at the V- node, the reference current flows through R1 and R2, forming a reference voltage V- = IB.LIM (R1 + R2). At the V+ node, the voltage consists of two parts: one part is the bias voltage IB generated by the reference current flowing through R3 and R4. LIM (R3 + R4), the other part is the sampling voltage Is generated by the sampling current Is flowing through R4. R4. Since R3 = R1, therefore V+ = IB LIM (R1 + R4) + (IOUT / K) LIM ) R4.

[0056] The positive input of comparator unit 1 is connected to V+, and the negative input is connected to V-. When V+ > V-, i.e., IB... LIM (R1 + R4) + (IOUT / K) LIM ) R4 > IB LIM When (R1 + R2) is connected, the comparator flips, outputting a high-level overcurrent trigger signal. From this, the overcurrent threshold IOUT can be derived. MAX for: IOUT MAX = IB LIM (R2 - R4) / R4 K LIM

[0057] As can be seen from the formula, the current limiting value IOUT MAX With bias current IB LIM The resistance ratio (R2-R4) / R4 and the sampling ratio K LIM Relevant. Due to IB LIM The reference current has a zero temperature coefficient, and resistors R2 and R4 can be well matched internally within the chip. Therefore, the current limiting value is insensitive to temperature and process drift, exhibiting high accuracy and stability. The overcurrent threshold can be adjusted by changing the ratio of R2 and R4, or by changing the reference current. In a preferred embodiment, R4 can be a fixed value, while R2 can be configured as a programmable resistor divider network via a digital control unit, thereby achieving digital adjustment of the overcurrent threshold.

[0058] The output of comparator unit 1 is the central component of the entire protection circuit. It drives two parallel protection paths: one is an analog fast shutdown path, and the other is a digital logic shutdown path.

[0059] In the fast shutdown path, the output of comparator unit 1 is directly connected to the control terminal (gate of the NMOS transistor) of fast shutdown unit 2. The drain of the NMOS transistor in fast shutdown unit 2 is connected to the gate G of the high-side power transistor, and the source is connected to the source S (i.e., the power supply terminal) of the high-side power transistor. Under normal operating conditions, the comparator output is low, the NMOS transistor is turned off, and the normal operation of the power transistor is not affected. Once an overcurrent occurs, the comparator output instantly flips to a high level, immediately turning on the NMOS transistor. Because the on-resistance of the NMOS transistor is very small, it quickly pulls down the gate voltage of the power transistor to near its source voltage (power supply voltage), thereby forcing the power transistor into the off region or linear region, greatly limiting the continued rise of the current. This path is completely analog, without any digital logic, so the response speed is extremely fast (down to the nanosecond level), and it can suppress current spikes as soon as they appear, effectively protecting the power transistor.

[0060] However, because the comparator output may quickly flip low again after the current drops in the fast turn-off path, causing the NMOS transistor to turn off and the power transistor to turn on again, oscillations may occur if the fault persists. Therefore, a second path is needed to achieve thorough and reliable turn-off and status recording.

[0061] In the digital logic shutdown path, the output of comparator unit 1 is first fed into an AND gate 5. The other input of AND gate 5 is the enable signal I1. A high level I1 indicates that the power transistor is in the ON state, ensuring that the overcurrent signal is only processed during the power transistor's on-time, thus avoiding false triggering during chip sleep or shutdown. The signal after AND gate 5 is then converted from a high-voltage (potentially tens of volts) overcurrent signal to a low-voltage (e.g., 1.8V or 3.3V) logic signal by a level conversion circuit 6. This low-voltage signal is then fed to the set (S) terminal of SR flip-flop 7. The reset (R) terminal of SR flip-flop 7 is connected to the reset signal output 9 of the digital control unit. The characteristic of SR flip-flop 7 is that once set (S terminal receives a high level), its output remains high, regardless of subsequent changes in the S terminal, until a reset signal (R terminal high level) is received. Therefore, even if the overcurrent pulse output by the comparator is very brief, the SR flip-flop 7 can "memorize" it and latch it into a continuous high-level state, ensuring that subsequent digital circuits can reliably capture this overcurrent event. The output of the SR flip-flop 7 is processed by the high-level delay unit 3 (used for pulse shaping and widening to ensure that the timing requirements of the back-end are met) and the first inverter 4 before being sent to the control terminal of the driver stage 10. Upon receiving this signal, the driver stage 10 will completely shut down the power transistor.

[0062] Embodiments of the present invention also provide an intelligent high-side switch chip, including: the overcurrent protection circuit as described above. The display device of the present invention incorporates the structural features, techniques, and effects of the above-described overcurrent protection circuit, which will not be repeated here. This embodiment provides an intelligent high-side switch chip including the overcurrent protection circuit described in Embodiment 1. Figure 2 The control flow of the chip is illustrated. For example... Figure 2 As shown, the dashed box illustrates the current limiting architecture of this invention. External control commands (such as SPI commands from the MCU) configure the registers inside the digital control unit via a digital interface. These register values ​​determine the overcurrent threshold (generated by controlling the reference voltage generation unit), the overcurrent shielding time, and the number of overcurrent retries. When the chip is operating, after the power transistor is turned on, the current limiting detection circuit (… Figure 1 (As shown) Real-time monitoring of output current. Once an overcurrent event exceeding a set threshold occurs, the analog fast shutdown path immediately activates, and the digital path records the event. The digital control unit, based on the configuration, attempts to restart after the shielding time has elapsed. A fault counter records whether an overcurrent event occurs again after the restart. Finally, the digital control unit reports the current fault status (e.g., normal, overcurrent occurred, retrying, permanent fault) to the MCU in real-time via the diagnostic interface, achieving complete closed-loop control and diagnostics.

[0063] Figure 2 This is a schematic diagram of the intelligent high-side switch control flow using the overcurrent protection circuit of the present invention. Figure 2 As shown, the digital control unit (whose logical functions are implemented through digital circuits, such as...) Figure 2 The digital control unit (DCU) receives a latched overcurrent signal and determines its next action based on its internal state machine configuration. For example, if configured for retry mode, the DCU will wait for a programmable "overcurrent shielding time" and then send a reset pulse through the restart signal output terminal 9 to reset the SR flip-flop 7 and attempt to restart the power transistor through the driver stage 10. Simultaneously, the DCU contains an internal fault counter to record the number of overcurrent events. When the number of overcurrent events reaches the user-configured "overcurrent retry count" within a preset time, the DCU will no longer attempt to restart but will permanently latch off the output and report a "permanent fault" to the system master unit through its fault diagnosis and reporting interface (such as a standard SPI interface).

[0064] Overcurrent shielding time can be implemented in several ways. A simple approach is to implement a timer within the digital control unit (DCU). The DCU starts the timer the instant the power transistor is turned on, or after each restart attempt. Before the timer overflows (i.e., during the shielding period), the DCU ignores any overcurrent signal from the SR flip-flop 7, or directly shields the overcurrent signal from entering subsequent circuitry by controlling AND gate 5 (e.g., controlling one input of AND gate 5 with a shielding signal). The length of the shielding time can be flexibly set by configuring register values ​​within the DCU.

[0065] Through the aforementioned dual-path and flexible digital control, the overcurrent protection circuit of this embodiment achieves both nanosecond-level fast current limiting and reliable state latching, flexible retry strategies, and fault diagnosis and reporting that meet functional safety requirements.

[0066] Compared with the prior art, the present invention has the following beneficial effects: Fast response and low power consumption: An open-loop analog path consisting of a comparator detection and a fast shutdown unit is used for real-time monitoring after the high-side power transistor is turned on. Once an overcurrent is detected, the fast shutdown unit (NMOS transistor) immediately activates, directly pulling down the power transistor gate with an extremely short delay (nanosecond level), achieving nanosecond-level current limiting. Simultaneously, due to the use of resistorless sampling and an open-loop comparison structure, the static power consumption of the entire protection circuit is very low. Fast shutdown and subsequent digital shutdown operate in parallel, providing dual protection that ensures both speed and complete shutdown.

[0067] High detection accuracy and stable threshold: Resistive sampling utilizes a current mirror to accurately replicate the current, avoiding the power consumption and voltage drop issues of the sampling resistor. The reference voltage is generated by a zero-temperature-coefficient reference current and a resistor divider network, ensuring a stable current limit (IOUT). MAX It is independent of temperature and power supply voltage, and depends only on the resistance ratio and sampling ratio. With careful design and adjustment, extremely high detection accuracy and temperature stability can be achieved.

[0068] Flexible and configurable protection strategies: The digital control unit integrates programmable registers, allowing overcurrent thresholds, overcurrent shielding time (to handle inrush currents), and overcurrent retry counts (to handle transient faults) to be flexibly configured via external commands. This enables the same chip to adapt to different types of loads (resistive, capacitive, inductive), greatly expanding the application range and effectively reducing the probability of false triggering. For example, a longer shielding time can be set for loads with large inrush currents, such as halogen lamps; and an appropriate number of retry counts can be configured for motor stall.

[0069] Meeting functional safety requirements: The circuit not only has protection functions but also complete diagnostic functions. Overcurrent events are recorded through a fault counter, and fault information (such as the number of overcurrents and whether a permanent shutdown has occurred) is reported to the system's main control unit (MCU) in real time through a fault diagnosis and reporting interface. This fully complies with the requirements of functional safety standards such as ISO 26262 for system fault detection and diagnosis capabilities, laying the foundation for building a highly reliable system.

[0070] High integration and few external components: The fully integrated resistorless sampling and built-in adjustable reference source enable the entire overcurrent protection circuit to be integrated inside the chip, eliminating the need for any external sampling resistors, capacitors or comparators. This greatly simplifies the system PCB design, reduces BOM cost and system size, and eliminates parasitic parameters and EMC problems introduced by external components.

[0071] In summary, the overcurrent protection circuit and intelligent high-side switch chip of the present invention solve the problems of contradiction between response speed and power consumption, easy false triggering, and inflexible adjustment in the prior art. They have the advantages of fast response, high precision, low power consumption, strong configurability, and meeting functional safety requirements.

[0072] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An overcurrent protection circuit, characterized in that, include: A resistanceless sampling unit is provided, wherein the input terminal of the resistanceless sampling unit is connected to the output power transistor of the intelligent high-side switching chip, and is used to sample the output current of the output power transistor to generate a sampling current (Is) proportional to the output current, and convert the sampling current (Is) into a sampling voltage. A reference voltage generation unit is used to generate an adjustable reference voltage; A comparator unit (1) has a first input terminal connected to the sampled voltage and a second input terminal connected to the reference voltage. It is used to compare the sampled voltage with the reference voltage and output an overcurrent trigger signal when the sampled voltage exceeds the reference voltage. The fast shutdown unit (2) has its input terminal connected to the output terminal of the comparator unit (1) and its output terminal connected to the control electrode of the output power transistor. It is used to directly and quickly pull down the control electrode potential of the output power transistor after receiving the overcurrent trigger signal, so as to clamp or limit the output current. The level conversion and latching unit has its input terminal connected to the output terminal of the comparator unit (1) and is used to convert the high voltage domain overcurrent trigger signal output by the comparator unit (1) into a low voltage domain signal and latch the signal. A digital control unit, the input terminal of which is connected to the output terminal of the level conversion and latching unit, and its output terminal is connected to the driver stage (10) of the intelligent high-side switch chip, for controlling the driver stage (10) to turn off the output power transistor after receiving the latched overcurrent signal; Furthermore, the digital control unit is equipped with a programmable register for receiving external control commands to adjust at least one of the following parameters: overcurrent threshold, overcurrent shielding time, and overcurrent retry count.

2. The overcurrent protection circuit according to claim 1, characterized in that, The resistorless sampling unit adopts a current mirror structure, and its sampling ratio is related to the size ratio of the output power transistor.

3. The overcurrent protection circuit according to claim 1, characterized in that, The reference voltage generation unit includes a reference current source with zero temperature coefficient that provides a reference current and a set of programmable resistor divider networks. The digital control unit adjusts the reference voltage by configuring the tap positions of the resistor divider networks, thereby adjusting the overcurrent threshold.

4. The overcurrent protection circuit according to claim 1, characterized in that, The fast shutdown unit (2) includes an NMOS transistor, the drain of which is connected to the gate of the output power transistor, the source of which is connected to the source of the output power transistor, and the gate of which is connected to the output terminal of the comparator unit (1).

5. The overcurrent protection circuit according to claim 1, characterized in that, The level conversion and latching unit includes an AND gate (5), a level conversion circuit (6), and an SR flip-flop (7). The two inputs of the AND gate (5) are connected to the output of the comparator unit (1) and an enable signal (I1), respectively. The output of the AND gate (5) is connected to the input of the level conversion circuit (6). The output of the level conversion circuit (6) is connected to the set terminal of the SR flip-flop (7). The level conversion circuit (6) converts the overcurrent trigger signal in the high voltage domain into a low voltage domain signal. The set terminal of the SR flip-flop (7) is connected to the output of the level conversion circuit (6). The reset terminal of the SR flip-flop (7) is connected to the restart signal output terminal (9) of the digital control unit, which is used to clear the latching state according to the restart signal.

6. The overcurrent protection circuit according to claim 1, characterized in that, The digital control unit further includes a fault counter for recording the number of overcurrent signals received within a preset time. When the number of overcurrent retry attempts reaches the overcurrent retry count, the digital control unit outputs a shutdown signal to shut down the output power transistor.

7. The overcurrent protection circuit according to claim 1, characterized in that, The digital control unit sets the overcurrent shielding time by configuring the comparator unit (1) or the level conversion and latching unit; during the overcurrent shielding time after the output power tube is turned on, it does not respond to the overcurrent trigger signal.

8. The overcurrent protection circuit according to claim 1, characterized in that, The digital control unit also includes a fault diagnosis and reporting interface, which is used to report the occurrence of overcurrent events, fault count status, and permanent shutdown information to the system main control unit.

9. The overcurrent protection circuit according to any one of claims 1 to 8, characterized in that, The digital control unit is connected to the drive stage (10) through a high-level delay (3) and a first inverter (4). The fast shutdown unit (2) responds to the overcurrent trigger signal faster than the digital control unit turns off the output power transistor through the drive stage (10).

10. A smart high-side switch chip, characterized in that, It includes the overcurrent protection circuit as described in any one of claims 1 to 9.

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