Converter and low-power control circuit and method thereof, secondary side control chip

Abstract

This application relates to the field of switching power supply technology, and discloses a converter and its low-power control circuit and method, as well as a secondary-side control chip. The converter includes a secondary-side control chip and a protocol chip disposed on the secondary side. The low-power control circuit includes: a voltage detection unit configured to detect the output voltage of the converter to obtain a voltage detection value, wherein the resistance value of the sampling resistor in the voltage detection unit is greater than the resistance value of the feedback resistor in the voltage feedback unit; and a control unit configured to control the converter to enter a sleep mode and control the voltage feedback unit to turn off when the secondary-side control chip receives a sleep signal, and to perform bang-bang control on the converter based on the voltage detection value when the converter is in sleep mode. This application significantly reduces standby power consumption by using the secondary-side control chip as the main controller for standby low-power control and by turning off the voltage feedback unit, which has high standby power consumption, when the converter is in standby mode.

Description

Technical Field

[0001] This application relates to the field of switching power supply technology, and in particular to a low-power control circuit for a converter, a secondary-side control chip, a converter, and a low-power control method for a converter. Background Technology

[0002] With the rapid development of power electronics technology, the market demand for low standby power consumption in switching converters is increasing, with some manufacturers even demanding zero standby power consumption (e.g., less than 5mW). In flyback converter applications, the main control chip is typically located on the primary side, and the output of the secondary side is fed back to the main control chip on the primary side via an optocoupler so that the main control chip can perform PWM control.

[0003] Therefore, in the current standby mode of flyback converters, the low standby power consumption is achieved by the primary-side main control chip using a hiccup mode. Its standby power consumption is much greater than 5mW, which cannot meet the requirement of zero standby power consumption. Summary of the Invention

[0004] The purpose of this application is to provide a low-power control circuit, a low-power control method, a secondary-side control chip, and a converter. By using the secondary-side control chip as the master controller for standby low-power control, it is not necessary to feed the output of the secondary side back to the primary side through an optocoupler. Furthermore, when the converter is in standby mode, the voltage feedback unit with high standby power consumption in the secondary-side control chip can be turned off, which can greatly reduce standby power consumption and meet the requirement of zero standby power consumption.

[0005] To achieve the above objectives, the main technical solutions adopted in this application include:

[0006] In a first aspect, embodiments of this application provide a low-power control circuit for a converter. The converter includes a secondary-side control chip and a protocol chip disposed on the secondary side. The secondary-side control chip communicates with the protocol chip to receive a sleep signal sent by the protocol chip. The low-power control circuit includes: a voltage detection unit configured to detect the output voltage of the converter to obtain a voltage detection value, wherein the resistance value of the sampling resistor in the voltage detection unit is greater than the resistance value of the feedback resistor in the voltage feedback unit of the secondary-side control chip; and a control unit configured to, when the secondary-side control chip receives the sleep signal, control the converter to enter a sleep mode and control the voltage feedback unit to turn off, and, when the converter is in the sleep mode, perform bang-bang control on the converter based on the voltage detection value.

[0007] According to the low-power control circuit of the converter provided in the embodiments of this application, the converter is controlled to enter sleep mode by communicating between the secondary control chip and the protocol chip to receive the sleep signal sent by the protocol chip. In this way, the secondary control chip on the secondary side can be used as the master controller for standby low-power control without having to feed back the output of the secondary side to the primary side through an optocoupler. Furthermore, when the converter enters sleep mode, the voltage feedback unit with high standby power consumption in the secondary control chip can be turned off, and the output voltage detected by the voltage detection unit with low standby power consumption can be used for bang-bang control, which greatly reduces standby power consumption and can meet the requirement of zero standby power consumption, thus saving energy and protecting the environment.

[0008] Optionally, in some embodiments of this application, the voltage feedback unit includes a resistor voltage divider module, one end of which receives the output voltage of the converter through a first controllable switch, and the other end of which is grounded. The control unit turns off the voltage feedback unit by controlling the first controllable switch to open.

[0009] Optionally, in some embodiments of this application, the resistor voltage divider module includes a first resistor and a second resistor connected in series, and a first node between the first resistor and the second resistor serves as the feedback terminal of the voltage feedback unit, wherein the resistance values ​​of the first resistor and the second resistor are respectively less than the resistance value of the sampling resistor.

[0010] Optionally, in some embodiments of this application, the secondary-side control chip includes a feedback pin, which is connected to the feedback terminal of the voltage feedback unit and the feedback control terminal of the protocol chip. The control unit receives the sleep signal based on the feedback pin so that the secondary-side control chip can multiplex the feedback pin.

[0011] Optionally, in some embodiments of this application, the protocol chip is configured with a first current source, a second current source, and a second controllable switch. The positive terminal of the first current source is connected to the negative terminal of the second current source, and a second node is provided. The second node is connected to the feedback control terminal of the protocol chip. The negative terminal of the first current source is connected to the ground terminal of the protocol chip, and the positive terminal of the second current source is connected to the power supply terminal of the protocol chip. The second controllable switch is connected in parallel with the first current source. The protocol chip sends the sleep signal to the feedback pin through the feedback control terminal by controlling the second controllable switch to close; the protocol chip sends an exit sleep signal to the feedback pin through the feedback control terminal by controlling the second controllable switch to open.

[0012] Optionally, in some embodiments of this application, the control unit includes: a first comparator, the positive input terminal of the first comparator being connected to the output terminal of the voltage detection unit, and the negative input terminal of the first comparator being connected to the feedback pin; a first trigger, the setting terminal of the first trigger being connected to the output terminal of the first comparator, and the output terminal of the first trigger being connected to the control terminal of the first controllable switch, the first trigger being configured to output a shutdown control signal when the first comparator receives the sleep signal, so as to control the first controllable switch to turn off.

[0013] Optionally, in some embodiments of this application, the control unit is further configured to, upon receiving an exit sleep signal at the feedback pin, control the converter to exit the sleep mode and control the first controllable switch to close, so as to control the converter according to the voltage feedback value of the voltage feedback unit.

[0014] Optionally, in some embodiments of this application, the control unit further includes: a second comparator, the positive input terminal of the second comparator being connected to the feedback pin, the negative input terminal of the second comparator being adapted to access a wake-up reference voltage, and the output terminal of the second comparator being connected to the reset terminal of the first flip-flop, wherein the first flip-flop is further configured to output a closing control signal when the second comparator receives the exit sleep signal, so as to control the first controllable switch to close.

[0015] Optionally, in some embodiments of this application, the voltage detection unit includes: a third resistor, one end of which is used to receive the output voltage of the converter; a fourth resistor, one end of which is connected to the other end of the third resistor and has a third node as the output terminal of the voltage detection unit, the other end of which is grounded, wherein the resistance values ​​of the third resistor and the fourth resistor are respectively greater than the resistance value of the feedback resistor.

[0016] Optionally, in some embodiments of this application, the control unit further includes: a third comparator, the positive input terminal of which is adapted to be connected to a first reference voltage, and the negative input terminal of which is connected to the third node; a fourth comparator, the positive input terminal of which is connected to the third node, and the negative input terminal of which is adapted to be connected to a second reference voltage, wherein the second reference voltage is greater than the first reference voltage; and a second flip-flop, the setting terminal of which is connected to the output terminal of the third comparator, the reset terminal of which is connected to the output terminal of the fourth comparator, and the second flip-flop being configured to generate a bangbang control signal based on the comparison signal output by the third comparator and the comparison signal output by the fourth comparator.

[0017] Optionally, in some other embodiments of this application, the secondary control chip and the protocol chip establish communication through a sleep enable pin to receive a sleep signal sent by the protocol chip.

[0018] Secondly, embodiments of this application provide a secondary-side control chip, including the low-power control circuit described in the above embodiments.

[0019] According to the secondary-side control chip provided in the embodiments of this application, based on the aforementioned low-power control circuit, when communicating with the protocol chip to receive the sleep signal sent by the protocol chip, the converter is controlled to enter sleep mode, thereby enabling it to act as the master controller to perform standby low-power control on the converter. This eliminates the need for optocouplers to feed back the secondary-side output to the primary-side. Furthermore, when the converter enters sleep mode, the voltage feedback unit with high standby power consumption in the chip can be turned off, and Bangbang control can be performed based on the output voltage detected by the voltage detection unit with low standby power consumption, greatly reducing standby power consumption and meeting the requirement of zero standby power consumption, thus saving energy and protecting the environment.

[0020] Thirdly, embodiments of this application also provide a converter, including: the low-power control circuit described in the above embodiments; or the secondary-side control chip described in the above embodiments.

[0021] According to the converter provided in the embodiments of this application, communication is established between the secondary control chip and the protocol chip to receive the sleep signal sent by the protocol chip, thereby realizing the control of entering the sleep mode. This enables the secondary control chip on the secondary side to act as the master controller for low-power standby control, eliminating the need to feed back the output of the secondary side to the primary side through an optocoupler. Furthermore, when entering the sleep mode, the voltage feedback unit with high standby power consumption in the secondary control chip can be turned off, and Bangbang control is performed based on the output voltage detected by the voltage detection unit with low standby power consumption, which greatly reduces standby power consumption and meets the requirement of zero standby power consumption, thus saving energy and protecting the environment.

[0022] Fourthly, embodiments of this application also provide a low-power control method for a converter. The converter includes a secondary-side control chip and a protocol chip disposed on the secondary side. The secondary-side control chip communicates with the protocol chip to receive a sleep signal sent by the protocol chip. The low-power control method includes: configuring a voltage detection unit in the secondary-side control chip to detect the output voltage of the converter and obtain a voltage detection value, wherein the resistance value of the sampling resistor in the voltage detection unit is greater than the resistance value of the feedback resistor in the voltage feedback unit of the secondary-side control chip; when the secondary-side control chip receives the sleep signal, controlling the converter to enter a sleep mode and controlling the voltage feedback unit to turn off; and when the converter is in the sleep mode, performing bang-bang control on the converter according to the voltage detection value.

[0023] According to the low-power control method for converters provided in this application, communication between the secondary-side control chip and the protocol chip is established to receive the sleep signal sent by the protocol chip, thereby enabling control to enter the sleep mode. This allows the secondary-side control chip to act as the master controller for low-power standby control, eliminating the need to feed back the secondary-side output to the primary side via an optocoupler. Furthermore, by configuring a voltage detection unit with lower standby power consumption in the secondary-side control chip to replace the voltage feedback unit with higher standby power consumption, the voltage feedback unit with higher standby power consumption in the secondary-side control chip can be shut down when the converter enters sleep mode. Bangbang control is then performed based on the output voltage detected by the voltage detection unit with lower standby power consumption, significantly reducing standby power consumption and meeting the requirement of zero standby power consumption, thus saving energy and protecting the environment.

[0024] Optionally, in some embodiments of this application, the secondary-side control chip includes a feedback pin, which is connected to the feedback terminal of the voltage feedback unit and the feedback control terminal of the protocol chip. The secondary-side control chip receives the sleep signal based on the feedback pin to multiplex the feedback pin.

[0025] Optionally, in some embodiments of this application, the protocol chip is configured with a first current source, a second current source, and a second controllable switch. The positive terminal of the first current source is connected to the negative terminal of the second current source and has a second node. The second node is connected to the feedback control terminal of the protocol chip. The negative terminal of the first current source is connected to the ground terminal of the protocol chip. The positive terminal of the second current source is connected to the power supply terminal of the protocol chip. The second controllable switch is connected in parallel with the first current source. The method further includes: when the protocol chip controls the second controllable switch to close, receiving a sleep signal sent by the feedback control terminal based on the feedback pin; when the protocol chip controls the second controllable switch to close, receiving an exit sleep signal sent by the feedback control terminal based on the feedback pin.

[0026] Optionally, in some embodiments of this application, when the feedback pin receives the exit sleep signal, the method further includes: controlling the converter to exit the sleep mode and controlling the voltage feedback unit to operate so as to control the converter according to the voltage feedback value of the voltage feedback unit.

[0027] Optionally, in some embodiments of this application, performing bangbang control on the converter based on the voltage detection value includes: determining a first reference voltage and a second reference voltage, wherein the second reference voltage is greater than the first reference voltage; comparing the voltage detection value with the first reference voltage and the second reference voltage respectively, and generating a bangbang control signal to perform bangbang control on the converter. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0029] Figure 1 This is a circuit diagram of a flyback converter in related technologies;

[0030] Figure 2 A circuit diagram of a converter provided in one embodiment of this application;

[0031] Figure 3 This is a schematic diagram illustrating communication between a secondary control chip and a protocol chip via the Sleep_EN pin, as provided in one embodiment of this application.

[0032] Figure 4 A waveform diagram illustrating ZVS control implemented by a converter according to an embodiment of this application;

[0033] Figure 5 A circuit diagram illustrating the multiplexing of the FB pin between the secondary control chip and the protocol chip according to one embodiment of this application;

[0034] Figure 6 A schematic diagram illustrating a secondary control chip as a feedback master controller in one embodiment of this application for feedback control;

[0035] Figure 7 A schematic diagram of Bangbang control of a converter in sleep mode according to an embodiment of this application;

[0036] Figure 8 A schematic diagram of control waveforms for a converter entering and exiting sleep mode and being in sleep mode, provided in an embodiment of this application;

[0037] Figure 9 This is a block diagram of a converter provided in one embodiment of this application;

[0038] Figure 10 A block diagram of a converter provided in another embodiment of this application;

[0039] Figure 11 This is a flowchart illustrating a low-power control method for a converter provided in one embodiment of this application. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] In related technologies, such as Figure 1 As shown, in flyback converter applications, the main control chip is typically placed on the primary side, and the output of the secondary side is fed back to the main control chip on the primary side via an isolation optocoupler so that the main control chip can perform PWM control. In this way, when the flyback converter performs hiccup control in standby mode, it needs to be controlled based on the output voltage fed back by the isolation optocoupler. This not only results in insufficient hiccup depth leading to high standby power consumption, but also in standby hiccup mode, due to the low COMP voltage of the main control chip, a relatively large current flows through the isolation optocoupler, thereby increasing the standby power consumption on both the primary and secondary sides, making it difficult to achieve the requirement of zero standby power consumption.

[0042] Therefore, the low-power control circuit of the converter, the secondary-side control chip with the low-power control circuit, the low-power control method of the converter and the converter provided in this application embodiment, by using the secondary-side control chip as the master controller for standby low-power control, do not need to feed the output of the secondary side back to the primary side through the isolation optocoupler, and can turn off the voltage feedback unit with large standby power consumption in the secondary-side control chip when the converter is in standby mode, which can greatly reduce standby power consumption and meet the requirement of zero standby power consumption.

[0043] The low-power control circuit of the converter, the secondary control chip having the low-power control circuit, the low-power control method of the converter, and the converter provided in the embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0044] refer to Figure 2 The diagram shown is a circuit schematic of a converter according to an embodiment of this application. Figure 2 As shown, the converter includes a transformer T1, a primary control chip U1 and a primary switch Qp located on the primary side, a secondary control chip U2 and a protocol chip U3 located on the secondary side, and a rectifier switch Qp. SR The secondary control chip U2 communicates with the protocol chip U3 to receive the sleep signal sent by the protocol chip U3.

[0045] Optionally, in some embodiments of this application, such as Figure 3 As shown, the secondary control chip U2 and the protocol chip U3 establish communication through the Sleep_EN pin to receive the sleep signal sent by the protocol chip U3, and perform standby control on the converter when the sleep signal is received.

[0046] In other words, if the number of pins on the secondary control chip U2 and the protocol chip U3 is sufficient, the secondary control chip U2 and the protocol chip U3 can communicate directly through the sleep enable pin Sleep_EN. In this way, when the protocol chip U3 detects that there is no load connected to the output port, it can use the sleep enable pin Sleep_EN to notify the secondary control chip U2 to control the converter to enter sleep standby mode.

[0047] Furthermore, such as Figure 3As shown, the low-power control circuit 100 includes a voltage detection unit 101 and a control unit 102. The voltage detection unit 101 is configured to detect the output voltage of the converter to obtain a voltage detection value Vo_sense, and the resistance values ​​of the sampling resistors (e.g., resistors R3 and R4) in the voltage detection unit 101 are greater than the resistance values ​​of the feedback resistors (e.g., resistors R1 and R2) in the voltage feedback unit 200 of the secondary-side control chip U2. The control unit 102 is configured to control the converter to enter a sleep mode and control the voltage feedback unit 200 to turn off when the secondary-side control chip U2 receives a sleep signal, and to perform bang-bang control on the converter based on the voltage detection value Vo_sense while the converter is in sleep mode.

[0048] Since the sampling resistors (e.g., R3 and R4) in the voltage detection unit 101 have greater resistance values ​​than the feedback resistors (e.g., R1 and R2) in the voltage feedback unit 200, the voltage feedback unit 200 is turned off after the converter enters sleep mode. The voltage detection unit 101 then replaces the voltage feedback unit 200 in detecting the converter's output voltage, significantly reducing system standby power consumption. Furthermore, the secondary-side control chip U2, located on the secondary side, receives the sleep signal sent by the protocol chip U3 for standby control, eliminating the need to isolate and feed back the converter's output to the primary side, reducing signal isolation transmission and lowering standby power consumption.

[0049] In the embodiments of this application, combined with Figures 2 to 4 As shown, the protocol chip U3 can connect a current source I1 from the FB pin to the ground pin GND. This allows it to change the output voltage by altering the magnitude of the current source I1 according to the load protocol requirements, thus achieving output voltage feedback. The secondary-side control chip U2 acts as the feedback master, and determines the start time of the switching cycle based on the secondary output feedback error amplification signal. Figure 4 The ZVS pulse starts at time t3. The ZVS pulse transmits the signal to the primary side through the transformer T. After the primary control chip U1 detects the turn-on signal, it turns on the primary switch Qp at time t5.

[0050] Specifically, such as Figure 4 As shown, during times t0 to t1: Vgsp is high, the primary switch Qp is turned on, and the energy is supplied to the magnetizing inductor of the transformer T for energy storage; during times t1 to t2: the primary switch Qp is turned off, Vgs_SR is high, and the rectifier switch Q... SR When turned on, the excitation current passes through the synchronous rectifier switch Q. SRFreewheeling; at times t2 to t3: entering the DCM free resonance stage, the magnetizing inductance and parasitic capacitances (such as the switching transistor Coss, transformer parasitic capacitance, etc.) resonate; at times t3 to t4: the output voltage feedback determines the ZVS drive pulse turn-on time t3, at the rectifier switch Q SR During the turn-on period, the excitation current increases negatively, preparing for the ZVS turn-on of the primary side. At times t4 to t5: the primary side detects a negative excitation current, and the negative excitation current is less than the set threshold Ineg. After a certain delay, the primary switch Qp is turned on at time t5, thereby realizing the ZVS turn-on of the primary switch Qp on the primary side.

[0051] Therefore, in the embodiments of this application, by using the secondary control chip U2 set on the secondary side as the feedback master controller, the ZVS turn-on of the primary switch Qp on the primary side can be realized, thereby avoiding hard turn-on of the primary switch and greatly reducing switching losses.

[0052] Optionally, in some embodiments of this application, such as Figure 3 or Figure 5 As shown, the voltage feedback unit 200 includes a resistor voltage divider module 201. One end of the resistor voltage divider module 201 receives the output voltage of the converter through a first controllable switch. For example, it can be connected to the VCC pin of the secondary control chip U2 through a MOSFET Q1. The other end of the resistor voltage divider module 201 is grounded. The control unit 102 turns off the voltage feedback unit 200 by controlling the first controllable switch, such as the MOSFET Q1, to turn it off.

[0053] Specifically, such as Figure 3 or Figure 5 As shown, the resistor voltage divider module 201 includes a first resistor R1 and a second resistor R2 connected in series, and the first node between the first resistor R1 and the second resistor R2 serves as the feedback terminal of the voltage feedback unit 200. The resistance values ​​of the first resistor R1 and the second resistor R2 are respectively smaller than the resistance values ​​of the sampling resistors, such as resistors R3 and R4.

[0054] By setting a first controllable switch, such as MOSFET Q1, in the voltage feedback unit 200, the control unit 102 can output a sleep control signal (Sleep) to turn off MOSFET Q1 after the converter enters sleep mode, thereby disconnecting the first resistor R1 and the second resistor R2 from the circuit. Since the VCC voltage remains constant, the resistance values ​​of the first resistor R1 and the second resistor R2 are less than the resistance values ​​of the sampling resistors, such as R3 and R4. Therefore, when the converter is in standby mode, the standby power consumption generated by the first resistor R1 and the second resistor R2 is greater than the standby power consumption generated by the sampling resistors, such as R3 and R4. This application can significantly reduce the system standby power consumption by turning off the first resistor R1 and the second resistor R2, which have higher standby power consumption. Where the resistance values ​​of the sampling resistors, such as R3 and R4, are sufficiently large, their standby power consumption can be ignored.

[0055] Optionally, in some embodiments of this application, such as Figure 5 As shown, the secondary control chip U2 includes a feedback pin FB, which is connected to the feedback terminal of the voltage feedback unit 200 and to the feedback control terminal, i.e., the feedback pin FB, of the protocol chip U3. The control unit 102 receives a sleep signal based on the feedback pin FB so that the secondary control chip U2 can multiplex the feedback pin FB.

[0056] Since the converter in this embodiment uses the secondary control chip U2 as the feedback master controller, it is more convenient to reuse the feedback pin FB. Therefore, it can realize the transmission and reception of the sleep signal without adding chip pins, which greatly reduces the chip design cost.

[0057] Specifically, such as Figure 5 As shown, the protocol chip U3 is equipped with a first current source I1, a second current source I2, and a second controllable switch, such as a MOSFET Q2. The positive terminal of the first current source I1 is connected to the negative terminal of the second current source I2, and a second node is formed. This second node is connected to the feedback control terminal (pin FB) of the protocol chip U3. The negative terminal of the first current source I1 is connected to the ground terminal (GND) of the protocol chip U3, and the positive terminal of the second current source I2 is connected to the power supply terminal (VCC) of the protocol chip. The second controllable switch, such as the MOSFET Q2, is connected in parallel with the first current source I1. The protocol chip U3 controls the second controllable switch, such as the MOSFET Q2, to close, thereby sending a sleep signal to the feedback pin through the feedback control terminal.

[0058] For example, when the protocol chip U3 detects that no load is connected to the output interface, it controls the MOSFET Q2 to turn on, thereby pulling the feedback voltage of the feedback control terminal, i.e., the pin, low. In this way, the control unit 102 detects the low-level sleep signal through the feedback pin FB, pulls the sleep control signal Sleep high, controls the MOSFET Q1 to turn off, and shuts down the voltage feedback unit 200, which greatly reduces the system standby power consumption.

[0059] Furthermore, such as Figure 5 As shown, the protocol chip U3 can also control the second controllable switch MOSFET Q2 to disconnect, so as to send an exit sleep signal to the feedback pin through the feedback control terminal.

[0060] In this way, when the feedback pin FB receives the exit sleep signal, the converter is controlled to exit the sleep mode, and the first controllable switch, such as MOSFET Q1, is controlled to close, connecting resistors R1 and R2 in the voltage feedback unit 200 so as to control the converter according to the voltage feedback value of the voltage feedback unit 200.

[0061] In other words, when protocol chip U3 detects a load connected to the output interface, it turns off MOSFET Q2 and simultaneously raises the feedback voltage through current source I2. This allows control unit 102 to detect a high-level exit sleep signal through feedback pin FB, pulling the sleep control signal Sleep low, controlling MOSFET Q1 to close, and enabling voltage feedback unit 200. The feedback pin then enters normal sampling and feedback mode, as follows: Figure 4 and Figure 6 As shown.

[0062] Optionally, in some embodiments of this application, such as Figure 5 As shown, the control unit 102 includes a first comparator 1021, a second comparator 1022, and a first flip-flop RS1. The positive input terminal of the first comparator 1021 is connected to the output terminal of the voltage detection unit 101, and the negative input terminal of the first comparator 1021 is connected to the feedback pin FB. The positive input terminal of the second comparator 1022 is connected to the feedback pin FB, and the negative input terminal of the second comparator 1022 is adapted to connect to the wake-up reference voltage wake_ref. The output terminal of the second comparator 1022 is connected to the reset terminal of the first flip-flop RS1, the setting terminal of the first flip-flop RS1 is connected to the output terminal of the first comparator 1021, and the output terminal of the first flip-flop RS1 is connected to the control terminal of the first controllable switch, such as the gate of MOSFET Q1. The first flip-flop RS1 is configured to output a turn-off control signal when the first comparator 1021 receives a sleep signal, so as to control the first controllable switch, such as MOSFET Q1, to turn off.

[0063] Furthermore, the first flip-flop RS1 is also configured to output a closing control signal when the second comparator 1022 receives an exit sleep signal, so as to control the first controllable switch to close, for example, turn on the MOSFET Q1.

[0064] Specifically, such as Figure 5As shown, when protocol chip U3 detects that no load is connected to the output interface, it controls MOSFET Q2 to turn on, pulling the voltage of pin FB low. This causes the first comparator 1021 to flip and output a high level, thus triggering the first flip-flop RS1 to output a high-level sleep control signal (i.e., the Sleep voltage is high). The Sleep voltage drives the PMOS transistor Q1 to turn off, cutting off the normal feedback voltage divider resistors R1 and R2, significantly reducing system power consumption. When protocol chip U3 detects that a load is connected to the output interface, it turns off MOSFET Q2 and simultaneously raises the voltage of pin FB through current source I2. When the feedback voltage is greater than the wake-up reference voltage wake_ref, the first flip-flop RS1 outputs a low-level exit sleep control signal (i.e., the Sleep voltage becomes low), MOSFET Q1 turns on, the converter exits sleep mode, and the feedback pin FB enters normal sampling and feedback. By using the secondary-side control chip U2 as the feedback master, ZVS turn-on of the primary-side primary switch Qp can be achieved.

[0065] Optionally, in some embodiments of this application, such as Figure 3 , Figure 5 and Figure 7 As shown, the voltage detection unit 101 includes a third resistor R3 and a fourth resistor R4. One end of the third resistor R3 is used to receive the output voltage of the converter, for example, it can be connected to the VCC pin of the secondary control chip U2 to receive the output voltage of the converter. One end of the fourth resistor R4 is connected to the other end of the third resistor R3 and has a third node, which serves as the output terminal of the voltage detection unit 101. The other end of the fourth resistor R4 is grounded. The resistance values ​​of the third resistor R3 and the fourth resistor R4 are respectively greater than the resistance values ​​of the feedback resistors, such as R1 and R2.

[0066] In the embodiments of this application, when the converter enters sleep mode, the first resistor R1 and the second resistor R2, which have smaller resistances, are replaced by the third resistor R3 and the fourth resistor R4, which have larger resistances, for output voltage detection. This can significantly reduce the system's standby power consumption. Furthermore, since the resistances of the third resistor R3 and the fourth resistor R4 are sufficiently large, the power consumption they generate is negligible.

[0067] Furthermore, such as Figure 7 As shown, the control unit 102 also includes a third comparator 1023, a fourth comparator 1024, and a second flip-flop RS2.

[0068] The positive input of the third comparator 1023 is adapted to be connected to the first reference voltage Vo_ref1, and the negative input of the third comparator 1023 is connected to the third node. The positive input of the fourth comparator 1024 is connected to the third node, and the negative input of the fourth comparator 1024 is adapted to be connected to the second reference voltage Vo_ref2, wherein the second reference voltage Vo_ref2 is greater than the first reference voltage Vo_ref1. The setting terminal of the second flip-flop RS2 is connected to the output terminal of the third comparator 1023, and the reset terminal of the second flip-flop RS2 is connected to the output terminal of the fourth comparator 1024. The second flip-flop RS2 is configured to generate a bangbang control signal based on the comparison signal output by the third comparator 1023 and the comparison signal output by the fourth comparator 1024 to perform bangbang control on the output voltage.

[0069] Specifically, refer to Figure 7 and Figure 8As shown, in the low-power control circuit of this embodiment, when the voltage of pin FB is high, the secondary-side control chip U2 acts as the feedback master to control the converter normally, achieving ZVS turn-on of the primary-side primary switch Qp, and the converter is in a load state. When the protocol chip U3 detects that no load is connected to the output interface, it controls the MOS transistor Q2 to turn on, pulling the voltage of pin FB low. The control unit 102 controls the converter to enter sleep mode. The first comparator 1021 flips to output a high level, thereby triggering the first trigger RS1 to output a high-level sleep control signal, i.e., the sleep voltage is high. The sleep voltage drives the control PMOS transistor Q1 to turn off, cutting off the normal feedback voltage divider resistors R1 and R2, greatly reducing system power consumption, and ensuring the converter is in sleep mode. In Mode 1, the voltage detection value Vo_sense output by the voltage detection unit 101 is compared by the third comparator 1023 and the fourth comparator 1024. Specifically, the voltage detection value Vo_sense is compared with the first reference voltage Vo_ref1 and the second reference voltage Vo_ref2. This comparison enables the output voltage to be bang-controlled by the second flip-flop RS2 outputting a bang-bang control signal. For example, when the voltage detection value Vo_sense drops to the first reference voltage Vo_ref1, Vgsp becomes high, controlling the primary switch on the primary side to turn on, enabling energy coupling and transfer, and increasing the output voltage until the voltage detection value Vo_sense drops to the second reference voltage Vo_ref2. When the voltage reaches the second reference voltage Vo_ref2, Vgsp goes low, and the primary switch turns off, repeating this process. Meanwhile, when the protocol chip U3 detects a load connection at the output interface, it turns off the MOSFET Q2 and simultaneously raises the voltage of pin FB through current source I2. When the feedback voltage is greater than the wake-up reference voltage wake_ref, the first trigger RS1 outputs a low-level exit sleep control signal, i.e., the Sleep voltage goes low, the MOSFET Q1 turns on, the converter exits sleep mode, and the feedback pin FB also enters normal sampling and feedback. Through the secondary-side control chip U2 set on the secondary side as the feedback master, the ZVS turn-on of the primary switch Qp on the primary side can be achieved, and the converter enters the load state.

[0070] Therefore, in the embodiments of this application, by using the secondary-side control chip as the feedback master controller, it is more convenient to reuse the feedback pin to communicate with the protocol chip, realize the entry and exit control of the converter standby sleep mode, and when the converter is in standby sleep mode, other functions can be turned off, only the low-power output bangbang control logic is retained. At the same time, the voltage feedback unit is replaced by a voltage detection unit with lower standby power consumption, thereby achieving ultra-low standby power consumption of the system and meeting the requirement of zero standby power consumption.

[0071] According to the low-power control circuit of the converter provided in the embodiments of this application, the converter is controlled to enter sleep mode by communicating between the secondary control chip and the protocol chip to receive the sleep signal sent by the protocol chip. In this way, the secondary control chip on the secondary side can be used as the master controller for standby low-power control without having to feed back the output of the secondary side to the primary side through an optocoupler. Furthermore, when the converter enters sleep mode, the voltage feedback unit with high standby power consumption in the secondary control chip can be turned off, and the output voltage detected by the voltage detection unit with low standby power consumption can be used for bang-bang control, which greatly reduces standby power consumption and can meet the requirement of zero standby power consumption, thus saving energy and protecting the environment.

[0072] Optionally, in some embodiments of this application, such as Figure 3 As shown, the secondary control chip U2 includes the low-power control circuit 100 described in the above embodiment.

[0073] In other words, the low-power control circuit 100 described in the above embodiments can be integrated and packaged in the secondary control chip U2.

[0074] According to the secondary-side control chip U2 provided in the embodiments of this application, based on the aforementioned low-power control circuit 100, when communicating with the protocol chip U3 to receive the sleep signal sent by the protocol chip U3, the converter is controlled to enter sleep mode, thereby enabling it to act as the master controller to perform standby low-power control on the converter. This eliminates the need for optocouplers to feed back the secondary-side output to the primary-side. Furthermore, when the converter enters sleep mode, the voltage feedback unit 200 with high standby power consumption in the chip can be turned off, and Bangbang control can be performed based on the output voltage detected by the voltage detection unit 101 with low standby power consumption, greatly reducing standby power consumption and meeting the requirement of zero standby power consumption, thus saving energy and protecting the environment.

[0075] like Figure 9 As shown, in some embodiments of this application, a converter 10 is also provided, which includes the low-power control circuit 100 described in the above embodiments.

[0076] And, as Figure 10 As shown, in some other embodiments of this application, a converter 10 is also provided, which includes the secondary-side control chip U2 described in the above embodiments.

[0077] According to the converter provided in the embodiments of this application, communication is established between the secondary control chip and the protocol chip to receive the sleep signal sent by the protocol chip, thereby realizing the control of entering the sleep mode. This enables the secondary control chip on the secondary side to act as the master controller for low-power standby control, eliminating the need to feed back the output of the secondary side to the primary side through an optocoupler. Furthermore, when entering the sleep mode, the voltage feedback unit with high standby power consumption in the secondary control chip can be turned off, and Bangbang control is performed based on the output voltage detected by the voltage detection unit with low standby power consumption, which greatly reduces standby power consumption and meets the requirement of zero standby power consumption, thus saving energy and protecting the environment.

[0078] In addition, such as Figure 11 As shown in the figure, this application embodiment also provides a low-power control method for a converter, wherein the converter includes a secondary-side control chip and a protocol chip disposed on the secondary side, and the secondary-side control chip and the protocol chip communicate to receive a sleep signal sent by the protocol chip. The low-power control method includes the following steps:

[0079] S1, by configuring a voltage detection unit in the secondary control chip, the output voltage of the converter is detected to obtain a voltage detection value, wherein the resistance value of the sampling resistor in the voltage detection unit is greater than the resistance value of the feedback resistor in the voltage feedback unit of the secondary control chip.

[0080] S2, when the secondary-side control chip receives a sleep signal, controls the converter to enter sleep mode and controls the voltage feedback unit to turn off, and performs bang-bang control on the converter based on the voltage detection value when the converter is in sleep mode.

[0081] In this design, since the sampling resistors (e.g., R3 and R4) in the voltage detection unit are larger than the feedback resistors (e.g., R1 and R2) in the voltage feedback unit, the voltage feedback unit is turned off after the converter enters sleep mode. The voltage detection unit then replaces the voltage feedback unit in detecting the converter's output voltage, significantly reducing system standby power consumption. Furthermore, the secondary-side control chip U2, located on the secondary side, receives the sleep signal sent by the protocol chip U3 for standby control, eliminating the need to isolate and feed back the converter's output to the primary side, reducing signal isolation transmission and further lowering standby power consumption.

[0082] Optionally, in some embodiments of this application, the secondary-side control chip includes a feedback pin, which is connected to the feedback terminal of the voltage feedback unit and the feedback control terminal of the protocol chip. The secondary-side control chip receives a sleep signal based on the feedback pin to multiplex the feedback pin.

[0083] Since the converter in this embodiment uses the secondary control chip U2 as the feedback master controller, it is more convenient to reuse the feedback pin FB. Therefore, it can realize the transmission and reception of the sleep signal without adding chip pins, which greatly reduces the chip design cost.

[0084] Optionally, in some embodiments of this application, such as Figure 5 As shown, the protocol chip U3 is equipped with a first current source I1, a second current source I2, and a second controllable switch, such as a MOSFET Q2. The positive terminal of the first current source I1 is connected to the negative terminal of the second current source I2, and it has a second node. The second node is connected to the feedback control terminal, i.e., pin FB, of the protocol chip U3. The negative terminal of the first current source I1 is connected to the ground terminal GND of the protocol chip U3. The positive terminal of the second current source I2 is connected to the power supply terminal VCC of the protocol chip. The second controllable switch, such as the MOSFET Q2, is connected in parallel with the first current source I1. The low-power method described above further includes: when the protocol chip controls the second controllable switch to be closed, receiving a sleep signal sent by the feedback control terminal based on the feedback pin; when the protocol chip controls the second controllable switch to be closed, receiving an exit sleep signal sent by the feedback control terminal based on the feedback pin.

[0085] For example, when the protocol chip U3 detects that no load is connected to the output interface, it controls the MOSFET Q2 to turn on, thereby pulling the feedback voltage of the feedback control terminal, i.e., the pin, low. In this way, the low-level sleep signal is detected through the feedback pin FB, and the sleep control signal Sleep is pulled high, controlling the MOSFET Q1 to turn off, thus shutting down the voltage feedback unit and greatly reducing the system standby power consumption.

[0086] Optionally, in some embodiments of this application, when the feedback pin receives an exit sleep signal, the above-described low-power method further includes: controlling the converter to exit sleep mode and controlling the voltage feedback unit to operate so as to control the converter according to the voltage feedback value of the voltage feedback unit.

[0087] In other words, when protocol chip U3 detects a load connected to the output interface, it turns off MOSFET Q2 and simultaneously raises the feedback voltage through current source I2. This triggers a high-level exit sleep signal detected by feedback pin FB, pulling the sleep control signal Sleep low, controlling MOSFET Q1 to close, and enabling voltage feedback unit 200. The feedback pin then enters normal sampling and feedback mode, as follows: Figure 4 and Figure 6 As shown.

[0088] In conclusion, as follows: Figure 5As shown, when protocol chip U3 detects that no load is connected to the output interface, it controls MOSFET Q2 to turn on, pulling the voltage of pin FB low. This causes the first comparator 1021 to flip and output a high level, thus triggering the first flip-flop RS1 to output a high-level sleep control signal (i.e., the Sleep voltage is high). The Sleep voltage drives the PMOS transistor Q1 to turn off, cutting off the normal feedback voltage divider resistors R1 and R2, significantly reducing system power consumption. When protocol chip U3 detects that a load is connected to the output interface, it turns off MOSFET Q2 and simultaneously raises the voltage of pin FB through current source I2. When the feedback voltage is greater than the wake-up reference voltage wake_ref, the first flip-flop RS1 outputs a low-level exit sleep control signal (i.e., the Sleep voltage becomes low), MOSFET Q1 turns on, the converter exits sleep mode, and the feedback pin FB enters normal sampling and feedback. By using the secondary-side control chip U2 as the feedback master, ZVS turn-on of the primary-side primary switch Qp can be achieved.

[0089] Optionally, in some embodiments of this application, bangbang control of the converter based on the voltage detection value includes: determining a first reference voltage and a second reference voltage, wherein the second reference voltage is greater than the first reference voltage; comparing the voltage detection value with the first reference voltage and the second reference voltage respectively, and generating a bangbang control signal to perform bangbang control on the converter.

[0090] Specific combination Figure 7 and Figure 8As shown, when the voltage at pin FB is high, the secondary-side control chip U2 acts as the feedback master controller to control the converter normally, achieving ZVS turn-on of the primary-side primary switch Qp, and the converter is in a load state. When the protocol chip U3 detects that no load is connected to the output interface, it controls the MOSFET Q2 to turn on, pulling the voltage at pin FB low, and controlling the converter to enter sleep mode. The first comparator 1021 flips to a high output, causing the first trigger RS1 to output a high-level sleep control signal, i.e., the sleep voltage is high. The sleep voltage drives the PMOS transistor Q1 to turn off, cutting off the normal feedback voltage divider resistors R1 and R2, greatly reducing system power consumption. Furthermore, the converter is in sleep mode. In Mode 1, the voltage detection value Vo_sense output by the voltage detection unit 101 is compared by the third comparator 1023 and the fourth comparator 1024. Specifically, the voltage detection value Vo_sense is compared with the first reference voltage Vo_ref1 and the second reference voltage Vo_ref2. This comparison enables the output voltage to be bang-controlled by the second flip-flop RS2 outputting a bang-bang control signal. For example, when the voltage detection value Vo_sense drops to the first reference voltage Vo_ref1, Vgsp becomes high, controlling the primary switch on the primary side to turn on, enabling energy coupling and transfer, and increasing the output voltage until the voltage detection value Vo_sense drops to the second reference voltage Vo_ref2. When the voltage reaches the second reference voltage Vo_ref2, Vgsp goes low, and the primary switch turns off, repeating this process. Meanwhile, when the protocol chip U3 detects a load connection at the output interface, it turns off the MOSFET Q2 and simultaneously raises the voltage of pin FB through current source I2. When the feedback voltage is greater than the wake-up reference voltage wake_ref, the first trigger RS1 outputs a low-level exit sleep control signal, i.e., the Sleep voltage goes low, the MOSFET Q1 turns on, the converter exits sleep mode, and the feedback pin FB also enters normal sampling and feedback. Through the secondary-side control chip U2 set on the secondary side as the feedback master, the ZVS turn-on of the primary switch Qp on the primary side can be achieved, and the converter enters the load state.

[0091] According to the low-power control method for converters provided in this application, communication between the secondary-side control chip and the protocol chip is established to receive the sleep signal sent by the protocol chip, thereby enabling control to enter the sleep mode. This allows the secondary-side control chip to act as the master controller for low-power standby control, eliminating the need to feed back the secondary-side output to the primary side via an optocoupler. Furthermore, by configuring a voltage detection unit with lower standby power consumption in the secondary-side control chip to replace the voltage feedback unit with higher standby power consumption, the voltage feedback unit with higher standby power consumption in the secondary-side control chip can be shut down when the converter enters sleep mode. Bangbang control is then performed based on the output voltage detected by the voltage detection unit with lower standby power consumption, significantly reducing standby power consumption and meeting the requirement of zero standby power consumption, thus saving energy and protecting the environment.

[0092] In the description of this specification, the terms "one embodiment," "some embodiments," "embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0093] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make modifications, alterations, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A low-power control circuit for a converter, characterized in that, The converter includes a secondary-side control chip and a protocol chip disposed on the secondary side. The secondary-side control chip communicates with the protocol chip to receive a sleep signal sent by the protocol chip. The low-power control circuit includes: A voltage detection unit is configured to detect the output voltage of the converter to obtain a voltage detection value, and the resistance value of the sampling resistor in the voltage detection unit is greater than the resistance value of the feedback resistor in the voltage feedback unit of the secondary control chip. The control unit is configured to, when the secondary-side control chip receives the sleep signal, control the converter to enter sleep mode and control the voltage feedback unit to turn off, and, when the converter is in the sleep mode, perform bang-bang control on the converter based on the voltage detection value.

2. The low-power control circuit according to claim 1, characterized in that, The voltage feedback unit includes a resistor voltage divider module. One end of the resistor voltage divider module receives the output voltage of the converter through a first controllable switch, and the other end of the resistor voltage divider module is grounded. The control unit shuts down the voltage feedback unit by controlling the first controllable switch to disconnect.

3. The low-power control circuit according to claim 2, characterized in that, The resistor voltage divider module includes a first resistor and a second resistor connected in series, and a first node between the first resistor and the second resistor serves as the feedback terminal of the voltage feedback unit, wherein the resistance values ​​of the first resistor and the second resistor are respectively less than the resistance value of the sampling resistor.

4. The low-power control circuit according to claim 3, characterized in that, The secondary-side control chip includes a feedback pin, which is connected to the feedback terminal of the voltage feedback unit and the feedback control terminal of the protocol chip. The control unit receives the sleep signal based on the feedback pin so that the secondary-side control chip can multiplex the feedback pin.

5. The low-power control circuit according to claim 4, characterized in that, The protocol chip is equipped with a first current source, a second current source, and a second controllable switch. The positive terminal of the first current source is connected to the negative terminal of the second current source, and a second node is provided. The second node is connected to the feedback control terminal of the protocol chip. The negative terminal of the first current source is connected to the ground terminal of the protocol chip. The positive terminal of the second current source is connected to the power supply terminal of the protocol chip. The second controllable switch is connected in parallel with the first current source. The protocol chip controls the second controllable switch to close, so as to send the sleep signal to the feedback pin through the feedback control terminal; The protocol chip controls the second controllable switch to disconnect, thereby sending an exit sleep signal to the feedback pin through the feedback control terminal.

6. The low-power control circuit according to claim 5, characterized in that, The control unit includes: A first comparator, the positive input terminal of which is connected to the output terminal of the voltage detection unit, and the negative input terminal of which is connected to the feedback pin; The first trigger is configured to output a shutdown control signal when the first comparator receives the sleep signal, thereby controlling the first controllable switch to shut down.

7. The low-power control circuit according to claim 6, characterized in that, The control unit is further configured to, upon receiving an exit sleep signal at the feedback pin, control the converter to exit the sleep mode and control the first controllable switch to close, so as to control the converter according to the voltage feedback value of the voltage feedback unit.

8. The low-power control circuit according to claim 7, characterized in that, The control unit further includes: The second comparator has its positive input connected to the feedback pin, its negative input adapted to receive a wake-up reference voltage, and its output connected to the reset terminal of the first flip-flop. The first flip-flop is further configured to output a closing control signal when the second comparator receives the exit sleep signal, so as to control the first controllable switch to close.

9. The low-power control circuit according to any one of claims 1-8, characterized in that, The voltage detection unit includes: A third resistor, one end of which is used to receive the output voltage of the converter; A fourth resistor, one end of which is connected to the other end of the third resistor and has a third node, serves as the output terminal of the voltage detection unit. The other end of the fourth resistor is grounded. The resistance values ​​of the third resistor and the fourth resistor are respectively greater than the resistance value of the feedback resistor.

10. The low-power control circuit according to claim 9, characterized in that, The control unit further includes: A third comparator, the positive input of which is adapted to be connected to a first reference voltage, and the negative input of which is connected to the third node; A fourth comparator, the positive input of which is connected to the third node, and the negative input of which is adapted to be connected to a second reference voltage, wherein the second reference voltage is greater than the first reference voltage; The second flip-flop has its setting terminal connected to the output terminal of the third comparator and its reset terminal connected to the output terminal of the fourth comparator. The second flip-flop is configured to generate a bangbang control signal based on the comparison signal output by the third comparator and the comparison signal output by the fourth comparator.

11. The low-power control circuit according to claim 1, characterized in that, The secondary control chip and the protocol chip establish communication through a sleep enable pin to receive the sleep signal sent by the protocol chip.

12. A secondary-side control chip, characterized in that, Includes the low-power control circuit according to any one of claims 1-11.

13. A converter, characterized in that, include: The low-power control circuit according to any one of claims 1-11; or The secondary control chip according to claim 12.

14. A low-power control method for a converter, characterized in that, The converter includes a secondary-side control chip and a protocol chip disposed on the secondary side. The secondary-side control chip communicates with the protocol chip to receive a sleep signal sent by the protocol chip. The low-power control method includes: By configuring a voltage detection unit in the secondary-side control chip, the output voltage of the converter is detected to obtain a voltage detection value, wherein the resistance value of the sampling resistor in the voltage detection unit is greater than the resistance value of the feedback resistor in the voltage feedback unit of the secondary-side control chip. When the secondary-side control chip receives the sleep signal, it controls the converter to enter sleep mode and controls the voltage feedback unit to turn off. When the converter is in sleep mode, it performs bang-bang control on the converter based on the voltage detection value.

15. The low-power control method according to claim 14, characterized in that, The secondary-side control chip includes a feedback pin, which is connected to the feedback terminal of the voltage feedback unit and the feedback control terminal of the protocol chip. The secondary-side control chip receives the sleep signal based on the feedback pin to multiplex the feedback pin.

16. The low-power control method according to claim 15, characterized in that, The protocol chip is equipped with a first current source, a second current source, and a second controllable switch. The positive terminal of the first current source is connected to the negative terminal of the second current source, and a second node is provided. The second node is connected to the feedback control terminal of the protocol chip. The negative terminal of the first current source is connected to the ground terminal of the protocol chip, and the positive terminal of the second current source is connected to the power supply terminal of the protocol chip. The second controllable switch is connected in parallel with the first current source. The method further includes: When the protocol chip controls the second controllable switch to close, a sleep signal sent by the feedback control terminal is received based on the feedback pin; When the protocol chip controls the second controllable switch to turn off, the exit sleep signal sent by the feedback control terminal is received based on the feedback pin.

17. The low-power control method according to claim 16, characterized in that, If the feedback pin receives the exit sleep signal, the method further includes: The converter is controlled to exit the sleep mode, and the voltage feedback unit is controlled to operate so as to control the converter according to the voltage feedback value of the voltage feedback unit.

18. The low-power control method according to any one of claims 14-17, characterized in that, Bangbang control of the converter based on the voltage detection value includes: A first reference voltage and a second reference voltage are determined, wherein the second reference voltage is greater than the first reference voltage; The voltage detection value is compared with the first reference voltage and the second reference voltage respectively to generate a bangbang control signal for bangbang control of the converter.

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