Power converter, control method thereof and switching power supply

Abstract

This application discloses a power converter, its control method, and a switching power supply. The power converter includes an upper transistor, a lower transistor, and an inductor, with the common node of the upper and lower transistors being a switching node. The power converter further includes: a pull-down branch connected between the switching node and ground; a negative current detection unit that outputs a valid enable signal when a negative current on the inductor reaches a set less-than-zero current threshold during the lower transistor's conduction period; and a pull-down control unit that, upon receiving the valid enable signal, controls the pull-down branch to conduct for a short period during the dead time between the lower transistor's turn-off and the upper transistor's turn-on, thereby reducing voltage spikes at the switching node. By conducting the pull-down branch for a period during the dead time, negative current is discharged to ground, reducing voltage spikes at the switching node, preventing damage to the lower transistor, and maintaining high efficiency and transient response speed of the power converter.

Description

Technical Field

[0001] This application relates to the field of switching power supply technology, specifically to a power converter and its control method and a switching power supply. Background Technology

[0002] With the rapid development of electronic systems, people have increasingly higher demands for high power density and high efficiency switching power supply converters, hoping to enhance transient response speed while maintaining the high efficiency of switching power supplies.

[0003] Taking a buck switching power supply as an example, during normal operation, the upper and lower transistors conduct alternately. The current flowing from the input terminal through the upper transistor and inductor to the output terminal is in the positive direction. During the period when the upper transistor is off and the lower transistor is on, if the load suddenly changes from heavy load to light load or other operating conditions occur, the current direction in the lower transistor may change, resulting in a negative current. As the conduction time of the lower transistor increases, the negative current becomes larger. When the lower transistor is turned off, the inductor current direction cannot change abruptly, causing the node voltage at the switching point between the upper and lower transistors to spike, requiring freewheeling through the body diode of the upper transistor. During the freewheeling period of the negative current through the upper transistor, the node voltage at the switching point oscillates very high due to the presence of parasitic inductance. Therefore, when the negative current is large or the parasitic inductance is large, the high node voltage may cause avalanche breakdown of the lower transistor.

[0004] To prevent the lower transistor from breaking down, existing technologies typically increase its withstand voltage. However, this increases the device's on-resistance, affecting the efficiency of the switching power supply. Conversely, prematurely turning off the lower transistor degrades the power supply's transient response. Currently, finding an efficient solution remains difficult. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a power converter, its control method, and a switching power supply.

[0006] According to one aspect of the present invention, a power converter is provided, comprising an upper transistor and a lower transistor connected in series, and an inductor connected to a common node of the upper transistor and the lower transistor, wherein the common node of the upper transistor and the lower transistor is a switching node. The power converter further comprises: a pull-down branch connected between the switching node and a ground terminal; a negative current detection unit that outputs a valid enable signal when a negative current on the inductor reaches a set current threshold during the conduction period of the lower transistor; and a pull-down control unit that, upon receiving the valid enable signal, controls the pull-down branch to conduct for a first time during the dead time from the start of the lower transistor's turn-off to the start of the upper transistor's turn-on, thereby reducing voltage spikes at the switching node.

[0007] Optionally, when the lower tube begins to turn off, the pull-down control unit controls the pull-down branch to turn off for a second time and then turn it back on for a first time, wherein the second time is greater than or equal to zero, and the sum of the first time and the second time is less than or equal to the dead time.

[0008] Optionally, the pull-down control unit controls the pull-down branch to either be synchronously turned on or remain off during the conduction of the lower tube.

[0009] Optionally, if the pull-down control unit does not receive the valid enable signal during the pull-down tube's conduction period, it controls the pull-down branch to remain off during the pull-down tube's off period.

[0010] Optionally, the pull-down branch includes a series-connected switching unit and a current-limiting resistor, the switching unit including at least one switch in parallel, the switch including a field-effect transistor and a junction transistor.

[0011] Optionally, the pull-down branch includes a series-connected switching unit and a CMOS transistor, the CMOS transistor operating in the linear region throughout the switching cycle and equivalent to a current-limiting resistor, the switching unit including at least one parallel-connected switch, the switch including a lateral double-diffused transistor.

[0012] Optionally, during the active period of the enable signal, the pull-down control unit determines the turn-off time of the lower transistor based on the drive signal of the lower transistor, and generates the active edge of the pull-down control signal based on the inactive edge of the drive signal of the lower transistor, thereby determining the conduction time of the pull-down branch. Specifically, the lower transistor is turned off when the inactive edge of the drive signal arrives, and the pull-down branch is turned on when the active edge of the pull-down control signal arrives. Preferably, a falling edge is used as the inactive edge, and a rising edge is used as the active edge.

[0013] Optionally, the pull-down control unit includes: a timing unit that starts timing at the turn-off moment of the pull-down transistor, generates a signal edge of a timing signal after timing for a second time, wherein the second time is greater than or equal to zero; a pulse generator that generates a pulse signal with a pulse width of a first time according to the signal edge of the timing signal; and a logic gate circuit that converts the pulse signal into a valid pull-down control signal during the effective period of the enable signal to control the pull-down branch to be turned on.

[0014] Optionally, the timing unit receives the drive signal of the lower transistor, delays the invalid edge of the drive signal of the lower transistor by a second time, and outputs it as the signal edge of the timing signal. The logic gate circuit receives the drive signal of the lower transistor and the pulse signal and performs logic processing to provide the pull-down control signal, so that the pull-down control signal is valid within the first time period and invalid outside the first time period of the dead time.

[0015] Optionally, the negative current detection unit includes: a comparator, whose non-inverting input and inverting input respectively receive a set characterization threshold and an inductor current characterization signal, and whose output provides a comparison signal; and a latch, whose input is connected to the output of the comparator, whose clock input receives the drive signal of the lower transistor, and whose output provides the enable signal. During the conduction period of the lower transistor, the latch causes the level of the enable signal to follow the level of the comparison signal. During the turn-off period of the lower transistor, the latch causes the level of the enable signal to be locked to the level of the comparison signal at the instant the lower transistor turns off. When the inductor current characterization signal begins to be less than the characterization threshold, it indicates that the negative current on the inductor has reached the current threshold.

[0016] According to another aspect of the present invention, a switching power supply is provided, comprising: a multi-phase power converter as described above, wherein the input terminals and output terminals of the multi-phase power converter are respectively connected, wherein the pull-down branch in each phase of the power converter is controlled to be turned on by the pull-down control unit of the respective phase.

[0017] According to another aspect of the present invention, a control method for a power converter is provided. The power converter includes an upper transistor and a lower transistor connected in series, an inductor connected to a common node of the upper transistor and the lower transistor, and a pull-down branch connected between the common node and a ground terminal. The common node of the upper transistor and the lower transistor is a switching node. The control method includes: generating an effective enable signal when a negative current on the inductor is detected to reach a set current threshold during the conduction period of the lower transistor; and, upon receiving the effective enable signal, controlling the pull-down branch to conduct for a first time during the dead time from the start of the lower transistor's turn-off to the start of the upper transistor's turn-on, so as to reduce the voltage spike of the switching node.

[0018] Optionally, when the lower tube begins to turn off, the lower branch is controlled to turn off for a second time and then turn on for a first time, wherein the second time is greater than or equal to zero, and the sum of the first time and the second time is less than or equal to the dead time.

[0019] Optionally, during the active period of the enable signal, the turn-off time of the lower transistor is determined based on the drive signal of the lower transistor, and the active edge of the pull-down control signal is generated based on the inactive edge of the drive signal of the lower transistor, thereby determining the active time of the pull-down branch.

[0020] The embodiments of the present invention have at least the following beneficial effects:

[0021] The power converter, control method, and switching power supply provided by this invention incorporate a pull-down branch between the switching node and the ground terminal. A negative current detection unit detects negative current in the circuit and provides an effective enable signal when the negative current reaches a current threshold. After generating the effective enable signal, during the dead time between the lower transistor's turn-off and the upper transistor's turn-on, the pull-down branch is controlled to conduct for a first time, allowing negative current to flow from the switching node to the ground terminal. This reduces voltage spikes and voltage oscillation amplitude at the switching node, preventing damage to the lower transistor. Adjusting the duration of this first time allows for regulation of the voltage spike's descent rate, precisely controlling the node voltage change rate to adjust the power converter's efficiency. Furthermore, the pull-down branch eliminates the need for premature turn-off of the lower transistor, ensuring a high transient response speed. In short, it maintains high efficiency while ensuring a fast transient response speed and reducing the voltage across the lower transistor, resulting in a simple and low-cost control scheme.

[0022] Furthermore, when the lower transistor begins to turn off, the pull-down branch is turned off for a second time before being turned on again for the first time, and the second time is set to be greater than or equal to zero. This allows for flexible adjustment of the turn-off time of the pull-down branch and precise control of the timing of the node voltage pull-down. In addition, the pull-down control unit controls the pull-down branch to either follow the conduction state of the lower transistor or remain off before the lower transistor turns off, allowing for switching between different efficiency requirements and improving the versatility of the power converter.

[0023] It should be noted that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the present invention. Attached Figure Description

[0024] Figure 1 A schematic circuit block diagram of a power converter according to an embodiment of the present invention is shown;

[0025] Figure 2 A schematic operating waveform diagram of a power converter according to an embodiment of the present invention is shown;

[0026] Figure 3 A schematic circuit diagram of the control circuit of a power converter according to an embodiment of the present invention is shown;

[0027] Figure 4 A schematic waveform diagram of each signal of the control circuit of the power converter according to an embodiment of the present invention is shown during operation;

[0028] Figure 5 A schematic flowchart of a control method for a power converter according to an embodiment of the present invention is shown. Detailed Implementation

[0029] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0030] Figure 1 A schematic circuit block diagram of a power converter according to an embodiment of the present invention is shown.

[0031] like Figure 1 As shown, the power converter 10 in this embodiment includes an upper transistor Q1, a lower transistor Q2, an inductor L, an output capacitor Cout, a pull-down branch 20, and a control circuit 100. Taking a buck topology as an example, the upper transistor Q1 and the lower transistor Q2 are connected in series between the input terminal and the ground terminal, receiving the input voltage Vin from the input terminal. The common node of the upper transistor Q1 and the lower transistor Q2 is the switching node SW. One end of the inductor L is coupled to the switching node SW, and the other end is coupled to the output terminal to provide the output voltage Vout. The output capacitor Cout is connected between the output terminal and the ground terminal to filter the output voltage Vout. The output terminal is also connected to the subsequent load to supply power to the load. The pull-down branch 20 is connected between the switching node SW and the ground terminal and includes a series-connected switching unit 21 and a current-limiting resistor R. The controlled terminal of the switching unit 21 is controlled by the pull-down control signal Vdr output by the control circuit 100 to conduct when needed, introducing negative current into the ground terminal, thereby reducing the voltage spike of the node voltage Vsw of the switching node SW.

[0032] The control circuit 100 includes an upper transistor drive unit 140, a lower transistor drive unit 130, a negative current detection unit 110, and a pull-down control unit 120. The upper transistor drive unit 140 is connected to the gate of the upper transistor Q1 and generates a drive signal Vg1 based on the error amplification signal Vcom to drive the upper transistor Q1. The lower transistor drive unit 130 is connected to the gate of the lower transistor Q2 and generates a drive signal Vg2 based on the error amplification signal Vcom to drive the lower transistor Q2. The pull-down control unit 120 generates a pull-down control signal Vdr to control the conduction and cutoff of the pull-down branch 20. The negative current detection unit 110 detects the direction and magnitude of the current flowing through the lower transistor Q2 through the inductor current characterization signal Vsen. When the inductor current characterization signal Vsen reaches the set characterization threshold Vncp during the conduction of the lower transistor Q2, it outputs a valid enable signal EN to indicate that the negative current on the inductor L has reached the set current threshold Incp, where the current threshold Incp is less than zero. The negative current on inductor L reaches the set current threshold Incp, meaning the negative current gradually decreases to less than or equal to the current threshold Incp, that is, the absolute value of the negative current increases to greater than or equal to the absolute value of the current threshold Incp.

[0033] The drive signal Vg2 generated by the lower transistor drive unit 130 is, for example, a PWM signal with a certain duty cycle. The pull-down control unit 120 is connected to both the lower transistor drive unit 130 and the negative current detection unit 110. After receiving a valid enable signal EN, the pull-down control unit 120 controls the pull-down branch 20 to conduct for a first time tp within the dead time according to the lower transistor drive signal Vg2, so as to discharge part of the negative current to ground, thereby reducing the voltage spike of the node voltage Vsw, and making the first time tp greater than zero. The dead time is the time between the lower transistor Q2 turning off in the current cycle and the upper transistor Q1 turning on in the next cycle.

[0034] Figure 2 A schematic operating waveform diagram of a power converter according to an embodiment of the present invention is shown.

[0035] Combination Figure 1 and Figure 2 During normal operation, the drive signal Vg1 of the upper transistor and the drive signal Vg2 of the lower transistor alternate, meaning that the upper transistor Q1 and the lower transistor Q2 alternately turn on and off, with a certain dead time between their on-times. During the conduction period of the upper transistor Q1, a current path is formed from the input terminal through the upper transistor Q1 and the inductor L to the output terminal, charging the inductor L and supplying power to the load. At this time, the inductor current IL rises, and its direction is taken as the positive direction. Figure 1 The direction is indicated by the middle arrow. During the conduction of the lower transistor Q2, Q2 freewheels, and the inductor current IL remains positive, meaning the current in the inductor is still positive. However, under conditions where the load suddenly changes from heavy to light or other special operating conditions, the current in inductor L may decrease from positive to zero and then become negative during the conduction of Q2. Furthermore, as the conduction time of Q2 increases, the absolute value of the negative current gradually increases. Therefore, when Q2 is turned off, because the current in inductor L cannot change abruptly, the body diode of the upper transistor Q1 freewheels, and the node voltage Vsw begins to oscillate and rise.

[0036] In this embodiment, the negative current in the circuit during the conduction of the lower transistor Q2 is detected by the negative current detection unit 110. The negative current detection unit 110 receives the inductor current characterization signal Vsen. When the inductor current characterization signal Vsen is less than or equal to a set characterization threshold Vncp, it outputs a valid enable signal EN to characterize that the negative current on the inductor is less than or equal to the current threshold Incp. Figure 2At time t0, for example, if the absolute value of the inductor current IL (which is a negative current at this time) increases to the absolute value of the current threshold Incp, that is, when the negative current flowing through the lower transistor Q2 reaches the current threshold Incp, a valid enable signal EN is output. The valid enable signal EN is, for example, a high level. The pull-down control unit 120 receives this valid enable signal EN. At time t1, the drive signal Vg2 of the lower transistor flips to a low level, and the lower transistor Q2 is turned off. Then, at time t2 after the lower transistor Q2 is turned off, the pull-down control unit 120 starts to control the pull-down branch 20 to conduct, and controls the pull-down branch 20 to turn off at time t3. The conduction time of the pull-down branch 20 is the first time, that is, the time period t2-t3 is the first time tp. Afterwards, at time t4, the upper transistor Q1 is turned on again. That is, during the dead time from when the lower transistor Q2 starts to turn off (at time t1) to when the upper transistor Q1 turns on again (at time t4), the pull-down branch 20 is controlled to conduct for a first time tp, so that during this first time tp, some negative current flows into the ground terminal through the pull-down branch 20, thereby reducing the voltage spike of the node voltage Vsw. From Figure 2 As can be seen, during the time period t1-t4, the oscillation amplitude of the node voltage Vsw is smaller than in the previous switching cycles, and the voltage spike is lower. This reduces the voltage spike of the node voltage Vsw through the pull-down branch 20, alleviating the pressure on the lower transistor Q2 and reducing the risk of breakdown of Q2. Figure 2 To clearly show the first-time teleport (TP), the dead time is drawn as large. In reality, the dead time is very short, and the first-time TP is only a few nanoseconds to tens of nanoseconds.

[0037] Furthermore, when the negative current on the inductor reaches the current threshold Incp, when the lower transistor Q2 begins to turn off, the pull-down branch 20 can be controlled to turn off first, reaching the second time td, and then turning on the first time tp. Figure 2 The time interval t1-t2 is designated as the second time interval td, during which pull-down branch 20 is turned off. After time t2, it is turned on again for the first time interval tp. This second time interval td can be set to be greater than or equal to zero, and the sum of the first time interval tp and the second time interval td should be less than or equal to the dead time (the time interval t1-t4). That is, pull-down branch 20 can be turned on at the moment the lower transistor Q2 is turned off, or after the second time interval td following the turn-off of the lower transistor Q2, and the turn-off time of pull-down branch 20 should be before or at the same time as the turn-on time of the upper transistor Q1. Since the node voltage Vsw will not oscillate to its highest point at the instant the lower transistor Q2 is turned off, an adjustable second time interval td can be set to select the pull-down timing of the node voltage Vsw, rapidly lowering it before it oscillates to its highest point to ensure system efficiency. In addition, the pull-down control unit 120 controls the pull-down branch 20 to be synchronously turned on or kept off during the conduction of the pull-down tube Q2. Figure 2In the same switching cycle, the pull-down control signal Vdr follows the waveform of the drive signal Vg2 of the lower transistor before time t1, and the pull-down branch 20 and the lower transistor Q2 have the same conduction state. Alternatively, pull-down branch 20 can be controlled to remain off during the conduction of lower transistor Q2. Therefore, when the second time td is zero, and pull-down branch 20 remains on during the conduction of lower transistor Q2, after lower transistor Q2 is turned off, pull-down branch 20 can continue to be on for the first time tp.

[0038] Furthermore, the negative current detection unit 110 is configured to latch the level of the enable signal EN at the turn-off moment of the lower transistor Q2. Thus, when a negative current reaching the current threshold is detected during the conduction period of the lower transistor Q2, a valid enable signal EN is generated, and this level is latched when the lower transistor Q2 is turned off, maintaining the enable signal EN at a high level throughout the entire turn-off period of the lower transistor Q2 (time period t0-t5). This prevents level transitions from affecting circuit operation and ensures that voltage spikes in the node voltage Vsw are smoothly reduced.

[0039] Figure 3 A schematic circuit diagram of the control circuit of a power converter according to an embodiment of the present invention is shown.

[0040] like Figure 3 As shown, in this embodiment, the pull-down branch 20 includes a series-connected switching unit 21 and a current-limiting resistor R. The switching unit 21 includes at least one switch connected in parallel, which may include a field-effect transistor, a junction transistor, or a general-purpose switch. Taking a MOS transistor Q3 as an example, the transistor Q3 is connected in series with the current-limiting resistor R, and the gate of the transistor Q3 receives the pull-down control signal Vdr. The transistor Q3 is, for example, a lateral double-diffused transistor (LDMOS). In other embodiments, the pull-down branch 20 may also include a series-connected switching unit 21 and a CMOS transistor. The CMOS transistor remains on throughout the switching cycle, operating in the linear region, and is equivalent to the current-limiting resistor R.

[0041] Furthermore, the negative current detection unit 110 includes a comparator COMP and a latch U1. The non-inverting and inverting inputs of the comparator COMP receive the threshold signal Vncp and the inductor current signal Vsen, respectively, and the output provides a comparison signal. The input of the latch U1 is connected to the output of the comparator COMP, the clock input CLK receives the drive signal Vg2 of the lower transistor Q2, and the output provides an enable signal EN. While the drive signal Vg2 of the lower transistor is high, the level of the enable signal EN output by the latch U1 follows the level of the comparison signal. When the drive signal Vg2 of the lower transistor flips to low, the level of the enable signal EN output by the latch U1 is latched. During the period when the lower transistor Q2 is off, the level of the enable signal EN follows the level of the latching moment. That is, during the entire period when the lower transistor Q2 is off, the level of the enable signal EN is locked at the level of the comparison signal at the time when the lower transistor Q2 is off. When the inductor current characterization signal Vsen is less than or equal to the characterization threshold Vncp, the negative current characterization signal Incp is less than or equal to the current threshold Incp (the absolute value of the negative current is greater than or equal to the absolute value of the current threshold Incp), generating a valid enable signal EN. Both the lower MOSFET drive unit 130 and the upper MOSFET drive unit 140 receive the error amplification signal Vcom to generate the corresponding drive signals Vg2 and Vg1 for the lower MOSFET and upper MOSFET, respectively. The error amplification signal Vcom is generated by the output voltage feedback signal Vo1 and the reference voltage Vref through the error amplifier EA. The output terminal is grounded through two series-connected voltage divider resistors (resistors Ru and Rp), and the feedback signal Vo1, characterizing the output voltage, is obtained at the midpoint of the two resistors. The feedback signal Vo1 and the reference voltage Vref are amplified by the error amplifier EA to obtain the error amplification signal Vcom. The lower MOSFET drive unit 130 includes, for example, a PWM generator 111 that generates a PWM signal based on the error amplification signal Vcom. Similarly, the upper MOSFET drive unit 140 may also include a PWM generator to generate a PWM signal based on the error amplification signal Vcom to control the on and off of the upper MOSFET Q1.

[0042] In this embodiment, after receiving a valid enable signal EN, the pull-down control unit 120 generates a pull-down control signal Vdr based on the drive signal Vg2 of the lower transistor. Specifically, during the valid period of the enable signal EN, the pull-down control unit 120 determines the turn-off time of the lower transistor Q2 based on the drive signal Vg2, and generates the valid edge of the pull-down control signal Vdr based on the invalid edge of the drive signal Vg2, thus determining the turn-on time of the pull-down branch 20. The invalid edge of the drive signal Vg2 turns off the lower transistor Q2, and the valid edge of the pull-down control signal Vdr turns on the pull-down branch 20. Preferably, a falling edge is used as the invalid edge, and a rising edge is used as the valid edge. The pull-down control unit 120 specifically includes a timing unit 121, a pulse generator 122, and a logic gate circuit 123. Timing unit 121 provides a timing signal Vdd and receives the drive signal Vg2 from the lower transistor Q2 to start timing at the turn-off moment of the lower transistor Q2. After timing for a second time td, it generates the signal edge of the timing signal Vdd, which is, for example, a falling edge. For example, timing unit 121 includes a delay unit that delays the falling edge of the drive signal Vg2 of the lower transistor by a second time td before outputting the timing signal Vdd. That is, timing unit 121 generates the rising edge of the timing signal Vdd following the rising edge of the drive signal Vg2 of the lower transistor, and generates the falling edge of the timing signal Vdd by delaying the falling edge of the drive signal Vg2 of the lower transistor by a second time td. Pulse generator 122 generates a pulse signal Vdp with a pulse width of a first time tp based on the falling edge of the timing signal Vdd. During the active period of the enable signal EN, logic gate circuit 123 converts the pulse signal Vdp into an active pull-down control signal Vdr to control the pull-down branch 20 to conduct. Furthermore, logic gate 123 receives the drive signal Vg2 from the lower transistor and the pulse signal Vdp, processes them logically to provide a pull-down control signal Vdr, making the pull-down control signal Vdr valid during the first time tp when the pulse signal Vdp is valid, and invalid during the dead time when the pulse signal Vdp is invalid. In one embodiment, logic gate 123 includes, for example, an OR gate U3, whose two inputs receive the pulse signal Vdp and the drive signal Vg2 from the lower transistor, respectively, to convert the pulse signal Vdp into the pull-down control signal Vdr, and provide the pull-down control signal Vdr from the output to the control terminal of transistor Q3, thereby controlling the conduction state of pull-down branch 20. The circuit design can be used to make pull-down branch 20 follow the conduction state of lower transistor Q2 during its conduction period. Of course, the structure of logic gate 123 can also be adjusted so that pull-down branch 20 remains off during the conduction period of lower transistor Q2. The specific structure of logic gate 123 is not limited here.

[0043] Furthermore, if the pull-down control unit 120 does not receive a valid enable signal EN during the conduction period of the lower transistor Q2, it will not generate a pulse signal Vdp. Therefore, during the turn-off period of the lower transistor Q2, the pull-down control unit 120 controls the pull-down branch 20 to remain off. In addition, the pull-down control unit 120 may also include a drive amplifier composed of an even number of inverters, which amplifies the output of the OR gate U3 and uses it as the pull-down control signal Vdr.

[0044] Figure 4 A schematic waveform diagram of each signal of the control circuit of the power converter according to an embodiment of the present invention is shown during operation.

[0045] Figure 4 Given Figure 3 The waveform diagrams of the control circuit signals in the embodiment are combined with... Figure 3 and Figure 4 As can be seen, at time t0, the drive signal Vg2 of the lower transistor flips from low level to high level, driving the lower transistor Q2 to conduct, while the enable signal EN is low level, which is invalid, indicating that the negative current has not reached the current threshold at this time. Figure 3 The timing signal Vdd output by the timing unit 121 flips from low to high level, following the drive signal Vg2 of the lower transistor. Since the timing signal Vdd does not generate a falling edge, the pulse signal Vdp is low. Correspondingly, in the first case, during the conduction of the lower transistor Q2, the pull-down control signal Vdr (1) follows the drive signal Vg2 of the lower transistor, and thus also flips to high level at time t0, and the conduction state of the pull-down branch 20 follows the conduction state of the lower transistor Q2. In the second case, during the conduction of the lower transistor Q2, the pull-down control signal Vdr (2) remains off, and thus is low at time t0, and the pull-down branch 20 is off. During the time period t0-t1, each signal maintains the above-mentioned level state.

[0046] At time t1, the negative current detection unit 110 detects that the inductor current characterization signal Vsen reaches the characterization threshold Vncp, and generates a high-level enable signal EN. Then at time t2, the drive signal Vg2 of the lower transistor flips to a low level, turning off the lower transistor Q2. The timing unit 121 receives the valid enable signal EN, and the lower transistor Q2 begins to turn off, so the second time td is started from time t2. When the second time td is greater than zero, the timing signal Vdd generated by the timing unit 121 remains at a high level, and no falling edge of the timing signal Vdd is generated. The pull-down control signal Vdr (1) provided by the pull-down control unit 120 follows the drive signal Vg2 of the lower transistor Q2 and also flips to a low level, turning off the pull-down branch 20, while the pull-down control signal Vdr (2) remains at a low level, and the pull-down branch 20 is turned off. Then, during the time period t2-t3, each signal maintains the above level state, and the time period t2-t3 is the second time td. Since the enable signal EN is high at time t2, it remains high throughout the entire period when the lower transistor Q2 is turned off.

[0047] At time t3, the second time td ends, and timing unit 121 generates the falling edge of timing signal Vdd. At this time, pulse generator 122 starts generating a high-level pulse signal Vdp. The high level of this pulse signal Vdp lasts for the first time tp, that is, the pulse width is the first time tp. t3-t4 is the first time tp. During this time period, pull-down control signals Vdr(1) and Vdr(2) both flip to high level, controlling pull-down branch 20 to conduct for the first time tp. At time t4, the first time tp ends, pull-down branch 20 is turned off, and the voltage spike of node voltage Vsw has decreased. Afterward, the absolute value of the negative current decreases, and the enable signal EN remains at a high level. During the time period t4-t5, the upper transistor Q1 is turned on for a period of time. Afterward, at time t5, the upper transistor Q1 is turned off, and the drive signal Vg2 of the lower transistor flips to high level again, and the lower transistor Q2 is turned on again. When the current transistor Q2 is turned on again, the corresponding pull-down control signal Vdr(1) follows the drive signal Vg2 of the current transistor to turn on the pull-down branch 20, while the pull-down control signal Vdr(2) remains at a low level to turn off the pull-down branch 20. At this time, the enable signal EN flips from a high level to a low level. The time period t2-t4 is the sum of the first time and the second time. This time is, for example, less than the dead time, and in some special cases, it can be equal to the dead time.

[0048] Furthermore, when the second time td provided by the timing unit 121 is equal to zero, the falling edge of the timing signal Vdd is generated at the moment the lower transistor Q2 is turned off, and a pulse signal with a duration of the first time tp is generated simultaneously. Therefore, in the first case, corresponding to... Figure 3The pull-down control signal Vdr(1) remains high during the time period t0-t2 and also remains high during the time period t2-t3. Therefore, it can be considered that it remains high during the time period t0-t3, and its waveform corresponds to Figure 4 Vdr(1) when td is 0. This pull-down control signal Vdr(1) keeps the pull-down branch 20 continuously conducting during the conduction of the lower transistor Q2, and continues to conduct for the first time tp after the lower transistor Q2 is turned off. In the second case, the pull-down control signal Vdr(2) maintains a low level during the t0-t2 time period, flips to a high level during the t2-t3 time period, and the high level lasts for the first time tp, and its waveform corresponds to Figure 4 Vdr(2) when td is 0. This pull-down control signal Vdr(2) keeps the pull-down branch 20 off during the conduction of the lower tube Q2, and turns it on for the first time tp after the lower tube Q2 is turned off.

[0049] It should be noted that, Figure 4 The waveform shown indicates that the turn-off time t2 of the lower transistor Q2 is later than t1, when the inductor current characterization signal Vsen drops to the characterization threshold Vncp. However, this does not mean that the turn-off time of the lower transistor Q2 must be later than the time when the inductor current characterization signal Vsen drops to the characterization threshold Vncp. In fact, the turn-off time of the lower transistor Q2 is determined by the control strategy of the lower transistor Q2 in the entire system. In reality, it is also possible that the turn-off time of the lower transistor Q2 coincides exactly with the time when the inductor current characterization signal Vsen drops to the characterization threshold Vncp t1. In reality, it is also possible that the turn-off time of the lower transistor Q2 is earlier than the time when the inductor current characterization signal Vsen drops to the characterization threshold Vncp t1, that is, during the turn-off period of the lower transistor Q2, the inductor current characterization signal Vsen is greater than the characterization threshold Vncp.

[0050] Furthermore, it should be noted that the node voltage Vsw oscillates during the dead time. The oscillation frequency typically remains relatively stable during the decay process, and can be determined based on parasitic inductance and capacitance. To avoid the problem of the pull-down branch turning on later than the node voltage Vsw oscillates to its highest point, resulting in ineffective reduction of the voltage spike at the switching node, the second time td needs to meet certain constraints. Preferably, the second time td is less than 1 / 4 of the oscillation period.

[0051] Furthermore, the present invention can also provide a switching power supply, which includes, for example, a multi-phase power converter as described in the above embodiments. The multi-phase power converters share the same input terminal and their output terminals are also connected, so that the input voltage and output voltage of each phase power converter are the same. Moreover, each phase power converter is connected to a corresponding pull-down branch, and each phase's pull-down branch is controlled by its respective phase's pull-down control unit, which will not be described in detail here.

[0052] Figure 5 A schematic flowchart of a control method for a power converter according to an embodiment of the present invention is shown.

[0053] This control method is applied to the aforementioned switching power supply and power converter. (See [link]) Figure 5 The control method of the power converter in this embodiment includes, for example, the following steps:

[0054] In step S101, when a negative current on the inductor is detected to reach a set current threshold during the conduction of the lower transistor, an effective enable signal is generated.

[0055] In step S102, after receiving a valid enable signal, during the dead time from the start of the lower transistor's turn-off to the start of the upper transistor's turn-on, the pull-down branch is controlled to turn on for the first time to reduce the voltage spikes of the switching node.

[0056] Furthermore, an inductor current characterization signal is used to characterize the current on the inductor. When the inductor current characterization signal reaches a set characterization threshold, the negative current on the inductor reaches a set current threshold, and the current threshold is less than zero.

[0057] Furthermore, the control method may further include controlling the pull-down branch to turn off for a second time after the lower transistor begins to turn off, and then turning it on for a first time, wherein the second time is greater than or equal to zero, and the sum of the first and second times is less than or equal to the dead time. Further, during the conduction period of the lower transistor, the pull-down branch either turns on synchronously with the lower transistor or remains off. And if no valid enable signal is received during the conduction period of the lower transistor, the pull-down branch is controlled to remain off during the turn-off period of the lower transistor. Further, during the valid period of the enable signal, the turn-off time of the lower transistor is determined based on the drive signal of the lower transistor, and the valid edge of the pull-down control signal is generated based on the invalid edge of the drive signal of the lower transistor to determine the conduction time of the pull-down branch.

[0058] The control method in this embodiment is based on the power converter described above. The specific circuit principle, structure and working process have been described above and will not be repeated here.

[0059] It is understood that the above embodiments of this application are mainly described and illustrated using a buck topology as an example, but are not limited to this converter structure. Other similar converters, such as boost converters, can also be used. Applying the control scheme of this application to similar converter structures can also achieve the same or similar beneficial technical effects. The embodiments of this application do not limit this.

[0060] It should be noted that the numerical values ​​in this article are for illustrative purposes only. In other embodiments of the present invention, other numerical values ​​may be sampled to implement this solution. The specific values ​​should be reasonably set according to the actual situation, and the present invention does not limit them.

[0061] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

[0062] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A power converter, comprising an upper transistor and a lower transistor connected in series, and an inductor connected to a common node of the upper transistor and the lower transistor, wherein the common node of the upper transistor and the lower transistor is a switching node, wherein, The power converter also includes: A pull-down branch is connected between the switch node and the ground terminal; The negative current detection unit outputs a valid enable signal when it detects a negative current on the inductor reaching a set current threshold during the conduction period of the lower transistor; and Upon receiving a valid enable signal, the pull-down control unit controls the pull-down branch to conduct for a first time during the dead time between the start of the lower transistor's turn-off and the start of the upper transistor's turn-on, in order to reduce the voltage spikes of the switching node.

2. The power converter according to claim 1, wherein, When the lower tube begins to turn off, the pull-down control unit controls the pull-down branch to turn off for a second time and then turn it back on for a first time. The second time is greater than or equal to zero, and the sum of the first time and the second time is less than or equal to the dead time.

3. The power converter according to claim 1, wherein, The pull-down control unit controls the pull-down branch to either be synchronously turned on or remain off during the conduction period of the lower tube.

4. The power converter according to claim 1, wherein, If the pull-down control unit does not receive the valid enable signal during the pull-down tube's on period, it controls the pull-down branch to remain off during the pull-down tube's off period.

5. The power converter according to claim 1, wherein, The pull-down branch includes a series-connected switching unit and a current-limiting resistor. The switching unit includes at least one switch connected in parallel, and the switch includes a field-effect transistor and a junction transistor.

6. The power converter according to claim 1, wherein, The pull-down branch includes a series-connected switching unit and a CMOS transistor. The CMOS transistor operates in the linear region throughout the switching cycle and is equivalent to a current-limiting resistor. The switching unit includes at least one switch connected in parallel, and the switch includes a lateral double-diffused transistor.

7. The power converter according to claim 1, wherein, During the active period of the enable signal, the pull-down control unit determines the turn-off time of the pull-down transistor based on the drive signal of the pull-down transistor, and generates the active edge of the pull-down control signal based on the inactive edge of the drive signal of the pull-down transistor, thereby determining the conduction time of the pull-down branch.

8. The power converter according to claim 1, wherein, The pull-down control unit includes: The timing unit starts timing at the moment the lower tube is turned off, and generates a timing signal edge after a second time interval, wherein the second time interval is greater than or equal to zero. A pulse generator generates a pulse signal with a pulse width of a first time according to the signal edge of the timing signal; and A logic gate circuit converts the pulse signal into a valid pull-down control signal during the period when the enable signal is active, so as to control the pull-down branch to conduct.

9. The power converter according to claim 8, wherein, The timing unit receives the drive signal from the lower transistor, delays the invalid edge of the drive signal from the lower transistor for a second time, and outputs it as the signal edge of the timing signal. The logic gate circuit receives the drive signal of the lower transistor and the pulse signal, performs logic processing to provide the pull-down control signal, so that the pull-down control signal is valid within the first time period, and invalid outside the first time period of the dead time period.

10. The power converter according to claim 1, wherein, The negative current detection unit includes: The comparator receives a set threshold value and an inductor current characterization signal at its non-inverting and inverting inputs, respectively, and provides a comparison signal at its output; and The latch has its input connected to the output of the comparator, its clock input receives the drive signal from the lower transistor, and its output provides the enable signal. Specifically, during the conduction period of the lower transistor, the latch causes the level of the enable signal to follow the level of the comparison signal, and during the de-energization period of the lower transistor, the level of the enable signal is locked to the level of the comparison signal at the instant the lower transistor is de-energized. When the inductor current characterization signal begins to fall below the characterization threshold, it indicates that the negative current on the inductor has reached the current threshold.

11. A switching power supply, comprising: The multiphase power converter according to any one of claims 1 to 10, wherein the input and output terminals of the multiphase power converter are respectively connected to, In each phase of the power converter, the pull-down branch is controlled to be turned on by the pull-down control unit of its respective phase.

12. A control method for a power converter, the power converter comprising an upper transistor and a lower transistor connected in series, an inductor connected to a common node of the upper transistor and the lower transistor, and a pull-down branch connected between the common node and a ground terminal, wherein the common node of the upper transistor and the lower transistor is a switching node, wherein... The control method includes: During the conduction of the lower transistor, when a negative current on the inductor is detected to reach a set current threshold, an effective enable signal is generated; Upon receiving a valid enable signal, during the dead time from when the lower transistor begins to turn off to when the upper transistor begins to turn on, the pull-down branch is controlled to turn on for the first time to reduce the voltage spike of the switching node.

13. The control method according to claim 12, wherein, When the lower tube begins to shut down, the lower branch is controlled to shut down for a second time before being turned on for a first time. The second time is greater than or equal to zero, and the sum of the first time and the second time is less than or equal to the dead time.

14. The control method according to claim 12, wherein, During the active period of the enable signal, the turn-off time of the lower transistor is determined based on the drive signal of the lower transistor, and the active edge of the pull-down control signal is generated based on the inactive edge of the drive signal of the lower transistor, thereby determining the active time of the pull-down branch.

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