A solar cell, a cell assembly, a photovoltaic system and a method of manufacturing the same

Abstract

This invention relates to the field of photovoltaic technology and provides a solar cell, a battery module, a photovoltaic system, and a method for fabricating the same. The solar cell includes: a silicon substrate and a first doped layer; the back surface of the silicon substrate has several first regions and several second regions alternately arranged along a first direction; the first doped layer is stacked within the first regions, and the first doped layer is doped with a first dopant element; each first region has a first grid line preset position extending along a second direction, which intersects the first direction; at the position corresponding to the first grid line preset position, the first doped layer has a first highly doped region, within which a second dopant element is doped, and the second dopant element has the opposite polarity to the first dopant element. The simultaneous presence of both dopant elements in the first highly doped region can significantly increase the carrier concentration, allowing electrons and holes to move more rapidly, thereby enhancing current conduction.

Description

Technical Field

[0001] This invention belongs to the field of photovoltaic technology, and particularly relates to a solar cell, a battery module, a photovoltaic system, and a method for preparing the same. Background Technology

[0002] In the field of solar cell technology, the contact performance between the electrode and the doped layer plays a crucial role in the overall performance of the cell. In traditional solar cell designs, the electrode typically makes direct contact with the doped layer to achieve conductivity. However, this direct contact method has significant drawbacks. Due to the mismatch between the physical and electrical properties at the interface, the contact resistance is high. High contact resistance causes a significant amount of current loss during transmission, resulting in the actual output power of the cell being far lower than the theoretical value. Furthermore, this reduces the conduction efficiency of charge carriers within the cell, thus affecting the overall photoelectric conversion efficiency and limiting the performance and economic benefits of solar cells in practical applications. Summary of the Invention

[0003] This invention provides a solar cell, a battery module, a photovoltaic system, and a method for manufacturing the same, aiming to solve the problems of high contact resistance, large current loss, and reduced efficiency in existing technologies.

[0004] The present invention is implemented as follows: a solar cell includes: a silicon substrate and a first doped layer; A silicon substrate has a backlight surface having a plurality of first regions and a plurality of second regions arranged alternately along a first direction. A first doped layer is stacked in the first region, and the first doped layer is doped with a first doping element. A first gate line is preset in the first region and extends along a second direction, which intersects with the first direction. At the position corresponding to the preset position of the first gate line, the first doped layer has a first highly doped region, and the first highly doped region is doped with a second doping element, the second doping element having the opposite polarity to the first doping element.

[0005] Optionally, the first doped layer has a first side facing the silicon substrate and a second side facing away from the silicon substrate, and the second doping element in the first highly doped region decreases from the second side to the first side.

[0006] Optionally, a first tunneling layer is further provided in the first region, the first tunneling layer being disposed between the silicon substrate and the first doped layer; The first highly doped zone is in direct contact with the first tunneling layer.

[0007] Optionally, the depth within the first highly doped region is d, where 10 < d ≤ 200 nm.

[0008] Optionally, in the first highly doped region, the ratio of the concentration of the first doped element to the concentration of the second doped element is in the range of 0.01% to 0.5%, and the first doped element is one or a combination of boron, gallium or other third group elements.

[0009] Optionally, in the first highly doped region, the concentration of the first dopant element is 2 × 10⁻⁶. 19 ~8×10 19 atom / cm 3 .

[0010] Optionally, within the first highly doped region, the concentration of the second dopant element is 3 × 10⁻⁶. 20 ~7×10 20 atom / cm 3 The second doping element is phosphorus, arsenic, or one or a combination of other Group V elements.

[0011] Optionally, a plurality of the first highly doped regions are provided within the first doped layer.

[0012] Optionally, within a single first region, a plurality of first highly doped regions are arranged along the second direction.

[0013] Optionally, several of the first highly doped regions are evenly distributed along the second direction.

[0014] Optionally, along the second direction, the distance between adjacent first highly doped regions is 250 μm to 400 μm.

[0015] Optionally, within a single first region, the first highly doped region extends along the second direction.

[0016] Optionally, a second doped layer is stacked in the second region, and the second doped layer is doped with the second doping element; The second region has a second gate line preset position, and at the position corresponding to the second gate line preset position, the second doped layer has a second highly doped region, and the second highly doped region is doped with a first doping element.

[0017] Optionally, an interval region is provided between the first region and the second region.

[0018] Optionally, the interval region is a trench.

[0019] The present invention also provides a battery assembly including the solar cell described above.

[0020] The present invention also provides a photovoltaic module, including the above-described battery module.

[0021] The present invention also provides a method for preparing a solar cell, comprising the following steps: A first doped layer and a first mask layer are sequentially fabricated on the back surface of the silicon substrate; Remove the first mask layer from the areas other than the first region, and remove the first doped layer and part of the silicon substrate from the areas not covered by the first mask layer; A second polycrystalline silicon layer is prepared on the back surface of the silicon substrate; Remove the second polysilicon layer at the position corresponding to the preset position of the first gate line; The second doping element is doped into the polysilicon layer to form the second doped layer, and the second doping element is diffused into the first doped layer corresponding to the first gate line preset position to form the first highly doped region, and a second mask layer is formed on the back surface of the silicon substrate. The second mask layer is used to remove areas other than the second region; Remove the second doped layer from the area not covered by the second mask layer; Remove the first mask layer and the second mask layer.

[0022] Optionally, the step preceding "sequentially fabricating the first doped layer and the first mask layer on the back surface of the silicon substrate" further includes the following steps: A first tunneling layer is prepared on the back surface of the silicon substrate.

[0023] Optionally, the step preceding "preparing a polycrystalline silicon layer on the back surface of the silicon substrate" further includes the following steps: A second tunneling layer is prepared on the back surface of the silicon substrate.

[0024] The beneficial effects achieved by this invention are due to the presence of a first highly doped region in the first doped layer at the preset position of the first gate line. The first doped layer is doped with a first doping element, and the first highly doped region is doped with a second doping element. The simultaneous presence of both doping elements in the first highly doped region significantly increases the carrier concentration. This allows electrons and holes to move more rapidly, thereby enhancing current conduction. Simultaneously, it facilitates better ohmic contact with the electrodes, reduces contact resistance, and further improves the battery's transmission efficiency. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of a solar cell provided by the present invention; Figure 2 This is a schematic diagram of another solar cell structure provided by the present invention; Figure 3 This is a schematic diagram of the steps involved in the fabrication of a solar cell; Figure 4 This is a schematic diagram of another type of solar cell provided by the present invention; Figure 5 This is a schematic diagram of the structure of a solar cell from a top-down perspective provided by the present invention.

[0026] Explanation of reference numerals in the attached figures: 100. Solar cell; 110. First region; 120. Second region; 101. Silicon substrate; 102. First tunneling layer; 103. First doped layer; 1031. First highly doped region; 104. Second tunneling layer; 105. Second doped layer; 1051. Second highly doped region; 106. Passivation layer; 107. Anti-reflection layer; 108. First grid line; 109. Second grid line; 201, First mask layer; 202, Second mask layer. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the invention, and should not be construed as limiting the invention. Furthermore, it should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0028] In the description of this invention, it should be understood that the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0030] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0031] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0032] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0033] This invention establishes a first highly doped region in a first doped layer at a predetermined position corresponding to the first gate line. The first doped layer is doped with a first doping element, and the first highly doped region is doped with a second doping element. The simultaneous presence of both doping elements in the first highly doped region significantly increases the carrier concentration. This allows electrons and holes to move more rapidly, thereby enhancing current conduction. Simultaneously, it facilitates better ohmic contact with the electrodes, reducing contact resistance and further improving the battery's transmission efficiency.

[0034] Example 1 like Figure 1 As shown, this embodiment provides a solar cell 100, including: a silicon substrate 101 and a first doped layer 103; A silicon substrate 101 has a backlight surface having a plurality of first regions 110 and a plurality of second regions 120 arranged alternately along a first direction. A first doped layer 103 is stacked in the first region 110. The first doped layer 103 is doped with a first doping element. A first gate line preset position is provided in the first region 110 and extends along a second direction. The second direction intersects with the first direction. At the position corresponding to the preset position of the first gate line, the first doped layer 103 has a first highly doped region 1031, and a second doping element is doped in the first highly doped region 1031. The second doping element has the opposite polarity to the first doping element.

[0035] The silicon substrate 101 has two main surfaces: a light-facing surface and a back-lighting surface. The light-facing surface directly faces the sunlight, while the back-lighting surface is on the other side. The two surfaces are positioned opposite each other.

[0036] Two distinct regions, a first region 110 and a second region 120, are arranged alternately on the backlight surface of the silicon substrate 101. Specifically, a plurality of first regions 110 and a plurality of second regions 120 are arranged alternately along a first direction, and both the first regions 110 and 120 extend along a second direction, which intersects the first direction. The first regions 110 and 120 can be arranged alternately along the lateral direction of the silicon substrate 101 and both extend along the longitudinal direction; that is, the first direction can be the lateral direction of the back contact battery, and the second direction can be the longitudinal direction of the back contact battery, and the two are perpendicular to each other. Of course, in other embodiments, the first direction and the second direction can also be other directions, for example, they can be the diagonal directions of the silicon substrate 101, and no specific limitation is made here. The first regions 110 and 120 do not overlap and are arranged adjacent to each other.

[0037] A first doped layer 103 is disposed in the first region 110, and a second doped layer 105 is disposed in the second region 120. The first doped layer 103 is doped with a first dopant element, and the second doped layer 105 is doped with a second dopant element. The first and second doped elements have opposite polarities. Specifically, the first dopant element can be a P-type dopant element and the second dopant element can be an N-type dopant element, or vice versa. The first and second polar doped layers form regions with different electrical properties, supporting the formation of a PN junction and the separation of charge carriers.

[0038] The first gate line preset position is used to set the position of the first gate line 108. At the position corresponding to the first gate line preset position, the first doped layer 103 has a first highly doped region 1031. A second doping element is doped in the first highly doped region 1031, that is, the first highly doped region 1031 is simultaneously doped with both the first doping element and the second doping element. The first highly doped region 1031 is a part of the first doped layer 103. The doping concentration of the first doping element in the first highly doped region 1031 is the same as the doping concentration of the first doping element at other positions in the first doped layer 103. At the same time, the second doping element is doped in the first highly doped region 1031. It can be understood that the first gate line contacts the first doped layer 103 to transport the charge carriers generated by the first doped layer 103, that is, the first gate line contacts the first highly doped region 1031.

[0039] Specifically, the first doped layer 103 is a P-type doped layer, so the first dopant element is a P-type dopant element, such as boron, which generates holes; the second dopant element is an N-type dopant element, such as phosphorus, which provides additional free electrons in the silicon lattice. The simultaneous presence of these two dopant elements in the first highly doped region 1031 significantly increases the concentration of charge carriers (electrons and holes). This high concentration of intrinsic charge carriers allows electrons and holes to move more quickly, thereby enhancing current conduction and enabling smoother transport of charge carriers generated in the first region 110 to the first gate line, improving the battery's transmission efficiency. Simultaneously, the high concentration of charge carriers results in a tighter contact between the electrode and the semiconductor, forming a better ohmic contact, thus reducing contact resistance. Lower contact resistance reduces energy loss during current transmission, further improving the battery's transmission efficiency.

[0040] In some embodiments, a first tunneling layer 102 is provided between the silicon substrate 101 and the first doped layer 103. The first tunneling layer 102 can provide a low-barrier channel, making it easier for photogenerated carriers (electrons and holes) to cross the interface through the tunneling effect, reducing carrier recombination at the interface and improving carrier collection efficiency.

[0041] Furthermore, the first highly doped region 1031 is in direct contact with the first tunneling layer 102, that is, there is a contact surface between the two, and the side of the first tunneling layer 102 facing away from the silicon substrate 101 is in contact with the first highly doped region 1031.

[0042] In this embodiment, a first highly doped region 1031 is formed in the first doped layer 103 at the position corresponding to the preset position of the first gate line. The first doped layer 103 is doped with a first doping element, and the first highly doped region 1031 is doped with a second doping element. The simultaneous presence of these two doping elements in the first highly doped region 1031 can greatly increase the carrier concentration. This allows electrons and holes to move more quickly, thereby enhancing current conduction capability. At the same time, it is beneficial to form a better ohmic contact with the electrode, reducing contact resistance and further improving the battery's transmission efficiency.

[0043] In some embodiments, such as Figure 2 As shown, the solar cell 100 further includes a passivation layer 106, an antireflection layer 107, a first grid line 108, and a second grid line 109. The passivation layer 106 and the antireflection layer 107 are sequentially stacked on the back surface of the solar cell 100, covering the functional layers on the silicon substrate 101. The first grid line 108 is located at a predetermined position, passes through the passivation layer 106 and the antireflection layer 107, and contacts the first highly doped region 1031. The second grid line 109 passes through the passivation layer 106 and the antireflection layer 107 and contacts the second doped layer 105.

[0044] In some embodiments, the first doped layer 103 has a first side facing the silicon substrate 101 and a second side facing away from the silicon substrate 101. The second dopant element in the first highly doped region 1031 decreases from the second side to the first side. The second side, facing away from the silicon substrate 101, is typically the side in contact with the electrode. The diffusion of the second dopant element from the second side to the first side results in a higher doping concentration near the electrode, with the second dopant element decreasing towards the first side. At the interface between the electrode and the semiconductor, a potential barrier exists that hinders carrier transport. The high concentration distribution of the second dopant element near the second side effectively reduces this interface barrier, making it easier for carriers (electrons or holes) to enter the electrode from the semiconductor, further improving the battery's electrical performance.

[0045] Furthermore, the depth within the first highly doped region 1031 is d, where 10 < d ≤ 200 nm. The thickness of the first doped layer 103 is typically in the range of 20~150 nm, and the depth d of the first highly doped region 1031 is controlled within the range of 10 < d ≤ 200 nm. The maximum depth of the first highly doped region 1031 is consistent with the thickness of the first doped layer 103, meaning that the first highly doped region 1031 diffuses from the first surface to the first surface. The depth of the first highly doped region 1031 optimizes the performance of local areas without compromising the overall structure of the first doped layer 103.

[0046] In some embodiments, a first tunneling layer 102 is disposed between a silicon substrate 101 and a first doped layer 103, and a first highly doped region 1031 is in contact with the first tunneling layer 102. That is, the first highly doped region 1031 penetrates the first doped layer 103.

[0047] In some embodiments, within the first highly doped region 1031, the ratio of the concentration of the first dopant element to the concentration of the second dopant element ranges from 0.01% to 0.5%. Specifically, the first doped layer may be a P-type doped layer, meaning the first dopant element is boron, gallium, or one or a combination of other Group 3 elements, and the second dopant element may be an N-type dopant element, meaning the second dopant element is phosphorus, arsenic, or one or a combination of other Group 5 elements.

[0048] The second dopant element is densely incorporated into the first highly doped region 1031, resulting in a high doping concentration of the second dopant element within this region, significantly higher than that of the first dopant element. It should be noted that since the second dopant element diffuses from the second surface to the first surface within the first highly doped region 1031, the closer to the second surface, the higher the doping concentration of the second dopant element. The doping concentration of the second dopant element is inversely proportional to its distance from the second surface. The doping concentration of the second dopant element within the first highly doped region 1031 refers to its average doping concentration within this region. Specifically, concentration measurement data of the second dopant element within the first highly doped region 1031 under different process conditions can be collected. The experimental data can be analyzed and fitted to establish an empirical formula, expressing the average doping concentration as a function of process parameters and structural parameters. Substituting these parameters into the empirical formula, the average doping concentration of the second dopant element within the first highly doped region 1031 can be calculated.

[0049] The concentration and mobility of charge carriers together determine the conductivity of semiconductor materials. Within the first highly doped region 1031, a suitable concentration ratio of the first dopant to the second dopant can optimize the material's conductivity. The first and second dopant elements are typically used to provide different types of charge carriers (e.g., N-type doping provides electrons, and P-type doping provides holes). Maintaining their concentration ratio within the range of 0.01% to 0.5% helps achieve a relatively reasonable balance of charge carrier concentration within the first highly doped region 1031. This effectively improves the carrier mobility, thereby enhancing the current conduction capability within the battery, reducing the series resistance, minimizing energy loss during internal battery transfer, and increasing the battery's output power.

[0050] Specifically, within the first highly doped region 1031, the concentration of the first dopant element is 2 × 10⁻⁶. 19 ~8×10 19 atom / cm 3 .

[0051] Specifically, within the first highly doped region 1031, the concentration of the second dopant element is 3 × 10⁻⁶. 20 ~7×10 20 atom / cm 3 .

[0052] In some embodiments, a plurality of first highly doped regions 1031 are provided within the first doped layer 103. Specifically, the plurality of first highly doped regions 1031 may be disposed in the first doped layer 103 corresponding to a preset position of the first gate line, that is, the orthographic projection of the plurality of first highly doped regions 1031 overlaps with the orthographic projection of the preset position of the first gate line. The plurality of first highly doped regions 1031 may be uniformly disposed, such as... Figure 5 As shown, it can also be set randomly; no restrictions are imposed here.

[0053] In some embodiments, within a single first region 110, a plurality of first highly doped regions 1031 are disposed along a second direction.

[0054] The first grid line extends along the second direction, and multiple first highly doped regions 1031 are arranged along the second direction, that is, along the extension direction of the first grid line, the multiple first highly doped regions 1031 are spaced apart. This increases the contact area between the highly doped region and the photogenerated carrier generation region. Under illumination, photogenerated carriers can diffuse to the first highly doped regions 1031 more quickly, thus being effectively collected. Compared to a single large-area highly doped region, multiple small-sized first highly doped regions 1031 can reduce the carrier diffusion distance, reduce the recombination probability of carriers during diffusion, improve carrier collection efficiency, and thus increase the short-circuit current of the solar cell 100. Furthermore, along the second direction, the spacing between adjacent first highly doped regions 1031 is equal. Specifically, the distance between adjacent first highly doped regions 1031 is 250μm~400μm.

[0055] In some embodiments, within a single first region 110, a first highly doped region 1031 extends along a second direction. That is, the first highly doped region 1031 is continuously arranged along the extension direction of all preset positions of the first solder strips. The extension of the first highly doped region 1031 along the second direction provides a more direct and smoother transport channel for photogenerated carriers. When the solar cell 100 is operating, photogenerated carriers can move rapidly along the extension direction of the highly doped region, reducing the recombination probability of carriers during transport, thereby improving the carrier collection efficiency and thus enhancing the photoelectric conversion efficiency of the solar cell 100.

[0056] In some embodiments, such as Figure 4 As shown, a second doped layer 105 is stacked in the second region 120, and the second doped layer 105 is doped with a second doping element. The second region 120 has a second gate line preset position. At the position corresponding to the second gate line preset position, the second doped layer 105 has a second highly doped region 1051, and the second highly doped region 1051 is doped with a first doping element.

[0057] The second gate line preset position is used to set the position of the second gate line 109. At the position corresponding to the second gate line preset position, the second doped layer 105 has a second highly doped region 1051, in which the first doping element is doped. That is, the second highly doped region 1051 is simultaneously doped with both the second doping element and the first doping element. The function of the second highly doped region 1051 is similar to that of the first highly doped region 1031, and will not be described in detail here.

[0058] In some embodiments, a second tunneling layer 104 is further disposed within the second region 120, and the second tunneling layer 104 is disposed between the silicon substrate 101 and the second doped layer 105. The function of the second tunneling layer 104 is similar to that of the first tunneling layer 102, and will not be described in detail here.

[0059] In some embodiments, a spacer region 130 is provided between the first region 110 and the second region 120. The spacer region 130 can serve as an electrical isolation layer between the first region 110 and the second region 120, reducing electrical interference between the two regions and improving carrier collection efficiency and the open-circuit voltage of the battery.

[0060] Furthermore, the spacing region 130 is a trench. The distance from the surface of the spacing region 130 to the light-facing surface of the silicon substrate 101 is less than the distance from the surface of the first region 110 and the second region 120 to the light-facing surface of the silicon substrate 101, thereby creating spatial isolation between the first region 110 and the second region 120.

[0061] Example 2 This embodiment provides a battery assembly, including the solar cell 100 described above.

[0062] The battery module may include multiple back-contact solar cells 100 each. The multiple back-contact solar cells 100 each in the battery module can be connected in series to form a battery string. The battery strings can be connected in series, in parallel, or in a series-parallel combination to achieve current collection and output. For example, the connection between the individual cells can be achieved by welding solder strips, or the connection between the battery strings can be achieved by busbars.

[0063] The battery module may also include a metal frame, a backsheet, photovoltaic glass, and an encapsulant film (not shown in the figures). The encapsulant film can be filled between the light-facing side of the solar cell 100 and the photovoltaic glass, the back-facing side and the backsheet, and adjacent cells. As a filler, it can be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulant film can be EVA film or POE film, and the specific choice can be made according to the actual situation. There are no restrictions here.

[0064] Photovoltaic glass can be applied to the encapsulating film on the light-facing side of the solar cell 100. The photovoltaic glass can be ultra-clear glass, which has high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can achieve a light transmittance of over 92%. It can protect the solar cell 100 while minimizing impact on its efficiency. Simultaneously, the encapsulating film bonds the photovoltaic glass and the solar cell 100 together, providing sealing, insulation, waterproofing, and moisture protection for the solar cell 100.

[0065] The backsheet can be attached to the adhesive film on the back side of the solar cell 100. The backsheet provides protection and support for the solar cell 100, offering reliable insulation, water resistance, and aging resistance. Multiple backsheet options are available, typically including tempered glass, acrylic glass, and aluminum alloy TPT composite adhesive film, etc. The specific choice depends on the specific circumstances and is not limited here. The backsheet, solar cell 100, adhesive film, and photovoltaic glass can be mounted on a metal frame. The metal frame serves as the main external support structure for the entire battery module, providing stable support and installation. For example, the battery module can be installed at the desired location using the metal frame.

[0066] The beneficial effects of the battery module in this embodiment are equivalent to those of the solar cell 100 described above, and will not be repeated here.

[0067] Example 3 This embodiment provides a photovoltaic system, including the aforementioned battery module.

[0068] Photovoltaic systems can be applied in photovoltaic power plants, such as ground-mounted, rooftop, and floating power plants, as well as in equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it's understandable that the application scenarios of photovoltaic systems are not limited to these; that is, photovoltaic systems can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation network as an example, a photovoltaic system can include photovoltaic arrays, combiner boxes, and inverters. A photovoltaic array can be a combination of multiple battery modules; for example, multiple battery modules can form multiple photovoltaic arrays. The photovoltaic arrays are connected to combiner boxes, which collect the current generated by the photovoltaic arrays. The collected current flows through an inverter and is converted into AC power required by the mains grid before being connected to the mains grid to achieve solar power supply.

[0069] The beneficial effects of the photovoltaic system in this embodiment are equivalent to those of the battery module described above, and will not be repeated here.

[0070] Example 4 like Figure 3 As shown, this embodiment provides a method for preparing a solar cell 100, which includes the following steps: S1. A first doped layer 103 and a first mask layer 201 are sequentially prepared on the back surface of a silicon substrate 101. S2. Remove the first mask layer 201 from the areas other than the first region 110, and remove the first doped layer 103 and part of the silicon substrate from the areas not covered by the first mask layer 201. S3. Prepare a polycrystalline silicon layer on the back surface of the silicon substrate 101; S4. Remove the polysilicon layer at the position corresponding to the preset position of the first gate line; S5. A second doping element is doped into the polysilicon layer to form a second doped layer 105, and the second doping element is diffused into the first doped layer 103 corresponding to the preset position of the first gate line to form a first highly doped region 1031, and a second mask layer 202 is formed on the back light surface of the silicon substrate 101. S6. Remove the second mask layer 202 within the first region 110; S7. Remove the second doped layer 105 from the area not covered by the second mask layer 202; S8. Remove the first mask layer 201 and the second mask layer 202.

[0071] In step S1, the silicon substrate 101 is typically made of single-crystal silicon. Before fabricating the first doped layer 103, the silicon substrate 101 needs to undergo conventional treatments such as polishing. The first doped layer 103 and the first mask layer 201 are fabricated on the silicon substrate 101. Typically, a first polycrystalline silicon layer is first deposited on the back surface of the silicon substrate 101. Specifically, the first polycrystalline silicon layer can be deposited on the back surface of the silicon substrate 101 using methods such as chemical vapor deposition (CVD) or solid-state crystallization. Then, a first dopant element is doped into the first polycrystalline silicon layer using a diffusion method. The first dopant element diffuses into the silicon lattice, and its atoms replace some of the silicon atoms, forming the first doped layer 103. During the diffusion process, in addition to the incorporation of the first dopant element into the polycrystalline silicon, a first mask layer 201 is formed on the surface of the polycrystalline silicon due to oxidation. If the first dopant element is phosphorus (P), the first mask layer 201 is a PSG layer (phosphosilicate glass); if the first dopant element is boron (B), the first mask layer 201 is a BSG layer (borosilicate glass). At this time, the entire backlight surface is covered by the first doped layer 103. The first mask layer 201 covers the first doped layer 103 and is used to protect specific areas in subsequent processes.

[0072] In some embodiments, a first tunneling layer 102 may be disposed between the first doped layer 103 and the silicon substrate 101. The first tunneling layer 102 is prepared before the first doped layer 103, that is, the first tunneling layer 102 is prepared on the back surface of the silicon substrate 101 before the first doped layer 103 is prepared. Common materials for the first tunneling layer 102 include silicon dioxide (SiO2), silicon nitride (Si3N4), and aluminum oxide (Al2O3), and the first tunneling layer 102 can be formed on the surface of the silicon substrate 101 by thermal oxidation or atomic layer deposition (ALD).

[0073] In step S2, a laser can be used to remove the first mask layer 201 outside the first region 110. The laser scanning path is planned according to the shape and size of the first region 110. Linear scanning, spiral scanning, or other methods can be used to ensure that the mask layer outside the first region 110 is uniformly irradiated by the laser. The scanning speed is generally controlled between 100 and 1000 mm / s, with the specific speed depending on the laser parameters and the characteristics of the mask layer.

[0074] In step S3, the second polysilicon layer serves as the base layer for subsequent doping and electrode fabrication. The second polysilicon layer is fabricated across the entire backlight surface; specifically, in the first region 110, the second polysilicon layer is stacked on top of the first mask layer 201. In other regions besides the first region 110, the second polysilicon layer is stacked on top of the silicon substrate 101. The fabrication of the second polysilicon layer is similar to the method used to set the first polysilicon layer in step S1, typically employing chemical vapor deposition (CVD) methods, such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), to deposit the polysilicon layer on the backlight surface of the silicon substrate 101. During the deposition process, parameters such as the flow rate, temperature, and pressure of the reactive gases need to be controlled to obtain a polysilicon layer with suitable grain size, crystal quality, and thickness.

[0075] In some embodiments, a second tunneling layer 104 may be disposed between the second polysilicon layer and the silicon substrate 101. The second tunneling layer 104 is prepared before the second polysilicon layer, that is, the second tunneling layer 104 is prepared in other regions of the silicon substrate 101 other than the first region before the second polysilicon layer is prepared. The preparation of the second tunneling layer 104 is similar to that of the first tunneling layer 102, and will not be described in detail here.

[0076] In step S4, the first gate line preset position is the location for subsequent electrode fabrication. The specific laser process removes the second polysilicon layer corresponding to the first gate line preset position, exposing the underlying functional layer. It should be noted that when removing the second polysilicon layer with a laser, the laser spot energy exhibits a Gaussian distribution. The energy at the edge of the laser spot may be lower than the complete ablation threshold of the second polysilicon, resulting in incomplete removal of that area. Alternatively, the deposited polysilicon layer may have microscopic inhomogeneities in thickness, density, and grain size. Thicker or denser areas require higher energy to burn through; if fixed parameters are used uniformly, harder areas are more likely to remain. Simultaneously, after cooling, some of the vaporized polysilicon material will redeposit back into the opening area, especially on the sidewalls and bottom. Therefore, the second polysilicon layer corresponding to the first gate line preset position cannot be completely removed, leaving some residue.

[0077] In step S5, a diffusion method can be used to introduce the second dopant element into the second polysilicon layer to form the second doped layer 105. Specifically, the second dopant element is diffused into the second polysilicon layer at high temperature using a thermal diffusion process. Because the second polysilicon layer has high porosity and diffusion coefficient, the second dopant element can diffuse rapidly within it. During the doping process, the second dopant element diffuses from the polysilicon layer towards the silicon substrate 101 below. Particularly at the location corresponding to the preset position of the first gate line, since the second polysilicon layer is removed, the first mask layer 201 cannot effectively shield the second element, and the second dopant element directly penetrates into the first doped layer 103, forming the first highly doped region 1031. Similar to the first mask layer 201, the second mask layer 202 is formed by oxidation on the surface of the polysilicon layer when the second dopant element diffuses into it. The second mask layer 202 is also used to protect specific areas. Since the first dopant and the second dopant have different polarities, when the first mask layer 201 is a BSG layer, the second mask layer 202 is a PSG layer; when the first mask layer 201 is a PSG layer, the second mask layer 202 is a BSG layer.

[0078] In step S6, similar to step S2, laser etching is used to remove the second mask layer 202 in areas other than the second region 120, exposing the second doped layer 105 in that region, in preparation for the subsequent removal of the second doped layer 105 in that region.

[0079] In some embodiments, a spacer region 130 is provided between the first region 110 and the second region 120, the spacer region 130 being used to isolate the first region 110 and the second region 120. At this time, the other regions besides the second region 120 include the first region 110 and the spacer region 130, and the second mask layer 202 within the first region 110 and the spacer region 130 needs to be removed.

[0080] In some embodiments, a second doped layer 105 is stacked in the second region 120, and the second doped layer 105 is doped with a second doping element; the second region 120 has a second gate line preset position, and at the position corresponding to the second gate line preset position, the second doped layer 105 has a second highly doped region 1051, and the second highly doped region 1051 is doped with a first doping element.

[0081] The method for setting the second high-doping zone 1051 is similar to the method for setting the first high-doping zone 1031, but the following steps are required between steps S5 and S6: S501. A third polycrystalline silicon layer is prepared on the back surface of the silicon substrate 101. S502, Remove the third polysilicon layer at the position corresponding to the preset position of the second gate line; S503, a first doping element is doped into the third polysilicon layer to form a doped layer, and the first doping element is diffused into the second doped layer 105 corresponding to the second gate line preset position to form a second highly doped region 1051, and a third mask layer is formed on the back light surface of the silicon substrate 101. S504. Remove all third mask layers from the backlight side; S505, Remove the doped layer from the area not covered by the third mask layer.

[0082] The above steps complete the setup of the second high-doping zone 1051. After completing the above steps, proceed to step S6.

[0083] In step S7, the second doped layer 105 in the area not covered by the second mask layer 202 is removed using wet etching or dry etching. The second doped layer 105 is formed by the diffusion of the second dopant element into the second polysilicon layer. It should be noted that at this time, the first region 110 is still covered by the first mask layer 201 that was not removed in step S2. Due to the protection of the first mask layer 201, the silicon substrate 101 and the functional layers covered by the first mask layer 201 will not be removed. The functional layers covering the first mask layer 201, including the second polysilicon layer and, in some embodiments, the second tunneling layer 104, are all removed.

[0084] When there is a gap region 130 between the first region 110 and the second region 120, the second mask layer 202 covers the second region 120, the first mask layer 201 covers the first region 110, the gap region 130 is not covered by the mask layer, and the polysilicon layer (and the second tunneling layer 104) and part of the silicon substrate 101 stacked in the gap region 130 are removed to form a trench.

[0085] In step S8, similar to steps S2 and S6, laser etching is used to remove all of the first mask layer 201 and the second mask layer 202, exposing the first doped layer 103 and the second doped layer 105 in the corresponding area, in preparation for the subsequent electrode setup. The electrode needs to be in direct contact with the first doped layer 103 and the second doped layer 105.

[0086] Further functional layers can be fabricated, such as a passivation layer 106 (Al2O3) and an antireflection layer 107 (SiN) sequentially fabricated on the back surface of the silicon substrate 101. x ), and fabrication of gate lines, such as Figure 2 As shown, the subsequent fabrication of other functional layers adopts conventional process flow, which will not be described in detail here.

[0087] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A solar cell, characterized in that, include: Silicon substrate, first doped layer; The backlight surface of the silicon substrate has a plurality of first regions and a plurality of second regions arranged alternately along a first direction. The first doped layer is stacked in the first region and is doped with a first doping element. The first region has a first gate line preset position that extends along a second direction and intersects with the first direction. At the position corresponding to the preset position of the first gate line, the first doped layer has a first highly doped region, and the first highly doped region is doped with a second doping element, the second doping element having the opposite polarity to the first doping element.

2. The solar cell as described in claim 1, characterized in that, The first doped layer has a first side facing the silicon substrate and a second side facing away from the silicon substrate, and the second doping element in the first highly doped region decreases from the second side to the first side.

3. The solar cell as described in claim 1, characterized in that, A first tunneling layer is also provided in the first region, and the first tunneling layer is disposed between the silicon substrate and the first doped layer; The first highly doped zone is in direct contact with the first tunneling layer.

4. The solar cell as described in claim 2, characterized in that, The depth of the first highly doped region is d, where 10 < d ≤ 200 nm.

5. The solar cell as described in claim 1, characterized in that, Within the first highly doped region, the ratio of the concentration of the first doped element to the concentration of the second doped element ranges from 0.01% to 0.5%, and the first doped element is one or a combination of boron, gallium, or other Group III elements.

6. The solar cell as described in claim 5, characterized in that, Within the first highly doped region, the concentration of the first dopant element is 2 × 10⁻⁶. 19 ~8×10 19 atom / cm 3 .

7. The solar cell as described in claim 5, characterized in that, Within the first highly doped region, the concentration of the second dopant element is 3 × 10⁻⁶. 20 ~7×10 20 atom / cm 3 The second doping element is phosphorus, arsenic, or one or a combination of other Group V elements.

8. The solar cell as claimed in claim 1, characterized in that, Multiple first highly doped regions are provided within the first doped layer.

9. The solar cell as claimed in claim 8, characterized in that, Within a single first region, a plurality of first highly doped regions are arranged along the second direction.

10. The solar cell as claimed in claim 9, characterized in that, Several of the first highly doped regions are evenly distributed along the second direction.

11. The solar cell as claimed in claim 10, characterized in that, Along the second direction, the distance between adjacent first highly doped regions is 250 μm to 400 μm.

12. The solar cell according to claim 1, characterized in that, Within a single first region, the first highly doped region extends along the second direction.

13. The solar cell according to claim 1, characterized in that, A second doped layer is stacked in the second region, and the second doped layer is doped with the second doping element; The second region has a second gate line preset position, and at the position corresponding to the second gate line preset position, the second doped layer has a second highly doped region, and the second highly doped region is doped with a first doping element.

14. The solar cell according to claim 1, characterized in that, An interval region is provided between the first region and the second region.

15. The solar cell as claimed in claim 14, characterized in that, The interval area is a trench.

16. A battery assembly, characterized in that, Includes the solar cell described in any one of claims 1 to 15.

17. A photovoltaic module, characterized in that, Includes the battery assembly as described in claim 16.

18. A method for preparing a solar cell, characterized in that, The method for preparing the solar cell according to claims 1 to 15 includes the following steps: A first doped layer and a first mask layer are sequentially fabricated on the back surface of the silicon substrate; Remove the first mask layer from the areas other than the first region, and remove the first doped layer and part of the silicon substrate from the areas not covered by the first mask layer; A second polycrystalline silicon layer is prepared on the back surface of the silicon substrate; Remove the second polysilicon layer at the position corresponding to the preset position of the first gate line; The second doping element is doped into the polysilicon layer to form the second doped layer, and the second doping element is diffused into the first doped layer corresponding to the first gate line preset position to form the first highly doped region, and a second mask layer is formed on the back surface of the silicon substrate. The second mask layer is used to remove areas other than the second region; Remove the second doped layer and the second tunneling layer from the areas not covered by the second mask layer; Remove the first mask layer and the second mask layer.

19. The method for preparing a solar cell as described in claim 18, characterized in that, The step preceding "sequentially fabricating the first doped layer and the first mask layer on the back surface of the silicon substrate" further includes the following steps: A first tunneling layer is prepared on the back surface of the silicon substrate.

20. The method for preparing a solar cell as described in claim 18, characterized in that, The step preceding "preparing a polycrystalline silicon layer on the back surface of the silicon substrate" also includes the following steps: A second tunneling layer is prepared on the back surface of the silicon substrate.

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