Semiconductor layout structure and double-gate oxide layer preparation method

Abstract

The present disclosure relates to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor layout structure and a double-gate oxide layer preparation method, wherein the first photoresist pattern extends along a first direction, the size along the first direction is L1, and the size along a second direction is W1; the second photoresist pattern extends along the second direction, the size along the first direction is W2, and the size along the second direction is L2; in the case that the first photoresist pattern intersects with the second photoresist pattern, W1 and W2 are both less than a first target value, and L1 and L2 are both less than a second target value; in the case that at least one of W1 and W2 is greater than or equal to the first target value, or at least one of L1 and L2 is greater than or equal to the second target value, the distance between the first photoresist pattern and the second photoresist pattern is greater than a target distance value, and the target distance value is related to the ratio of the second target value to the first target value. At least the residue in the photoresist etching process can be effectively reduced, and damage to the substrate caused by the residue can be avoided.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor layout structure and a method for preparing a double gate oxide layer. Background Technology

[0002] With the rapid development of semiconductor fabrication technology, the market has placed higher demands on the integration and performance of semiconductor structures. In order to enable chips to have both high performance and high reliability, it is necessary to fabricate two oxide layers of different thicknesses on the same chip.

[0003] Traditional techniques can cause substrate damage during the fabrication of oxide layers of varying thicknesses, resulting in uneven contact surfaces between silicon oxide and the silicon substrate, which in turn degrades chip performance. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor layout structure and a method for preparing a dual-gate oxide layer to address the problems mentioned in the background technology. This method can at least effectively reduce the residues in the photoresist etching process and avoid uneven contact between the oxide layer and the silicon substrate caused by damage to the substrate due to residues or damage to the substrate due to residue removal.

[0005] To achieve the above and other objectives, according to various embodiments of the present disclosure, one aspect of the present disclosure provides a semiconductor layout structure, including a first photoresist pattern and a second photoresist pattern; the first photoresist pattern extends along a first direction, with a dimension L1 along the first direction and a dimension W1 along a second direction; the second photoresist pattern extends along a second direction, with a dimension W2 along the first direction and a dimension L2 along the second direction; wherein, when the first photoresist pattern and the second photoresist pattern intersect, W1 and W2 are both less than a first target value, and L1 and L2 are both less than a second target value; when at least one of W1 and W2 is greater than or equal to the first target value, or at least one of L1 and L2 is greater than or equal to the second target value, the spacing between the first photoresist pattern and the second photoresist pattern is greater than a target spacing value, and the target spacing value is related to the ratio of the second target value to the first target value.

[0006] In the above embodiments, when the first photoresist pattern and the second photoresist pattern intersect, W1 and W2 are both set to be less than the first target value, and L1 and L2 are both set to be less than the second target value. When at least one of W1 and W2 is greater than or equal to the first target value, or at least one of L1 and L2 is greater than or equal to the second target value, the spacing between the first and second photoresist patterns is set to be greater than the target spacing value, and the target spacing value is related to the ratio of the second target value to the first target value. This avoids the intersecting first and second photoresist patterns forming an intercepting dam; or the first and / or second photoresist patterns being too large, causing an interception effect, resulting in the generation of more easily corroded residues on the substrate surface during the wet removal of the substrate surface oxide layer based on the first and second photoresist patterns, thereby avoiding damage to the substrate due to residues, or damage to the substrate due to residue removal, leading to uneven contact surfaces between the oxide layer and the silicon substrate.

[0007] In some embodiments, the semiconductor layout structure further includes a third photoresist pattern and a fourth photoresist pattern; the third photoresist pattern extends along a first direction, with a dimension of L3 along the first direction and a dimension of W3 along a second direction; the first photoresist pattern and the third photoresist pattern are spaced apart along the second direction; the fourth photoresist pattern extends along the second direction, with a dimension of W4 along the first direction and a dimension of L4 along the second direction; the second photoresist pattern and the fourth photoresist pattern are spaced apart along the first direction; wherein, when the third photoresist pattern and the fourth photoresist pattern intersect, W3 and W4 are both less than a first target value, and L3 and L4 are both less than a second target value; when at least one of W3 and W4 is greater than or equal to the first target value, or at least one of L3 and L4 is greater than or equal to the second target value, the spacing between the third photoresist pattern and the fourth photoresist pattern is greater than a target spacing value, and the target spacing value is related to the ratio of the second target value to the first target value.

[0008] In the above embodiments, when the third and fourth photoresist patterns intersect, W3 and W4 are both set to be less than the first target value, and L3 and L4 are both set to be less than the second target value. When at least one of W3 and W4 is greater than or equal to the first target value, or at least one of L3 and L4 is greater than or equal to the second target value, the spacing between the third and fourth photoresist patterns is set to be greater than the target spacing value, and the target spacing value is related to the ratio of the second target value to the first target value. This avoids the intersecting third and fourth photoresist patterns forming an interception dam, or the third and / or fourth photoresist patterns being too large and causing an interception effect, which would result in the generation of more easily corroded residues on the substrate surface during the wet removal of the substrate oxide layer based on the third and fourth photoresist patterns. This avoids damage to the substrate due to residues, or damage to the substrate due to residue removal, resulting in an uneven contact surface between the oxide layer and the silicon substrate.

[0009] In some embodiments, when the first photoresist pattern and the fourth photoresist pattern intersect, W1 and W4 are both less than the first target value, and L1 and L4 are both less than the second target value; this avoids the first photoresist pattern and the fourth photoresist pattern forming an intercepting dam; when at least one of W1 and W4 is greater than or equal to the first target value, or at least one of L1 and L4 is greater than or equal to the second target value, the spacing between the first photoresist pattern and the fourth photoresist pattern is greater than the target spacing value, to avoid the first photoresist pattern and / or the fourth photoresist pattern being too large, which would result in the generation of more easily corroded residues on the substrate surface during the wet removal of the oxide layer based on the first photoresist pattern and the fourth photoresist pattern, thereby avoiding damage to the substrate due to residues, or damage to the substrate due to the removal of residues, resulting in an uneven contact surface between the oxide layer and the silicon substrate.

[0010] In some embodiments, when the second and third photoresist patterns intersect, W2 and W3 are both less than the first target value, and L2 and L3 are both less than the second target value, to avoid the second and third photoresist patterns forming an intercepting dam. When at least one of W2 and W3 is greater than or equal to the first target value, or at least one of L2 and L3 is greater than or equal to the second target value, the spacing between the second and third photoresist patterns is greater than the target spacing value, to avoid the second and / or third photoresist patterns being too large, which would result in the generation of more easily corroded residues on the substrate surface during the wet removal of the substrate oxide layer based on the second and third photoresist patterns, thereby avoiding damage to the substrate due to residues or damage to the substrate due to residue removal, leading to uneven contact surfaces between the oxide layer and the silicon substrate.

[0011] Some embodiments of this disclosure also disclose a method for preparing a dual-gate oxide layer, including:

[0012] A front layer is provided, the top surface of which includes a first oxide layer;

[0013] A first photoresist pattern and a second photoresist pattern are formed on the top surface of a first oxide layer. The first photoresist pattern extends along a first direction, with a dimension of L1 along the first direction and a dimension of W1 along a second direction. The second photoresist pattern extends along a second direction, with a dimension of W2 along the first direction and a dimension of L2 along the second direction. Wherein, when the first photoresist pattern and the second photoresist pattern intersect, both W1 and W2 are less than a first target value, and both L1 and L2 are less than a second target value. Where at least one of W1 and W2 is greater than or equal to the first target value, or at least one of L1 and L2 is greater than or equal to the second target value, the distance between the first photoresist pattern and the second photoresist pattern is greater than a target distance value, and the target distance value is related to the ratio of the second target value to the first target value.

[0014] Based on the first photoresist pattern and the second photoresist pattern, the first oxide layer is wet-etched to expose the top surface of the substrate in the target area;

[0015] After forming a second oxide layer on the top surface of the substrate in the target area, the first photoresist pattern and the second photoresist pattern are removed; the thickness of the first oxide layer is greater than the thickness of the second oxide layer.

[0016] In the above embodiments, a first photoresist pattern and a second photoresist pattern are formed on the top surface of the first oxide layer on the top surface of the front layer; the first photoresist pattern extends along a first direction, with a dimension of L1 along the first direction and a dimension of W1 along a second direction; the second photoresist pattern extends along a second direction, with a dimension of W2 along the first direction and a dimension of L2 along the second direction; when the first photoresist pattern and the second photoresist pattern intersect, W1 and W2 are both set to be less than a first target value, and L1 and L2 are both set to be less than a second target value; when at least one of W1 and W2 is greater than or equal to the first target value, or at least one of L1 and L2 is greater than or equal to the second target value, the spacing between the first photoresist pattern and the second photoresist pattern is set to be greater than a target spacing value, and the target spacing value is related to the ratio of the second target value to the first target value. To avoid the first and second photoresist patterns intersecting to form a barrier; or to prevent the first and / or second photoresist patterns from being too large, causing a barrier effect, resulting in the generation of more residues on the top surface of the substrate in the target area during the wet removal of the first oxide layer based on the first and second photoresist patterns, which are easy to corrode the substrate, thereby avoiding damage to the substrate due to residues, or damage to the substrate due to the removal of residues, resulting in an uneven contact surface between the oxide layer and the silicon substrate.

[0017] In some embodiments, during the formation of the first photoresist pattern and the second photoresist pattern, a third photoresist pattern is formed. The third photoresist pattern extends along a first direction, with a dimension of L3 along the first direction and a dimension of W3 along a second direction. The first photoresist pattern and the third photoresist pattern are spaced apart along the second direction. Wherein, when the second photoresist pattern and the third photoresist pattern intersect, both W2 and W3 are less than a first target value, and both L2 and L3 are less than a second target value. Wherein, if at least one of W2 and W3 is greater than or equal to the first target value, or if at least one of L2 and L3 is greater than or equal to the second target value, the distance between the second photoresist pattern and the third photoresist pattern is greater than a target distance value, and the target distance value is related to the ratio of the second target value to the first target value.

[0018] In some embodiments, during the formation of the first photoresist pattern and the second photoresist pattern, a fourth photoresist pattern is formed. The fourth photoresist pattern extends along a second direction, with a dimension of W4 along the first direction and a dimension of L4 along the second direction. The second photoresist pattern and the fourth photoresist pattern are spaced apart along the first direction. Wherein, when the first photoresist pattern and the fourth photoresist pattern intersect, both W1 and W4 are less than a first target value, and both L1 and L4 are less than a second target value. Where at least one of W1 and W4 is greater than or equal to the first target value, or at least one of L1 and L4 is greater than or equal to the second target value, the distance between the first photoresist pattern and the fourth photoresist pattern is greater than a target distance value.

[0019] In some embodiments, when the third photoresist pattern and the fourth photoresist pattern intersect, W3 and W4 are both less than the first target value, and L3 and L4 are both less than the second target value; when at least one of W3 and W4 is greater than or equal to the first target value, or at least one of L3 and L4 is greater than or equal to the second target value, the spacing between the third photoresist pattern and the fourth photoresist pattern is greater than the target spacing value.

[0020] In some embodiments, the target area includes an array region.

[0021] In some embodiments, an ultraviolet laser is used to directly break the molecular bonds of the photoresist, physically removing the first and second photoresist patterns. This non-contact physical removal of the first and second photoresist patterns avoids damage to the substrate.

[0022] The above-described embodiments can produce at least the following unexpected technical effects:

[0023] When the first and second photoresist patterns intersect, W1 and W2 are both set to be less than the first target value, and L1 and L2 are both set to be less than the second target value. When at least one of W1 and W2 is greater than or equal to the first target value, or at least one of L1 and L2 is greater than or equal to the second target value, the spacing between the first and second photoresist patterns is set to be greater than the target spacing value, which is related to the ratio of the second target value to the first target value. This avoids the intersecting first and second photoresist patterns forming a barrier; or the first and / or second photoresist patterns being too large, causing a barrier effect. This prevents the formation of excessive residues on the substrate surface during the wet removal of the oxide layer based on the first and second photoresist patterns, which could easily corrode the substrate. This avoids damage to the substrate due to residues, or damage to the substrate during residue removal, resulting in an uneven contact surface between the oxide layer and the silicon substrate. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a magnified schematic diagram of a local area after photolithography development and removal of a thick oxide layer in a thin oxide region, obtained by using fluorescence microscopy or ion sensing imaging techniques in one embodiment.

[0026] Figure 2 for Figure 1 A magnified schematic diagram of a local area obtained by using fluorescence microscopy or ion sensing imaging techniques after removing residues from the corresponding semiconductor region using an acid washing process.

[0027] Figure 3 This is a partial top view schematic diagram of a thin oxide layer removed from a thin oxide region in one embodiment;

[0028] Figure 4 This is a partial top view schematic diagram of another embodiment after the thick oxide layer in the thin oxygen region has been removed;

[0029] Figure 5 This is a schematic flowchart of a method for preparing a dual-gate oxide layer according to an embodiment of the present disclosure;

[0030] Figure 6 This is a top view schematic diagram of a semiconductor layout structure provided in one embodiment of the present disclosure;

[0031] Figure 7 This is a top view schematic diagram of a semiconductor layout structure provided in another embodiment of the present disclosure.

[0032] Explanation of reference numerals in the attached figures:

[0033] PR_m, Residual photoresist; T, Residue; A, Depression; PR1, Photoresist pillar; PR_C, Photoresist residue; PR11, First photoresist pattern; PR12, Second photoresist pattern; PR13, Third photoresist pattern; PR14, Fourth photoresist pattern. Detailed Implementation

[0034] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0036] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0037] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0038] Furthermore, the terms “first”, “second”, etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0039] Traditional transistors have only one gate oxide layer, while dual gate oxide (DGO) is like putting a double layer of protective clothing on the transistor. DGO uses precise control of the oxidation process to create two oxide layers of different thicknesses on the same chip. The thinner oxide layer (e.g., 2nm-3nm thick) is used for high-speed core circuitry, while the thicker oxide layer (e.g., 5nm-7nm thick) is used for high-voltage interface circuitry. This design allows the chip to possess both high performance and high reliability.

[0040] However, after preparing the thick oxide layer, it is necessary to remove the thick oxide layer in the thin oxide regions to grow a thin oxide layer. Using fluorescence microscopy or ion-sensing imaging techniques, a magnified schematic diagram of the area after photolithography development and removal of the thick oxide layer in the thin oxide regions is obtained, as shown below. Figure 1 As shown, residue T exists on the substrate surrounding the remaining photoresist PR_m. If the residue T is removed using an acid washing process, a magnified local schematic diagram obtained using fluorescence microscopy or ion-sensing imaging techniques is shown below. Figure 2As shown, a depression A exists on the substrate surrounding the remaining photoresist PR_m. Depression A can cause interface damage between the subsequently formed thin oxide layer and the substrate, which may eventually transform into an electrical interface trap, directly manifesting as defects such as increased dark current, increased white spots, or deteriorated noise.

[0041] Further observation of the DGO process revealed that after the thick oxide layer is prepared, the photoresist needs to be developed to remove the thick oxide layer in the thin oxide regions in order to grow a thin oxide layer. It was found that... Figure 3 The morphology of the photoresist pillar PR1 shown in the diagram indicates that a large amount of residual photoresist PR_C exists on the substrate surrounding the inner side of the photoresist pillar PR1; and it was found that... Figure 4 The diagram illustrates the morphology of photoresist pillar PR1. A significant amount of residual photoresist PR_C remains on the substrate surrounding the inner side of PR1. Removing this residual PR_C using an acid washing process inevitably damages the substrate surface in the thin oxide region, leading to surface depressions. Therefore, it is crucial to minimize the formation of residual photoresist PR_C on the substrate after photoresist development.

[0042] To address the aforementioned and other issues, this application aims to provide a semiconductor layout structure and a method for fabricating a dual-gate oxide layer, which can at least effectively reduce residues during photoresist etching, and avoid uneven contact between the oxide layer and the silicon substrate due to damage to the substrate caused by residues or damage to the substrate caused by removing residues.

[0043] Please refer to Figure 5 In some embodiments, a method for preparing a dual-gate oxide layer is provided, comprising:

[0044] Step S10: Provide a front layer, the top surface of which includes a first oxide layer;

[0045] Step S20: A first photoresist pattern and a second photoresist pattern are formed on the top surface of the first oxide layer; the first photoresist pattern extends along a first direction, with a dimension of L1 along the first direction and a dimension of W1 along a second direction; the second photoresist pattern extends along a second direction, with a dimension of W2 along the first direction and a dimension of L2 along the second direction; wherein, when the first photoresist pattern and the second photoresist pattern intersect, W1 and W2 are both less than a first target value, and L1 and L2 are both less than a second target value; when at least one of W1 and W2 is greater than or equal to the first target value, or at least one of L1 and L2 is greater than or equal to the second target value, the distance between the first photoresist pattern and the second photoresist pattern is greater than a target distance value, and the target distance value is related to the ratio of the second target value to the first target value;

[0046] Step S30: Wet etching of the first oxide layer based on the first photoresist pattern and the second photoresist pattern to expose the top surface of the substrate in the target area;

[0047] Step S40: After forming a second oxide layer on the top surface of the substrate in the target area, remove the first photoresist pattern and the second photoresist pattern; the thickness of the first oxide layer is greater than the thickness of the second oxide layer.

[0048] For example, please continue to refer to Figures 5-6 A first photoresist pattern PR11 and a second photoresist pattern PR12 are formed on the top surface of the first oxide layer on the top surface of the front layer. The first photoresist pattern PR11 extends along a first direction (e.g., the ox direction), with a dimension of L1 along the first direction and a dimension of W1 along a second direction (e.g., the oy direction). The second photoresist pattern PR12 extends along a second direction, with a dimension of W2 along the first direction and a dimension of L2 along the second direction. When the first photoresist pattern PR11 and the second photoresist pattern PR12 intersect, W1 and W2 are both set to be less than a first target value, and L1 and L2 are both set to be less than a second target value.

[0049] In some embodiments, during the formation of the first photoresist pattern PR11 and the second photoresist pattern PR12, a third photoresist pattern PR13 is formed. The third photoresist pattern PR13 extends along a first direction (e.g., the ox direction), with a dimension of L3 along the first direction and a dimension of W3 along a second direction (e.g., the oy direction). The first photoresist pattern PR11 and the third photoresist pattern PR13 are spaced apart along the second direction. Wherein, when the second photoresist pattern PR12 and the third photoresist pattern PR13 intersect, W2 and W3 are both smaller than the first target value, and L2 and L3 are both smaller than the second target value.

[0050] In some embodiments, during the formation of the first photoresist pattern PR11 and the second photoresist pattern PR12, a third photoresist pattern PR13 is formed. The third photoresist pattern PR13 extends along a first direction (e.g., the ox direction), with a dimension of L3 along the first direction and a dimension of W3 along a second direction (e.g., the oy direction). The first photoresist pattern PR11 and the third photoresist pattern PR13 are spaced apart along the second direction. If at least one of W2 and W3 is greater than or equal to a first target value, or at least one of L2 and L3 is greater than or equal to a second target value, the spacing between the second photoresist pattern PR12 and the third photoresist pattern PR13 is greater than a target spacing value, and the target spacing value is related to the ratio of the second target value to the first target value.

[0051] In some embodiments, during the formation of the first photoresist pattern PR11 and the second photoresist pattern PR12, a fourth photoresist pattern PR14 is formed. The fourth photoresist pattern PR14 extends along a second direction, has a dimension of W4 along the first direction, and a dimension of L4 along the second direction. The second photoresist pattern PR12 and the fourth photoresist pattern PR14 are spaced apart along the first direction. Wherein, when the first photoresist pattern PR11 and the fourth photoresist pattern PR14 intersect, W1 and W4 are both less than a first target value, and L1 and L4 are both less than a second target value.

[0052] In some embodiments, during the formation of the first photoresist pattern PR11 and the second photoresist pattern PR12, a fourth photoresist pattern PR14 is formed. The fourth photoresist pattern PR14 extends along a second direction, has a dimension of W4 along the first direction, and a dimension of L4 along the second direction. The second photoresist pattern PR12 and the fourth photoresist pattern PR14 are spaced apart along the first direction. If at least one of W1 and W4 is greater than or equal to a first target value, or at least one of L1 and L4 is greater than or equal to a second target value, the spacing between the first photoresist pattern PR11 and the fourth photoresist pattern PR14 is greater than a target spacing value.

[0053] In some embodiments, during the formation of the first photoresist pattern PR11 and the second photoresist pattern PR12, a third photoresist pattern PR13 and a fourth photoresist pattern PR14 are formed. The third photoresist pattern PR13 extends along a first direction (e.g., the ox direction), with a dimension of L3 along the first direction and a dimension of W3 along a second direction (e.g., the oy direction). The fourth photoresist pattern PR14 extends along a second direction, with a dimension of W4 along the first direction and a dimension of L4 along the second direction. When the third photoresist pattern PR13 and the fourth photoresist pattern PR14 intersect, W3 and W4 are both less than a first target value, and L3 and L4 are both less than a second target value.

[0054] Please refer to Figure 7 In some embodiments, during the formation of the first photoresist pattern PR11 and the second photoresist pattern PR12, a third photoresist pattern PR13 and a fourth photoresist pattern PR14 are formed. The third photoresist pattern PR13 extends along a first direction (e.g., the ox direction), with a dimension of L3 along the first direction and a dimension of W3 along a second direction (e.g., the oy direction). The fourth photoresist pattern PR14 extends along a second direction, with a dimension of W4 along the first direction and a dimension of L4 along the second direction. If at least one of W3 and W4 is greater than or equal to a first target value, or at least one of L3 and L4 is greater than or equal to a second target value, the spacing between the third photoresist pattern PR13 and the fourth photoresist pattern PR14 is greater than a target spacing value.

[0055] In some embodiments, the target region includes an array region. The top surface of the front layer includes a first oxide layer, on which a first photoresist pattern and a second photoresist pattern are formed. The first photoresist pattern extends along a first direction, with a dimension L1 along the first direction and a dimension W1 along a second direction. The second photoresist pattern extends along a second direction, with a dimension W2 along the first direction and a dimension L2 along the second direction. Wherein, when the first and second photoresist patterns intersect, W1 and W2 are both less than a first target value, and L1 and L2 are both less than a second target value; at least one of W1 and W2 is greater than or equal to the first target value. When the target value, or at least one of L1 and L2, is greater than or equal to the second target value, the spacing between the first and second photoresist patterns is greater than the target spacing value, which is related to the ratio of the second target value to the first target value. A first oxide layer is wet-etched based on the first and second photoresist patterns to expose the top surface of the substrate in the array region. After forming the second oxide layer on the top surface of the substrate in the array region, ultraviolet lasers are used to directly break the molecular bonds of the photoresist, physically removing the first and second photoresist patterns. The thickness of the first oxide layer is greater than the thickness of the second oxide layer. For example, the thickness of the first oxide layer can be 5nm-7nm, and the thickness of the second oxide layer can be 2nm-3nm. The second oxide layer in the array region is used for high-speed core circuits, and the first oxide layer in the peripheral region is used for high-voltage interface circuits, allowing the chip to simultaneously possess high performance and high reliability. Furthermore, non-contact substrate-based physical removal of the first and second photoresist patterns avoids damage to the substrate.

[0056] For example, the first target value is 195μm-205μm. For instance, the first target value can be 195μm, 200μm, or 205μm, etc.

[0057] For example, the second target value is 1195μm-1205μm. For instance, the second target value can be 1195μm, 1198μm, 1200μm, 1202μm or 1205μm, etc.

[0058] For example, the target spacing value is 5μm-7μm, such as 5μm, 6μm or 7μm.

[0059] For example, the target spacing value = (second target value ÷ first target value) × 1, where the target spacing value has the same unit as either the first or second target value. The first target value can be set to 200 μm, the second target value to 1200 μm, and the target spacing value to 6 μm.

[0060] Please refer to Figure 6In some embodiments, a semiconductor layout structure is provided, including a first photoresist pattern PR11 and a second photoresist pattern PR12; the first photoresist pattern PR11 extends along a first direction (e.g., the ox direction), with a dimension of L1 along the first direction and a dimension of W1 along a second direction (e.g., the oy direction); the second photoresist pattern PR12 extends along a second direction, with a dimension of W2 along the first direction and a dimension of L2 along the second direction; wherein, when the first photoresist pattern PR11 and the second photoresist pattern PR12 intersect, W1 and W2 are both less than a first target value, and L1 and L2 are both less than a second target value; when at least one of W1 and W2 is greater than or equal to the first target value, or at least one of L1 and L2 is greater than or equal to the second target value, the spacing between the first photoresist pattern PR11 and the second photoresist pattern PR12 is greater than a target spacing value, and the target spacing value is related to the ratio of the second target value to the first target value.

[0061] For example, please continue to refer to Figure 6 When the first photoresist pattern PR11 and the second photoresist pattern PR12 intersect, W1 and W2 are both set to be less than the first target value, and L1 and L2 are both set to be less than the second target value. When at least one of W1 and W2 is greater than or equal to the first target value, or at least one of L1 and L2 is greater than or equal to the second target value, the spacing between the first photoresist pattern PR11 and the second photoresist pattern PR12 is set to be greater than the target spacing value, and the target spacing value is related to the ratio of the second target value to the first target value. This avoids the intersecting first photoresist pattern PR11 and the second photoresist pattern PR12 forming an intercepting dam; or the size of the first photoresist pattern PR11 and / or the second photoresist pattern PR12 being too large, resulting in an intercepting effect. This prevents the formation of more easily corroded residues on the substrate surface during the wet removal of the substrate oxide layer based on the first photoresist pattern PR11 and the second photoresist pattern PR12, thereby avoiding damage to the substrate due to residues or damage to the substrate during residue removal, resulting in an uneven contact surface between the oxide layer and the silicon substrate.

[0062] Please refer to Figure 7In some embodiments, the semiconductor layout structure further includes a third photoresist pattern PR13 and a fourth photoresist pattern PR14; the third photoresist pattern PR13 extends along a first direction (e.g., the ox direction), with a dimension of L3 along the first direction and a dimension of W3 along a second direction (e.g., the oy direction); the second photoresist pattern PR12 and the third photoresist pattern PR13 are spaced apart along the second direction; the fourth photoresist pattern PR14 extends along the second direction, with a dimension of W4 along the first direction and a dimension of L4 along the second direction; the first photoresist pattern PR13... 1. The fourth photoresist pattern PR14 is spaced along the first direction; wherein, when the first photoresist pattern PR11 intersects with the fourth photoresist pattern PR14, W1 and W4 are both less than the first target value, and L1 and L4 are both less than the second target value; when at least one of W1 and W4 is greater than or equal to the first target value, or at least one of L1 and L4 is greater than or equal to the second target value, the distance d between the first photoresist pattern PR11 and the fourth photoresist pattern PR14 is greater than the target distance value, and the target distance value is related to the ratio of the second target value to the first target value.

[0063] In the above embodiments, when the first photoresist pattern PR11 and the fourth photoresist pattern PR14 intersect, W1 and W4 are both set to be less than the first target value, and L1 and L4 are both set to be less than the second target value. When at least one of W1 and W4 is greater than or equal to the first target value, or at least one of L1 and L4 is greater than or equal to the second target value, the distance between the first photoresist pattern PR11 and the fourth photoresist pattern PR14 is set to be greater than the target distance value, and the target distance value is related to the ratio of the second target value to the first target value. This avoids the intersecting first photoresist pattern PR11 and the fourth photoresist pattern PR14 forming an interception dam, or the first photoresist pattern PR11 and / or the fourth photoresist pattern PR14 being too large and causing an interception effect, resulting in the generation of more residues that are easy to corrode the substrate on the substrate surface during the wet removal of the oxide layer based on the first photoresist pattern PR11 and the fourth photoresist pattern PR14. This avoids damage to the substrate due to residues, or damage to the substrate due to the removal of residues, resulting in an uneven contact surface between the oxide layer and the silicon substrate.

[0064] In some embodiments, when the second photoresist pattern PR12 and the third photoresist pattern PR13 intersect, W2 and W3 are both less than the first target value, and L2 and L3 are both less than the second target value, to avoid the second photoresist pattern PR12 and the third photoresist pattern PR13 forming an intercepting dam; when at least one of W2 and W3 is greater than or equal to the first target value, or at least one of L2 and L3 is greater than or equal to the second target value, the spacing between the second photoresist pattern PR12 and the third photoresist pattern PR13 is greater than the target spacing value, to avoid the second photoresist pattern PR12 and / or the third photoresist pattern PR13 being too large, resulting in the generation of more residues that are easy to corrode the substrate on the substrate surface during the wet removal of the oxide layer based on the second photoresist pattern PR12 and the third photoresist pattern PR13, thereby avoiding damage to the substrate due to residues, or damage to the substrate due to the removal of residues, resulting in an uneven contact surface between the oxide layer and the silicon substrate.

[0065] In some embodiments, when the third photoresist pattern PR13 and the fourth photoresist pattern PR14 intersect, W3 and W4 are both less than the first target value, and L3 and L4 are both less than the second target value. When at least one of W3 and W4 is greater than or equal to the first target value, or at least one of L3 and L4 is greater than or equal to the second target value, the spacing between the third photoresist pattern PR13 and the fourth photoresist pattern PR14 is greater than the target spacing value. This avoids the intersecting third photoresist pattern PR13 and the fourth photoresist pattern PR14 forming a barrier, or the third photoresist pattern PR13 and / or the fourth photoresist pattern PR14 being too large and causing a barrier effect, which would result in the generation of more easily corroded residues on the substrate surface during the wet removal of the substrate oxide layer based on the third photoresist pattern PR13 and the fourth photoresist pattern PR14. This avoids damage to the substrate due to residues, or damage to the substrate due to residue removal, leading to an uneven contact surface between the oxide layer and the silicon substrate.

[0066] The above-described embodiments can produce at least the following unexpected technical effects:

[0067] When the first photoresist pattern PR11 intersects with the second photoresist pattern PR12, W1 and W2 are both set to be less than the first target value, and L1 and L2 are both set to be less than the second target value. When at least one of W1 and W2 is greater than or equal to the first target value, or at least one of L1 and L2 is greater than or equal to the second target value, the spacing between the first photoresist pattern PR11 and the second photoresist pattern PR12 is set to be greater than the target spacing value, which is related to the ratio of the second target value to the first target value. This avoids the intersecting first photoresist pattern PR11 and second photoresist pattern PR12 forming a barrier; or the size of the first photoresist pattern PR11 and / or the second photoresist pattern PR12 being too large, causing a barrier effect. This prevents the formation of more easily corroded residues on the substrate surface during the wet removal of the substrate oxide layer based on the first photoresist pattern PR11 and the second photoresist pattern PR12, thus avoiding damage to the substrate due to residues or damage to the substrate during residue removal, resulting in an uneven contact surface between the oxide layer and the silicon substrate.

[0068] It should be understood that, although Figure 5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 5 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0069] In some embodiments, a computer device is provided, including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of any of the dual-gate oxide preparation methods in the embodiments of this disclosure.

[0070] In some embodiments, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the dual-gate oxide layer preparation methods in the embodiments of this disclosure.

[0071] In some embodiments, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of any of the dual-gate oxide layer preparation methods described above.

[0072] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this disclosure can include non-volatile, volatile, or combinations thereof. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), or graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this disclosure can include relational databases, non-relational databases, or combinations thereof. Non-relational databases can include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this disclosure can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, or quantum computing-based data processing logic devices, etc., and are not limited to these.

[0073] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0074] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0075] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The embodiments described above are merely illustrative of several implementation methods of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these modifications and improvements all fall within the scope of protection of this disclosure.

Claims

1. A semiconductor layout structure, characterized in that, include: A first photoresist pattern extends along a first direction, with a dimension of L1 along the first direction and a dimension of W1 along the second direction; The second photoresist pattern extends along the second direction, with a dimension of W2 along the first direction and a dimension of L2 along the second direction; Wherein, when the first photoresist pattern and the second photoresist pattern intersect, and the intersection point is the endpoint of the first photoresist pattern and the endpoint of the second photoresist pattern, W1 and W2 are both less than the first target value, and L1 and L2 are both less than the second target value. If at least one of W1 and W2 is greater than or equal to the first target value, or at least one of L1 and L2 is greater than or equal to the second target value, the spacing between the first photoresist pattern and the second photoresist pattern is greater than the target spacing value, which is related to the ratio of the second target value to the first target value.

2. The semiconductor layout structure according to claim 1, characterized in that, Also includes: The third photoresist pattern extends along the first direction, with a dimension of L3 along the first direction and a dimension of W3 along the second direction; The first photoresist pattern and the third photoresist pattern are spaced apart along the second direction; The fourth photoresist pattern extends along the second direction, with a dimension of W4 along the first direction and a dimension of L4 along the second direction; The second photoresist pattern and the fourth photoresist pattern are spaced apart along the first direction; Wherein, when the third photoresist pattern and the fourth photoresist pattern intersect, and the intersection point is the endpoint of the third photoresist pattern and the endpoint of the fourth photoresist pattern, W3 and W4 are both less than the first target value, and L3 and L4 are both less than the second target value. If at least one of W3 and W4 is greater than or equal to the first target value, or if at least one of L3 and L4 is greater than or equal to the second target value, the spacing between the third photoresist pattern and the fourth photoresist pattern is greater than the target spacing value, which is related to the ratio of the second target value to the first target value.

3. The semiconductor layout structure according to claim 2, characterized in that, When the first photoresist pattern intersects with the fourth photoresist pattern, and the intersection point is the endpoint of the first photoresist pattern and the endpoint of the fourth photoresist pattern, W1 and W4 are both less than the first target value, and L1 and L4 are both less than the second target value. If at least one of W1 and W4 is greater than or equal to the first target value, or if at least one of L1 and L4 is greater than or equal to the second target value, the spacing between the first photoresist pattern and the fourth photoresist pattern is greater than the target spacing value.

4. The semiconductor layout structure according to claim 2, characterized in that, When the second photoresist pattern intersects with the third photoresist pattern, and the intersection point is the endpoint of the second photoresist pattern and the endpoint of the third photoresist pattern, W2 and W3 are both less than the first target value, and L2 and L3 are both less than the second target value. If at least one of W2 and W3 is greater than or equal to the first target value, or if at least one of L2 and L3 is greater than or equal to the second target value, the spacing between the second photoresist pattern and the third photoresist pattern is greater than the target spacing value.

5. A method for preparing a dual-gate oxide layer, characterized in that, include: A front layer is provided, the top surface of which includes a first oxide layer; A first photoresist pattern and a second photoresist pattern are formed on the top surface of the first oxide layer; The first photoresist pattern extends along a first direction, with a dimension of L1 along the first direction and a dimension of W1 along the second direction; The second photoresist pattern extends along the second direction, with a dimension of W2 along the first direction and a dimension of L2 along the second direction; wherein, when the first photoresist pattern and the second photoresist pattern intersect, and the intersection point is the endpoint of the first photoresist pattern and the endpoint of the second photoresist pattern, W1 and W2 are both less than a first target value, and L1 and L2 are both less than a second target value; when at least one of W1 and W2 is greater than or equal to the first target value, or at least one of L1 and L2 is greater than or equal to the second target value, the distance between the first photoresist pattern and the second photoresist pattern is greater than a target distance value, the target distance value being related to the ratio of the second target value to the first target value; Based on the first photoresist pattern and the second photoresist pattern, the first oxide layer is wet-etched to expose the top surface of the substrate in the target area; After forming a second oxide layer on the top surface of the substrate in the target region, the first photoresist pattern and the second photoresist pattern are removed; the thickness of the first oxide layer is greater than the thickness of the second oxide layer.

6. The method for preparing a dual-gate oxide layer according to claim 5, characterized in that, During the formation of the first photoresist pattern and the second photoresist pattern, a third photoresist pattern is formed. The third photoresist pattern extends along the first direction, with a dimension of L3 along the first direction and a dimension of W3 along the second direction. The first photoresist pattern and the third photoresist pattern are spaced apart along the second direction; wherein, when the second photoresist pattern and the third photoresist pattern intersect, and the intersection point is the endpoint of the second photoresist pattern and the endpoint of the third photoresist pattern, W2 and W3 are both less than the first target value, and L2 and L3 are both less than the second target value; when at least one of W2 and W3 is greater than or equal to the first target value, or at least one of L2 and L3 is greater than or equal to the second target value, the distance between the second photoresist pattern and the third photoresist pattern is greater than the target distance value, and the target distance value is related to the ratio of the second target value to the first target value.

7. The method for preparing a dual-gate oxide layer according to claim 6, characterized in that, During the formation of the first photoresist pattern and the second photoresist pattern, a fourth photoresist pattern is formed. The fourth photoresist pattern extends along the second direction, with a dimension of W4 along the first direction and a dimension of L4 along the second direction. The second photoresist pattern and the fourth photoresist pattern are spaced apart along the first direction; wherein, when the first photoresist pattern and the fourth photoresist pattern intersect, and the intersection point is the endpoint of the first photoresist pattern and the endpoint of the fourth photoresist pattern, W1 and W4 are both less than the first target value, and L1 and L4 are both less than the second target value. If at least one of W1 and W4 is greater than or equal to the first target value, or if at least one of L1 and L4 is greater than or equal to the second target value, the spacing between the first photoresist pattern and the fourth photoresist pattern is greater than the target spacing value.

8. The method for preparing a dual-gate oxide layer according to claim 7, characterized in that, When the third photoresist pattern and the fourth photoresist pattern intersect, and the intersection point is the endpoint of the third photoresist pattern and the endpoint of the fourth photoresist pattern, W3 and W4 are both less than the first target value, and L3 and L4 are both less than the second target value. If at least one of W3 and W4 is greater than or equal to the first target value, or if at least one of L3 and L4 is greater than or equal to the second target value, the spacing between the third photoresist pattern and the fourth photoresist pattern is greater than the target spacing value.

9. The method for preparing a dual-gate oxide layer according to any one of claims 5-8, characterized in that, The target area includes the array region.

10. The method for preparing a dual-gate oxide layer according to any one of claims 5-8, characterized in that, Ultraviolet laser is used to directly break the molecular bonds of the photoresist, physically removing the first and second photoresist patterns.

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