Three-level bidirectional dc converter control method

Abstract

This application provides a control method for a three-level bidirectional DC-DC converter. The method includes: acquiring an operating command set and electrical sample values; combining and judging the operating command set to obtain the current operating state; extracting the voltage loop reference bias, voltage loop proportional-integral (PI) control parameters, and current loop PI control parameters; obtaining a current loop reference value through PI control based on the current operating state, network command voltage, voltage loop reference bias, bus voltage, and battery voltage; obtaining a base duty cycle and voltage equalization compensation amount based on the current loop PI control parameters, current loop reference value, inductor current, and upper and lower bus voltage division; superimposing the base duty cycle and voltage equalization compensation amount to obtain the final duty cycle; and generating a gate trigger signal based on the final duty cycle. This method is used to adaptively adjust control parameters according to the operating state to reduce bus voltage fluctuations and improve energy conversion stability.

Description

Technical Field

[0001] This application relates to the field of electronic control, and in particular to a control method for a three-level bidirectional DC-DC converter. Background Technology

[0002] The three-level bidirectional DC-DC converter is a key device for energy conversion and dispatching in high-power hybrid locomotives. This converter connects the power battery to the intermediate DC bus and needs to frequently switch between traction discharge and braking charging energy flows, while maintaining stable bus voltage and ensuring dynamic balance of the midpoint potential in the three-level topology.

[0003] In existing technologies, three-level bidirectional DC-DC converters typically employ a dual closed-loop control structure with a voltage loop and a current loop connected in series. The control error is calculated by collecting bus voltage and inductor current, and after proportional-integral regulation, the drive duty cycle of the switching transistors is generated, thereby controlling the converter's output power. To address the midpoint potential drift problem unique to three-level topologies, an independent midpoint potential balancing control loop is usually added to the dual closed-loop control. The operating condition identification process is generally based on changes in a single operating parameter, and fixed control parameters are used to complete the adjustment and control across the entire operating range.

[0004] Existing technologies cannot dynamically adjust control parameters according to operating conditions, resulting in a mismatch between voltage loop error calculation and operating conditions, leading to bus voltage fluctuations, dynamic response lag, and decreased power transmission efficiency. Summary of the Invention

[0005] This application provides a three-level bidirectional DC-DC converter control method to achieve adaptive adjustment of control parameters according to the operating state, thereby reducing bus voltage fluctuations and improving energy conversion stability.

[0006] In a first aspect, embodiments of this application provide a three-level bidirectional DC-DC converter control method, including:

[0007] The system acquires a set of operating instructions, electrical sampling values, and network command voltages. The set of operating instructions includes start instructions, stop instructions, status identification information, handle position information, and actual power command values. The electrical sampling values ​​include bus voltage, battery voltage, inductor current, and voltage divider between upper and lower buses.

[0008] The current running state is obtained by combining and judging the information in the running instruction set through a preset state machine logic;

[0009] Extract the voltage loop reference value bias, voltage loop proportional-integral control parameters, and current loop proportional-integral control parameters corresponding to the current operating state from the preset control parameter library;

[0010] Based on the current operating state, the network command voltage, the voltage loop reference value bias, the bus voltage, and the battery voltage, the current loop reference value is obtained through voltage loop proportional-integral control.

[0011] The base duty cycle and voltage equalization compensation amount are obtained based on the current loop proportional-integral control parameters, the current loop reference value, the inductor current, and the voltage division of the upper and lower busbars.

[0012] The base duty cycle is superimposed with the equalization compensation amount to obtain the final duty cycle, and a gate trigger signal is generated based on the final duty cycle.

[0013] In one possible implementation, the current running state is obtained by combining and judging information from the set of running instructions through preset state machine logic, including:

[0014] Obtain multiple preset running state switching conditions, and associate each running state switching condition with a corresponding target running state;

[0015] The system uses a preset state machine logic to determine whether the start command, stop command, status identifier information, handle position information, and actual power command value satisfy any of the conditions in the operation state switching conditions.

[0016] If the conditions are met, the current running state is updated to the target running state associated with the met conditions.

[0017] In one possible implementation, based on the current operating state, the network command voltage, the voltage loop reference bias, the bus voltage, and the battery voltage, a current loop reference value is obtained through voltage loop proportional-integral control, including:

[0018] When the current operating state is a discharge-type operating state, the bus voltage is used as the voltage loop feedback value, and the difference between the voltage loop feedback value and the sum of the network command voltage and the voltage loop reference value bias is calculated to obtain the voltage loop error;

[0019] When the current operating state is a charging operating state, the battery voltage is used as the voltage loop feedback value. The difference between the sum of the network command voltage and the voltage loop reference value bias and the voltage loop feedback value is calculated to obtain the voltage loop error.

[0020] The voltage loop error is calculated by performing proportional-integral operation on the voltage loop proportional-integral control parameters to obtain the current loop reference value.

[0021] In one possible implementation, the base duty cycle and voltage equalization compensation are obtained based on the current loop proportional-integral control parameters, the current loop reference value, the inductor current, and the voltage division of the upper and lower buses, including:

[0022] Subtracting the current loop reference value from the inductor current yields the current loop error;

[0023] The base duty cycle is obtained by performing proportional-integral calculation on the current loop error using the current loop proportional-integral control parameters.

[0024] The voltage difference between the upper and lower busbars is obtained based on the voltage division of the upper and lower busbars.

[0025] The difference between the upper and lower busbars is filtered to obtain the filtered difference.

[0026] The voltage equalization compensation amount is obtained by performing proportional-integral calculation on the filtered difference using preset proportional-integral control parameters of the voltage equalization loop.

[0027] In one possible implementation, the difference between the upper and lower busbars is filtered to obtain a filtered difference, including:

[0028] Obtain the preset cutoff frequency of the filtering process;

[0029] The difference between the upper and lower busbars is subjected to a first-order low-pass filter operation based on the preset cutoff frequency to obtain the filtered difference.

[0030] In one possible implementation, the step of superimposing the base duty cycle with the equalization compensation amount to obtain the final duty cycle includes:

[0031] Monitor the current operating status;

[0032] When the change in the current operating state is detected, the basic duty cycle is adjusted;

[0033] The adjusted base duty cycle is superimposed with the equalization compensation amount to obtain the final duty cycle.

[0034] In one possible implementation, adjusting the base duty cycle includes:

[0035] Obtain the preset ramp start rate and preset stop ramp;

[0036] When the current operating state switches from stop to start, the foundation duty cycle is adjusted linearly according to the preset ramp start rate to obtain the adjusted foundation duty cycle.

[0037] When the current operating state switches from start to stop, the basic duty cycle is linearly reduced according to the preset stop slope to obtain the adjusted basic duty cycle.

[0038] In one possible implementation, before generating the gate trigger signal based on the final duty cycle, the method further includes:

[0039] Acquire multiple physical quantity sample values, including voltage sample values, current sample values, and temperature sample values;

[0040] The sampled values ​​of the physical quantities and the network command voltage are filtered and analyzed to obtain state data;

[0041] Fault feature parameters are extracted from the status data, and the fault feature parameters are compared with a preset protection threshold.

[0042] When the fault characteristic parameters exceed the preset protection threshold, a derating operation command or an alarm command is generated.

[0043] In one possible implementation, fault characteristic parameters are extracted from the status data, and the fault characteristic parameters are compared with a preset protection threshold, including:

[0044] Extract battery voltage polarity characteristic parameters. When the battery voltage polarity characteristic parameters meet the preset reverse connection conditions and continue for a preset first duration, generate a polarity reverse connection fault signal.

[0045] The deviation between the electrical sampled value and the network command voltage is calculated. When the deviation exceeds a preset deviation threshold and continues for a preset second duration, a sampling deviation fault signal is generated.

[0046] In one possible implementation, generating a gate trigger signal based on the final duty cycle includes:

[0047] Determine the corresponding gate conduction combination based on the current operating state;

[0048] Multiple gate trigger signals are generated based on the final duty cycle and the gate conduction combination;

[0049] When the current operating state is a discharge-type operating state, the gate trigger signal corresponding to the boost channel is opened, and the gate trigger signal corresponding to the buck channel is blocked;

[0050] When the current operating state is the charging operating state, the gate trigger signal corresponding to the buck channel is opened, and the gate trigger signal corresponding to the boost channel is blocked.

[0051] Secondly, embodiments of this application provide a three-level bidirectional DC-DC converter control device, comprising:

[0052] The acquisition module is used to acquire the operating instruction set, electrical sampling values, and network instruction voltage. The operating instruction set includes start instruction, stop instruction, status identification information, handle position information, and actual power instruction value. The electrical sampling values ​​include bus voltage, battery voltage, inductor current, and upper and lower bus voltage division.

[0053] The judgment module is used to combine and judge the information in the running instruction set through preset state machine logic to obtain the current running state;

[0054] The acquisition module is also used to extract the voltage loop reference value bias, voltage loop proportional-integral control parameter and current loop proportional-integral control parameter corresponding to the current operating state from the preset control parameter library;

[0055] The analysis module is used to obtain the current loop reference value based on the current operating state, the network command voltage, the voltage loop reference value bias, the bus voltage, and the battery voltage through voltage loop proportional-integral control.

[0056] The analysis module is also used to obtain the basic duty cycle and voltage equalization compensation amount based on the current loop proportional-integral control parameters, the current loop reference value, the inductor current, and the voltage division of the upper and lower busbars.

[0057] The generation module is used to superimpose the base duty cycle and the equalization compensation amount to obtain the final duty cycle, and generate a gate trigger signal based on the final duty cycle.

[0058] In one possible implementation, the determination module is specifically used for:

[0059] Obtain multiple preset running state switching conditions, and associate each running state switching condition with a corresponding target running state;

[0060] The system uses a preset state machine logic to determine whether the start command, stop command, status identifier information, handle position information, and actual power command value satisfy any of the conditions in the operation state switching conditions.

[0061] If the conditions are met, the current running state is updated to the target running state associated with the met conditions.

[0062] In one possible implementation, the analysis module is specifically used for:

[0063] When the current operating state is a discharge-type operating state, the bus voltage is used as the voltage loop feedback value, and the difference between the voltage loop feedback value and the sum of the network command voltage and the voltage loop reference value bias is calculated to obtain the voltage loop error;

[0064] When the current operating state is a charging operating state, the battery voltage is used as the voltage loop feedback value. The difference between the sum of the network command voltage and the voltage loop reference value bias and the voltage loop feedback value is calculated to obtain the voltage loop error.

[0065] The voltage loop error is calculated by performing proportional-integral operation on the voltage loop proportional-integral control parameters to obtain the current loop reference value.

[0066] In one possible implementation, the analysis module is specifically used for:

[0067] Subtracting the current loop reference value from the inductor current yields the current loop error;

[0068] The base duty cycle is obtained by performing proportional-integral calculation on the current loop error using the current loop proportional-integral control parameters.

[0069] The voltage difference between the upper and lower busbars is obtained based on the voltage division of the upper and lower busbars.

[0070] The difference between the upper and lower busbars is filtered to obtain the filtered difference.

[0071] The voltage equalization compensation amount is obtained by performing proportional-integral calculation on the filtered difference using preset proportional-integral control parameters of the voltage equalization loop.

[0072] In one possible implementation, the analysis module is further configured to:

[0073] Obtain the preset cutoff frequency of the filtering process;

[0074] The difference between the upper and lower busbars is subjected to a first-order low-pass filter operation based on the preset cutoff frequency to obtain the filtered difference.

[0075] In one possible implementation, the generation module is specifically used for:

[0076] Monitor the current operating status;

[0077] When the change in the current operating state is detected, the basic duty cycle is adjusted;

[0078] The adjusted base duty cycle is superimposed with the equalization compensation amount to obtain the final duty cycle.

[0079] In one possible implementation, the generation module is further configured to:

[0080] Obtain the preset ramp start rate and preset stop ramp;

[0081] When the current operating state switches from stop to start, the foundation duty cycle is adjusted linearly according to the preset ramp start rate to obtain the adjusted foundation duty cycle.

[0082] When the current operating state switches from start to stop, the basic duty cycle is linearly reduced according to the preset stop slope to obtain the adjusted basic duty cycle.

[0083] In one possible implementation, the generation module is further configured to:

[0084] Acquire multiple physical quantity sample values, including voltage sample values, current sample values, and temperature sample values;

[0085] The sampled values ​​of the physical quantities and the network command voltage are filtered and analyzed to obtain state data;

[0086] Fault feature parameters are extracted from the status data, and the fault feature parameters are compared with a preset protection threshold.

[0087] When the fault characteristic parameters exceed the preset protection threshold, a derating operation command or an alarm command is generated.

[0088] In one possible implementation, the generation module is further configured to:

[0089] Extract battery voltage polarity characteristic parameters. When the battery voltage polarity characteristic parameters meet the preset reverse connection conditions and continue for a preset first duration, generate a polarity reverse connection fault signal.

[0090] The deviation between the electrical sampled value and the network command voltage is calculated. When the deviation exceeds a preset deviation threshold and continues for a preset second duration, a sampling deviation fault signal is generated.

[0091] In one possible implementation, the generation module is specifically used for:

[0092] Determine the corresponding gate conduction combination based on the current operating state;

[0093] Multiple gate trigger signals are generated based on the final duty cycle and the gate conduction combination;

[0094] When the current operating state is a discharge-type operating state, the gate trigger signal corresponding to the boost channel is opened, and the gate trigger signal corresponding to the buck channel is blocked;

[0095] When the current operating state is the charging operating state, the gate trigger signal corresponding to the buck channel is opened, and the gate trigger signal corresponding to the boost channel is blocked.

[0096] Thirdly, embodiments of this application provide an electronic device, including: a memory and a processor;

[0097] The memory stores computer-executed instructions;

[0098] The processor executes computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0099] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0100] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0101] Sixthly, embodiments of this application provide a three-level bidirectional DC-DC converter, comprising:

[0102] The DC bus side capacitor bank includes a first capacitor and a second capacitor connected in series, with the midpoint between the first capacitor and the second capacitor leading out.

[0103] A switching transistor group, comprising multiple switching transistors, wherein the switching transistor group is connected to an inductor to form a boost channel and a buck channel;

[0104] The control module is configured to perform the first aspect and / or various possible implementations of the first aspect as described above, to generate a gate trigger signal based on the current operating state, and to control the conduction combination of the switch group.

[0105] The three-level bidirectional DC-DC converter control method provided in this application identifies the current operating state of the locomotive and adaptively matches the voltage loop reference value bias and control parameters. Then, based on the cascaded adjustment of the voltage loop and current loop and the equalization compensation of the voltage division of the upper and lower buses, it generates a gate drive signal. This achieves the effect of adaptively adjusting the control parameters according to the operating state to reduce bus voltage fluctuations and improve energy conversion stability. Attached Figure Description

[0106] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0107] Figure 1 A schematic diagram of a scenario for controlling a three-level bidirectional DC-DC converter provided in this application;

[0108] Figure 2 A flowchart illustrating the control method for the three-level bidirectional DC-DC converter provided in this application;

[0109] Figure 3 A schematic diagram of the three-level bidirectional DC-DC converter topology provided in this application;

[0110] Figure 4 A schematic diagram of the control architecture provided in this application;

[0111] Figure 5 This application provides a schematic diagram of multi-condition state transitions.

[0112] Figure 6 A schematic diagram of the structure of the three-level bidirectional DC-DC converter control device provided in this application;

[0113] Figure 7 A schematic diagram of the structure of the electronic device provided in this application.

[0114] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0115] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0116] First, let me explain the terms used in this application:

[0117] Network command voltage: refers to the voltage target value issued by the locomotive network system.

[0118] State machine logic refers to the processing rules that determine and transition the state of input information based on preset conditions and rules.

[0119] Current operating state: refers to the current working mode of the locomotive as determined by the state machine logic.

[0120] Control parameter library: refers to a database that pre-stores voltage loop reference bias, voltage loop proportional-integral control parameters, and current loop proportional-integral control parameters for different operating states.

[0121] Voltage loop reference bias: refers to the correction value added to the network command voltage for different operating conditions.

[0122] Voltage loop proportional-integral control parameters: These refer to the proportional and integral coefficients used for voltage loop error adjustment.

[0123] Current loop proportional-integral control parameters: These refer to the proportional and integral coefficients used for current loop error adjustment.

[0124] Voltage loop feedback value: refers to the feedback signal selected from the bus voltage or battery voltage for voltage loop error calculation.

[0125] Voltage loop error: refers to the difference between the voltage loop reference value and the voltage loop feedback value.

[0126] Current loop reference value: refers to the current command value output after the voltage loop error is calculated using proportional-integral operations.

[0127] Current loop error: refers to the difference between the current loop reference value and the inductor current.

[0128] Basic duty cycle: refers to the duty cycle signal output after the current loop error is processed by proportional-integral operation.

[0129] Voltage equalization compensation: refers to the midpoint potential correction value output after filtering and proportional-integral calculation based on the voltage difference between the upper and lower busbars.

[0130] The proportional-integral control parameters of the equalizing ring refer to the proportional and integral coefficients used to adjust the differential pressure between the upper and lower busbars.

[0131] Upper and lower busbar voltage difference: refers to the difference between the voltage distribution of the upper busbar and the voltage distribution of the lower busbar.

[0132] Filtering: This refers to the operation of smoothing the difference between the upper and lower bus lines using a first-order low-pass filter algorithm.

[0133] Preset cutoff frequency: refers to the frequency threshold set during filtering.

[0134] Discharge-type operating state: refers to the operating mode in which the battery needs to discharge to support the bus voltage during traction or constant speed operation.

[0135] Charging operation mode: refers to the operation mode that requires charging the battery during fast charging or electric braking.

[0136] The specific application scenario of this application is the real-time control of a three-level bidirectional DC-DC converter in a mild hybrid locomotive. Based on the above scenario, it is clear that existing technologies, which use fixed-parameter voltage and current dual-loop control and simple mode-switching logic, suffer from the technical problem of being unable to adaptively adjust the voltage loop reference bias and control parameters according to different operating states such as locomotive traction, electric braking, constant speed, fast charging, and shutdown.

[0137] The three-level bidirectional DC-DC converter control method provided in this application identifies the operating state through a preset state machine logic and extracts the corresponding voltage loop reference value bias and proportional-integral control parameters. It combines the bus voltage or battery voltage as feedback values ​​to perform cascaded adjustment of the voltage loop and current loop. At the same time, it uses voltage equalization compensation based on the voltage difference between the upper and lower buses to generate a gate trigger signal. This solves the above-mentioned technical problem of not being able to adaptively adjust parameters according to the operating state.

[0138] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0139] Figure 1 This is a schematic diagram illustrating an application scenario of the three-level bidirectional DC-DC converter control method provided in this application, such as... Figure 1 As shown, it includes: terminal 101 and server 102.

[0140] Terminal 101 is used to collect the locomotive's operating command set, electrical sample values, and network command voltage, and send the collected data to server 102. Server 102 is used to receive the operating command set, electrical sample values, and network command voltage sent by terminal 101, and execute the three-level bidirectional DC-DC converter control method to generate a gate trigger signal.

[0141] Figure 2 This is a flowchart illustrating the three-level bidirectional DC-DC converter control method provided in this application. The execution entity in this embodiment can be... Figure 1 The server 102 in the illustrated embodiment can also be other computer-related devices, and this embodiment is not particularly limited.

[0142] like Figure 2 As shown, the control method for this three-level bidirectional DC-DC converter includes the following steps:

[0143] Step S201: Obtain the operating instruction set, electrical sampling values ​​and network instruction voltage. The operating instruction set includes start instruction, stop instruction, status identification information, handle position information and actual power instruction value. The electrical sampling values ​​include bus voltage, battery voltage, inductor current and upper and lower bus voltage division.

[0144] Specifically, the control unit receives the operating command set and network command voltage from the host computer via the communication bus, and simultaneously reads the electrical sampling values ​​collected by the voltage and current sensors through the analog-to-digital converter interface. All input signals required for control are collected uniformly, providing complete data for subsequent state identification and closed-loop control. Information from different sources corresponds to different needs of the control system: the operating command set corresponds to driver operation and system scheduling requirements, the electrical sampling values ​​reflect the real-time operating status of the converter, and the network command voltage serves as the control target for the voltage loop. By synchronously acquiring data from multiple sources, control lag or misjudgment caused by missing or asynchronous information is avoided, improving the control system's response speed and data consistency.

[0145] For example, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the three-level bidirectional DC-DC converter topology provided in this application. In the diagram, capacitors C1 and C2 on the DC bus side are connected in series and led out at the midpoint. Switches Q1 to Q4 are connected to inductors L1 and L2. The bus voltage in the electrical sampling values ​​is taken from both ends of C1 and C2, the battery voltage is taken from both ends of U0, the inductor current is taken from the L1 or L2 branch, and the upper and lower bus voltage dividers are taken from both ends of C1 and C2, respectively. This topology achieves boost voltage in discharge mode or buck voltage in charging mode by controlling the gate trigger signals of Q1 to Q4.

[0146] Step S202: Combine and judge the information in the running instruction set through the preset state machine logic to obtain the current running state.

[0147] Specifically, at least two types of information from the acquired start command, stop command, status identifier information, handle position information, and actual power command value are input into a preset state machine. The state machine internally stores multiple operating state switching conditions, each condition associated with a corresponding target operating state. The state machine sequentially compares the input information with each switching condition; when a condition is met, it outputs the associated target operating state as the current operating state.

[0148] The state machine is a decision-making model based on finite state automata. Its transition rules predefine the operating states corresponding to different combinations of information, accurately distinguishing various operating modes of the locomotive, including shutdown, fast charging, traction, electric braking, and constant speed. By using multi-dimensional information combinations for judgment rather than single signal switching, the robustness of state recognition is improved, enabling accurate identification of operating states and ensuring precise matching of control parameters with the current operating conditions.

[0149] like Figure 4 As shown, Figure 4 The diagram shows the control architecture provided in this application. In the diagram, the logic conversion control receives start command, stop command, status identification information, handle position information and actual power command value, and outputs the current running status through the preset state machine logic, realizing the status recognition of multiple information combination judgment.

[0150] Step S203: Extract the voltage loop reference bias, voltage loop proportional-integral control parameters, and current loop proportional-integral control parameters corresponding to the current operating state from the preset control parameter library.

[0151] Specifically, the parameter library stores the voltage loop reference bias, voltage loop proportional-integral (PI) control parameters, and current loop PI control parameters for each operating state in key-value pairs. The corresponding parameters are extracted through comparison and lookup. This provides adjustment coefficients suitable for the current operating condition for the voltage and current loop PI controllers, while also providing voltage loop reference correction for subsequent error calculations. This enables the converter to achieve a faster dynamic response under traction conditions, stable steady-state accuracy under charging conditions, and avoids overshoot or oscillation caused by improper parameters during operating condition switching.

[0152] Step S204: Based on the current operating status, network command voltage, voltage loop reference value bias, bus voltage, and battery voltage, obtain the current loop reference value through voltage loop proportional-integral control.

[0153] Specifically, the voltage loop can use a proportional-integral controller to eliminate steady-state errors. The error calculation method is adjusted according to the energy flow direction to ensure the correct polarity of the negative feedback closed loop. Biasing actively raises the bus voltage under traction conditions and actively lowers the charging voltage under electric braking conditions to adapt to the voltage requirements of different operating conditions. By converting the network command voltage into a current command as the setpoint for the inner loop current regulation, and simultaneously achieving adaptive voltage deviation correction under operating conditions, the voltage loop output becomes smooth and error-free in steady state. The current loop reference value can be adjusted in advance according to changes in operating conditions, improving the control accuracy and response speed of the bus voltage.

[0154] Step S205: Obtain the base duty cycle and equalization compensation amount based on the current loop proportional-integral control parameters, current loop reference value, inductor current, and voltage division of the upper and lower buses.

[0155] Specifically, the current loop reference value is subtracted from the inductor current sample value to obtain the current loop error. This error is then input to a proportional-integral (PI) controller using current loop PPI control parameters, which outputs the base duty cycle. Simultaneously, the upper and lower voltage divisions in the upper and lower bus voltage dividers are subtracted to obtain the upper and lower bus voltage difference. This difference is then subjected to a first-order low-pass filter to obtain the filtered difference. This filtered difference is then input to a PPI controller using voltage equalization loop PPI control parameters, which outputs the voltage equalization compensation.

[0156] By controlling the midpoint potential balance of the three-level topology, a base duty cycle without midpoint potential compensation is generated. At the same time, the compensation amount required to maintain midpoint balance is calculated independently, achieving precise power control. The voltage equalization ring effectively suppresses midpoint potential drift and prevents the three-level converter from experiencing increased stress on the switching transistors or damage to the capacitors due to voltage imbalance.

[0157] Step S206: The base duty cycle is superimposed with the equalization compensation to obtain the final duty cycle, and a gate trigger signal is generated based on the final duty cycle.

[0158] Specifically, the voltage equalization compensation is added to the base duty cycle as a correction term, finely adjusting the conduction time of each switch without changing the dominant role of the current loop to achieve midpoint potential balance. The gate conduction combination selects either boost or buck operating mode according to the operating conditions to prevent simultaneous conduction of the upper and lower transistors or reverse energy flow.

[0159] The output of the control algorithm is converted into a signal that actually drives the switching transistor, thus directly controlling the power transistor of the converter. Ultimately, the duty cycle simultaneously meets the requirements of current tracking accuracy and midpoint balance, and the gate trigger signal is output according to the correct operating mode, ensuring the safe and efficient operation of the converter under different operating conditions.

[0160] The three-level bidirectional DC-DC converter control method provided in this invention identifies the locomotive's operating state through a preset state machine logic and adaptively loads the corresponding voltage loop bias and proportional-integral control parameters. Then, by combining the cascaded adjustment of the voltage loop and current loop with the voltage equalization compensation of the upper and lower bus voltages, the final duty cycle is generated. This achieves dynamic matching between the operating state and control parameters, reduces bus voltage fluctuations, and improves energy conversion stability.

[0161] This embodiment provides a detailed description of the process described in the above embodiment, which combines and judges information in the running instruction set using preset state machine logic to obtain the current running state. The specific implementation of this process includes the following steps:

[0162] Step a1: Obtain multiple preset running state switching conditions, and associate each running state switching condition with the corresponding target running state.

[0163] Specifically, the control unit reads a pre-built state transition condition table from its internal non-volatile memory. Each record in the state transition condition table contains a set of decision conditions and the target operating state bound to those conditions. The state transition condition table is constructed based on the physical constraints and operational logic of the locomotive operation, including the transition relationships between five states: shutdown, fast charging, traction, electric braking, and constant speed.

[0164] By presetting multiple combinations of operating condition codes, handle positions, power directions, and start / stop signals as conditions, the complexity of real-time online analysis is reduced, the determinism of state judgment is improved, and an executable judgment basis is provided for the state machine, so that state transitions do not depend on a single signal, but are based on the comprehensive matching result of multiple information.

[0165] Step a2: Determine whether the start command, stop command, status identifier information, handle position information, and actual power command value meet any of the conditions in the operation state switching conditions through the preset state machine logic.

[0166] Specifically, the start command, stop command, status identifier information, handle position information, and actual power command value are used as the current input vector, and compared with the acquired operating state switching conditions. The state machine logic checks whether the current input vector corresponds to all the decision items defined in a certain switching condition according to a preset priority order or sequential traversal method. When any condition is met, subsequent comparisons are stopped and the matched condition is recorded. For example, when the handle position is in traction mode and the power command is positive, the state machine logic determines it to be a traction condition; when the handle position is in braking mode and the power command is negative, it is determined to be an electric braking condition.

[0167] The state machine can adopt a deterministic finite automaton model and employs deterministic logic comparison to ensure the accuracy of state judgment. The state machine logically compares the current input vector with each switching condition and outputs the matching result. By selecting the unique condition triggered by the current input vector from multiple preset conditions, a target basis is provided for subsequent state updates. Through multi-information combination matching, misjudgments of the state caused by noise from a single sensor or transient communication anomalies are prevented, improving anti-interference capabilities.

[0168] Step a3: If satisfied, update the current running state to the target running state associated with the satisfied condition.

[0169] Specifically, once the switching conditions are found to be met, the target running state identifier associated with those conditions is extracted. The current running state variable is then assigned the target running state identifier, and optionally, the state transition time and triggering condition information are recorded for logging purposes. If no conditions are met, the current running state remains unchanged.

[0170] By transforming the results of condition matching into state variables usable in the control process for subsequent steps such as parameter extraction, error calculation, and gate control, a smooth and deterministic switching of locomotive operating state is achieved, ensuring the accuracy and consistency of the current operating state within each control cycle and providing reliable state input for parameter adaptation.

[0171] like Figure 5 As shown, Figure 5 The multi-condition state transition diagram provided in this application predefines a shutdown state, a fast charging state, a traction state, an electric braking state, and a constant speed state, as well as the switching conditions between each state. The preset state machine logic determines whether the preset multiple operating state switching conditions are met based on start commands, stop commands, state identifier information, handle position information, and actual power command values. If met, the current operating state is updated to the target operating state associated with the met conditions. The transition paths from the shutdown state to the fast charging state, from the fast charging state to the traction state, and from the traction state to the electric braking state in the diagram all correspond to different combinations of conditions. In the diagram, discharge-type operating states (traction, constant speed) correspond to the Boost operating mode, and charging-type operating states (fast charging, electric braking) correspond to the Buck operating mode. This is illustrated in the table below:

[0172]

[0173] This invention achieves state recognition based on multi-dimensional information combination judgment by acquiring multiple preset operating state switching conditions, then combining and matching multiple types of information in the input instruction set using preset state machine logic, and taking the target operating state associated with the matched condition as the current operating state. This reduces misjudgment of single signal switching and improves the reliability of state recognition.

[0174] This embodiment details the process described in the above embodiment of obtaining the current loop reference value through voltage loop proportional-integral control based on the current operating state, network command voltage, voltage loop reference value bias, bus voltage, and battery voltage. The specific implementation of this process includes the following steps:

[0175] Step b1: When the current operating state is a discharge-type operating state, the bus voltage is used as the voltage loop feedback value. The difference between the voltage loop feedback value and the sum of the network command voltage and the voltage loop reference value bias is calculated to obtain the voltage loop error.

[0176] Specifically, it determines whether the current operating state belongs to the discharge category, which includes traction and constant speed states. After determining that it is a discharge category, the bus voltage is selected from the electrical sampling values ​​as the voltage loop feedback value. At the same time, the network command voltage and the voltage loop reference value bias are added to obtain the reference composite value. Finally, the difference between the voltage loop feedback value and the reference composite value is calculated, and the output is the voltage loop error.

[0177] Under discharge conditions, the converter operates in boost mode, with the power battery supplying power to the DC bus. The control objective is to maintain the bus voltage stable near the network command value. A negative feedback closed loop is formed using the bus voltage as the feedback value. The error is calculated by subtracting the reference value from the feedback value, ensuring the correct adjustment direction of the proportional-integral regulator output. The addition of a bias causes the target bus voltage value to proactively increase by a positive offset to adapt to the response requirements of sudden load increases under traction conditions.

[0178] The voltage loop error reflects the degree of deviation of the bus voltage from the command value. Its polarity is automatically adapted to the operating conditions, ensuring the correct polarity of the regulator output current command in boost mode and providing a reasonable setpoint for the current loop.

[0179] Step b2: When the current operating state is charging mode, the battery voltage is used as the voltage loop feedback value. The difference between the sum of the network command voltage and the voltage loop reference value bias and the voltage loop feedback value is calculated to obtain the voltage loop error.

[0180] Specifically, when the current operating state is a charging state, which includes fast charging state and electric braking state, the battery voltage is selected from the electrical sampling value as the voltage loop feedback value. The network command voltage is added to the voltage loop reference value bias to obtain the reference composite value. Then, the difference between the reference composite value and the voltage loop feedback value is calculated, and the output is the voltage loop error.

[0181] During charging operations, the converter operates in buck mode, charging the power battery with braking energy or external power. The control target is to ensure the battery voltage does not exceed the upper charging voltage limit. A negative feedback closed loop is formed using the battery voltage as the feedback value. The error is calculated by subtracting the feedback value from the reference value, causing the regulator to increase the charging current when the battery voltage is lower than the target value. A negative bias is applied, causing the target charging voltage to actively decrease by an offset, providing a buffer for braking energy feedback.

[0182] The deviation between the charging upper limit command and the actual battery voltage is converted into a voltage loop error signal. The target value is adjusted by negative bias to adapt to the voltage impact during braking energy feedback. The error polarity matches the adjustment direction in buck mode, ensuring a smooth charging process and battery safety.

[0183] Step b3: Perform proportional-integral calculations on the voltage loop error using the voltage loop proportional-integral control parameters to obtain the current loop reference value.

[0184] Specifically, the voltage loop error signal is input to the proportional-integral (PI) controller. The PI controller uses voltage loop PI control parameters bound to the current operating state, including the proportional coefficient and integral coefficient. The controller performs proportional and integral operations on the error signal, adds the two results, and outputs the value as the current loop reference value.

[0185] Proportional-integral (PI) regulators can eliminate steady-state errors and improve dynamic response speed. The proportional term responds instantly to the current error, while the integral term accumulates historical errors to eliminate steady-state error. The output of the voltage loop serves as the setpoint for the inner loop, providing the inductor current command required to maintain voltage balance. Since the equivalent load and output impedance of the converter differ under different operating conditions, state-bound PPI parameters effectively avoid overshoot and oscillation, achieving steady-state error-free voltage control.

[0186] This invention selects either the bus voltage or the battery voltage as the voltage loop feedback value based on the discharge or charging operating state, and calculates the voltage loop error in different ways, such as subtracting the reference value from the feedback value or subtracting the feedback value from the reference value. The error is then adjusted according to the proportional-integral control parameters bound to the operating state to obtain the current loop reference value. This achieves condition-adaptive matching of the voltage loop error calculation polarity, avoiding control divergence caused by polarity errors, and improving the dynamic response performance and steady-state accuracy of the voltage loop.

[0187] This embodiment provides a detailed explanation of the process in the above embodiment for obtaining the base duty cycle and voltage equalization compensation amount based on the current loop proportional-integral control parameters, current loop reference values, inductor current, and voltage division of the upper and lower busbars. The specific implementation of this process includes the following steps:

[0188] Step c1: Subtract the current loop reference value from the inductor current to obtain the current loop error.

[0189] Specifically, the current loop employs a negative feedback structure, driving the regulator by comparing the deviation between the current command and the actual current, thus ensuring the actual current follows the command. Inductor current is a direct representation of the converter's energy transfer; the sign of the error reflects the direction and magnitude of the deviation of the actual current from the command. The deviation between the current command and the actual current is extracted as an error signal, providing input for the proportional-integral (PI) regulation of the current loop.

[0190] Step c2: Perform proportional-integral calculation on the current loop error using the current loop proportional-integral control parameters to obtain the basic duty cycle.

[0191] Specifically, the current loop error signal is input to the proportional-integral (PI) controller. The PI controller uses current loop PI control parameters bound to the current operating state, including proportional and integral coefficients. The PI controller performs proportional and integral operations on the error, adds the two results, and limits the output value to the effective range of the duty cycle to obtain the base duty cycle signal.

[0192] The current loop proportional-integral (PI) regulator eliminates steady-state tracking errors and improves dynamic response speed. The proportional term responds instantly to the current error to accelerate tracking, while the integral term eliminates steady-state error to ensure steady-state accuracy. The output duty cycle controls the on-time ratio of the switching transistor, directly determining the charging and discharging slope of the inductor current. By converting the current error into a switching transistor duty cycle command, closed-loop control of the inductor current is achieved.

[0193] Step c3: Obtain the voltage difference between the upper and lower busbars based on the voltage division between the upper and lower busbars.

[0194] Specifically, the voltage division values ​​of the upper and lower busbars are read from the electrical sampling values, and the difference between the upper and lower busbars is obtained through differential calculation. The difference reflects the degree of midpoint potential shift; a positive difference indicates that the voltage of the upper capacitor is higher than that of the lower capacitor, and a negative difference indicates that the voltage of the lower capacitor is higher than that of the upper capacitor. The difference between the upper and lower busbars directly and linearly reflects the direction and magnitude of the midpoint potential imbalance. The quantified value of the midpoint potential shift is extracted and used as the basis for the adjustment of the equalizing loop.

[0195] Step c4: Filter the difference between the upper and lower busbars to obtain the filtered difference.

[0196] Specifically, the difference between the upper and lower bus signals may contain switching frequency ripple and sampling noise. Directly using this for proportional-integral (PI) regulation can lead to high-frequency fluctuations in the voltage equalization loop output. Low-pass filtering can remove high-frequency components while retaining the low-frequency deviation that reflects the midpoint potential trend, making the voltage equalization loop regulation smoother and more stable. By inputting the difference between the upper and lower bus signals into the low-pass filter algorithm module to perform a first-order low-pass filter operation on the input signal, and outputting the smoothed difference signal as the filtered difference, high-frequency noise and ripple in the original difference signal can be effectively suppressed, improving the stability and anti-interference capability of the voltage equalization loop regulation.

[0197] Step c5: Perform proportional-integral calculation on the filtered difference using preset equalization loop proportional-integral control parameters to obtain the equalization compensation amount.

[0198] Specifically, the preset proportional-integral control parameters for the voltage equalization loop include proportional and integral coefficients. Proportional and integral calculations are performed on the filtered difference, and the results are summed, with the output value serving as the voltage equalization compensation. Closed-loop correction is applied to the midpoint potential offset; the proportional term compensates for the current offset in real time, while the integral term eliminates static offset to ensure long-term balance. The compensation output is a correction value for the duty cycle; a positive compensation increases the conduction time of the lower tube to lower the bus voltage, while a negative compensation has the opposite effect.

[0199] It effectively converts the midpoint potential offset into a correction signal for the base duty cycle, achieving dynamic balance of the upper and lower bus voltages and avoiding capacitor damage or increased stress on the switching transistors caused by voltage imbalance.

[0200] In some alternative implementations, step c4 above includes:

[0201] Step c41: Obtain the preset cutoff frequency for filtering.

[0202] Specifically, a preset cutoff frequency limits the passband range of the filter; signal components below the cutoff frequency are retained, while those above are attenuated. Selecting a suitable cutoff frequency requires striking a balance between ripple removal and maintaining response speed, providing frequency boundary parameters for low-pass filtering operations and determining the smoothness of the filter. The obtained cutoff frequency value enables the filtering process to effectively remove switching frequency ripple without affecting the equalizing loop's response to low-frequency changes in the midpoint potential.

[0203] For example, when the difference between the upper and lower bus voltages fluctuates at high frequencies due to the switching frequency (e.g., 10kHz), the low-pass filter retains the low-frequency component reflecting the midpoint potential trend, making the output of the equalizing loop proportional-integral controller smoother and more stable. This avoids abrupt changes in the equalizing loop output caused by high-frequency noise in the original difference signal, thus improving the anti-interference capability of the midpoint potential balance control.

[0204] Step c42: Perform a first-order low-pass filter operation on the difference between the upper and lower buses according to the preset cutoff frequency to obtain the filtered difference.

[0205] Specifically, iterative filtering is performed on the difference signal according to the transfer function. A weighted average is calculated using the filtering result from the previous time step and the original difference at the current time step. The weights are determined by the cutoff frequency and the sampling period. The filtered difference at the current time step is then output. The filtering time constant is inversely proportional to the cutoff frequency; the lower the cutoff frequency, the stronger the smoothing effect but the slower the response. By performing a low-pass filter with a specified cutoff frequency on the difference between the upper and lower buses, high-frequency noise is removed while retaining the low-frequency deviation component.

[0206] This invention provides a method for obtaining the current loop error by subtracting the current loop reference value from the inductor current, and then using the current loop proportional-integral control parameters to calculate the base duty cycle. Simultaneously, it extracts the voltage difference between the upper and lower buses based on the voltage divider, and after first-order low-pass filtering, uses the voltage equalization loop proportional-integral control parameters to calculate the voltage equalization compensation amount. This achieves decoupling control between precise current loop tracking and active midpoint potential balancing, effectively suppressing the midpoint potential drift problem in a three-level topology while ensuring power tracking performance.

[0207] This embodiment provides a detailed explanation of the process in the above embodiments of obtaining the final duty cycle by superimposing the basic duty cycle and the equalization compensation amount. The specific implementation of this process includes the following steps:

[0208] Step d1: Monitor the current operating status.

[0209] Specifically, the operating state may switch between different control cycles, such as switching from stop to start or from traction to electric braking. By monitoring and comparing the state values ​​periodically, the boundary moments of state transitions can be accurately captured, achieving real-time capture of state transition events.

[0210] Step d2: When a switch in the current operating state is detected, the basic duty cycle is adjusted.

[0211] Specifically, when a state transition is detected, the basic duty cycle is paused and directly output to the superposition, and the electrical impact caused by the sudden change is avoided by adjusting the duty cycle; if no transition is detected, the unadjusted basic duty cycle is used directly.

[0212] If the base duty cycle changes abruptly during state switching, it can cause an inductor current surge, leading to bus voltage fluctuations or increased stress on the power transistors. By gradually adjusting the duty cycle over multiple control cycles, inrush currents can be effectively suppressed. Smoothing the base duty cycle during the transition phase of state switching significantly reduces current spikes and voltage overshoots, protecting power devices. For example, during traction-to-electricity switching, the duty cycle gradually decreases from its current value to the target value at a preset slope, allowing the inductor's stored energy to be smoothly released through the load, thereby suppressing current surges and reducing power transistor stress.

[0213] Step d3: The adjusted base duty cycle is superimposed with the equalization compensation amount to obtain the final duty cycle.

[0214] Specifically, the adjusted base duty cycle and the equalization compensation amount are algebraically added together, and the result is used as the final duty cycle. The addition operation supports both positive and negative compensation amounts, which can be positive or negative values.

[0215] The voltage equalization compensation represents the direction and magnitude of the correction for the midpoint potential drift. After being superimposed on the base duty cycle, the duty cycle of the switching transistor is finely adjusted to balance the voltages of the upper and lower buses without changing the dominant regulation effect of the current loop. By superposition, decoupled control of current following and midpoint balance is achieved. The final duty cycle obtained ensures that the inductor current follows the command quickly and effectively suppresses the midpoint potential drift.

[0216] In some alternative implementations, step d2 above includes:

[0217] Step d21: Obtain the preset ramp start rate and preset stop ramp.

[0218] Specifically, a preset ramp start-up rate is used for linearly increasing the duty cycle during startup, while a preset shutdown ramp is used for linearly decreasing the duty cycle during shutdown. The startup and shutdown processes have different sensitivities to the duty cycle change rate. During startup, a rapid establishment of the output voltage is required while avoiding overshoot; during shutdown, a smooth release of stored energy is needed to prevent voltage drop. Presetting these two sets of parameters independently optimizes the dynamic characteristics of startup and shutdown, providing a reference for the rate of change of linear increment and linear decrement adjustments, and controlling the speed of the transition process.

[0219] Step d22: When the current running state switches from stopped to started, the base duty cycle is linearly increased according to the preset ramp start rate to obtain the adjusted base duty cycle.

[0220] Specifically, when the current operating state is detected to switch from a stopped state to any starting state, a linear incremental adjustment is triggered. The adjustment module uses the current base duty cycle as the starting value and increases the duty cycle output at a preset ramp start rate in each consecutive control cycle until it reaches the target value of the original base duty cycle. Each intermediate value during this period is used as the adjusted base duty cycle output.

[0221] Linear increments allow the duty cycle to gradually rise from zero or its current value to the target value at a constant slope, avoiding abrupt changes in the duty cycle. This smooth increase in duty cycle during device startup suppresses instantaneous current surges, effectively eliminating current spikes characteristic of traditional hard-start methods and reducing stress damage to power transistors and inductors.

[0222] Step d23: When the current running state switches from start to stop, the basic duty cycle is linearly reduced according to the preset stop slope to obtain the adjusted basic duty cycle.

[0223] Specifically, when the current operating state is detected to switch from any start state to stop state, a linear decreasing adjustment is triggered. The adjustment module uses the current base duty cycle as the starting value and reduces the duty cycle output according to the preset stop slope in each consecutive control cycle until it is reduced to zero. During this period, each intermediate value is used as the adjusted base duty cycle output.

[0224] Linear reduction allows the duty cycle to gradually decrease from its current value to zero at a constant slope, enabling the inductor's stored energy to be released smoothly through the load and avoiding voltage backlash or discontinuous current oscillations caused by a sudden drop in the duty cycle to zero. During equipment shutdown, a smooth reduction in the duty cycle ensures orderly energy release, preventing bus voltage drops or backlashes during shutdown, and allowing the inductor current to decay smoothly to zero, avoiding voltage overshoot and electromagnetic interference caused by hard shutdown.

[0225] For example, under traction conditions, if the load inertia is large (such as traction of a heavy-duty carriage), the system adopts a gentler ramp start-up rate (e.g., 500V / s) to gradually increase the bus voltage and avoid voltage overshoot caused by sudden load changes. Under shutdown conditions, a gentler shutdown ramp (e.g., 300A / s) is adopted to allow the inductor energy to be gradually released through the load, preventing voltage backflow. By gradually adjusting the duty cycle, a smooth energy transition under different load scenarios is achieved.

[0226] This invention monitors the current operating status and adjusts the base duty cycle linearly by increasing or decreasing it when a state switch is detected. The adjusted base duty cycle is then superimposed with the voltage equalization compensation to obtain the final duty cycle. This achieves a smooth transition of the duty cycle during startup and shutdown, suppresses current surges and voltage fluctuations caused by state switches, and effectively extends the service life of the equipment.

[0227] This embodiment provides a detailed description of the process before generating the gate trigger signal based on the final duty cycle in the above embodiments. The specific implementation of this process also includes the following steps:

[0228] Step m1: Obtain multiple physical quantity sample values, including voltage sample values, current sample values, and temperature sample values.

[0229] Specifically, the voltage sampling values ​​include redundant measurements of the bus voltage and battery voltage, the current sampling values ​​include inductor current and input / output current, and the temperature sampling values ​​include the power module substrate temperature and reactor winding temperature.

[0230] Voltage and current reflect the electrical operating point of the converter, while temperature reflects the thermal load status, providing a data basis for fault feature extraction and threshold comparison.

[0231] Step m2 involves filtering and analyzing the sampled physical quantities and network command voltages to obtain state data.

[0232] Specifically, the sampled physical quantities and network command voltage are input into the Kalman filter algorithm model. Through recursive calculations in two steps—prediction and update—the fused state estimate is output as the state data. Kalman filtering can fuse multi-source measurement data and suppress sensor noise. Through recursive calculations of model prediction and measurement update, it obtains the optimal state estimate in the sense of minimum variance. During the filtering process, the reliability of each measurement value is automatically analyzed to reduce the impact of abnormal noise interference on the state estimate.

[0233] By denoising and fusing the original sampled values ​​and network commands, random noise and instantaneous spikes are eliminated, generating reliable state data for fault feature extraction and improving the accuracy and stability of fault feature parameter extraction.

[0234] Step m3: Extract fault characteristic parameters from the status data and compare the fault characteristic parameters with the preset protection threshold.

[0235] Specifically, quantitative features reflecting the system's health status are extracted from the status data, including battery voltage polarity, voltage-current deviation, temperature value, and bus voltage difference. Each extracted fault characteristic parameter is then compared numerically with its corresponding preset protection threshold to determine if it exceeds the safety limits. Threshold comparisons can employ hysteresis comparison or delayed confirmation mechanisms to avoid frequent triggering near critical values.

[0236] By converting filtered state data into discernible fault indicators, quantitative fault detection is achieved.

[0237] Step m4: When the fault characteristic parameters exceed the preset protection threshold, generate a derating operation command or an alarm command.

[0238] Specifically, when the comparison result determines that the fault characteristic parameter exceeds the corresponding threshold, different levels of response instructions are generated according to the fault level. For minor, recoverable faults, an alarm instruction is generated, which only records the fault information and provides a notification without interrupting operation. For faults that affect safety but are not urgent, a derating operation instruction is generated, limiting the output power or reducing the voltage and current limits. For severe faults, a shutdown instruction or gate blocking instruction is generated.

[0239] A tiered response strategy is adopted based on the severity and urgency of the fault to avoid over-protection that results in a complete shutdown during a fault, while ensuring rapid disconnection in the event of a severe fault. Tiered protection reduces the impact on normal operation while ensuring safety, derating operation allows the equipment to operate with faults for a limited time, and alarm notifications are sent to operators for timely handling.

[0240] In some alternative implementations, step m3 above includes:

[0241] Step m31: Extract battery voltage polarity characteristic parameters. When the battery voltage polarity characteristic parameters meet the preset reverse connection conditions and continue for a preset first duration, generate a polarity reverse connection fault signal.

[0242] Specifically, the battery voltage value and sign are read from the status data, and the voltage sign is used as a polarity characteristic parameter. The preset reverse connection condition is defined as the battery voltage being negative and its absolute value exceeding the reverse connection judgment threshold. When this condition is met continuously for a preset first duration, a polarity reverse connection fault signal is generated.

[0243] When connected correctly, the battery voltage is positive; when reversed, the voltage sampling value is negative. Because voltage fluctuations may occur momentarily during reverse connection, a duration threshold is set to avoid false alarms caused by instantaneous disturbances. Reverse connection faults are irreversible hardware wiring errors; upon detection, startup must be immediately disabled and an alarm triggered. By checking for reverse connection of the power battery before powering on or running the equipment, it is possible to prevent electrolytic capacitor explosions or power transistor damage caused by reverse connection.

[0244] Step m32: Calculate the deviation between the electrical sample value and the network command voltage. When the deviation exceeds the preset deviation threshold and continues for a preset second duration, generate a sampling deviation fault signal.

[0245] Specifically, the bus voltage sample value or battery voltage sample value is read from the status data, and subtracted from the network command voltage to obtain the absolute value of the deviation. The absolute value of the deviation is compared with a preset deviation threshold. When the deviation value continuously exceeds the threshold for a preset second duration, a sampling deviation fault signal is generated.

[0246] During normal operation, the sampled values ​​should remain within a certain deviation range from the network command values. If the deviation remains excessively large, it indicates a sampling channel malfunction, communication interference, or sensor abnormality. Setting a duration threshold avoids false alarms caused by momentary communication interruptions. By detecting anomalies in the sampling system or communication link, it effectively identifies anomalies such as sensor drift, communication interruptions, or network command errors, ensuring the reliability of control logic input data and preventing equipment malfunction due to erroneous data.

[0247] In some optional implementations, step m3 above further includes:

[0248] Step m33: Extract temperature characteristic parameters.

[0249] Specifically, temperature characteristic parameters include the absolute temperature and rate of temperature change of the power module and reactor, which directly reflect the equipment's heat generation and heat dissipation conditions. By extracting temperature-related quantitative indicators, a basis for over-temperature protection and derating control can be provided.

[0250] Step m34: When the temperature characteristic parameter exceeds the preset first temperature threshold, a temperature alarm signal is generated.

[0251] Specifically, the extracted power module temperature or reactor temperature is compared with a preset first temperature threshold. If either temperature exceeds the threshold but does not reach a higher threshold range, a temperature alarm signal is generated, recorded in the fault log, and uploaded to the network.

[0252] The first temperature threshold is set as the lower limit of the maximum safe operating temperature allowed for continuous operation of the equipment. Exceeding this value indicates that the temperature is too high but does not endanger equipment safety. The alarm signal prompts the operator to pay attention to the heat dissipation status or reduce the load.

[0253] Step m35: When the temperature characteristic parameter exceeds the preset second temperature threshold but does not exceed the preset first temperature threshold, a temperature derating signal is generated.

[0254] Specifically, when the temperature characteristic parameter exceeds a preset second temperature threshold (the second threshold is higher than the first threshold) but is simultaneously lower than the first temperature threshold, a temperature derating signal is generated. This signal triggers the control system to automatically reduce the output power or limit the maximum current to reduce heat generation.

[0255] The second temperature threshold corresponds to the temperature point at which the equipment can operate for short periods but is not suitable for long-term operation. Derating operation actively limits power to suppress further temperature rise, allowing the equipment to maintain reduced power output without overheating, thus avoiding system interruption caused by direct shutdown.

[0256] Step m36: When the temperature characteristic parameter exceeds the preset third temperature threshold but does not exceed the preset second temperature threshold, a temperature shutdown signal is generated.

[0257] Specifically, when the temperature characteristic parameter exceeds a preset third temperature threshold (the third threshold is higher than the second threshold) and is simultaneously lower than the second temperature threshold, a temperature shutdown signal is generated. This signal triggers the control unit to immediately block all gate trigger signals, cut off power output, and report an overheating fault.

[0258] The third temperature threshold is set as the highest permissible temperature limit for the equipment. Exceeding this value will cause insulation damage to the power module or reactor, solder fatigue, or burnout. In this case, power transmission must be stopped immediately to protect the hardware. An emergency shutdown should be performed when the temperature reaches a dangerous level to prevent permanent damage to the equipment.

[0259] The temperature shutdown signal quickly cuts off power when triggered by extreme temperatures, effectively protecting the power module and reactor and preventing catastrophic failures.

[0260] In some optional implementations, the method further includes: directly blocking all gate trigger signals when any physical quantity sample value exceeds a preset hardware protection threshold.

[0261] Specifically, a separate hardware comparator circuit can be set up, with key physical quantities such as bus voltage sampling values ​​and inductor current sampling values ​​directly connected to the comparator input. The comparator's reference voltage is set to a hardware protection threshold. When the sampled value exceeds the threshold, the comparator output flips, and this signal is directly connected to the enable terminal of the gate drive circuit, immediately blocking all gate trigger signals without software processing. At the same time, the fault status is latched and reported.

[0262] For severe overvoltage or overcurrent, the power transistor must be shut down within microseconds to prevent it from exploding. Hardware protection, as the last line of defense, operates independently of software and is unaffected by program crashes or infinite loops. It provides a fast protection channel independent of software, blocking the gate with minimal delay in the event of extreme faults.

[0263] This invention obtains state data by acquiring multiple physical quantity sampling values ​​and performing Kalman filtering analysis. It extracts fault characteristic parameters such as polarity, deviation, and temperature and compares them with preset multi-level protection thresholds to generate corresponding derating instructions, alarm instructions, or shutdown instructions. At the same time, it sets up an independent hardware comparator to directly block the gate when the physical quantity exceeds the limit. This realizes a hierarchical fault protection that combines software hierarchical diagnosis with hardware rapid disconnection, improves the coverage and response speed of fault detection, and maximizes the continuous operation capability of the system while ensuring safety.

[0264] This embodiment provides a detailed description of the process for generating a gate trigger signal based on the final duty cycle in the above embodiments. The specific implementation of this process includes the following steps:

[0265] Step n1: Determine the corresponding gate conduction combination based on the current operating state.

[0266] Specifically, based on the state type, the system queries a preset gate conduction combination table for the conduction combination associated with that state. The conduction combination determines the conduction order and pairing relationship of multiple switches in the converter within a switching cycle; different operating states correspond to different combination modes.

[0267] A three-level bidirectional DC-DC converter topology includes multiple switches, and the turn-on timing requirements for these switches differ between boost and buck modes. Discharge operation requires the activation of the switch group corresponding to the boost channel, while charging operation requires the activation of the switch group corresponding to the buck channel. A turn-on combination table pre-stores the legal switch pairings for each mode, preventing shoot-through of switches on the same bridge arm or mixing of modes.

[0268] By mapping the operating state to specific switching transistor drive configurations, short circuits caused by mismatch during mode switching are eliminated, ensuring the safe driving of power transistors.

[0269] Step n2: Generate multiple gate trigger signals based on the final duty cycle and gate conduction combination.

[0270] Specifically, the final duty cycle is converted into the conduction time of the pulse width modulation wave. The conduction time is calculated based on the carrier period to determine the pulse width corresponding to the duty cycle. Simultaneously, according to the gate conduction combination, the same pulse width modulation wave is distributed to multiple switch drive channels specified in the combination. After necessary dead-time insertion and level conversion of the drive signals for each channel, multiple gate trigger signals are output.

[0271] The final duty cycle is a dimensionless value between 0 and 1, which needs to be converted into the actual high and low level timing by the pulse width modulation module. This is achieved by converting the digital duty cycle in the control domain into the actual switching drive waveform in the power domain and distributing it to each switch according to the correct grouping.

[0272] Step n3: When the current operating state is a discharge-type operating state, open the gate trigger signal corresponding to the boost channel and block the gate trigger signal corresponding to the buck channel.

[0273] Specifically, when the current operating state is determined to be a discharge-type operating state, the control unit sets the enable bit of the gate trigger signal of the corresponding switch in the boost channel to the open state, allowing the pulse width modulation wave to be output to the drive circuit of these switches; at the same time, it sets the enable bit of the gate trigger signal of the corresponding switch in the buck channel to the closed state, forcibly pulling the drive signal of these switches low and keeping them off. In discharge mode, the buck channel switches are reliably turned off, avoiding unexpected conduction during boost operation and improving safety.

[0274] Step n4: When the current operating state is the charging operating state, open the gate trigger signal corresponding to the buck channel and block the gate trigger signal corresponding to the boost channel.

[0275] Specifically, when the current operating state is determined to be a charging state, the control unit sets the enable bit of the gate trigger signal of the switch corresponding to the buck channel to the open state, allowing the pulse width modulation wave to be output to the drive circuit of these switches; at the same time, it sets the enable bit of the gate trigger signal of the switch corresponding to the boost channel to the closed state, forcibly turning off the switch of the boost channel.

[0276] During charging operations, the converter operates in buck mode, requiring only the buck channel's switching transistors to adjust their duty cycles, while the boost channel's switching transistors should remain off. Mutual exclusion enable settings ensure that the switching transistors in both modes are not activated simultaneously, fundamentally preventing mode conflicts.

[0277] The buck channel's drive output is selectively activated based on the operating conditions, while the boost channel's output is disabled, thus achieving safe driving in charging mode.

[0278] This invention determines the corresponding gate conduction combination based on the current operating state, generates multiple gate trigger signals based on the final duty cycle and conduction combination, and opens the boost channel and blocks the buck channel in the discharge state, and opens the buck channel and blocks the boost channel in the charging state, thereby achieving gate-level interlocking isolation between boost and buck operating modes and ensuring safety and reliability under different operating states.

[0279] Figure 6 This is a schematic diagram of the structure of the three-level bidirectional DC-DC converter control device provided in this application. Figure 6 As shown, the three-level bidirectional DC-DC converter control device 60 includes:

[0280] The acquisition module 601 is used to acquire the operating instruction set, electrical sampling values ​​and network instruction voltage. The operating instruction set includes start instruction, stop instruction, status identification information, handle position information and actual power instruction value. The electrical sampling values ​​include bus voltage, battery voltage, inductor current and upper and lower bus voltage division.

[0281] The judgment module 602 is used to combine and judge the information in the running instruction set through preset state machine logic to obtain the current running state;

[0282] The acquisition module 601 is also used to extract the voltage loop reference value bias, voltage loop proportional-integral control parameters and current loop proportional-integral control parameters corresponding to the current operating state from the preset control parameter library;

[0283] Analysis module 603 is used to obtain current loop reference value based on current operating status, network command voltage, voltage loop reference value bias, bus voltage and battery voltage through voltage loop proportional-integral control;

[0284] Analysis module 603 is also used to obtain the basic duty cycle and equalization compensation amount based on the current loop proportional-integral control parameters, current loop reference value, inductor current and upper and lower bus voltage division.

[0285] The generation module 604 is used to superimpose the basic duty cycle and the equalization compensation amount to obtain the final duty cycle, and generate the gate trigger signal based on the final duty cycle.

[0286] In one possible implementation, the determination module 602 is specifically used for:

[0287] Obtain multiple preset running state switching conditions, and associate each running state switching condition with the corresponding target running state;

[0288] The preset state machine logic determines whether the start command, stop command, status identifier information, handle position information, and actual power command value meet any of the conditions in the operation state switching conditions.

[0289] If the conditions are met, the current running state will be updated to the target running state associated with the met conditions.

[0290] In one possible implementation, the analysis module 603 is specifically used for:

[0291] When the current operating state is a discharge-type operating state, the bus voltage is used as the voltage loop feedback value. The difference between the voltage loop feedback value and the sum of the network command voltage and the voltage loop reference value offset is calculated to obtain the voltage loop error.

[0292] When the current operating state is charging mode, the battery voltage is used as the voltage loop feedback value. The difference between the sum of the network command voltage and the voltage loop reference value bias and the voltage loop feedback value is calculated to obtain the voltage loop error.

[0293] The voltage loop error is calculated using proportional-integral control parameters of the voltage loop to obtain the reference value of the current loop.

[0294] In one possible implementation, the analysis module 603 is specifically used for:

[0295] Subtract the current loop reference value from the inductor current to obtain the current loop error;

[0296] The base duty cycle is obtained by performing proportional-integral calculations on the current loop error using the current loop proportional-integral control parameters.

[0297] The voltage difference between the upper and lower busbars is obtained based on the voltage division between the upper and lower busbars.

[0298] The difference between the upper and lower busbars is filtered to obtain the filtered difference.

[0299] The equalization compensation amount is obtained by performing proportional-integral calculation on the filtered difference using preset equalization ring proportional-integral control parameters.

[0300] In one possible implementation, the analysis module 603 is further configured to:

[0301] Obtain the preset cutoff frequency for filtering;

[0302] The difference between the upper and lower buses is subjected to a first-order low-pass filter operation based on the preset cutoff frequency to obtain the filtered difference.

[0303] In one possible implementation, the generation module 604 is specifically used for:

[0304] Monitor the current operating status;

[0305] When a change in the current operating state is detected, the base duty cycle is adjusted;

[0306] The adjusted base duty cycle is superimposed with the equalization compensation to obtain the final duty cycle.

[0307] In one possible implementation, the generation module 604 is further configured to:

[0308] Obtain the preset ramp start rate and preset stop ramp;

[0309] When the current operating state switches from stopped to started, the foundation duty cycle is adjusted linearly according to the preset ramp start rate to obtain the adjusted foundation duty cycle;

[0310] When the current operating state switches from start to stop, the base duty cycle is linearly reduced according to the preset stop slope to obtain the adjusted base duty cycle.

[0311] In one possible implementation, the generation module 604 is further configured to:

[0312] Acquire multiple physical quantity sample values, including voltage sample values, current sample values, and temperature sample values;

[0313] The sampled values ​​of physical quantities and the network command voltage are filtered and analyzed to obtain state data;

[0314] Extract fault characteristic parameters from the status data and compare the fault characteristic parameters with preset protection thresholds;

[0315] When the fault characteristic parameters exceed the preset protection threshold, a derating operation command or alarm command is generated.

[0316] In one possible implementation, the generation module 604 is further configured to:

[0317] Extract battery voltage polarity characteristic parameters. When the battery voltage polarity characteristic parameters meet the preset reverse connection conditions and continue for a preset first duration, generate a polarity reverse connection fault signal.

[0318] The deviation between the electrical sample value and the network command voltage is calculated. When the deviation exceeds the preset deviation threshold and continues for a preset second duration, a sampling deviation fault signal is generated.

[0319] In one possible implementation, the generation module 604 is specifically used for:

[0320] Determine the corresponding gate conduction combination based on the current operating status;

[0321] Multiple gate trigger signals are generated based on the final duty cycle and gate conduction combination;

[0322] When the current operating state is a discharge-type operating state, the gate trigger signal corresponding to the boost channel is opened, and the gate trigger signal corresponding to the buck channel is blocked;

[0323] When the current operating state is charging mode, the gate trigger signal corresponding to the buck channel is opened, and the gate trigger signal corresponding to the boost channel is blocked.

[0324] The three-level bidirectional DC-DC converter control device provided in this embodiment can execute the method provided in the above-described method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0325] Figure 7 A schematic diagram of the structure of the electronic device provided in this application. Figure 7 As shown, the electronic device 70 provided in this embodiment includes at least one processor 701 and a memory 702. Optionally, the device 70 further includes a communication component 703. The processor 701, memory 702, and communication component 703 are connected via a bus 704.

[0326] In a specific implementation, at least one processor 701 executes computer execution instructions stored in memory 702, causing at least one processor 701 to perform the above-described method.

[0327] The specific implementation process of processor 701 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0328] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0329] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0330] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0331] This application also provides a three-level bidirectional DC-DC converter, comprising:

[0332] The DC bus side capacitor bank includes a first capacitor and a second capacitor connected in series, with the midpoint between the first capacitor and the second capacitor leading out.

[0333] A switching transistor group, comprising multiple switching transistors, is connected to an inductor to form a boost path and a buck path;

[0334] The control module is used to execute the above method to generate a gate trigger signal based on the current operating state and control the conduction combination of the switching transistor group.

[0335] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0336] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0337] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0338] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0339] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0340] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0341] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0342] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0343] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0344] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A control method for a three-level bidirectional DC-DC converter, characterized in that, include: The system acquires a set of operating instructions, electrical sampling values, and network command voltages. The set of operating instructions includes start instructions, stop instructions, status identification information, handle position information, and actual power command values. The electrical sampling values ​​include bus voltage, battery voltage, inductor current, and voltage divider between upper and lower buses. The current running state is obtained by combining and judging the information in the running instruction set through a preset state machine logic; Extract the voltage loop reference value bias, voltage loop proportional-integral control parameters, and current loop proportional-integral control parameters corresponding to the current operating state from the preset control parameter library; Based on the current operating state, the network command voltage, the voltage loop reference value bias, the bus voltage, and the battery voltage, the current loop reference value is obtained through voltage loop proportional-integral control. The base duty cycle and voltage equalization compensation amount are obtained based on the current loop proportional-integral control parameters, the current loop reference value, the inductor current, and the voltage division of the upper and lower busbars. The base duty cycle is superimposed with the equalization compensation amount to obtain the final duty cycle, and a gate trigger signal is generated based on the final duty cycle.

2. The method according to claim 1, characterized in that, The current running state is obtained by combining and judging information from the set of running instructions through a preset state machine logic, including: Obtain multiple preset running state switching conditions, and associate each running state switching condition with a corresponding target running state; The system uses a preset state machine logic to determine whether the start command, stop command, status identifier information, handle position information, and actual power command value satisfy any of the conditions in the operation state switching conditions. If the conditions are met, the current running state is updated to the target running state associated with the met conditions.

3. The method according to claim 2, characterized in that, Based on the current operating state, the network command voltage, the voltage loop reference bias, the bus voltage, and the battery voltage, the current loop reference value is obtained through voltage loop proportional-integral control, including: When the current operating state is a discharge-type operating state, the bus voltage is used as the voltage loop feedback value, and the difference between the voltage loop feedback value and the sum of the network command voltage and the voltage loop reference value bias is calculated to obtain the voltage loop error; When the current operating state is a charging operating state, the battery voltage is used as the voltage loop feedback value. The difference between the sum of the network command voltage and the voltage loop reference value bias and the voltage loop feedback value is calculated to obtain the voltage loop error. The voltage loop error is calculated by performing proportional-integral operation on the voltage loop proportional-integral control parameters to obtain the current loop reference value.

4. The method according to claim 3, characterized in that, The base duty cycle and voltage equalization compensation amount are obtained based on the current loop proportional-integral control parameters, the current loop reference value, the inductor current, and the voltage division of the upper and lower buses, including: Subtracting the current loop reference value from the inductor current yields the current loop error; The base duty cycle is obtained by performing proportional-integral calculation on the current loop error using the current loop proportional-integral control parameters. The voltage difference between the upper and lower busbars is obtained based on the voltage division of the upper and lower busbars. The difference between the upper and lower busbars is filtered to obtain the filtered difference. The voltage equalization compensation amount is obtained by performing proportional-integral calculation on the filtered difference using preset proportional-integral control parameters of the voltage equalization loop.

5. The method according to claim 4, characterized in that, The difference between the upper and lower busbars is filtered to obtain the filtered difference, including: Obtain the preset cutoff frequency of the filtering process; The difference between the upper and lower busbars is subjected to a first-order low-pass filter operation based on the preset cutoff frequency to obtain the filtered difference.

6. The method according to claim 1, characterized in that, The step of superimposing the base duty cycle with the equalization compensation amount to obtain the final duty cycle includes: Monitor the current operating status; When the change in the current operating state is detected, the basic duty cycle is adjusted; The adjusted base duty cycle is superimposed with the equalization compensation amount to obtain the final duty cycle.

7. The method according to claim 6, characterized in that, Adjusting the base duty cycle includes: Obtain the preset ramp start rate and preset stop ramp; When the current operating state switches from stop to start, the foundation duty cycle is adjusted linearly according to the preset ramp start rate to obtain the adjusted foundation duty cycle. When the current operating state switches from start to stop, the basic duty cycle is linearly reduced according to the preset stop slope to obtain the adjusted basic duty cycle.

8. The method according to claim 1, characterized in that, Before generating the gate trigger signal based on the final duty cycle, the process also includes: Acquire multiple physical quantity sample values, including voltage sample values, current sample values, and temperature sample values; The sampled values ​​of the physical quantities and the network command voltage are filtered and analyzed to obtain state data; Fault feature parameters are extracted from the status data, and the fault feature parameters are compared with a preset protection threshold. When the fault characteristic parameters exceed the preset protection threshold, a derating operation command or an alarm command is generated.

9. The method according to claim 8, characterized in that, Extracting fault characteristic parameters from the status data and comparing the fault characteristic parameters with a preset protection threshold includes: Extract battery voltage polarity characteristic parameters. When the battery voltage polarity characteristic parameters meet the preset reverse connection conditions and continue for a preset first duration, generate a polarity reverse connection fault signal. The deviation between the electrical sampled value and the network command voltage is calculated. When the deviation exceeds a preset deviation threshold and continues for a preset second duration, a sampling deviation fault signal is generated.

10. The method according to claim 1, characterized in that, Generate a gate trigger signal based on the final duty cycle, including: Determine the corresponding gate conduction combination based on the current operating state; Multiple gate trigger signals are generated based on the final duty cycle and the gate conduction combination; When the current operating state is a discharge-type operating state, the gate trigger signal corresponding to the boost channel is opened, and the gate trigger signal corresponding to the buck channel is blocked; When the current operating state is the charging operating state, the gate trigger signal corresponding to the buck channel is opened, and the gate trigger signal corresponding to the boost channel is blocked.

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