A passivation process for the isolation region of a crystalline silicon cell based on atomic layer deposition
By combining layered alumina deposition process with PECVD silicon nitride layer, the problems of insufficient density and adhesion of traditional ALD alumina technology in the passivation of crystalline silicon cell surface are solved, realizing efficient passivation of the isolation area of crystalline silicon cell and improving the stability and performance of the cell.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 云南润阳世纪光伏科技有限公司
- Filing Date
- 2026-02-24
- Publication Date
- 2026-06-19
AI Technical Summary
Existing atomic layer deposition alumina technology with a single process window cannot simultaneously meet the requirements of high passivation quality and high density when passivating the surface of high-efficiency crystalline silicon cells. Furthermore, traditional thin films have insufficient adhesion to subsequent dielectric layers, leading to an increased risk of interface failure, especially on complex stacked structures and large-size silicon wafers.
A layered alumina deposition process is adopted, in which a hydroxyl reaction substrate is formed on the surface of the silicon wafer by pre-activating it with water, two layers of alumina are deposited in steps, and the surface of the second layer is modified by hydroxylation. Combined with PECVD deposition of silicon nitride layer, strong chemical bonding is formed to improve adhesion and interface stability.
It achieves high-stability passivation of the isolation region of crystalline silicon solar cells, balancing passivation effect and reliability, increasing negative fixed charge density, reducing interface state density, and enhancing the film's resistance to damp heat and interface stability.
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Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor thin film deposition and surface / interface passivation technology for crystalline silicon photovoltaic devices, and particularly to a passivation process for the isolation region of crystalline silicon cells based on atomic layer deposition. Background Technology
[0002] Alumina is widely used for surface passivation of crystalline silicon solar cells due to its strong negative fixed charge (Qf) and low interface state density (Dit). However, existing atomic layer deposition (ALD) alumina technology with a single process window has limitations in meeting the increasingly comprehensive requirements for surface passivation in high-efficiency crystalline silicon solar cells. Specifically: 1. To achieve high passivation quality (high negative charge, low interface state), specific nucleation and growth conditions are often required, which may lead to insufficient film density and reduced reliability in humid and hot environments; conversely, pursuing high density may impair its passivation performance.
[0003] 2. The outermost surface of a traditional ALD (alumina oxide) thin film faces the subsequent dielectric layer (such as SiN). x Insufficient adhesion can lead to interface failure in subsequent processes or long-term use, affecting the long-term stability and yield of the product.
[0004] 3. The above problems are more prominent when applied to complex stacked structures (such as the tunneling oxide / polycrystalline silicon layer of TOPCon) or large-size silicon wafers. Traditional single-process technology cannot be optimized for different interfaces and growth stages.
[0005] Therefore, it is necessary to design a passivation process for the isolation region of crystalline silicon cells based on atomic layer deposition to solve the above problems. Summary of the Invention
[0006] The purpose of this invention is to provide a passivation process for the isolation region of crystalline silicon cells based on atomic layer deposition that is suitable for BC cells, TOPCon cells, etc., with high passivation efficiency and high density.
[0007] To achieve the above objectives, the present invention adopts the following technical solution: a passivation process for the isolation region of a crystalline silicon solar cell based on atomic layer deposition, comprising the following steps: S1. Water pre-activation is performed on the silicon wafer surface in the atomic layer deposition chamber; after water treatment, hydroxyl groups (-OH) are uniformly attached to the entire silicon substrate surface, providing an ideal reaction substrate for uniform nucleation of subsequent alumina deposition; S2. A first alumina layer with a thickness of d1 nm is deposited by using a cycle in which the water exposure time is longer than the trimethylaluminum exposure time, where 3≤d1≤5. This alumina layer provides relatively excellent electrical passivation performance and extremely high negative fixed charge density. S3. A second alumina layer with a thickness of d2nm is deposited on the surface of the first alumina layer by cycling with a trimethylaluminum exposure time longer than the water exposure time, where 4≤d2≤7. This alumina layer has good density and serves as a barrier layer, providing good resistance to damp heat and degradation. S4. The surface of the second alumina layer is modified by hydroxylation to form a hydroxyl termination layer; the outer surface of the second alumina layer is terminated with -OH to promote subsequent medium nucleation and interface stability, as well as to improve and reduce internal impurities, making it more compact; the hydroxylated surface can form strong chemical bonds (such as Si-O-Si bonds) with the silicon nitride layer deposited by subsequent PECVD, improving interlayer adhesion and interface stability. S5. PECVD is used to deposit a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride and silicon oxynitride stack.
[0008] As a further improved technical solution of the present invention, in step S1, N1 “water pulse-purge” cycles are used to treat the silicon wafer surface, where 2≤N1≤6, the water pulse time of each cycle is t1=100-500ms, and the purging time is T1=5-15s.
[0009] As a further improved technical solution of the present invention, in step S2, N2 cycles of "trimethylaluminum pulse-purge-water pulse-purge" deposition are performed, where 5≤N2≤15, the trimethylaluminum pulse time t2=50-150ms, the purge time T2=8-12s; the water pulse time t3=200-600ms, and the purge time T3=8-12s.
[0010] As a further improvement of the present invention, in step S2, the ratio of H2O to trimethylaluminum is greater than or equal to 3:2.
[0011] As a further improved technical solution of the present invention, in step S3, N3 cycles of "trimethylaluminum pulse-purge-water pulse-purge" deposition are performed, 8≤N3≤20, trimethylaluminum pulse t4=150-400ms, purge T4=8-12s; water pulse t5=80-150ms, purge T5=8-12s.
[0012] As a further improvement of the present invention, in step S3, the ratio of H2O to trimethylaluminum is less than 2:3.
[0013] As a further improved technical solution of the present invention, in step S4, the surface of the second alumina layer is treated with N4 “water pulse-purge” cycles, where 1≤N4≤4, the water pulse time of each cycle is t6=150-250ms, and the purging time is T6=8-10s.
[0014] As a further improved technical solution of the present invention, in step S5, the thickness of the silicon nitride layer is 50-80nm, the thickness of the silicon oxynitride layer is 50-70nm, and the thickness of the silicon nitride and silicon oxynitride stack is 50-80nm.
[0015] As can be seen from the above technical solutions, this invention achieves high-stability passivation of the isolation region of crystalline silicon solar cells by pre-activating the silicon wafer surface, combined with atomic layer deposition (ALD) layered alumina, and further performing PECVD to generate a covering film. The layered function from the interface to the film layer works synergistically, specifically achieving the following effects: the passivation effect and reliability are balanced; water pretreatment and the first alumina layer can provide better electrical passivation performance, improve the negative fixed charge of the alumina film, reduce the low interface state density, reduce the load current density, and improve the implicit open-circuit voltage of the overall device; the second alumina layer has high density, which can provide the device with better resistance to damp heat and improve chemical stability; the second water treatment can further reduce the defects of alumina, and the hydroxylated surface can form strong chemical bonds (such as Si-O-Si bonds) with the subsequently PECVD deposited silicon nitride layer, improving interlayer adhesion and interface stability. Detailed Implementation
[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to specific embodiments. Example
[0017] The silicon wafer is passivated using the following process: S1. Provide several double-sided textured silicon wafers and an ALD (Atomic Layer Deposition) cavity with an internal temperature of 275℃. Inside the ALD cavity, two "water pulse-purge" cycles are used to process the surface of the silicon wafers. The water pulse time for each cycle is t1=200ms and the purge time is T1=10s.
[0018] S2. Perform 13 cycles of "trimethylaluminum pulse-purge-water pulse-purge" deposition on the silicon wafer. The trimethylaluminum pulse time t2 = 150 ms, and the purge time T2 = 10 s; the water pulse time t3 = 225 ms, and the purge time T3 = 10 s; the ratio of H2O to trimethylaluminum is 3:2. The thickness of the deposited first alumina layer is 4.3 nm. S3. Perform 13 cycles of "trimethylaluminum pulse-purge-water pulse-purge" deposition on the silicon wafer to deposit a second alumina layer on the surface of the first alumina layer. The trimethylaluminum pulse t4 = 300ms, purge T4 = 10s; the water pulse t5 = 150ms, purge T5 = 10s. The ratio of H2O to trimethylaluminum is 1:2. The thickness of the second alumina layer is 5.5nm.
[0019] S4. The surface of the second alumina layer is treated using two "water pulse-purge" cycles. The water pulse time t6 = 200 ms for each cycle, and the purging time T... 6= 10s.
[0020] S5. Prepare the PECVD reaction chamber with an internal temperature of 300-350℃. Transfer the silicon wafer with completed ALD alumina deposition to the PECVD reaction chamber and deposit a silicon nitride layer with a thickness of 75nm (refractive index n≈2.05) using mainstream photovoltaic technology. The annealing temperature is 400℃ and the annealing time is 20min. Example
[0021] The silicon wafer is passivated using the following process: S1, Same as Example 1.
[0022] S2. Perform 15 cycles of "trimethylaluminum pulse-purge-water pulse-purge" deposition on the silicon wafer. The trimethylaluminum pulse time t2 = 150 ms, the purge time T2 = 10 s; the water pulse time t3 = 450 ms, the purge time T3 = 12 s; and the ratio of H2O to trimethylaluminum is 3:1. The thickness of the deposited first alumina layer is 4.5 nm. S3. Perform 15 cycles of "trimethylaluminum pulse-purge-water pulse-purge" deposition on the silicon wafer to deposit a second alumina layer on the surface of the first alumina layer. The trimethylaluminum pulse t4 = 450 ms, purge T4 = 10 s; the water pulse t5 = 150 ms, purge T5 = 10 s. The ratio of H2O to trimethylaluminum is 1:3. The thickness of the second alumina layer is 5.8 nm.
[0023] S4. The surface of the second alumina layer is treated using two "water pulse-purge" cycles. The water pulse time t6 = 200 ms for each cycle, and the purging time T... 6= 10s.
[0024] S5, same as Example 1.
[0025] Comparative Example 1 The silicon wafer is passivated using the following process: S1. Provide several double-sided textured silicon wafers and an ALD (Atomic Layer Deposition) chamber with an internal temperature of 275℃. Within the ALD chamber, perform 26 cycles of "trimethylaluminum pulse-purge-water pulse-purge" deposition on the silicon wafers. The trimethylaluminum pulse time t2 = 150ms, purge time T2 = 10s; the water pulse time t3 = 225ms, purge time T3 = 10s; and the ratio of H2O to trimethylaluminum is 3:2. The deposited alumina layer thickness is 9.8nm.
[0026] S2 is the same as S5 in Example 1.
[0027] Comparative Example 2 The silicon wafer is passivated using the following process: S1. Provide several double-sided textured silicon wafers and an ALD (Atomic Layer Deposition) chamber with an internal temperature of 275℃. Within the ALD chamber, perform 26 cycles of "trimethylaluminum pulse-purge-water pulse-purge" deposition on the silicon wafers. The trimethylaluminum pulse time t2 = 150ms, purge time T2 = 10s; the water pulse time t3 = 225ms, purge time T3 = 10s; and the ratio of H2O to trimethylaluminum is 3:2. The deposited alumina layer thickness is 9.8nm.
[0028] S2. Two "water pulse-purge" cycles are used to treat the surface of the alumina layer. The water pulse time t6 = 200ms for each cycle, and the purging time T. 6= 10s.
[0029] S3 is the same as S5 in Example 1.
[0030] Comparative Example 3 The silicon wafer is passivated using the following process: S1, Same as Example 1.
[0031] S3. Perform 13 cycles of "trimethylaluminum pulse-purge-water pulse-purge" deposition on the silicon wafer. The trimethylaluminum pulse t4 = 300ms, and the purge t4 = 10s; the water pulse t5 = 150ms, and the purge t5 = 10s. The ratio of H2O to trimethylaluminum is 1:2. The thickness of the first alumina layer is 5.5nm.
[0032] S2. Perform 13 cycles of "trimethylaluminum pulse-purge-water pulse-purge" deposition on the silicon wafer. The trimethylaluminum pulse time t2 = 150 ms, and the purge time T2 = 10 s; the water pulse time t3 = 225 ms, and the purge time T3 = 10 s; the ratio of H2O to trimethylaluminum is 3:2. The thickness of the deposited second alumina layer is 4.3 nm. S4-S5, same as Example 1.
[0033] The following performance tests were performed on the passivated silicon wafers of each embodiment and comparative example: carrier lifetime, implied open-circuit voltage (ImpliedVoc), implied fill factor (ImpliedFF), and dark saturation current density (J). 0 / 2 Please refer to Table 1 for the test results.
[0034] Table 1. Silicon wafer performance test data for the examples and comparative examples.
[0035] The data in the table clearly shows that the performance of Examples 1 and 2 is significantly better than that of Comparative Examples 1-3, indicating that the process of the present invention is effective in improving the passivation performance of silicon wafers. Specifically: 1. The carrier lifetimes of Examples 1 and 2 are 15009 μs and 17414 μs, respectively, which are much higher than those of the comparative examples (12157~12912 μs). This indicates that the water pre-activation and the first alumina layer in the examples reduce early defects and residual carbon, thereby increasing the carrier survival time. The second alumina layer improves network cross-linking and compactness, enhances stability under humid heat and slight chemical erosion, and provides a better passivation effect.
[0036] 2. J in the embodiment 0 / 2 The values were only 1.75 fA / cm² and 1.70 fA / cm², far lower than the comparative examples (2.18~2.31 fA / cm²). J 0 / 2 It is the most sensitive indicator of interface passivation effect; the lower the value, the weaker the interface composite. The low J value in the example... 0 / 2 Direct evidence shows that water pre-activation eliminates nucleation defects, and the first alumina layer reduces residual carbon and interface states, thereby significantly improving interface stability. In addition, the hydroxyl termination of the second alumina layer and the silicon nitride layer significantly improve metallization adhesion and crack resistance.
[0037] 3. The implicit open-circuit voltages of the embodiments are 745.2mV and 745.6mV, slightly higher than those of the comparative examples (742.6~743.2mV). This is because the dark saturation current density (J) of the embodiments is higher. 0 / 2 The lower value directly increased ImpliedVoc, reflecting a better interface passivation effect.
[0038] 4. The implicit fill factors of the embodiments are 87.17% and 87.37%, which are higher than those of the comparative examples (86.62%~86.78%). This indicates that the carrier collection efficiency of the embodiments is higher, which is a comprehensive manifestation of long minority carrier lifetime and high ImpliedVoc, indicating that the final battery fill factor (FF) is better.
[0039] The above embodiments are only used to illustrate the present invention and are not intended to limit the technical solutions described in the present invention. The understanding of this specification should be based on those skilled in the art. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still make modifications or equivalent substitutions to the present invention. All technical solutions and improvements that do not depart from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.
Claims
1. A passivation process for the isolation region of a crystalline silicon solar cell based on atomic layer deposition, characterized in that, Includes the following steps: S1. Water pre-activation of the silicon wafer surface within the atomic layer deposition cavity; S2. A first alumina layer with a thickness of d1 nm is deposited by using a cycle in which the water exposure time is longer than the trimethylaluminum exposure time, where 3≤d1≤5; S3. Using a cycle in which the exposure time of trimethylaluminum is longer than the exposure time of water, a second alumina layer with a thickness of d2nm is deposited on the surface of the first alumina layer, where 4≤d2≤7; S4. The surface of the second alumina layer is modified by hydroxylation to form a hydroxyl-terminated layer; S5. PECVD is used to deposit a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride and silicon oxynitride stack.
2. The passivation process for the isolation region of a crystalline silicon solar cell based on atomic layer deposition as described in claim 1, characterized in that: In step S1, the silicon wafer surface is treated with N1 "water pulse-purge" cycles, where 2≤N1≤6. The water pulse time for each cycle is t1=100-500ms and the purging time is T1=5-15s.
3. The passivation process for the isolation region of a crystalline silicon solar cell based on atomic layer deposition as described in claim 1, characterized in that: In step S2, N2 cycles of "trimethylaluminum pulse-purge-water pulse-purge" deposition are performed, with 5≤N2≤15. The trimethylaluminum pulse time t2=50-150ms and the purge time T2=8-12s; the water pulse time t3=200-600ms and the purge time T3=8-12s.
4. The passivation process for the isolation region of a crystalline silicon solar cell based on atomic layer deposition as described in claim 3, characterized in that: In step S2, the ratio of H2O to trimethylaluminum is greater than or equal to 3:
2.
5. The passivation process for the isolation region of a crystalline silicon solar cell based on atomic layer deposition as described in claim 1, characterized in that: In step S3, N3 cycles of "trimethylaluminum pulse-purge-water pulse-purge" deposition are performed, with 8≤N3≤20. The trimethylaluminum pulse t4 = 150-400ms, the purge T4 = 8-12s; the water pulse t5 = 80-150ms, the purge T5 = 8-12s.
6. The passivation process for the isolation region of a crystalline silicon solar cell based on atomic layer deposition as described in claim 5, characterized in that: In step S3, the ratio of H2O to trimethylaluminum is less than 2:
3.
7. The passivation process for the isolation region of a crystalline silicon solar cell based on atomic layer deposition as described in claim 1, characterized in that: In step S4, the surface of the second alumina layer is treated with N4 "water pulse-purge" cycles, where 1 ≤ N4 ≤ 4. The water pulse time t6 = 150-250 ms and the purging time T6 = 8-10 s for each cycle are 150-250 ms and 1-4 ms respectively.
8. The passivation process for the isolation region of a crystalline silicon solar cell based on atomic layer deposition as described in claim 1, characterized in that: In step S5, the thickness of the silicon nitride layer is 50-80 nm, the thickness of the silicon oxynitride layer is 50-70 nm, and the thickness of the silicon nitride and silicon oxynitride stack is 50-80 nm.