Miniature light emitting diode chip and micro display panel

Abstract

This invention relates to a miniature light-emitting diode (LED) chip and a microdisplay panel. The miniature LED chip includes: a driving backplane having conductive vias and a conductive circuit layer, the conductive vias being configured to electrically connect the conductive circuit layer to a conductive structure; a light-emitting region configured to emit light and including one or more miniature LEDs arranged in an array; a non-light-emitting region that does not emit light; a conductive structure disposed in the light-emitting region and the non-light-emitting region, electrically connecting the miniature LEDs to the conductive vias in the light-emitting region; and a first boundary structure configured to electrically isolate the conductive structure in the non-light-emitting region from the conductive structure in the light-emitting region. The miniature LED chip of this invention has a first boundary structure that electrically isolates or insulates the conductive structure in the non-light-emitting region from the conductive structure in the light-emitting region, reducing heat generation in the chip.

Description

Technical Field

[0001] This invention relates to the field of micro light-emitting diode technology, and more particularly to a micro light-emitting diode chip and a micro display panel. Background Technology

[0002] Micro-LED (Micro Light Emitting Diode) is an emerging display technology that miniaturizes traditional light-emitting diodes to the micrometer level and integrates these tiny LED arrays onto a single chip, thereby enabling the formation of high-density display panels.

[0003] However, the heat generation of existing miniature light-emitting diode chips still needs to be further reduced. Summary of the Invention

[0004] To address at least some of the problems mentioned above in the prior art, the present invention aims to provide a miniature light-emitting diode chip, comprising:

[0005] A drive backplane having conductive vias and a conductive wiring layer, the conductive vias being configured to electrically connect the conductive wiring layer to a conductive structure;

[0006] The light-emitting region is configured to emit light and includes one or more miniature light-emitting diodes arranged in an array.

[0007] Non-luminescent regions do not emit light;

[0008] A conductive structure disposed in the light-emitting region and the non-light-emitting region, wherein a micro-light-emitting diode is electrically connected to a conductive aperture in the light-emitting region; and

[0009] A first boundary structure is configured to electrically isolate the conductive structure in the non-light-emitting region from the conductive structure in the light-emitting region.

[0010] Furthermore, the non-luminescent region includes:

[0011] A first region, surrounding the light-emitting region, the first region having a conductive structure; and

[0012] The second region is not directly adjacent to the light-emitting region.

[0013] Furthermore, the first boundary structure electrically isolates the conductive structure in the first region from the conductive structure in the light-emitting region.

[0014] Furthermore, the conductive structure includes:

[0015] A second bonding metal layer, which electrically contacts a conductive hole; and

[0016] A first bonding metal layer is located above the second bonding metal layer and makes electrical contact with the micro light-emitting diode.

[0017] Furthermore, the conductive structure also includes:

[0018] A first conductive layer is disposed on top of a first bonding metal layer.

[0019] Furthermore, the first region also includes:

[0020] An insulating layer is disposed on the conductive structure;

[0021] A second conductive layer is disposed above the insulating layer; and

[0022] A top conductive metal layer is disposed on top of the second conductive layer.

[0023] Furthermore, the first boundary structure includes:

[0024] An electrical isolation section having a groove to separate the conductive structure in the non-light-emitting region from the conductive structure in the light-emitting region.

[0025] Furthermore, the electrical isolation portion is arranged in one or more of the following locations:

[0026] The boundary between the luminescent and non-luminescent areas; and

[0027] In the non-luminous area, at a certain distance from the luminous area.

[0028] Furthermore, when the non-luminescent region is at a certain distance from the luminescent region, the first boundary structure also includes:

[0029] The transition section is located between the light-emitting area and the electrically isolated section and is in electrical contact with the light-emitting area.

[0030] Furthermore, the width of the electrical isolation portion is not less than 2 μm, and its depth is 0.1-3 μm; and / or

[0031] The width of the transition section is 10um-100um.

[0032] Furthermore, the conductive hole is filled with a metal selected from one or more of copper, gold, and aluminum.

[0033] Furthermore, the electrical isolation portion also has the following structure arranged within the groove:

[0034] An insulating layer covers the inner side of the conductive structure in the first region and the side of the transition portion.

[0035] A second conductive layer is disposed above the insulating layer; and

[0036] A top conductive metal layer is disposed on top of the second conductive layer.

[0037] Furthermore, the transition section includes:

[0038] Conductive structure;

[0039] An insulating layer is disposed on the conductive structure;

[0040] A second conductive layer is disposed on top of the insulating layer; and

[0041] A top conductive metal layer is disposed on top of the second conductive layer.

[0042] Furthermore, the conductive structure of the transition portion is in electrical contact with the conductive structure of the light-emitting region.

[0043] Furthermore, the conductive structure of the transition section is disconnected from and does not contact the conductive structure of the first region.

[0044] Furthermore, the conductive structure of the transition portion includes:

[0045] A second bonding metal layer, which electrically contacts a conductive hole; and

[0046] A first bonding metal layer is located on top of the second bonding metal layer.

[0047] Furthermore, the conductive structure also includes:

[0048] A first conductive layer is disposed on top of a first bonding metal layer.

[0049] Furthermore, the insulating layer of the first region and the insulating layer of the transition portion are connected;

[0050] The second conductive layer of the first region is connected to the second conductive layer of the transition portion; and

[0051] The top conductive metal layer of the first region is connected to the top conductive metal layer of the transition portion.

[0052] Furthermore, the conductive circuit layer is electrically connected to an external power source.

[0053] Furthermore, the first region has a second boundary structure that electrically isolates the second region from the first region.

[0054] Furthermore, the second boundary structure consists of an insulating dielectric layer and the outer edge of the first region, wherein the insulating dielectric layer wraps around the outer edge of the first region.

[0055] Furthermore, the edge of the first region includes:

[0056] Conductive structure;

[0057] An insulating layer is located above the conductive structure;

[0058] A second conductive layer is located above the insulating layer, wherein the outer edge of the insulating layer extends outward relative to the second conductive layer;

[0059] A top conductive metal layer is located on the upper surface of the second conductive layer, the side surface of the second conductive layer, and the upper surface at the outer edge of the insulating layer.

[0060] Furthermore, the insulating dielectric layer covers the upper surface at the outer edge of the top conductive metal layer, the outer surface of the top conductive metal layer, the outer surface of the insulating layer, and the outer surface of the conductive structure.

[0061] Furthermore, the second region has a plurality of lead electrodes, which are in electrical contact with the drive backplate.

[0062] Furthermore, the top conductive metal layer is in electrical contact with the light-emitting region and with a portion of the lead electrode.

[0063] The present invention also provides a micro-display panel, comprising:

[0064] Miniature light-emitting diode chip;

[0065] A shielding layer is disposed on one side, two sides, three sides, or around the light-emitting area of ​​the micro LED chip;

[0066] A plastic encapsulation frame surrounds a micro LED chip, the plastic encapsulation frame exposing the light-emitting area and at least a partial shielding layer.

[0067] The present invention has at least the following beneficial effects:

[0068] (1) The micro light-emitting diode chip of the present invention has a first boundary structure that electrically isolates or insulates the conductive structure in the non-light-emitting region from the conductive structure in the light-emitting region, thereby disconnecting the conductive structure that originally served as the current path between the non-light-emitting region and the light-emitting region. As a result, there is no longer a current path from the conductive hole of the driving back plate to the conductive structure in the non-light-emitting region and then to the light-emitting region. Therefore, when the micro light-emitting diode in the light-emitting region is working, electrons or holes will no longer accumulate at the conductive hole below the non-light-emitting region, thereby significantly reducing the generation of chip heat and thus avoiding performance degradation or even damage to the micro light-emitting diode.

[0069] (2) When the first boundary structure cuts off the conductive structure, a groove is formed. Other layers of the light-emitting diode chip (such as insulating layer, conductive layer, metal layer, etc.) can also be deposited in the groove. The insulating layer deposited at the bottom of the groove will further promote the insulating effect of the groove, while the conductivity of other layers deposited on the insulating layer is basically unaffected by the groove.

[0070] (3) In this invention, when the groove is arranged at a certain distance from the light-emitting area in the non-light-emitting area, a transition portion is formed in the area within that distance. The transition portion is the electrical structure between the groove and the light-emitting area. The presence of the transition portion ensures that the light-emitting area is not damaged when the groove is etched. Since the width of the transition area is small, the number of conductive holes in the area is not large, thus avoiding excessive heat generation.

[0071] (4) In addition, by electrically isolating the conductive structures of the light-emitting area and the non-light-emitting area from each other, it is possible to prevent the normal operation of the light-emitting area from being affected by the failure of the conductive structure in the non-light-emitting area (such as leakage, short circuit, etc.). Attached Figure Description

[0072] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the embodiments of the invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0073] Figure 1A and 1B A schematic diagram of the structure of an existing micro light-emitting diode chip is shown;

[0074] Figure 2 A cross-sectional schematic diagram of a micro light-emitting diode chip according to an embodiment of the present invention is shown;

[0075] Figure 3 A top view schematic diagram of a miniature light-emitting diode chip according to an embodiment of the present invention is shown;

[0076] Figure 4 A schematic cross-sectional view of the first region according to an embodiment of the present invention is shown;

[0077] Figure 5 An example of an embodiment of the invention is shown along Figure 3 A cross-sectional view of line AA' in the middle;

[0078] Figure 6 A schematic diagram showing the current flow when the miniature light-emitting diode chip according to the present invention is in operation is shown;

[0079] Figure 7 An embodiment of the present invention is shown. Figure 3 Cross-sectional view at point B;

[0080] Figure 8 A cross-sectional schematic diagram of a third boundary structure according to an embodiment of the present invention is shown;

[0081] Figure 9 A top view schematic diagram of the light-emitting area of ​​a micro light-emitting diode chip according to an embodiment of the present invention is shown;

[0082] Figure 10 A top view schematic diagram of a current extension structure according to an embodiment of the present invention is shown;

[0083] Figure 11 A longitudinal cross-sectional schematic diagram of the light-emitting region of a micro light-emitting diode chip according to an embodiment of the present invention is shown;

[0084] Figure 12 A longitudinal cross-sectional schematic diagram of a current extension structure according to an embodiment of the present invention is shown;

[0085] Figure 13 A longitudinal cross-sectional schematic diagram of a current-extending structure according to another embodiment of the present invention is shown.

[0086] Figure 14 A longitudinal cross-sectional schematic diagram of a micro light-emitting diode chip according to another embodiment of the present invention is shown; and

[0087] Figure 15 A longitudinal cross-sectional schematic diagram of a micro-light-emitting diode chip with microlenses according to an embodiment of the present invention is shown. Detailed Implementation

[0088] It should be noted that the components in the accompanying drawings may be shown exaggerated for illustrative purposes and may not be to scale.

[0089] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0090] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0091] It should also be noted that, in the embodiments of the present invention, only a portion of the parts or components may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added as needed for specific scenarios.

[0092] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values ​​are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0093] It should also be noted that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not explicitly or implicitly suggest that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0094] Furthermore, the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step, and is not a limitation on the order of each step. In different embodiments of the present invention, the order of each step can be adjusted according to the process.

[0095] In this application, the term "configuration" refers to setting the shape, structure, material and / or function of a target object to achieve a desired technical effect. "Configuration" includes a variety of alternative technical means to achieve the technical effect, which become apparent from the teachings of this application.

[0096] In this invention, the term "horizontal profile" has the following meanings: for regular shapes, it refers to the horizontal dimension; for irregular shapes, it refers to the maximum horizontal dimension. For example, for a hemispherical microlens, its horizontal profile refers to its bottom diameter; for a cylindrical micro-light-emitting diode, its horizontal profile refers to the diameter of its cylindrical cross-section. The maximum horizontal profile refers to the maximum value of the aforementioned dimension.

[0097] First, we will explain the reasons for the heat generation of existing micro LED chips.

[0098] Figure 1A and 1B A schematic diagram of the structure of an existing micro light-emitting diode chip is shown.

[0099] like Figure 1A and 1BAs shown, a conventional micro LED chip includes a driving backplane 002 and a functional layer 001 disposed on the driving backplane. The driving backplane 002 and the functional layer 001 are connected by metal bonding and are electrically connected. A first metal bonding layer 011 is disposed on the lower surface of the functional layer 001, and a second metal bonding layer 021 is disposed on the upper surface of the driving backplane 002. The functional layer 001 is disposed on the driving backplane 002 by bonding the first metal bonding layer 011 and the second metal bonding layer 021.

[0100] The drive backplane 002 has multiple conductive holes 022, conductive lines 023, and electrodes 024. The conductive holes 022 are located below and electrically contact the second metal bonding layer 021. The electrodes 024 are located on the surface of the drive backplane 002. The conductive lines 023 are located within the drive backplane 002 and are electrically connected to both the conductive lines 023 and the electrodes 024. The electrodes 024 are not in contact with the second metal bonding layer 021.

[0101] Functional layer 001 includes a light-emitting region 012 and a non-light-emitting region 013. The non-light-emitting region 013 is located around the light-emitting region 012, surrounding and enclosing it. The light-emitting region 012 contains a plurality of micro light-emitting diodes arranged in an array. The micro light-emitting diodes are electrically connected to the first metal bonding layer 011.

[0102] The non-light-emitting region 013 has a lead electrode 014, which is used for bonding to the flexible circuit board leads during packaging. The lead electrode 014 is not electrically connected to the drive backplane 002 through the first metal bonding layer and the second metal bonding layer. Instead, the lead electrode 014 is in direct electrical contact with the electrode 024 of the drive backplane 002.

[0103] When the miniature LED chip is operating, current flows from the outside of the chip through the lead electrode 014 to the driving backplane 002, and then through the driving backplane 002 to the miniature LED. Under normal circumstances, the current flows through the conductive lines inside the driving backplane to the conductive hole 022 below the miniature LED, then through the second metal bonding layer 021 and the first metal bonding layer 011 below the miniature LED, and finally to the miniature LED.

[0104] Through research, the inventors discovered that because the first metal bonding layer 011 and the second metal bonding layer 021 directly below the non-light-emitting region 013 are electrically connected to the first metal bonding layer 011 and the second metal bonding layer 021 directly below the light-emitting region 012, and the second metal bonding layer 021 directly below the non-light-emitting region 013 is in electrical contact with the conductive hole, a portion of the current transmitted from the lead electrode 014 to the driving backplane is conducted through the conductive hole 022 to the first metal bonding layer 011 and the second metal bonding layer 021 directly below the non-light-emitting region, and then transmitted to the micro-light-emitting diode through the first metal bonding layer 011 and the second metal bonding layer 021. This causes electrons or holes to accumulate at the conductive hole 022 directly below the non-light-emitting region, generating heat. Since there are many conductive holes 022 directly below the non-light-emitting region, the amount of heat generated is significant, which may degrade chip performance or even damage the chip.

[0105] Figure 2 A cross-sectional schematic diagram of a micro light-emitting diode chip according to an embodiment of the present invention is shown; Figure 3 A top view schematic diagram of a miniature light-emitting diode chip according to an embodiment of the present invention is shown; Figure 4 A schematic cross-sectional view of the first region according to an embodiment of the present invention is shown; Figure 5 A schematic cross-sectional view along line AA' in FIG1 is shown according to an embodiment of the present invention.

[0106] like Figure 2 As shown, the miniature light-emitting diode chip includes a driving backplane 2 and a functional layer 1 disposed on the driving backplane. The driving backplane 2 and the functional layer 1 are connected by metal bonding and are electrically connected. The driving backplane 2 has multiple conductive holes 21 and a conductive circuit layer 22. The conductive holes 21 are located on the conductive circuit layer 22 and are in electrical contact with the conductive circuit layer 22. The metal filled in the conductive holes 21 is selected from one or more of copper, gold, and aluminum.

[0107] The driving backplane 2 can be, for example, a thin film transistor (TFT) board or an integrated circuit (IC) board.

[0108] like Figure 3 As shown, functional layer 1 includes a light-emitting region 12 and non-light-emitting regions (15, 16, 18). The non-light-emitting regions (15, 16, 18) are located around the light-emitting region 12, surrounding it. The light-emitting region 12 contains multiple micro-light-emitting diodes arranged in an array. The light-emitting region 12 also includes a conductive structure, which is electrically connected to the micro-light-emitting diodes and the conductive vias 21 of the driving backplane. The conductive wiring layer of the driving backplane is electrically connected to the conductive structure of the light-emitting region through the conductive vias.

[0109] The non-light-emitting regions include a first region 15 and a second region 16. The first region 15 surrounds the light-emitting region 12. The non-light-emitting regions have a conductive structure and a first boundary structure 20. The conductive structure is in electrical contact with the driving backplate 2, and the first boundary structure 20 is configured to electrically isolate the conductive structure of the non-light-emitting regions (15, 16, 18) from the conductive structure of the light-emitting region 12.

[0110] In some embodiments, such as Figure 4 As shown, the first region 15 includes a conductive structure 300, an insulating layer 123, a second conductive layer 124, and a top conductive metal layer 125 arranged sequentially from bottom to top.

[0111] An insulating layer 123 is located above the conductive structure 300. A second conductive layer 124 is located above the insulating layer 123. A top conductive metal layer 125 is located above the second conductive layer 124.

[0112] In some embodiments, the conductive structure 300 includes a first metal bonding layer 120, a second metal bonding layer 121, and a first conductive layer 122, wherein the first metal bonding layer 120 is located on the second metal bonding layer 121, and the first conductive layer 122 is located on the first metal bonding layer 120.

[0113] In other embodiments, the first region includes, from bottom to top, a conductive structure, an insulating layer, a second conductive layer, and a top conductive metal layer. The conductive structure includes a first metal bonding layer and a second metal bonding layer, with the first metal bonding layer located above the second metal bonding layer.

[0114] In some embodiments, the first boundary structure 20 serves as the boundary between the first region 15 and the light-emitting region 12, and also as the boundary between the light-emitting region 12 and the non-light-emitting region. The first boundary structure 20 surrounds the light-emitting region 12, and electrically isolates the conductive structure of the first region 15 from the conductive structure of the light-emitting region 12.

[0115] In some embodiments, such as Figure 5 As shown, the first boundary structure 20 includes an electrical isolation section 60 and a transition section 70. The electrical isolation section 60 is arranged in the first region 15 at a certain distance from the light-emitting region 12.

[0116] Both the electrical isolation portion 60 and the transition portion 70 surround the light-emitting region 10, with the transition portion 70 adjacent to the light-emitting region. The conductive structure of the transition portion 70 is in electrical contact with the conductive structure of the light-emitting region 12. The electrical isolation portion 60 is located between the transition portion 70 and the first region 15. Furthermore, the width of the electrical isolation portion 60 is not less than 2 micrometers, preferably 10 μm.

[0117] The transition portion 70 includes a conductive structure 300, an insulating layer 123, a second conductive layer 124, and a top conductive metal layer 125. The insulating layer 123 is located above the conductive structure 300. The second conductive layer 124 is located above the insulating layer 123. The top conductive metal layer 125 is located above the second conductive layer 124. The width of the transition portion 70 is 10µm-100µm.

[0118] In some embodiments, the conductive structure includes a first metal bonding layer 120, a second metal bonding layer 121, and a first conductive layer 122. The first metal bonding layer 120 is located above the second metal bonding layer 121. The first conductive layer 122 is located above the first metal bonding layer 120.

[0119] In other embodiments, the conductive structure includes a first metal bonding layer and a second metal bonding layer. The first metal bonding layer is located on top of the second metal bonding layer.

[0120] The electrical isolation section 60 has a groove to separate the conductive structure 300 in the first region 15 from the conductive structure in the light-emitting region 12. At the location of the electrical isolation section 60, the conductive structure 300 in the first region and the conductive structure in the light-emitting region are disconnected from each other and do not come into contact.

[0121] In addition, an insulating layer 123, a second conductive layer 124, and a conductive metal layer 125 are sequentially disposed within the electrical isolation section 60. The insulating layer 123 covers the inner surface of the conductive structure 300 in the first region and the side surface of the conductive structure 300 in the transition section 70.

[0122] The second conductive layer 124 within the electrical isolation section 60 is located above the insulating layer 123. The top conductive metal layer 125 is located above the second conductive layer 124.

[0123] Furthermore, the first bonding metal layer of the transition portion and the first bonding metal layer of the first region are disconnected from each other and do not contact each other, with a gap of at least 2 μm; the second bonding metal layer of the transition portion and the second bonding metal layer of the first region are disconnected from each other and do not contact each other, with a gap of at least 2 μm; the first conductive layer of the transition portion and the first conductive layer of the first region are disconnected from each other and do not contact each other, with a gap of at least 2 μm.

[0124] The electrical isolation portion 60 is recessed downward relative to the first region and the transition portion. The depth of the downward recess of the electrical isolation portion 60 is 0.1-3 μm, which is the same as or greater than the thickness of the conductive structure.

[0125] In other embodiments, the electrical isolation portion is arranged at the boundary between the light-emitting region and the non-light-emitting region, thus eliminating the transition portion. The electrical isolation portion separates the conductive structure of the first region from the conductive structure of the light-emitting region.

[0126] Furthermore, the insulating layer of the first region, the insulating layer of the electrically isolated portion, and the insulating layer of the transition portion are connected and deposited simultaneously. The second conductive layer of the first region, the second conductive layer of the electrically isolated portion, and the second conductive layer of the transition portion are connected and deposited simultaneously. The conductive metal layer of the second region, the conductive metal layer of the electrically isolated portion, and the conductive metal layer of the transition portion are connected and deposited simultaneously.

[0127] In some embodiments, the second region 16 includes a plurality of lead electrodes 17. The lead electrodes are used for wire bonding to external circuit board leads during packaging. The lead electrodes 17 are not electrically connected to the drive backplane 2 through conductive structures in the non-light-emitting area; instead, the lead electrodes 17 are in direct electrical contact with the drive backplane 2.

[0128] In some embodiments, the drive backplane 2 further includes electrodes electrically connected to the conductive wiring layer in the drive backplane 2. The electrodes of the drive backplane 2 are located directly below the lead electrode 17, and the lead electrode 17 is in electrical contact with the electrodes of the drive backplane 2.

[0129] In some embodiments, the second region 16 further includes a plurality of test electrodes 18, which are electrically in contact with the drive backplane. The test electrodes 18 are used to electrically connect to a test device when testing the chip. Further, the size of the test electrodes 18 is smaller than the size of the lead electrodes 17. Further, the plurality of test electrodes 18 are located on both sides of the area occupied by the plurality of lead electrodes 17.

[0130] Figure 6 A schematic diagram showing the current flow when the micro light-emitting diode chip according to the present invention is in operation is shown.

[0131] like Figure 6 As shown, after the micro LED chip is electrically connected to the external circuit board, during operation, the current is transmitted through the lead electrode 17 to the electrode 23 of the driving backplate 2, from the electrode 23 of the driving backplate 2 to the conductive line layer 22 inside the driving backplate 2, and then through the conductive line layer 22 to the conductive hole 21 below the micro LED in the light-emitting area 12, and then through these conductive holes to the conductive structure 300 below, and finally through the conductive structure 300 below the micro LED to the micro LED.

[0132] Due to the presence of the electrical isolation portion of the first boundary structure, the conductive structure 300 in the non-light-emitting region is not connected to the conductive structure 300 in the light-emitting region 12. Current will not be transmitted from the conductive hole 21 of the driving backplate to the conductive structure 300 in the non-light-emitting region and then to the micro light-emitting diode in the light-emitting region 12. Therefore, electrons or holes will not accumulate at the multiple conductive holes directly below the non-light-emitting region, thereby significantly reducing the generation of chip heat.

[0133] Furthermore, by electrically isolating the conductive structures of the light-emitting area from those of the non-light-emitting area, it is possible to prevent the normal operation of the light-emitting area from being affected by malfunctions (such as leakage or short circuits) in the conductive structures of the non-light-emitting area.

[0134] In some embodiments, such as Figure 5 As shown, the first region 15 has a second boundary structure 30, which is the boundary between the first region 15 and the second region 16, and the second boundary structure 30 electrically isolates the first region 15 and the second region 16.

[0135] The second boundary structure 30 consists of an insulating dielectric layer 126 and the edge of the second region. The insulating dielectric layer 126 wraps around the outer edge of the first region, and the edge of the second region is the part covered by the insulating dielectric layer 126.

[0136] The edge of the second boundary structure 30 includes a conductive structure 300, an insulating layer 123, a second conductive layer 124, and a conductive metal layer 125.

[0137] The conductive structure 300 includes a first metal bonding layer 120, a second metal bonding layer 121, and a first conductive layer 122.

[0138] The first metal bonding layer 120 is located on the upper surface of the second metal bonding layer 121.

[0139] The first conductive layer 122 is located on the upper surface of the first bonding metal layer 120. Furthermore, the outer edge of the first conductive layer 122 is flush with the outer edge of the first bonding metal layer 120.

[0140] The insulating layer 123 is located on the upper surface of the first conductive layer 122. Furthermore, the outer edge of the conductive structure 300 extends outward relative to the insulating layer 123 by a certain distance.

[0141] The second conductive layer 124 is located on the upper surface of the insulating layer 123. Furthermore, the outer edge of the insulating layer 123 extends outward relative to the second conductive layer 124 by a certain distance.

[0142] The top conductive metal layer 125 is located on the upper surface of the outer edge of the second conductive layer 124, the side surface of the second conductive layer 124, and the upper surface of the insulating layer 123.

[0143] Furthermore, the outer edge of the top conductive metal layer 125 is flush with the outer edge of the insulating layer 123.

[0144] The insulating dielectric layer 126 covers the side of the top conductive metal layer 125, the side of the insulating isolation layer 123, the surface of the first conductive layer 122 facing away from the first bonding metal layer 120, the side of the first conductive layer 122, the outer side of the first bonding metal layer 120, and the outer side of the second metal bonding layer 121.

[0145] In other embodiments, the edge of the second boundary structure includes a conductive structure, an insulating layer, a second conductive layer, and a conductive metal layer. The conductive structure includes a first metal bonding layer and a second metal bonding layer.

[0146] Figure 3 A top view schematic diagram of a micro light-emitting diode chip according to an embodiment of the present invention is shown. Figure 7 An embodiment of the present invention is shown. Figure 3 A cross-sectional view at point B.

[0147] like Figure 3 As shown, the miniature light-emitting diode chip also includes a chip boundary structure 40, which surrounds the functional layer. The chip boundary structure 40 is a frame with a certain width surrounding the chip. The chip boundary structure 40 is electrically isolated from the non-light-emitting area of ​​the functional layer.

[0148] like Figure 7 As shown, the chip boundary structure 40 includes a boundary metal structure 41 with a cross-section on its outer side; and a protective layer 42 disposed on the outer side of the boundary metal structure 41 to protect the outer side from etching. It should be noted that "outer side" refers to the side away from the light-emitting area.

[0149] The boundary metal structure 41 is located on the driving backplate 2. The boundary metal structure 41 includes a first bonding metal layer 120 and a second bonding metal layer 121. The first bonding metal layer 120 is located on the second bonding metal layer 121. In some embodiments, the protective layer 42 covers the outer side of the boundary metal structure 41; or covers the outer side of the boundary metal structure 41 and the area beyond the outer side. It should be noted that "outer side" refers to the side away from the light-emitting area.

[0150] The material of protective layer 42 is an insulating dielectric material, selected from SiN and SiO. x Al y O z It is one or more of AlN, where x = 1-3, y = 1-3, z = 2-4. The thickness of the protective layer 42 is 0.1-3 μm.

[0151] In some embodiments, the chip boundary structure 40 further includes a first conductive layer 122, a semiconductor layer 127, a transparent conductive layer 128, an isolation insulating layer 123, and an insulating dielectric layer 126.

[0152] The first conductive layer 122 is disposed on the first bonding metal layer 120.

[0153] An epitaxial layer 127 is disposed on top of the first conductive layer 122. The epitaxial layer 127 is configured as a non-light-emitting dummy layer. The bottom dimension of the epitaxial layer 127 is larger than its top dimension. Further, the bottom dimension of the epitaxial layer 127 is smaller than the dimension of the first conductive layer 122. The presence of the epitaxial layer 127 in the chip boundary structure 40 increases the height of the chip boundary structure 40, thereby increasing the height difference between the chip boundary structure 40 and the dicing track. This results in a significant height difference between the chip boundary structure 40 and the dicing track, facilitating the positioning of the dicing track when dicing the chip along it.

[0154] A transparent conductive layer 128 is disposed on top of the epitaxial layer 127.

[0155] In some embodiments, the protective layer 42 covers the outer surfaces of the first bonding metal layer 120, the second bonding metal layer 121 and the epitaxial layer 127, as well as the upper surface of the transparent conductive layer 128.

[0156] In some embodiments, the insulating layer 123 covers the protective layer 42, the inner side of the epitaxial layer 127, a portion of the upper surface of the first bonding metal layer 120, the inner side of the first bonding metal layer 120, and the inner side of the second bonding metal layer 121. It should be noted that "inner side" refers to the side closer to the light-emitting region.

[0157] In some embodiments, the insulating dielectric layer 126 is located on the upper surface of the insulating layer 123.

[0158] In some embodiments, the outer edge of the drive backplate 2 extends beyond the outer edge of the boundary metal structure 41, such that a portion of the edge of the drive backplate 2 is not covered by the boundary metal structure 41. The drive backplate 2 has a metal structure 24 at its edge, and the protective layer 42 also covers the edge of the drive backplate 2 that is not covered by the boundary metal structure 41 to protect the metal structure from etching.

[0159] The manufacturing process of micro LED chips involves a series of fabrication processes on a wafer-by-wafer basis, with hundreds of chips being produced simultaneously. Once all the chip layers are fabricated, the wafer is diced into individual chips along dicing lines. The dicing line is the area between the boundary structures of two chips on the wafer.

[0160] In chip fabrication, a transparent conductive layer, an epitaxial layer, a first conductive layer, and a first bonding metal layer are first deposited on a wafer. A second bonding metal layer is then deposited on a driving backplane. The multilayer structure on the wafer is then transferred to the driving backplane via bonding. Next, dicing lines are fabricated. On a chip-by-chip basis, the transparent conductive layer, epitaxial layer, first conductive layer, first bonding metal layer, and second bonding metal layer are etched sequentially to disconnect the transparent conductive layer, epitaxial layer, first conductive layer, first bonding metal layer, and second bonding metal layer between chips. This also removes metal from the dicing lines to facilitate subsequent chip dicing. Then, a protective layer is deposited on a wafer-by-wafer basis, covering the entire wafer and the outer surfaces of the first and second bonding metal layers, the second conductive layer, the epitaxial layer, the transparent conductive layer, and the top surface. Finally, the chip fabrication process is performed, sequentially etching the protective layer, transparent conductive layer, and epitaxial layer to remove portions of the protective layer, transparent conductive layer, and epitaxial layer located in non-light-emitting areas. The etching process preserves the transparent conductive layer, epitaxial layer, and protective layer located at the edge of the chip. The protective layer covers the outer surfaces of the first and second bonding metal layers located at the chip edge, the outer surface of the epitaxial layer, and the upper and outer surfaces of the transparent conductive layer.

[0161] Subsequent chip manufacturing processes include etching processes, such as etching the epitaxial layer located in the light-emitting region to form a light-emitting mesa.

[0162] A protective layer covering the outer surfaces of the first and second bonding metal layers is retained at the chip edge to protect these outer surfaces from etching in subsequent processes. If the protective layer, transparent conductive layer, and epitaxial layer located in a portion of the non-light-emitting area are not retained at the chip edge, the outer surfaces of the first and second bonding metal layers will be exposed. During the etching process in subsequent chip manufacturing, these outer surfaces will be etched, releasing metal particles. These metal ions may diffuse onto the light-emitting mesa of the micro-LED, affecting its light emission.

[0163] Similarly, the portion of the drive backplate 2 that extends beyond the outer edge of the boundary metal structure 41 is covered by the protective layer 42, which also prevents the metal structure on the surface of the drive backplate 2 from being etched.

[0164] The deposition of the isolation insulating layer and the insulating dielectric layer is performed after the fabrication of the light-emitting mesa. Following the deposition of the isolation insulating layer and the insulating dielectric layer, chip surface structure fabrication steps involving etching processes are performed. The isolation insulating layer and the insulating dielectric layer located at the chip edge are retained, and the isolation insulating layer and the insulating dielectric layer at the chip edge are covered with a protective layer to further protect the outer surfaces of the first bonding metal layer and the second bonding metal layer.

[0165] like Figure 3 As shown, functional layer 2 also includes a chip alignment region 18. The chip alignment region 18 is used for alignment in each photolithography process during chip manufacturing. A first region 12 surrounds the chip alignment region 18. Functional layer 2 also includes a third boundary structure 50 that serves as the boundary between the first region 12 and the chip alignment region 18.

[0166] Figure 8 A cross-sectional schematic diagram of a third boundary structure according to an embodiment of the present invention is shown.

[0167] In some embodiments, such as Figure 8 As shown, the third boundary structure 50 is located on the drive backplate 2. The third boundary structure 50 includes a first bonding metal layer 120 and a second bonding metal layer 121, as well as a first boundary portion 51, a second boundary portion 52, and a third boundary portion 53 disposed on the first bonding metal layer 120. The second boundary portion 52 is located between the first boundary portion 51 and the third boundary portion 53.

[0168] The first bonding metal layer 120 is located on the second bonding metal layer 121, and the second bonding metal layer 121 is in electrical contact with the conductive hole 21 of the driving backplate 2.

[0169] The first boundary portion 51 includes a first conductive layer 122, an insulating layer 123, a second conductive layer 124, a top conductive metal layer 125, and an insulating dielectric layer 126, which are arranged sequentially.

[0170] The first conductive layer 122 is located on the first bonding metal layer 120.

[0171] The insulating layer 123 is located above the first conductive layer 122.

[0172] The second conductive layer 124 is located above the insulating layer 123. The insulating layer 123 extends outward relative to the second conductive layer 124 by a certain distance.

[0173] The top conductive metal layer 125 is located on the upper surface of the second conductive layer 124 and the upper surface of the insulating layer 123.

[0174] The insulating dielectric layer 126 covers the upper surface and sides of the top conductive metal layer 125.

[0175] The second boundary portion 52 includes a first conductive layer 122, an insulating layer 123, and an insulating dielectric layer 126 arranged sequentially.

[0176] The first conductive layer 122 is located on the first bonding metal layer 121.

[0177] The insulating layer 123 is located above the first conductive layer 122.

[0178] The insulating dielectric layer 126 is located above the insulating isolation layer 123.

[0179] The third boundary portion 53 includes a first conductive layer 122, an epitaxial layer 127, a transparent conductive layer 128, an insulating layer 123, and an insulating dielectric layer 126 arranged sequentially.

[0180] The first conductive layer 122 is located on the first bonding metal layer 121.

[0181] The epitaxial layer 127 is located on the first conductive layer 122.

[0182] The transparent conductive layer 128 is located on the epitaxial layer 127.

[0183] The insulating layer 123 is located on top of the insulating layer 123.

[0184] The insulating dielectric layer 126 is located above the insulating isolation layer 123.

[0185] The first conductive layer 122 of the first boundary portion 51, the second boundary portion 52, and the third boundary portion 53 is connected. The insulating layer 123 of the first boundary portion 51, the second boundary portion 52, and the third boundary portion 53 is connected. The insulating dielectric layer 126 of the first boundary portion 51, the second boundary portion 52, and the third boundary portion 53 is connected.

[0186] The present invention also provides a micro light-emitting diode wafer comprising the aforementioned plurality of micro light-emitting diode chips and dicing channels. Further, the dicing channel between two adjacent micro light-emitting diode chips has multiple metal structures.

[0187] The present invention also provides a micro display panel comprising a micro light-emitting diode chip, a shielding layer, and a plastic encapsulation frame.

[0188] In some embodiments, the shielding layer is disposed on one side, two sides, three sides, or around the light-emitting area of ​​the micro LED chip; further, the inner edge of the shielding layer is flush with or extends beyond the inner edge of the top conductive metal layer.

[0189] In some embodiments, a plastic encapsulation frame surrounds the packaged micro LED chip, with the encapsulation frame exposing the light-emitting area and at least a partial shielding layer.

[0190] When packaging a miniature LED chip, there will be non-light-emitting areas that are not encapsulated by the plastic encapsulation frame. To prevent reflection from the exposed top conductive metal layer of the non-light-emitting area, a shielding layer made of black light-absorbing material is needed to pre-shield the exposed top conductive metal layer. The plastic encapsulation frame surrounds the packaged miniature LED chip, exposing the light-emitting area and at least part of the shielding layer.

[0191] The location of the shielding layer is determined based on the position of the exposed top conductive metal layer. If the top conductive metal layer is exposed on all four sides of the light-emitting area, a shielding layer can be placed around the perimeter of the light-emitting area. If the top conductive metal layer is exposed on two adjacent or opposite sides of the light-emitting area, a shielding layer needs to be placed on the opposite or adjacent sides of the light-emitting area. If the top conductive metal layer is exposed on three or one side of the light-emitting area, a shielding layer should be placed on three or one side of the light-emitting area. The shielding layer needs to completely cover the top conductive metal layer not covered by the plastic encapsulation frame. The edge of the shielding layer can be flush with the inner edge of the top conductive metal layer, or it can extend beyond the inner edge of the top metal layer, covering a portion of the light-emitting area, for example, extending 5 micrometers beyond the inner edge of the top conductive metal layer into the light-emitting area.

[0192] Each microLED chip has a size not exceeding 1 cm, preferably not exceeding 20 micrometers. MicroLEDs are formed in an array within the microLED chip, with resolutions such as 720*480, 640*480, 1920*1080, 1280*720, 2K, or 4K. The diameter of the microLED structure is in the nanometer range, for example, 20 nm to 100 nm. Each microLED can form at least a portion of the pixel elements on the microLED chip.

[0193] In some embodiments, the spacing of the micro-LED array, i.e. the minimum center-to-center distance between the micro-LEDs, can be between about 2 micrometers and about 50 micrometers.

[0194] In some embodiments, the number of pixels on a micro LED chip can range from thousands to millions.

[0195] The following section details the light-emitting area of ​​a miniature LED chip.

[0196] Figure 9 A top view schematic diagram of the light-emitting area of ​​a micro light-emitting diode chip according to an embodiment of the present invention is shown; Figure 10 A top view schematic diagram of a current extension structure according to an embodiment of the present invention is shown; Figure 11 A longitudinal cross-sectional schematic diagram of the light-emitting region of a micro light-emitting diode chip according to an embodiment of the present invention is shown.

[0197] like Figure 9 and11 As shown, the current extension structure 102 is located between the miniature light-emitting diodes 101 in the light-emitting area. The current extension structure 102 surrounds the miniature light-emitting diodes 101. The current extension structure 102 is electrically connected to the miniature light-emitting diodes 101.

[0198] like Figure 11 As shown, the miniature light-emitting diode 101 includes a first transparent conductive layer 104, a light-emitting mesa 103, an insulating layer 105, and a second transparent conductive layer 106.

[0199] In an embodiment of the present invention, the light-emitting platform 103 is located between the first transparent conductive layer 104 and the second transparent conductive layer 106. The light-emitting platform 103 is located on the first transparent conductive layer 104, and the first transparent conductive layer 104 is in contact with the bottom surface of the light-emitting platform 103.

[0200] The size of the first transparent conductive layer 104 is larger than the size of the light-emitting platform 103.

[0201] In an embodiment of the present invention, the second transparent conductive layer 106 is located on the top and side of the light-emitting platform 103, and the second transparent conductive layers 106 of all micro light-emitting diodes are electrically connected to each other. The second transparent conductive layer 106 is also electrically connected to the current spreading structure 102.

[0202] In embodiments of the present invention, the material of the first transparent conductive layer 104 and / or the second transparent conductive layer 106 may include indium tin oxide (In2O5Sn), thereby improving conductivity and light emission.

[0203] It should be noted that the materials of the first transparent conductive layer 104 and / or the second transparent conductive layer 106 may also include other suitable materials, such as fluorine-doped tin oxide (FTO) or zinc oxide (ZnO).

[0204] In an embodiment of the present invention, the insulating layer 105 is located on the side of the light-emitting platform 103 and the side of the first transparent conductive layer 104, and the insulating layers 105 of all the micro-light-emitting diodes are interconnected. The insulating layer 105 is used to isolate the first transparent conductive layer 104 and the second transparent conductive layer 106. Furthermore, the insulating layer 105 is transparent.

[0205] In other embodiments, the insulating layer 105 covers the side surface of the first transparent conductive layer 104, the side surface of the light-emitting platform 103, and a portion of the top area.

[0206] Since the size of the first transparent conductive layer 104 is larger than the size of the bottom of the light-emitting platform 103, a step is formed. The insulating layer 105 and the second transparent conductive layer 106 cover the sides of the first transparent conductive layer 104 and the light-emitting platform 103. Due to the step at the first transparent conductive layer 104, there will also be steps in the insulating layer 105 and the second transparent conductive layer 106.

[0207] In an embodiment of the present invention, the bottom dimension of the light-emitting platform 103 is larger than the top dimension of the light-emitting platform 103. It should be noted that the transverse cross-sectional shape of the light-emitting platform 103 is not limited to a circle, but may also be other suitable shapes, such as rectangles, squares, or polygons.

[0208] like Figure 11 As shown, the light-emitting mesa 103 includes a first type epitaxial layer 1031, a second type epitaxial layer 1032, and a light-emitting layer 1033 located between the two.

[0209] In an embodiment of the present invention, a first type epitaxial layer 1031 is located above the light-emitting layer 1033, and a second type epitaxial layer 1032 is located below the light-emitting layer 1033. The second type epitaxial layer 1032 is electrically connected to the first transparent conductive layer 104, and the first type epitaxial layer 1031 is electrically connected to the second transparent conductive layer 106.

[0210] In some embodiments, the light-emitting layer is formed of a plurality of stacked quantum well layers, particularly superlattice stacked quantum well layers. Preferably, the superlattice stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers.

[0211] In some embodiments, the first type epitaxial layer is a semiconductor material having a first conductivity type and includes multiple semiconductor layers. The primary substrate material of the first type epitaxial layer may be, but is not limited to, materials such as Ga, N, As, P, In, or Al. Furthermore, the first type epitaxial layer may include, from top to bottom, a confinement layer and a waveguide layer; additionally, in some embodiments, an ohmic contact layer may be formed on the confinement layer.

[0212] In some embodiments, the second type of epitaxial layer is a semiconductor material having a second conductivity type and includes multiple semiconductor layers. The main substrate material of the second type of epitaxial layer may be, but is not limited to, materials such as Ga, N, As, P, In, or Al. Furthermore, the second type of epitaxial layer may, from top to bottom, include, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; additionally, an ohmic contact layer may be formed below the window layer. In one embodiment, the first conductivity type is different from the second conductivity type.

[0213] In some embodiments, the first type of epitaxial layer is an N-type GaN layer or an N-type AlGaN layer, and the second type of epitaxial layer is a P-type GaN layer or a P-type AlGaN layer. That is, the material of the second type of epitaxial layer can be a material layer of a second conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P, and the first type of epitaxial layer can be a material layer of a first conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P. In one embodiment, the light-emitting layer includes a multi-quantum-well layer and an electron-blocking layer. The multi-quantum-well layer is an InGaN / GaN multi-quantum-well layer, an InGaN / AlGaN multi-quantum-well layer, or an InGaAs / AlGaAs multi-quantum-well layer. In another embodiment, the first type of epitaxial layer can also be a P-type GaN layer or a P-type AlGaN layer, and the second type of epitaxial layer can be an N-type GaN layer or an N-type AlGaN layer.

[0214] In some embodiments, the light-emitting layer includes at least one quantum well layer. The thickness of the quantum well layer is between 20 nm and 40 nm, for example, 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the light-emitting layer is a multiple quantum well (MQW).

[0215] In some embodiments, one of the first type epitaxial layer and the second type epitaxial layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer. The N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al. x In 1-x P, where x ranges from 0.1 to 0.5, for example, x is 0.5. Furthermore, in these embodiments, the thickness of the N-type cladding layer is no greater than 350 nm, for example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e⁻¹. 17 cm -3 up to 1e 18 cm -3 In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer formed on the doped N-type contact layer. The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e⁻¹. 18 cm-3 up to 1e 19 cm -3 In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al). x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. The thickness of the N-type spacer layer is 50 nm to 75 nm, for example, 65 nm. In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light-emitting layer, and the doped P-type contact layer is formed on the P-type cladding layer.

[0216] In some embodiments, the material of the P-type coating is Al. x In 1-x P, where x is 0.3 to 0.5, for example, x is 0.5. In such an embodiment, the thickness of the P-type coating is no greater than 380 nm, for example, the thickness of the P-type coating is 360 nm.

[0217] In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is 10 nm to 30 nm, for example, 20 nm.

[0218] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first-doped P-type transition layer formed on the P-type cladding layer, and a second-doped P-type transition layer formed on the first-doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al). x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the thickness of the P-type spacer layer is 50 nm to 70 nm, for example, 65 nm.

[0219] In some embodiments, the material of the first doped P-type transition layer is (Al) x Ga 1-x ) y In 1-yP, where x ranges from 0.1 to 0.3 and y ranges from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is that y is 1 to 5 times x. In some embodiments, the thickness of the first doped P-type transition layer is 20 nm to 40 nm, for example, 30 nm.

[0220] In some embodiments, the material of the second doped P-type transition layer is Al. x Ga 1-x As, where x ranges from 0.5 to 0.9, for example, x is 0.6. In some embodiments, the thickness of the second doped P-type transition layer is from 10 nm to 30 nm, for example, 20 nm.

[0221] In some embodiments, the doping concentration of the second-doped P-type transition layer is greater than the doping density of the first-doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times that of the second-doped P-type transition layer.

[0222] In some embodiments, the doping concentration of the doped P-type contact layer is greater than the doping concentration of the second-doped P-type transition layer. Furthermore, in some embodiments, the doping concentration of the second-doped P-type transition layer is 2 to 4 times that of the first-doped P-type transition layer.

[0223] For example, the doping concentration of the first doped P-type transition layer is greater than 1e. 18 cm -3 The doping density of the second-doped P-type transition layer is 2e 18 cm -3 -4e 18 cm -3 Within the range, the doping density of the doped P-type contact layer is greater than 5e 18 cm -3 .

[0224] In an embodiment of the present invention, the micro-light-emitting diode 101 further includes a first bonding layer 107 and a second bonding layer 202. The first bonding layer 107 is located on the side of the first transparent conductive layer 104 facing away from the light-emitting platform 103, that is, the first bonding layer 107 is located below the first transparent conductive layer 104. The second bonding layer 202 is located below the first bonding layer 107. The second bonding layer 202 is in electrical contact with the conductive hole 21 of the driving backplate 2. Each micro-light-emitting diode 101 corresponds to one conductive hole 21.

[0225] The number of first bonding layers 107 and second bonding layers 202 is the same as the number of light-emitting mesa 103. The first bonding layer 107 and the second bonding layer 202 of each micro LED 101 are independent, and all first bonding layers 107 are not connected to each other, and all second bonding layers 202 are not connected to each other.

[0226] The dimensions of the first bonding layer 107 and the second bonding layer 202 are greater than or equal to the dimensions of the first transparent conductive layer 104.

[0227] In an embodiment of the present invention, the insulating layer 105 also covers the side surface of the first bonding layer 107.

[0228] Figure 12 A longitudinal cross-sectional schematic diagram of a current extension structure according to an embodiment of the present invention is shown.

[0229] like Figure 12 As shown, the current extension structure 102 can be divided into a first part 1023 whose inner wall is in direct contact with the micro LED, and a second part 1024 whose inner wall is not in direct contact with the micro LED. The second part 1024 is located above the first part 1023. As shown in the figure, it is divided by a dashed line; the part below the dashed line is the first part 1023, and the part above the dashed line is the second part 1024. The inner wall of the first part 1023 is in electrical contact with the second transparent conductive layer 106.

[0230] The second part 1024 of the current extension structure 102 has a three-dimensional shape. For example... Figure 12 As shown, in one embodiment, the three-dimensional shape of the second part 1024 is a cup shape with an open bottom, and the angle α between the inner wall of the second part 1024 and the horizontal direction is at least 90°, such that light incident from the micro light-emitting diode 101 onto the inner wall is reflected to the outside of the micro light-emitting diode 101.

[0231] The cup-shaped structure creates a reflective effect. When light from the miniature LED shines at a wide angle onto the inner wall of the cup-shaped metal, the reflection increases the light extraction efficiency at narrow angles. This cup-shaped structure achieves better light focusing.

[0232] Figure 13 A longitudinal cross-sectional schematic diagram of a current-extending structure according to another embodiment of the present invention is shown.

[0233] like Figure 13 As shown, in another embodiment, the three-dimensional shape of the second part 1024 is a bowl shape with an open bottom, and the inner wall of the second part 1024 is arc-shaped. The angle β between the tangent at each point on the inner wall and the horizontal direction is at least 90°, so that the light incident from the micro light-emitting diode 101 onto the inner wall is reflected to the outside of the micro light-emitting diode 101.

[0234] The current extension structure 102 has a light-reflecting surface facing the light-emitting diode 101, for example, it is made of metal, so that the current extension structure 102 can at least partially reflect the light emitted by the light-emitting diode 101. Figure 11As shown, the reflection process is as follows: light emitted from the light-emitting layer of the LED 101 passes through its transparent layer (e.g., a second transparent conductive layer). A first portion of this light (with a sufficiently small exit angle to avoid hitting the side current extension structure 102, within a preset exit angle, such as ±20°) is emitted directly. A second portion of this light (with a sufficiently large exit angle to hit the side current extension structure 102) hits the current extension structure 102 and is reflected before being emitted, changing the light path direction to within the preset exit angle, thereby effectively improving the light extraction rate. Preferably, the proportion of light reflected by the current extension structure 102 to the light emitted by the LED 101 can be, for example, 10%-60%. By providing a current extension structure 102 with light reflection capability, the amount of light absorbed by the sidewalls can be significantly reduced, thereby significantly increasing the total light output. Simultaneously, the current extension structure 102 can also isolate light, preventing light crosstalk between adjacent LEDs 101.

[0235] In an embodiment of the present invention, the current extension structure 102 is electrically connected to the second transparent conductive layer 106. By arranging the current extension structure 102 to surround the second transparent conductive layer 106 of the micro LED 101 in an electrical contact manner, the electrical contact area between the current extension structure 102 and the micro LED 101 can be significantly increased, thereby enabling the active layer (light-emitting layer) of the micro LED 101 to emit light more uniformly, effectively avoiding light emission only at or near the electrical contact area or excessively high brightness at or near the electrical contact area.

[0236] like Figure 11 As shown, the current extension structure 102 has an inner wall 1021 facing the micro LED and an outer wall 1022 facing away from the micro LED. The lower ends of the outer walls 1022 of adjacent current extension structures 102 are connected.

[0237] The bottom dimension of the current extension structure is larger than the top dimension. Since the bottoms of adjacent current extension structures 102 are connected, the longitudinal cross-section of two adjacent current extension structures 102 exhibits a bifurcated peak shape.

[0238] Furthermore, the longitudinal cross-sectional shape of two adjacent current extension structures 102 may be asymmetrical, and their heights may be different; no restrictions are imposed here.

[0239] The bottoms of adjacent current extension structures 102 are connected. Furthermore, all current extension structures 102 are connected into a single unit, with an overall top-view shape as shown... Figure 10 As shown.

[0240] In an embodiment of the present invention, the bottom of the current extension structure 102 is lower than the light-emitting platform 103 of the micro light-emitting diode 101.

[0241] In embodiments of the present invention, the top of the current extension structure 102 may be higher than the top of the light-emitting mesa 103; the top of the current extension structure 102 may also be flush with the top of the light-emitting mesa 103; the top of the current extension structure 102 may also be slightly lower than the top of the light-emitting mesa 103 (0-1 micrometer). One, two, or three of the above situations may coexist in a single chip.

[0242] Preferably, the top of the current extension structure 102 is higher than the top of the light-emitting platform 103 of the micro light-emitting diode 101. By making the height of the top of the current extension structure 102 greater than the height of the top plane of the light-emitting platform 103 of the micro light-emitting diode 101, a higher current extension structure 102 can be obtained, which further increases the chance of light reflection and increases the light extraction efficiency.

[0243] In this embodiment, the top view (i.e., cross-sectional shape) of the micro LED 101 is circular, and the top view of the overall current expansion structure is the grid shape remaining after removing the circle (e.g., Figure 10 ).

[0244] In other embodiments, the top view shape of the micro LED 101 may also be other suitable shapes, such as rectangles, squares, or regular polygons. The top view shape of the overall current extension structure may also be the shape remaining after removing other suitable shapes, such as the grid shape remaining after removing rectangles, squares, or polygons.

[0245] like Figure 11 As shown, the bottom dimension of the current extension structure 102 is larger than the top dimension. By making the bottom dimension of the current extension structure 102 larger than the top dimension, a more stable current extension structure 102 can be obtained, thereby improving the stability of the miniature light-emitting diode 101 device.

[0246] In an embodiment of the present invention, the number of current extension structures 102 may be the same as the number of micro light-emitting diodes 101, with each current extension structure 102 surrounding one micro light-emitting diode 101.

[0247] In other embodiments, the number of current extension structures 102 may be 1 / 4 or 1 / 9 of the number of micro LEDs 101, with each current extension structure 102 surrounding 4 micro LEDs 101 or 9 micro LEDs 101, without limitation.

[0248] In an embodiment of the present invention, the current extension structure 102 can be a multilayer structure, and the current extension structure 102 includes one or more main metal layers.

[0249] In this embodiment of the invention, the material of the main metal layer can be one or more of Pt, Au, Al, and Ag. The current spreading structure can increase the current spread between adjacent micro-LEDs, reduce the resistance between adjacent micro-LEDs, and reduce losses. The current spreading structure allows the current to spread rapidly and uniformly to all micro-LEDs.

[0250] In some embodiments, the current extension structure 102 may further include: an isolation layer corresponding to each main metal layer; wherein the isolation layer and the main metal layer are staggered, and each main metal layer is located on the corresponding isolation layer.

[0251] By employing isolation layers that correspond one-to-one with each main metal layer, and by staggering the isolation layers with the main metal layers, with each main metal layer located on its corresponding isolation layer, the influence of electromigration within the current extension structure 102 can be effectively suppressed by setting the isolation layers. Especially when the density of micro-light-emitting diodes 101 in the micro-light-emitting diode chip is large, it is possible to increase the height of the current extension structure 102 by setting the isolation layers, thereby further improving the light extraction efficiency through the higher current extension structure 102.

[0252] Furthermore, the isolation layer may include a titanium (Ti) metal layer. It should be noted that the isolation layer material may also include other suitable materials, such as titanium nitride (TiN).

[0253] In some embodiments, the current spreading structure 102 may further include: an adhesive layer located at the bottom layer of the current spreading structure 102, and an isolation layer and a main metal layer located on the adhesive layer.

[0254] An adhesive layer is formed between the micro-light-emitting diodes 101, and the isolation layer and the main metal layer are located on the adhesive layer. The adhesive layer can effectively improve the bottom stability of the current extension structure 102. Especially when the density of micro-light-emitting diodes 101 in the micro-light-emitting diode chip is large, the adhesive layer can be set to increase the height of the current extension structure 102, thereby further improving the light extraction efficiency through the higher current extension structure 102.

[0255] Furthermore, the adhesive layer may include a chromium (Cr) metal layer. It should be noted that the adhesive layer material may also include other suitable materials, such as one or more of the following: titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0256] In this embodiment of the invention, the current spreading structure 102 may further include: an anti-diffusion layer corresponding to the isolation layer, with each isolation layer located on the corresponding anti-diffusion layer.

[0257] By forming anti-diffusion layers that correspond one-to-one with the isolation layers, and with each isolation layer located on the corresponding anti-diffusion layer, the stability of the current extension structure 102 can be improved by utilizing the high hardness and good corrosion resistance of the anti-diffusion layer. Especially when the density of micro-light-emitting diodes 101 in the micro-light-emitting diode chip is large, the height of the current extension structure 102 can be increased by setting the anti-diffusion layer, thereby further improving the light extraction efficiency through the higher current extension structure 102.

[0258] The anti-diffusion layer may include a platinum (Pt) metal layer or a nickel (Ni) metal layer. It should be noted that the anti-diffusion layer may be a single platinum metal layer, a single nickel metal layer, or a stack of single platinum metal layers and single nickel metal layers.

[0259] Figure 14 A longitudinal cross-sectional schematic diagram of a micro light-emitting diode chip according to another embodiment of the present invention is shown.

[0260] In some embodiments, such as Figure 14 As shown, there is a gap 1025 in the current extension structure 102.

[0261] The current extension structure 102 can be formed by metal vapor deposition. The gaps 1025 are formed during the metal vapor deposition process. The presence of the gaps has the advantage of reducing the film stress in the current extension structure 102. The number of gaps 1025 is not fixed, and the position of the gaps 1025 in the current extension structure 102 is not fixed. For example, the gaps 1025 may exist in the second part and / or the first part of the current extension structure 102. Figure 14 The number and location of the overlapping gaps 1025 are for illustrative purposes only.

[0262] Figure 15 A longitudinal cross-sectional schematic diagram of a micro-light-emitting diode chip with microlenses according to an embodiment of the present invention is shown.

[0263] like Figure 15 As shown, the micro-LED chip also includes a microlens 300. The microlens 300 is disposed on the micro-LED, wherein at least one microlens 300 is disposed on the light-emitting platform of the micro-LED to form a microlens array, adjacent microlenses 300 are connected, and the horizontal profile of the microlens 300 is larger than the maximum horizontal profile of the micro-LED.

[0264] like Figure 15As shown, in an embodiment of the present invention, a gap 301 is provided between adjacent microlenses. In an embodiment of the present invention, the bottom of the gap 301 is higher than the top of the light-emitting mesa 103. In another embodiment of the present invention, the bottom of the gap 301 is lower than the top of the light-emitting mesa 103 and higher than the bottom of the light-emitting mesa 103. In yet another embodiment of the present invention, the bottom of the gap is located above the current extension structure 102. Specifically, as shown, the gap 301 is located between two adjacent current extension structures (i.e., between bifurcation peaks).

[0265] In addition, such as Figure 15 As shown, in embodiments of the present invention, the microlens may also have an air gap 302 inside. Each lens may have multiple air gaps, and the size and length of each air gap may be the same or different. Furthermore, within the same chip, the number of air gaps and / or the position and / or size of the air gaps in different microlenses may be the same or different. As shown, in some embodiments of the present invention, the air gap 302 is located at the edge of the microlens 300, specifically, for example, on both sides of the light-emitting mesa 103, preferably, it is located between the light-emitting mesa 103 and the current extension structure 102. Also, as shown, in some embodiments of the present invention, the top of the air gap 302 is higher than the top of the light-emitting mesa 103, and its bottom may be higher than or lower than the top of the light-emitting mesa 103. As shown, in some embodiments of the present invention, the bottom of the air gap 302 is higher than the top of the current extension structure 102. In still other embodiments of the present invention, the bottom of the air gap 302 is lower than the top of the current extension structure 102. It should be noted that in other embodiments of the present invention, the microlens may also be without an air gap 302.

[0266] The materials of the first bonding metal layer 120, the second bonding metal layer 121, the first conductive layer 122, and the insulating layer 123 in the non-light-emitting region are the same as the materials of the first bonding metal layer 107, the second bonding layer 202, the first transparent conductive layer 104, and the insulating layer 105 of the micro-light-emitting diode, and can be deposited simultaneously. The top conductive metal layer 125 is made of the same material as the current spreading structure 102 and is deposited simultaneously. The top conductive metal layer 125 is connected to the current spreading structure 102.

[0267] The second conductive layer 124 can be made of the same material as the second transparent conductive layer of the micro light-emitting diode, or it can be made of a different material, and the two can be deposited simultaneously.

[0268] The insulating dielectric layer 126 is made of the same material as the microlens 300, and can be deposited simultaneously.

[0269] The transparent conductive layer 128 and the second transparent conductive layer 106 of the micro light-emitting diode can be made of the same material.

[0270] The epitaxial layer 127 is made of the same material as the light-emitting mesa 103 of the micro-LED.

[0271] The first bonding metal layer 120, the second bonding metal layer 121, the first conductive layer 122, and the isolation insulating layer 123 of the transition portion of the first boundary structure are respectively connected to the first bonding metal layer 107, the second bonding layer 202, the first transparent conductive layer 104, and the insulating layer 105 of the micro light-emitting diode.

[0272] While some embodiments of the present invention have been described in this application, those skilled in the art will understand that these embodiments are merely illustrative. Numerous variations, alternatives, and improvements will arise in those skilled in the art under the teachings of this invention without departing from its scope. The appended claims are intended to define the scope of the invention and thereby cover methods and structures within the scope of the claims themselves and their equivalents.

Claims

1. A miniature light-emitting diode chip, characterized in that, include: A drive backplane having conductive vias and a conductive wiring layer, the conductive vias being configured to electrically connect the conductive wiring layer to a conductive structure; The light-emitting region is configured to emit light and includes one or more miniature light-emitting diodes arranged in an array. Non-luminescent regions do not emit light; A conductive structure is arranged in the light-emitting region and the non-light-emitting region, and a micro light-emitting diode is electrically connected to a conductive hole in the light-emitting region; as well as A first boundary structure is configured to electrically isolate the conductive structure in the non-light-emitting region from the conductive structure in the light-emitting region.

2. The micro light-emitting diode chip according to claim 1, characterized in that, The non-luminescent region includes: A first region, surrounding the light-emitting region, the first region having a conductive structure; and The second region is not directly adjacent to the light-emitting region.

3. The micro light-emitting diode chip according to claim 2, characterized in that, The first boundary structure electrically isolates the conductive structure in the first region from the conductive structure in the light-emitting region.

4. The micro light-emitting diode chip according to claim 2, characterized in that, The conductive structure includes: A second bonding metal layer, which electrically contacts a conductive hole; and A first bonding metal layer is located above the second bonding metal layer and makes electrical contact with the micro light-emitting diode.

5. The micro light-emitting diode chip according to claim 4, characterized in that, The conductive structure further includes: A first conductive layer is disposed on top of a first bonding metal layer.

6. The micro light-emitting diode chip according to claim 4, characterized in that, The first region also includes: An insulating layer is disposed on the conductive structure; A second conductive layer is disposed above the insulating layer; and A top conductive metal layer is disposed on top of the second conductive layer.

7. The micro light-emitting diode chip according to claim 6, characterized in that, The first boundary structure includes: An electrical isolation section having a groove to separate the conductive structure in the non-light-emitting region from the conductive structure in the light-emitting region.

8. The micro light-emitting diode chip according to claim 7, characterized in that, The electrical isolation unit is disposed in one or more of the following locations: The boundary between the luminescent and non-luminescent areas; and In the non-luminous area, at a certain distance from the luminous area.

9. The micro light-emitting diode chip according to claim 8, characterized in that, When the non-luminescent region is at a certain distance from the luminescent region, the first boundary structure also includes: The transition section is located between the light-emitting area and the electrically isolated section and is in electrical contact with the light-emitting area.

10. The micro light-emitting diode chip according to claim 9, characterized in that, The electrical isolation portion has a width of not less than 2 μm and a depth of 0.1-3 μm; and / or The width of the transition section is 10um-100um.

11. The micro light-emitting diode chip according to claim 1, characterized in that, The conductive hole is filled with a metal selected from one or more of copper, gold, and aluminum.

12. The micro light-emitting diode chip according to claim 7, characterized in that, The electrical isolation section also has the following structure arranged within the groove: An insulating layer covers the inner side of the conductive structure in the first region and the side of the transition portion. A second conductive layer is disposed above the insulating layer; and A top conductive metal layer is disposed on top of the second conductive layer.

13. The micro light-emitting diode chip according to claim 9, characterized in that, The transition section includes: Conductive structure; An insulating layer is disposed on the conductive structure; A second conductive layer is disposed on top of the insulating layer; and A top conductive metal layer is disposed on top of the second conductive layer.

14. The micro light-emitting diode chip according to claim 13, characterized in that, The conductive structure of the transition section is in electrical contact with the conductive structure of the light-emitting region.

15. The micro light-emitting diode chip according to claim 14, characterized in that, The conductive structure of the transition section is disconnected from and does not contact the conductive structure of the first region.

16. The micro light-emitting diode chip according to claim 13, characterized in that, The conductive structure of the transition portion includes: A second bonding metal layer, which electrically contacts a conductive hole; and A first bonding metal layer is located on top of the second bonding metal layer.

17. The miniature light-emitting diode chip according to claim 16, characterized in that, The conductive structure further includes: A first conductive layer is disposed on top of a first bonding metal layer.

18. The micro light-emitting diode chip according to claim 13, characterized in that, The insulating layer of the first region is connected to the insulating layer of the transition portion; The second conductive layer of the first region is connected to the second conductive layer of the transition portion; and The top conductive metal layer of the first region is connected to the top conductive metal layer of the transition portion.

19. The micro light-emitting diode chip according to claim 1, characterized in that, The conductive circuit layer is electrically connected to an external power source.

20. The micro light-emitting diode chip according to claim 6, characterized in that, The first region has a second boundary structure that electrically isolates the second region from the first region.

21. The miniature light-emitting diode chip according to claim 20, characterized in that, The second boundary structure consists of an insulating dielectric layer and the outer edge of the first region, wherein the insulating dielectric layer wraps around the outer edge of the first region.

22. The micro light-emitting diode chip according to claim 21, characterized in that, The edge of the first region includes: Conductive structure; An insulating layer is located above the conductive structure; A second conductive layer is located above the insulating layer, wherein the outer edge of the insulating layer extends outward relative to the second conductive layer; A top conductive metal layer is located on the upper surface of the second conductive layer, the side surface of the second conductive layer, and the upper surface at the outer edge of the insulating layer.

23. The micro light-emitting diode chip according to claim 22, characterized in that, The insulating dielectric layer covers the upper surface at the outer edge of the top conductive metal layer, the outer surface of the top conductive metal layer, the outer surface of the insulating layer, and the outer surface of the conductive structure.

24. The micro light-emitting diode chip according to claim 23, characterized in that, The second region has multiple lead electrodes, which are in electrical contact with the drive backplate.

25. The micro light-emitting diode chip according to claim 24, characterized in that, The top conductive metal layer is in electrical contact with the light-emitting area and also in electrical contact with a portion of the lead electrodes.

26. A micro-display panel, characterized in that, include: The miniature light-emitting diode chip according to any one of claims 1-25; A shielding layer is disposed on one side, two sides, three sides, or around the light-emitting area of ​​the micro LED chip; A plastic encapsulation frame surrounds a micro LED chip, the plastic encapsulation frame exposing the light-emitting area and at least a partial shielding layer.

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