Three-dimensional memory with improved thermal effects and methods of manufacturing the same

Abstract

The application relates to a three-dimensional memory for improving thermal effects and a manufacturing method thereof. The manufacturing method of the three-dimensional memory for improving thermal effects comprises the following steps: forming a substrate, wherein the substrate comprises a substrate, a bottom dielectric layer located on the substrate, a first contact structure penetrating through the bottom dielectric layer, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structure, a storage hole penetrating through the intermediate dielectric layer and exposing the first contact structure, and a storage structure covering the inner wall of the storage hole and being in contact with the first contact structure; depositing a polysilicon material on the substrate by using a low-pressure chemical vapor deposition process, and injecting a doping element into the polysilicon material to form a low-pressure chemical deposition layer covering the storage structure and filling the storage hole. The application can effectively improve the thermal effect problem of the three-dimensional memory in the manufacturing process, and can actively change the corresponding stress between the low-pressure chemical deposition layer and the storage layer, so that the storage performance is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a three-dimensional memory for improving thermal effects and a method for manufacturing the same. Background Technology

[0002] Phase-change memories (PCMs) or ferroelectric RAMs (FeRAMs) are devices that integrate memory cells in back-end-of-line (BEOL) processes, where the memory cells are inserted between two adjacent metal layers. A memory cell typically consists of upper and lower electrode layers and an intermediate ferroelectric storage layer. The storage performance of a ferroelectric memory is directly proportional to the effective area of ​​the ferroelectric storage layer and the electrode layer within the memory cell. Traditional ferroelectric memories typically employ metal-organic chemical vapor deposition (MOCVD) or physical vapor deposition to deposit tungsten metal onto the upper electrode layer as its lead-out structure. However, the deposition of tungsten and subsequent alloying processes usually involve high temperatures (e.g., above 700°C). These high temperatures can lead to uncontrolled crystallization, elemental diffusion, interface reactions, and stress relaxation in the ferroelectric storage layer within the memory cell, resulting in a decrease in the performance of the three-dimensional memory. Furthermore, because tungsten is a rigid metal, the stress state between it and the memory cell cannot be controlled, making it difficult to optimize the phase transition kinetics of the PCM and the polarization reversal efficiency of the ferroelectric material, thus limiting the improvement of the performance of three-dimensional memory devices.

[0003] Therefore, how to improve the thermal effect problem in the manufacturing process of 3D memory, ensure the stability of 3D memory performance, and at the same time achieve effective control of stress between the top electrode layer lead-out structure and the memory layer, so as to lay the foundation for improving the performance of 3D memory, is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] This invention provides a three-dimensional memory for improving thermal effects and a method for manufacturing the same. It addresses the thermal effects during the manufacturing process of the three-dimensional memory, ensures the stability of the three-dimensional memory's performance, and effectively controls the stress between the upper electrode layer lead-out structure and the memory layer, thus laying the foundation for improving the performance of the three-dimensional memory.

[0005] According to some embodiments, the present invention provides a method for manufacturing a three-dimensional memory for improving thermal effects, comprising the following steps: A substrate is formed, the substrate including a substrate, a bottom dielectric layer on the substrate, a first contact structure penetrating the bottom dielectric layer, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structure, a storage hole penetrating the intermediate dielectric layer and exposing the first contact structure, and a storage structure covering the inner wall of the storage hole, wherein the storage structure is in contact with the first contact structure. Polycrystalline silicon material is deposited on the substrate using a low-pressure chemical vapor deposition process, and dopant elements are implanted into the polycrystalline silicon material to form a low-pressure chemical deposition layer that covers the memory structure and fills the memory holes, and the low-pressure chemical deposition layer is electrically connected to the memory structure. A first lead-out structure is formed above the substrate and electrically connected to the low-pressure chemical deposition layer.

[0006] In some embodiments, the specific steps for forming the substrate include: A substrate is provided, the substrate including an active region, and the substrate including a top surface and a bottom surface that are distributed opposite to each other, the active region including a channel region and a source region and a drain region distributed on opposite sides of the channel region along a first direction, the first direction being parallel to the top surface of the substrate; Form the bottom dielectric layer covering the top surface of the substrate; A first contact structure is formed that penetrates the bottom dielectric layer along a second direction and is electrically connected to the drain region, wherein the second direction intersects the top surface of the substrate perpendicularly; An intermediate dielectric layer is formed covering the bottom dielectric layer and the first contact structure; A storage hole is formed that penetrates the intermediate dielectric layer along the second direction and exposes the first contact structure; A storage structure is formed covering the inner wall of the storage hole, and the storage structure is electrically connected to the first contact structure.

[0007] In some embodiments, the intermediate dielectric layer includes: A first intermediate dielectric layer covers the bottom dielectric layer and the first contact structure, and the material of the first intermediate dielectric layer includes silicon nitride; A second intermediate dielectric layer covering the first intermediate dielectric layer, wherein the material of the second intermediate dielectric layer includes silicon dioxide; A third intermediate dielectric layer covers the second intermediate dielectric layer, and the material of the third intermediate dielectric layer includes silicon oxynitride.

[0008] In some embodiments, the substrate includes a top surface and a bottom surface that are distributed opposite to each other. The substrate includes a plurality of memory cells spaced apart along a first direction. Each memory cell includes the first contact structure and the memory aperture. The first direction is parallel to the top surface of the substrate. The memory structures in adjacent memory cells are connected as a single unit to form an initial memory structure. The specific steps of depositing polycrystalline silicon material on the substrate using a low-pressure chemical vapor deposition process and implanting dopant elements into the polycrystalline silicon material to form a low-pressure chemical deposition layer covering the memory structure and filling the memory aperture include: Polycrystalline silicon material is deposited on the substrate using a low-pressure chemical vapor deposition process, and doping elements are implanted into the polycrystalline silicon material to form an initial low-pressure chemical deposition layer that continuously covers the entire surface of the initial memory structure away from the substrate and fills the multiple memory holes. An etching process is used to remove a portion of the initial low-pressure chemical deposition layer and a portion of the initial memory structure above the intermediate dielectric layer, disconnecting the connection between the memory structures in adjacent memory cells, and forming a plurality of low-pressure chemical deposition layers that are connected one-to-one with and independent of the plurality of memory structures.

[0009] In some embodiments, the substrate includes a top surface and a bottom surface that are distributed opposite to each other. The substrate includes a plurality of memory cells spaced apart along a first direction. Each memory cell includes the first contact structure and the memory aperture. The first direction is parallel to the top surface of the substrate. The memory structures in adjacent memory cells are connected as a single unit to form an initial memory structure. The specific steps of depositing polycrystalline silicon material on the substrate using a low-pressure chemical vapor deposition process and implanting dopant elements into the polycrystalline silicon material to form a low-pressure chemical deposition layer covering the memory structure and filling the memory aperture include: Polycrystalline silicon material is deposited on the substrate using a low-pressure chemical vapor deposition process, and doping elements are implanted into the polycrystalline silicon material to form an initial low-pressure chemical deposition layer that covers the surface of the initial memory structure away from the substrate and fills the multiple memory holes. The initial low-pressure chemical deposition layer and the initial storage structure located on the top surface of the intermediate medium layer are removed by chemical mechanical polishing process, the connection between the storage structures in adjacent storage cells is disconnected, and multiple low-pressure chemical deposition layers are formed that are connected to each of the multiple storage structures in a one-to-one manner and are independent of each other.

[0010] In some embodiments, the specific steps of depositing polycrystalline silicon material on the substrate using a low-pressure chemical vapor deposition process and implanting dopant elements into the polycrystalline silicon material to form a low-pressure chemical deposition layer covering the storage structure and filling the storage holes include: A polycrystalline silicon material is deposited on the substrate using a low-pressure chemical vapor deposition process to form a polycrystalline silicon material layer that covers the storage structure and fills the storage holes. The doping element is implanted into the polycrystalline silicon material layer using an ion implantation process to form the low-pressure chemical deposition layer. The low-pressure chemical deposition layer is subjected to rapid thermal annealing.

[0011] In some embodiments, the doping element is any one or a combination of two or more of arsenic, phosphorus and boron.

[0012] In some embodiments, the deposition temperature of the low-pressure chemical vapor deposition process is 550°C to 650°C.

[0013] In some embodiments, the specific steps of forming a first lead-out structure located above the substrate and electrically connected to the low-pressure chemical deposition layer include: A top dielectric layer is formed covering the intermediate dielectric layer, the low-pressure chemical deposition layer, and the storage structure; A first lead-out structure is formed that penetrates the top dielectric layer and is electrically connected to the low-pressure chemical deposition layer.

[0014] According to other embodiments, the present invention also provides a three-dimensional memory for improving thermal effects, comprising: The substrate includes a substrate, a bottom dielectric layer on the substrate, a first contact structure penetrating the bottom dielectric layer, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structure, a storage hole penetrating the intermediate dielectric layer and exposing the first contact structure, and a storage structure covering the inner wall of the storage hole, wherein the storage structure is in contact with the first contact structure. A low-pressure chemical deposition layer covers the surface of the storage structure and fills the storage holes. The material of the low-pressure chemical deposition layer includes polycrystalline silicon and doped elements, and the low-pressure chemical deposition layer is electrically connected to the storage structure. The first lead-out structure is located above the substrate and is electrically connected to the low-pressure chemical deposition layer.

[0015] In some embodiments, the storage structure covers the inner wall of the storage hole and a portion of the intermediate dielectric layer opposite to the top surface of the substrate, and the low-pressure chemical deposition layer fills the storage hole and covers the surface of the storage structure located on the top surface of the intermediate dielectric layer.

[0016] In some embodiments, the storage structure is flush with the top surface of the substrate, the low-pressure chemical deposition layer is flush with the top surface of the substrate, and the intermediate dielectric layer is flush with the top surface of the substrate.

[0017] In some embodiments, the doping element is any one or a combination of two or more of arsenic, phosphorus and boron.

[0018] In some embodiments, it also includes: A top dielectric layer covers the intermediate dielectric layer, the low-pressure chemical deposition layer, and the storage structure, wherein the first lead-out structure penetrates the top dielectric layer and is electrically connected to the low-pressure chemical deposition layer.

[0019] In some embodiments, the storage structure includes: The lower electrode layer covers the inner wall of the storage hole and is electrically connected to the first contact structure. A storage layer covers the surface of the lower electrode layer, and the material of the storage layer is a phase change material or a ferroelectric material; An upper electrode layer covers the surface of the storage layer, and the low-pressure chemical deposition layer covers the surface of the upper electrode layer and is electrically connected to the upper electrode layer.

[0020] This invention provides a three-dimensional memory and its manufacturing method for improving thermal effects. It involves depositing polycrystalline silicon material onto a substrate using a low-pressure chemical vapor deposition (LPCVD) process and implanting dopant elements into the polycrystalline silicon material to form an LCVD layer that covers the memory structure and fills the memory vias. The LCVD layer is electrically connected to the memory structure. Specifically, this invention uses doped polycrystalline silicon instead of traditional tungsten as the filler material and employs LCVD to deposit the polycrystalline silicon material. Because the deposition temperature of the LCVD process is relatively low (e.g., around 600°C), it significantly reduces the thermal effects during filler material formation, preventing damage to the memory structure (especially the memory layer) due to high temperatures. This effectively improves the thermal effect problem during the manufacturing process of the three-dimensional memory, enhancing its performance and lifespan. Using doped polycrystalline silicon for filling eliminates the need for subsequent alloying processes, improving the yield of the three-dimensional memory and effectively reducing its manufacturing cost. Moreover, the polycrystalline silicon material deposited by low-pressure chemical vapor deposition has good step coverage, which can effectively fill memory holes with high aspect ratio or even extremely high aspect ratio, reduce or even avoid the generation of filling holes or gaps, and ensure uniform contact resistance between the memory structure (e.g., the upper electrode layer in the memory structure) and the low-pressure chemical deposition layer.

[0021] Furthermore, this invention employs a low-pressure chemical vapor deposition (LPCVD) process to deposit polycrystalline silicon material onto a substrate and implants dopant elements into the polycrystalline silicon material to form an LCVD layer that covers the storage structure and fills the storage holes. By adjusting doping parameters such as the type, concentration, and temperature of the dopant elements, the stress state of the LCVD layer can be adjusted, thereby actively changing the relative stress between the LCVD layer and the storage structure (especially the storage layer in the storage structure), optimizing the phase transition and ferroelectric polarization reversal efficiency, and improving storage performance.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a flowchart of a method for manufacturing a three-dimensional memory for improving thermal effects according to a specific embodiment of the present invention; Figure 2 This is a schematic diagram of the structure after the first contact structure is formed in a specific embodiment of the present invention; Figure 3 This is a schematic diagram of the structure after the intermediate dielectric layer is formed in a specific embodiment of the present invention; Figure 4 This is a schematic diagram of the structure after the storage hole is formed in a specific embodiment of the present invention; Figure 5 This is a schematic diagram of the structure after the initial storage structure is formed in a specific embodiment of the present invention; Figure 6 This is a schematic diagram of the structure after the initial low-pressure chemical deposition layer is formed, according to a specific embodiment of the present invention; Figure 7 This is a schematic diagram of the structure after the formation of the low-pressure chemical deposition layer in a specific embodiment of the present invention; Figure 8 This is a schematic diagram of the structure after the top dielectric layer is formed in a specific embodiment of the present invention; Figure 9 This is a schematic diagram of the structure after the first lead-out structure is formed in a specific embodiment of the present invention; Figure 10 This is another structural schematic diagram of a specific embodiment of the present invention after the formation of a low-pressure chemical deposition layer; Figure 11 This is another structural schematic diagram of a specific embodiment of the present invention after the formation of the top dielectric layer; Figure 12 This is another structural diagram of a specific embodiment of the present invention after the formation of the first lead-out structure.

[0025] Explanation of reference numerals in the attached figures 20. Substrate 21. Bottom dielectric layer 22. Gate dielectric layer 23. Gate conductive layer 24. Isolation sidewall 25. Second contact structure 26. First contact structure 30. First intermediate dielectric layer 31. Second intermediate dielectric layer 32. Third intermediate dielectric layer 40. Storage Hole 50. Initial storage structure 60. Initial low-pressure chemical deposition layer 70. Divider groove 71. Storage Structure 72. Low-pressure chemical deposition layer 80. First Top Dielectric Layer 81. Second Top Dielectric Layer 82. Third Top Dielectric Layer 90. First lead-out structure 91. Second lead-out structure Detailed Implementation The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] This specific embodiment provides a method for manufacturing a three-dimensional memory to improve thermal effects. Figure 1 This is a flowchart illustrating a method for manufacturing a three-dimensional memory to improve thermal effects, according to a specific embodiment of the present invention. Figure 1 As shown, the method for manufacturing the three-dimensional memory for improving thermal effects includes the following steps: Step S11: Form a substrate, the substrate including a substrate, a bottom dielectric layer on the substrate, a first contact structure penetrating the bottom dielectric layer, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structure, a storage hole penetrating the intermediate dielectric layer and exposing the first contact structure, and a storage structure covering the inner wall of the storage hole, wherein the storage structure is in contact with the first contact structure. Step S12: Polycrystalline silicon material is deposited on the substrate using a low-pressure chemical vapor deposition process, and doping elements are implanted into the polycrystalline silicon material to form a low-pressure chemical deposition layer that covers the storage structure and fills the storage holes, and the low-pressure chemical deposition layer is electrically connected to the storage structure. Step S13: Form a first lead-out structure located above the substrate and electrically connected to the low-pressure chemical deposition layer.

[0027] Figure 2 This is a schematic diagram of the structure after the first contact structure is formed according to a specific embodiment of the present invention. Figure 3 This is a schematic diagram of the structure after the intermediate dielectric layer is formed in a specific embodiment of the present invention. Figure 4 This is a schematic diagram of the structure after the storage hole is formed according to a specific embodiment of the present invention. Figure 5 This is a schematic diagram of the structure after the initial storage structure is formed according to a specific embodiment of the present invention. In some embodiments, the specific steps for forming the substrate include: A substrate 20 is provided, the substrate 20 including an active region, and the substrate 20 including a top surface and a bottom surface that are distributed opposite to each other. The active region includes a channel region and a source region and a drain region distributed on opposite sides of the channel region along a first direction D1, the first direction D1 being parallel to the top surface of the substrate 20. The bottom dielectric layer 21 is formed to cover the top surface of the substrate 20, such as... Figure 2 As shown; A first contact structure 26 is formed, extending along a second direction D2 through the bottom dielectric layer 21 and electrically connected to the drain region. The second direction D2 intersects perpendicularly with the top surface of the substrate 20. Figure 2 As shown; The intermediate dielectric layer is formed to cover the bottom dielectric layer 21 and the first contact structure 26, such as Figure 3 As shown; The storage hole 40 is formed by penetrating the intermediate dielectric layer along the second direction D2 and exposing the first contact structure 26, such as... Figure 4 As shown; A storage structure is formed covering the inner wall of the storage hole 40, and the storage structure is electrically connected to the first contact structure 26, such as... Figure 5 As shown.

[0028] In some embodiments, such as Figure 3 As shown, the intermediate dielectric layer includes: A first intermediate dielectric layer 30 covers the bottom dielectric layer 21 and the first contact structure 26, and the material of the first intermediate dielectric layer 30 includes silicon nitride; A second intermediate dielectric layer 31 covers the first intermediate dielectric layer 30, and the material of the second intermediate dielectric layer 31 includes silicon dioxide; A third intermediate dielectric layer 32 covers the second intermediate dielectric layer 31, and the material of the third intermediate dielectric layer 32 includes silicon oxynitride.

[0029] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. The substrate 20 includes at least a plurality of active regions arranged at intervals along the first direction D1 and shallow trench isolation regions located between adjacent active regions. Each active region includes a channel region and source and drain regions located on opposite sides of the channel region along the first direction D1. The substrate 20 includes a top surface and a bottom surface distributed opposite each other along the second direction D2. A gate structure is also disposed on the top surface of the substrate 20. The gate structure includes a gate dielectric layer 22 located above the channel region, a gate conductive layer 23 covering the surface of the gate dielectric layer 22, and isolation sidewalls 24 covering the sidewalls of the gate dielectric layer 22 and the sidewalls of the gate conductive layer 23, such as Figure 2 As shown. The bottom dielectric layer 21 covers the top surface of the substrate 20 and the gate structure. In one example, the material of the bottom dielectric layer 21 can be an oxide material, such as silicon dioxide. After forming the bottom dielectric layer 21, a first contact hole penetrating the bottom dielectric layer 21 along the second direction D2 and exposing the drain region and a second contact hole penetrating the bottom dielectric layer 21 along the second direction D2 and exposing the source region can be formed by etching. Then, a material such as tungsten is deposited in the contact holes by deposition to form a plurality of first contact structures 26 that are electrically connected to the drain regions of the plurality of active regions, and a second contact structure 25 that is electrically connected to the source regions. In one example, two adjacent active regions along the first direction D1 share the source region. In this specific embodiment, "plural" refers to two or more.

[0030] After forming the first contact structure 26 and the second contact structure 25, silicon nitride is deposited on the bottom dielectric layer 21 to form a first intermediate dielectric layer 30 covering the bottom dielectric layer 21, the first contact structure 26, and the second contact structure 25. Next, silicon dioxide is deposited on the first intermediate dielectric layer 30 to form a second intermediate dielectric layer 31 covering the first intermediate dielectric layer 30. Then, silicon oxynitride is deposited on the second intermediate dielectric layer 31 to form a third intermediate dielectric layer 32 covering the second intermediate dielectric layer 31, as follows... Figure 3As shown, the first intermediate dielectric layer 30, the second intermediate dielectric layer 31, and the third intermediate dielectric layer 32 together serve as the intermediate dielectric layer.

[0031] After forming the intermediate dielectric layer, etching is performed downwards from the top surface of the intermediate dielectric layer away from the substrate 20 to form the storage via 40, which penetrates the intermediate dielectric layer at least along the second direction D2 and exposes at least the top surface of the first contact structure 26 away from the substrate 20. Figure 4 As shown. In one example, the storage hole 40 only penetrates the intermediate dielectric layer, meaning that the bottom of the storage hole 40 only exposes the top surface of the first contact structure 26. In another example, the storage hole 40 penetrates the intermediate dielectric layer and extends into the bottom dielectric layer 21, such that the storage hole 40 exposes the top surface and part of the sidewall of the first contact structure 26, thereby increasing the area of ​​the subsequently formed storage structure.

[0032] After forming the storage via 40, a material such as TiN is deposited on the substrate to form a lower electrode layer that covers the inner wall of the storage via 40 and is electrically connected to the first contact structure 26. Next, a phase change material or ferroelectric material is deposited on the substrate to form a storage layer covering the lower electrode layer. Then, a material such as TiN is deposited again on the substrate to form an upper electrode layer covering the storage layer. The lower electrode layer, the storage layer, and the upper electrode layer together constitute the storage structure. In one example, the storage structures deposited within multiple storage vias 40 are connected together to form an initial storage structure 50, such as... Figure 5 As shown.

[0033] Figure 6 This is a schematic diagram of the structure after the initial low-pressure chemical deposition layer is formed, according to a specific embodiment of the present invention. Figure 7 This is a schematic diagram of the structure after the formation of a low-pressure chemical deposition layer, according to a specific embodiment of the present invention. In some embodiments, such as... Figure 6 and Figure 7 As shown, the substrate 20 includes a top surface and a bottom surface that are relatively distributed. The substrate includes a plurality of memory cells arranged at intervals along a first direction D1. Each memory cell includes the first contact structure 26 and the memory hole 40. The first direction D1 is parallel to the top surface of the substrate 20. The memory structures in adjacent memory cells are connected as a single unit to form an initial memory structure 50. The specific steps of depositing polycrystalline silicon material on the substrate using a low-pressure chemical vapor deposition process and implanting dopant elements into the polycrystalline silicon material to form a low-pressure chemical deposition layer 72 covering the memory structure and filling the memory hole 40 include: Polycrystalline silicon material is deposited on the substrate using a low-pressure chemical vapor deposition process, and doping elements are implanted into the polycrystalline silicon material to form an initial low-pressure chemical deposition layer 60 that continuously covers the entire surface of the initial storage structure 50 away from the substrate 20 and fills the multiple storage holes 40. An etching process is used to remove a portion of the initial low-pressure chemical deposition layer 60 above the intermediate dielectric layer and a portion of the initial storage structure 50, disconnecting the connection between the storage structures 71 in adjacent storage cells, and forming a plurality of low-pressure chemical deposition layers 72 that are connected one-to-one with and independent of the plurality of storage structures 71.

[0034] In some embodiments, the specific steps of depositing polycrystalline silicon material on the substrate using a low-pressure chemical vapor deposition process and implanting dopant elements into the polycrystalline silicon material to form a low-pressure chemical deposition layer covering the storage structure and filling the storage via 40 include: A polycrystalline silicon material is deposited on the substrate using a low-pressure chemical vapor deposition process to form a polycrystalline silicon material layer that covers the storage structure and fills the storage holes. The doping element is implanted into the polycrystalline silicon material layer using an ion implantation process to form the low-pressure chemical deposition layer. The low-pressure chemical deposition layer is subjected to rapid thermal annealing.

[0035] Specifically, during the formation of the memory structure, the memory structures within multiple memory cells are connected together to form the initial memory structure 50. Next, a low-pressure chemical vapor deposition (LPCVD) process is used to deposit polysilicon material onto the substrate, forming an initial polysilicon material layer that continuously covers the entire surface of the initial memory structure 50 away from the substrate 20. In one example, the initial polysilicon material layer continuously fills multiple memory vias 40. Then, an ion implantation process is used to implant dopant elements into the initial polysilicon material layer, forming an initial LCVD layer 60 that is electrically connected to the initial memory structure 50, such as... Figure 6As shown. Next, the initial low-pressure chemical deposition layer 60 is subjected to rapid thermal annealing to activate the doped elements and stabilize the stress inside the initial low-pressure chemical deposition layer 60. Then, an etching process is used to etch away a portion of the initial low-pressure chemical deposition layer 60 above the intermediate dielectric layer and a portion of the initial memory structure 50, forming a partition trench 70 that continuously penetrates the initial low-pressure chemical deposition layer 60 and the initial memory structure 50 along the second direction D2, exposing the top surface of the intermediate dielectric layer (e.g., the third intermediate dielectric layer 32). The partition trench 70 divides the initial memory structure 50 into multiple independent memory structures 71, and divides the initial low-pressure chemical deposition layer 60 into multiple low-pressure chemical deposition layers 72 that are electrically connected to each of the multiple memory structures 71 and are independent of each other, such as... Figure 7 As shown.

[0036] This specific embodiment employs the low-pressure chemical vapor deposition (LPCVD) process to deposit polycrystalline silicon material to form the LCVD layer 72, which is electrically connected to the upper electrode layer in the memory structure 71 and fills the memory vias 40. Because the deposition temperature of the LCVD process is relatively low (e.g., around 600°C), it significantly reduces the thermal effect during the formation of the filling material, preventing damage to the memory structure (especially the memory layer) due to high temperatures. This effectively improves the thermal effect problem during the manufacturing process of the 3D memory, thereby enhancing its performance and lifespan. Using doped polycrystalline silicon material for filling eliminates the need for subsequent alloying processes, improving the yield of the 3D memory and effectively reducing its manufacturing cost. Furthermore, the polycrystalline silicon material deposited using low-pressure chemical vapor deposition (LPCVD) has good step coverage, which can effectively fill memory holes with high aspect ratios or even extremely high aspect ratios, reducing or even avoiding the generation of filling holes or gaps. This ensures uniform contact resistance between the memory structure (e.g., the upper electrode layer in the memory structure) and the LCVD layer, and can increase the depth while reducing the area of ​​the memory cell, thus achieving the goal of reducing the device size while maintaining the phase change performance of the memory.

[0037] In some embodiments, the doping element is any one or a combination of two or more of arsenic, phosphorus and boron.

[0038] Specifically, arsenic, phosphorus, and boron, or a combination of two or more of these elements, are implanted into the polycrystalline silicon material layer via ion implantation to form a low-pressure chemical deposition layer 72 with conductive properties. By implanting these dopants into the polycrystalline silicon material layer and then performing rapid thermal annealing, the doping concentration of the dopants and the stress within the low-pressure chemical deposition layer 72 can be precisely controlled. This actively adjusts the tensile and compressive stress distribution between the low-pressure chemical deposition layer 72 and the storage layer in the storage structure 71, promoting the phase transformation of the phase change material in the storage layer or the polarization reversal of the ferroelectric material in the storage layer. Ultimately, this improves the read / write speed, fatigue characteristics, and data retention capability of the three-dimensional memory. For example, if the material of the storage layer is HfO2, the low-pressure chemical deposition layer 72 can generate compressive stress on the storage layer by injecting arsenic or phosphorus elements, while the low-pressure chemical deposition layer 72 can generate tensile stress on the storage layer by injecting boron elements. By adjusting the injection dosage of the dopant elements (i.e., the doping concentration of the dopant elements in the low-pressure chemical deposition layer 72), the magnitude of the compressive and tensile stresses can be adjusted accordingly. Subsequently, rapid thermal annealing is used to fix the stress, thereby maximizing the storage effect of the storage layer and thus actively adjusting the distribution of tensile and compressive stresses between the low-pressure chemical deposition layer 72 and the storage layer in the storage structure 71.

[0039] To effectively reduce thermal effects while ensuring sufficient filling of the storage vias 40 with polycrystalline silicon material, in some embodiments, the deposition temperature of the low-pressure chemical vapor deposition process is 550°C to 650°C. In one example, the deposition temperature of the low-pressure chemical vapor deposition process is 600°C.

[0040] Figure 8 This is a schematic diagram of the structure after the top dielectric layer is formed, according to a specific embodiment of the present invention. Figure 9 This is a schematic diagram of the structure after the formation of the first lead-out structure according to a specific embodiment of the present invention. In some embodiments, the specific steps for forming the first lead-out structure located above the substrate and electrically connected to the low-pressure chemical deposition layer 72 include: A top dielectric layer is formed covering the intermediate dielectric layer, the low-pressure chemical deposition layer 72, and the storage structure 71, such as... Figure 8 As shown; A first lead-out structure 90 is formed, penetrating the top dielectric layer and electrically connected to the low-pressure chemical deposition layer 72, such as... Figure 9 As shown.

[0041] Specifically, after forming the low-pressure chemical deposition layer 72, silicon nitride material is deposited on top of the substrate to form a first top dielectric layer 80 that continuously covers the top surface of the multiple low-pressure chemical deposition layers 72 and the intermediate dielectric layer. Next, silicon dioxide material is deposited on top of the substrate to form a second top dielectric layer 81 covering the first top dielectric layer 80. Then, silicon oxynitride material is deposited on top of the substrate to form a third top dielectric layer 82 covering the second top dielectric layer 81, as follows. Figure 8 As shown, the first top dielectric layer 80, the second top dielectric layer 81, and the third top dielectric layer 82 together serve as the top dielectric layer. Next, etching begins from the top surface of the third top dielectric layer 82 to form a first lead-out hole that continuously penetrates the third top dielectric layer 82, the second top dielectric layer 81, and the first top dielectric layer 80 along the second direction D2, exposing the low-pressure chemical deposition layer 72. A second lead-out hole is also formed that continuously penetrates the third top dielectric layer 82, the second top dielectric layer 81, the first top dielectric layer 80, and the intermediate dielectric layer along the second direction D2, exposing the second contact structure 25. Conductive material such as tungsten is deposited in the first lead-out hole and the second lead-out hole to form the first lead-out structure 90 electrically connected to the low-pressure chemical deposition layer 72, and the second lead-out structure 91 electrically connected to the second contact structure 25. Figure 9 As shown.

[0042] Since the storage structure 71 covers the inner wall of the storage hole 40 and part of the intermediate dielectric layer away from the top surface of the substrate 20, the low-pressure chemical deposition layer 72 fills the storage hole 40 and covers the surface of the storage structure 71 located on the top surface of the intermediate dielectric layer. See [link to documentation]. Figure 7 This increases the process window for forming the first lead-out hole, reduces the etching difficulty of the first lead-out hole, and further simplifies the manufacturing process of three-dimensional memory.

[0043] Figure 10 This is another structural schematic diagram of the present invention after the formation of the low-pressure chemical deposition layer. Figure 11 This is another structural diagram of a specific embodiment of the present invention after the formation of the top dielectric layer. Figure 12This is another structural schematic diagram of the present invention after the formation of the first lead-out structure. In some other embodiments, the substrate 20 includes a top surface and a bottom surface that are relatively distributed. The substrate includes a plurality of memory cells arranged at intervals along a first direction D1. Each memory cell includes the first contact structure 26 and the memory hole 40. The first direction D1 is parallel to the top surface of the substrate 20. The memory structures in adjacent memory cells are connected as a whole to form an initial memory structure 50. The specific steps of depositing polycrystalline silicon material on the substrate using a low-pressure chemical vapor deposition process and implanting doping elements into the polycrystalline silicon material to form a low-pressure chemical deposition layer covering the memory structure and filling the memory hole include: Polycrystalline silicon material is deposited on the substrate using a low-pressure chemical vapor deposition process, and doping elements are implanted into the polycrystalline silicon material to form an initial low-pressure chemical deposition layer 60 that covers the surface of the initial storage structure 50 away from the substrate and fills the plurality of storage holes 40. The initial low-pressure chemical deposition layer 60 and the initial storage structure 50 located on the top surface of the intermediate medium layer are removed by chemical mechanical polishing process, the connection between the storage structures 71 in adjacent storage cells is disconnected, and a plurality of low-pressure chemical deposition layers 72 are formed that are connected one-to-one with the plurality of storage structures 71 and are independent of each other.

[0044] Specifically, during the formation of the storage structure, the storage structures within multiple storage cells are connected together to form the initial storage structure 50, such as... Figure 5 As shown. Next, the polysilicon material is deposited on the substrate using the low-pressure chemical vapor deposition process to form an initial polysilicon material layer that continuously covers the entire surface of the initial memory structure 50 facing away from the substrate 20. In one example, the initial polysilicon material layer continuously fills a plurality of the memory holes 40. Next, the dopant element is implanted into the initial polysilicon material layer using an ion implantation process to form an initial low-pressure chemical deposition layer 60 that is electrically connected to the initial memory structure 50, as shown. Figure 6As shown. Next, the initial low-pressure chemical deposition layer 60 is subjected to rapid thermal annealing to activate the doping elements and stabilize the stress inside the initial low-pressure chemical deposition layer 60. Then, a portion of the initial low-pressure chemical deposition layer 60 and a portion of the initial memory structure 50 are removed using a chemical mechanical polishing process, with the intermediate dielectric layer serving as the polishing cutoff layer. This ensures that the remaining initial low-pressure chemical deposition layer 60 and the remaining initial memory structure 50 are flush with the top surface of the intermediate dielectric layer (e.g., the top surface of the third intermediate dielectric layer 32), thereby disconnecting the connection between the memory structures 71 in adjacent memory cells and forming multiple low-pressure chemical deposition layers 72 that are connected one-to-one with and independent of each memory structure 71, such as... Figure 10 As shown. The chemical mechanical polishing (CMP) process can separate adjacent memory structures 71 and adjacent low-pressure chemical deposition layers 72, eliminating the need for etching processes that separate the initial low-pressure chemical deposition layer 60 and the initial memory structure 50. This simplifies the manufacturing process of the 3D memory, improves the manufacturing yield, and helps to further reduce the manufacturing cost. Furthermore, since both the memory structure 71 and the low-pressure chemical deposition layer 72 are flush with the top surface of the intermediate dielectric layer, the distance between adjacent memory structures and between adjacent low-pressure chemical deposition layers 72 is increased, thereby further reducing the parasitic capacitance effect between adjacent memory cells.

[0045] In one example, in forming such Figure 10 Following the structure shown, silicon nitride, silicon dioxide, and silicon oxynitride are sequentially deposited on top of the substrate to form a first top dielectric layer 80, a second top dielectric layer 81 covering the top surface of the multiple low-pressure chemical deposition layers 72 and the intermediate dielectric layer, and a third top dielectric layer 82 covering the first top dielectric layer 80 and the second top dielectric layer 81. Figure 11As shown, the first top dielectric layer 80, the second top dielectric layer 81, and the third top dielectric layer 82 together serve as the top dielectric layer. Next, etching begins from the top surface of the third top dielectric layer 82 to form a first lead-out hole that continuously penetrates the third top dielectric layer 82, the second top dielectric layer 81, and the first top dielectric layer 80 along the second direction D2, exposing the low-pressure chemical deposition layer 72. A second lead-out hole is also formed that continuously penetrates the third top dielectric layer 82, the second top dielectric layer 81, the first top dielectric layer 80, and the intermediate dielectric layer along the second direction D2, exposing the second contact structure 25. Conductive material such as tungsten is deposited in the first lead-out hole and the second lead-out hole to form the first lead-out structure 90 electrically connected to the low-pressure chemical deposition layer 72, and the second lead-out structure 91 electrically connected to the second contact structure 25. Figure 12 As shown.

[0046] In another example, in forming as Figure 10 Following the structure shown, silicon dioxide and silicon oxynitride are sequentially deposited on the substrate to form a second top dielectric layer 81 that continuously covers the top surface of the multiple low-pressure chemical vapor deposition layers 72 and the intermediate dielectric layer, and a third top dielectric layer 82 covering the second top dielectric layer 81. This eliminates the need to deposit silicon nitride to form the first top dielectric layer 80. This is because the low-pressure chemical vapor deposition layer 72, deposited using low-pressure chemical vapor deposition and implanted with doped elements via ion implantation, can actively adjust the relative stress (e.g., the distribution of tensile and compressive stress) between the low-pressure chemical vapor deposition layer and the memory structure (especially the memory layer within the memory structure). Therefore, stress adjustment of the memory layer via silicon nitride is unnecessary, thus eliminating the need for silicon nitride deposition and better reducing power consumption.

[0047] This specific embodiment also provides a three-dimensional memory for improving thermal effects, wherein the three-dimensional memory can be employed as follows: Figures 1-12 The method for manufacturing a three-dimensional memory for improving thermal effects is shown below. The structure of the three-dimensional memory can be found in [reference needed]. Figure 9 and Figure 12 .like Figures 1-12 As shown, the three-dimensional memory for improving thermal effects includes: The substrate includes a substrate 20, a bottom dielectric layer 21 located on the substrate 20, a first contact structure 26 penetrating the bottom dielectric layer 21, an intermediate dielectric layer covering the bottom dielectric layer 21 and the first contact structure 26, a storage hole 40 penetrating the intermediate dielectric layer and exposing the first contact structure 26, and a storage structure 71 covering the inner wall of the storage hole 40, wherein the storage structure 71 is electrically connected to the first contact structure 26. A low-pressure chemical deposition layer 72 covers the surface of the storage structure 71 and fills the storage hole 40. The material of the low-pressure chemical deposition layer 72 includes polycrystalline silicon material and doping elements, and the low-pressure chemical deposition layer 72 is electrically connected to the storage structure 71. The first lead-out structure 90 is located above the substrate and is electrically connected to the low-pressure chemical deposition layer 72.

[0048] In some embodiments, the storage structure 71 covers the inner wall of the storage hole 40 and a portion of the intermediate dielectric layer away from the top surface of the substrate 20, and the low-pressure chemical deposition layer 72 fills the storage hole 40 and covers the surface of the storage structure 71 located on the top surface of the intermediate dielectric layer.

[0049] In other embodiments, the storage structure 71 is opposite to the top surface of the substrate 20, the low-pressure chemical deposition layer 72 is opposite to the top surface of the substrate 20, and the intermediate dielectric layer is flush with the top surface of the substrate 20.

[0050] In some embodiments, the doping element is any one or a combination of two or more of arsenic, phosphorus and boron.

[0051] In some embodiments, the three-dimensional memory for improving thermal effects further includes: The top dielectric layer covers the intermediate dielectric layer, the low-pressure chemical deposition layer 72, and the storage structure 71. The first lead-out structure 90 penetrates the top dielectric layer and is electrically connected to the low-pressure chemical deposition layer 72.

[0052] In some embodiments, the storage structure 71 includes: The lower electrode layer covers the inner wall of the storage hole 40 and is electrically connected to the first contact structure 26. A storage layer covers the surface of the lower electrode layer, and the material of the storage layer is a phase change material or a ferroelectric material; An upper electrode layer covers the surface of the storage layer, and the low-pressure chemical deposition layer 72 covers the surface of the upper electrode layer and is electrically connected to the upper electrode layer.

[0053] This specific embodiment provides a three-dimensional memory and its manufacturing method for improving thermal effects. It involves depositing polycrystalline silicon material on a substrate using a low-pressure chemical vapor deposition (LPCVD) process and implanting dopant elements into the polycrystalline silicon material to form an LCVD layer that covers the memory structure and fills the memory vias. The LCVD layer is electrically connected to the memory structure. Specifically, this embodiment uses doped polycrystalline silicon instead of traditional tungsten as the filler material and employs LCVD to deposit the polycrystalline silicon material. Because the deposition temperature of the LCVD process is relatively low (e.g., around 600°C), it significantly reduces the thermal effects during filler material formation, preventing damage to the memory structure (especially the memory layer) due to high temperatures. This effectively improves the thermal effect problem during the manufacturing process of the three-dimensional memory, enhancing its performance and lifespan. Using doped polycrystalline silicon for filling eliminates the need for subsequent alloying processes, improving the yield of the three-dimensional memory and effectively reducing its manufacturing cost. Moreover, the polycrystalline silicon material deposited by low-pressure chemical vapor deposition has good step coverage, which can effectively fill memory holes with high aspect ratio or even extremely high aspect ratio, reduce or even avoid the generation of filling holes or gaps, and ensure uniform contact resistance between the memory structure (e.g., the upper electrode layer in the memory structure) and the low-pressure chemical deposition layer.

[0054] Furthermore, this specific embodiment employs a low-pressure chemical vapor deposition (LPCVD) process to deposit polycrystalline silicon material onto a substrate and implants dopant elements into the polycrystalline silicon material to form an LCVD layer that covers the storage structure and fills the storage holes. By adjusting doping parameters such as the type, concentration, and temperature of the dopant elements, the stress state of the LCVD layer can be adjusted, thereby actively changing the relative stress between the LCVD layer and the storage structure (especially the storage layer in the storage structure), optimizing the phase transition and ferroelectric polarization reversal efficiency, and improving storage performance.

[0055] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0056] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this invention can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0057] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a three-dimensional memory for improving thermal effects, characterized in that, Includes the following steps: A substrate is formed, the substrate including a substrate, a bottom dielectric layer on the substrate, a first contact structure penetrating the bottom dielectric layer, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structure, a storage hole penetrating the intermediate dielectric layer and exposing the first contact structure, and a storage structure covering the inner wall of the storage hole, wherein the storage structure is in contact with the first contact structure. Polycrystalline silicon material is deposited on the substrate using a low-pressure chemical vapor deposition process, and dopant elements are implanted into the polycrystalline silicon material to form a low-pressure chemical deposition layer that covers the memory structure and fills the memory holes, and the low-pressure chemical deposition layer is electrically connected to the memory structure. A first lead-out structure is formed above the substrate and electrically connected to the low-pressure chemical deposition layer.

2. The method for manufacturing a three-dimensional memory for improving thermal effects according to claim 1, characterized in that, The specific steps for forming the substrate include: A substrate is provided, the substrate including an active region, and the substrate including a top surface and a bottom surface that are distributed opposite to each other, the active region including a channel region and a source region and a drain region distributed on opposite sides of the channel region along a first direction, the first direction being parallel to the top surface of the substrate; Form the bottom dielectric layer covering the top surface of the substrate; A first contact structure is formed that penetrates the bottom dielectric layer along a second direction and is electrically connected to the drain region, wherein the second direction intersects the top surface of the substrate perpendicularly; An intermediate dielectric layer is formed covering the bottom dielectric layer and the first contact structure; A storage hole is formed that penetrates the intermediate dielectric layer along the second direction and exposes the first contact structure; A storage structure is formed covering the inner wall of the storage hole, and the storage structure is electrically connected to the first contact structure.

3. The method for manufacturing a three-dimensional memory for improving thermal effects according to claim 1, characterized in that, The intermediate dielectric layer includes: A first intermediate dielectric layer covers the bottom dielectric layer and the first contact structure, and the material of the first intermediate dielectric layer includes silicon nitride; A second intermediate dielectric layer covering the first intermediate dielectric layer, wherein the material of the second intermediate dielectric layer includes silicon dioxide; A third intermediate dielectric layer covers the second intermediate dielectric layer, and the material of the third intermediate dielectric layer includes silicon oxynitride.

4. The method for manufacturing a three-dimensional memory for improving thermal effects according to claim 1, characterized in that, The substrate includes a top surface and a bottom surface that are distributed opposite to each other. The substrate includes a plurality of memory cells that are spaced apart along a first direction. Each memory cell includes the first contact structure and the memory hole. The first direction is parallel to the top surface of the substrate. The memory structures in adjacent memory cells are connected as a whole as an initial memory structure. The specific steps of depositing polycrystalline silicon material on the substrate using a low-pressure chemical vapor deposition (LPCVD) process and implanting dopant elements into the polycrystalline silicon material to form a LCVD layer covering the storage structure and filling the storage holes include: Polycrystalline silicon material is deposited on the substrate using a low-pressure chemical vapor deposition process, and doping elements are implanted into the polycrystalline silicon material to form an initial low-pressure chemical deposition layer that continuously covers the entire surface of the initial memory structure away from the substrate and fills the multiple memory holes. An etching process is used to remove a portion of the initial low-pressure chemical deposition layer and a portion of the initial memory structure above the intermediate dielectric layer, disconnecting the connection between the memory structures in adjacent memory cells, and forming a plurality of low-pressure chemical deposition layers that are connected one-to-one with and independent of the plurality of memory structures.

5. The method for manufacturing a three-dimensional memory for improving thermal effects according to claim 1, characterized in that, The substrate includes a top surface and a bottom surface that are distributed opposite to each other. The substrate includes a plurality of memory cells that are spaced apart along a first direction. Each memory cell includes the first contact structure and the memory hole. The first direction is parallel to the top surface of the substrate. The memory structures in adjacent memory cells are connected as a whole as an initial memory structure. The specific steps of depositing polycrystalline silicon material on the substrate using a low-pressure chemical vapor deposition (LPCVD) process and implanting dopant elements into the polycrystalline silicon material to form a LCVD layer covering the storage structure and filling the storage holes include: Polycrystalline silicon material is deposited on the substrate using a low-pressure chemical vapor deposition process, and doping elements are implanted into the polycrystalline silicon material to form an initial low-pressure chemical deposition layer that covers the surface of the initial memory structure away from the substrate and fills the multiple memory holes. The initial low-pressure chemical deposition layer and the initial storage structure located on the top surface of the intermediate medium layer are removed by chemical mechanical polishing process, the connection between the storage structures in adjacent storage cells is disconnected, and multiple low-pressure chemical deposition layers are formed that are connected to each of the multiple storage structures in a one-to-one manner and are independent of each other.

6. The method for manufacturing a three-dimensional memory for improving thermal effects according to claim 1, characterized in that, The specific steps of depositing polycrystalline silicon material on the substrate using a low-pressure chemical vapor deposition (LPCVD) process and implanting dopant elements into the polycrystalline silicon material to form a LCVD layer covering the storage structure and filling the storage holes include: A polycrystalline silicon material is deposited on the substrate using a low-pressure chemical vapor deposition process to form a polycrystalline silicon material layer that covers the storage structure and fills the storage holes. The doping element is implanted into the polycrystalline silicon material layer using an ion implantation process to form the low-pressure chemical deposition layer. The low-pressure chemical deposition layer is subjected to rapid thermal annealing.

7. The method for manufacturing a three-dimensional memory for improving thermal effects according to claim 1, characterized in that, The doping element is any one or a combination of two or more of arsenic, phosphorus and boron.

8. The method for manufacturing a three-dimensional memory for improving thermal effects according to claim 1, characterized in that, The deposition temperature of the low-pressure chemical vapor deposition process is 550℃~650℃.

9. The method for manufacturing a three-dimensional memory for improving thermal effects according to claim 1, characterized in that, The specific steps for forming the first lead-out structure located above the substrate and electrically connected to the low-pressure chemical deposition layer include: A top dielectric layer is formed covering the intermediate dielectric layer, the low-pressure chemical deposition layer, and the storage structure; A first lead-out structure is formed that penetrates the top dielectric layer and is electrically connected to the low-pressure chemical deposition layer.

10. A three-dimensional memory for improving thermal effects, characterized in that, include: The substrate includes a substrate, a bottom dielectric layer on the substrate, a first contact structure penetrating the bottom dielectric layer, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structure, a storage hole penetrating the intermediate dielectric layer and exposing the first contact structure, and a storage structure covering the inner wall of the storage hole, wherein the storage structure is in contact with the first contact structure. A low-pressure chemical deposition layer covers the surface of the storage structure and fills the storage holes. The material of the low-pressure chemical deposition layer includes polycrystalline silicon and doped elements, and the low-pressure chemical deposition layer is electrically connected to the storage structure. The first lead-out structure is located above the substrate and is electrically connected to the low-pressure chemical deposition layer.

11. The three-dimensional memory for improving thermal effects according to claim 10, characterized in that, The storage structure covers the inner wall of the storage hole and a portion of the intermediate dielectric layer opposite to the top surface of the substrate, and the low-pressure chemical deposition layer fills the storage hole and covers the surface of the storage structure located on the top surface of the intermediate dielectric layer.

12. The three-dimensional memory for improving thermal effects according to claim 10, characterized in that, The storage structure is opposite to the top surface of the substrate, the low-pressure chemical deposition layer is opposite to the top surface of the substrate, and the intermediate dielectric layer is flush with the top surface of the substrate.

13. The three-dimensional memory for improving thermal effects according to claim 10, characterized in that, The doping element is any one or a combination of two or more of arsenic, phosphorus and boron.

14. The three-dimensional memory for improving thermal effects according to claim 10, characterized in that, Also includes: A top dielectric layer covers the intermediate dielectric layer, the low-pressure chemical deposition layer, and the storage structure, wherein the first lead-out structure penetrates the top dielectric layer and is electrically connected to the low-pressure chemical deposition layer.

15. The three-dimensional memory for improving thermal effects according to claim 10, characterized in that, The storage structure includes: The lower electrode layer covers the inner wall of the storage hole and is electrically connected to the first contact structure. A storage layer covers the surface of the lower electrode layer, and the material of the storage layer is a phase change material or a ferroelectric material; An upper electrode layer covers the surface of the storage layer, and the low-pressure chemical deposition layer covers the surface of the upper electrode layer and is electrically connected to the upper electrode layer.

Images