An image sensor and a manufacturing method thereof

Abstract

The application discloses an image sensor and a manufacturing method thereof, comprising the following steps: providing a plurality of substrates, ion implantation is performed on the substrates to form a first well region and a second well region on the substrates, and high-temperature annealing treatment is performed on the first well region and the second well region; a gate oxide layer and a polysilicon layer are sequentially formed on the surface of the substrate; ion implantation is performed on the first well region and the second well region to form a source and a drain on the substrate; annealing treatment is performed on the source and the drain; wherein, after each processing step ends, it is determined whether to perform low-temperature heat treatment on the substrate: when the number of substrates currently to be processed by the low-temperature heat treatment equipment is less than or equal to a set threshold, the low-temperature heat treatment is performed on the substrate in the low-temperature heat treatment equipment; when the number of substrates currently to be processed by the low-temperature heat treatment equipment is greater than the set threshold, the next processing step is performed on the substrate. The method can dynamically realize low-temperature heat treatment on the substrate after different processing steps end, improves white pixels, and improves production efficiency.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and more specifically to an image sensor and its manufacturing method. Background Technology

[0002] In the actual manufacturing process of CMOS image sensors, when using plasma technology to etch or deposit materials, the plasma may damage the photosensitive element and introduce metal impurity ions. This causes the image chip to generate electrons in the dark, which are then incorrectly collected by the photodiode, resulting in a large number of white pixels (WPs), thus affecting product yield. To improve the white pixel problem in CMOS image sensors, furnace tube processes are typically used. However, due to the limited capacity of furnace tubes, products often accumulate at the furnace tube processing station, impacting the overall production efficiency of the production line. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of existing technologies that lead to reduced production efficiency when improving the white pixel problem on wafers.

[0004] To achieve the above objectives, the present invention provides a method for manufacturing an image sensor, comprising at least the following processing steps:

[0005] Step S1: Provide a plurality of substrates, perform ion implantation on the substrates to form a first well region and a second well region on the substrates, and perform high-temperature annealing on the first well region and the second well region.

[0006] Step S2: A gate oxide layer and a polysilicon layer are sequentially formed on the surface of the substrate;

[0007] Step S3: Ion implantation is performed into the first well region and the second well region to form the source and drain on the substrate;

[0008] Step S4: Anneal the source and drain electrodes.

[0009] Starting from step S1, after each processing step, it is determined sequentially whether to perform a low-temperature heat treatment step on the substrate:

[0010] When the number of substrates to be processed in the low-temperature heat treatment equipment is less than or equal to a set threshold, the substrates are subjected to low-temperature heat treatment in the low-temperature heat treatment equipment.

[0011] When the number of substrates to be processed in the low-temperature heat treatment equipment is greater than the set threshold, the next processing step is performed on the substrates.

[0012] Optionally, after performing low-temperature heat treatment on the substrate, the next processing step can be performed directly without further determining whether to perform low-temperature heat treatment on the substrate.

[0013] Optionally, after all processing steps are completed, the substrate undergoes a single low-temperature heat treatment step.

[0014] Optionally, after steps S1 to S3 are completed, if the number of substrates to be processed in the low-temperature heat treatment equipment is greater than a set threshold, then after step S4 is completed, the substrates are subjected to low-temperature heat treatment in the low-temperature heat treatment equipment.

[0015] Optionally, the temperature of the low-temperature heat treatment is 550℃~650℃, and the time of the low-temperature heat treatment is 1h~10h.

[0016] Optionally, the low-temperature heat treatment equipment includes at least a rapid heat treatment furnace or furnace tubes.

[0017] Optionally, the furnace tube is a horizontal furnace tube or a vertical furnace tube.

[0018] Optionally, it further includes forming a pad oxide layer on the substrate surface after step S1 ends and before step S2 begins.

[0019] Optionally, the method further includes: after step S2 ends and before step S3 begins, etching the polysilicon layer using an etching process to form a polysilicon gate, and forming sidewalls on both sides of the polysilicon gate.

[0020] Optionally, the method further includes: after forming sidewalls on both sides of the polysilicon gate, removing the pad oxide layer using a wet etching process.

[0021] Optionally, in step S1, the first well region is an N-well region or a P-well region, and the second well region is a P-well region or an N-well region.

[0022] Optionally, in step S1, the high-temperature annealing temperature is 600℃~1000℃.

[0023] Optionally, in step S3, the ion includes at least one or more of phosphorus, arsenic, and boron.

[0024] Optionally, in step S4, the annealing temperature is at least 950°C.

[0025] The present invention also provides an image sensor formed by the above-described manufacturing method.

[0026] Compared to the prior art, the beneficial effects of the present invention include at least the following:

[0027] (1) The image sensor manufacturing method of the present invention includes high-temperature annealing of the well region, forming a gate oxide layer and a polysilicon layer on the substrate surface, forming a source and a drain by ion implantation, and annealing the source and drain. Starting from the first processing step (high-temperature annealing of the well region), after each processing step, a logical judgment method is used to determine whether to perform low-temperature heat treatment on the substrate. If the number of substrates to be processed in the low-temperature heat treatment equipment is less than or equal to a set threshold, it means that the substrates are not piling up in the processing station of the low-temperature heat treatment equipment, and the substrates can be subjected to low-temperature heat treatment. If the number of substrates to be processed in the low-temperature heat treatment equipment is greater than the set threshold, it means that the substrates are piling up in the processing station of the low-temperature heat treatment equipment, and the substrates are not subjected to low-temperature heat treatment, and the next processing step is directly performed. By dynamically adjusting the position of low-temperature heat treatment on the substrate through the above logical judgment method, the production efficiency of the entire product line is greatly improved while improving the white pixels.

[0028] (2) If the number of substrates to be processed by the low-temperature heat treatment equipment is greater than the set threshold after the first three processing steps are completed, then no further logical judgment is required after the last processing step is completed. The substrates are directly subjected to low-temperature heat treatment, ensuring that the substrates are subjected to low-temperature heat treatment at least once in the entire production process. By improving the white pixels, the image quality is improved.

[0029] (3) While the white pixels of the image sensor are reduced, the full well capacity (FWC) is almost not lost, so a balance can be maintained between improving image quality and maintaining image sensor performance. Attached Figure Description

[0030] Figure 1 This is a flowchart of a method for manufacturing an image sensor according to the present invention.

[0031] Figure 2 The diagram below illustrates the relationship between the white pixels and the full-well capacity of an image sensor after the image sensor manufacturing method of the present invention is adopted as an example. Detailed Implementation

[0032] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] In the description of this invention, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0034] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0035] It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, and are only used to facilitate and clearly illustrate the purpose of this invention.

[0036] Definition: The “set threshold” mentioned in this invention refers to the maximum number of wafers that the low-temperature heat treatment equipment can process per unit time or the maximum production capacity that can be achieved.

[0037] The applicant discovered that, for CMOS image sensors, low-temperature thermal processing of the wafer during the manufacturing process can significantly improve the white pixel problem, mainly for the following reasons:

[0038] (1) Reduce metal impurity ion contamination: Low temperature heat treatment can capture the immersed metal ions by strengthening the barrier layer, effectively preventing other electronic contamination of the pixel area, thereby reducing the generation of white pixels.

[0039] (2) Repairing interface defects: Low-temperature heat treatment helps to repair plasma damage, reduce interface defects, and thus improve the performance of white pixels.

[0040] (3) Reduce dark current: Low temperature heat treatment helps to reduce dark current because the generation of dark current is related to impurities and surface states introducing additional energy levels in the band gap, making it easier for electrons to jump. By reducing dark current, the generation of white pixels can be reduced.

[0041] This application attempts to use furnace tube technology for low-temperature heat treatment of wafers to improve the white pixel problem. The specific operation process includes: setting the temperature in the furnace tube in advance, transferring the wafer into the furnace tube, and holding the wafer at the set annealing temperature for a period of time after reaching the set annealing temperature to allow the atoms in the material to move and rearrange, which helps to eliminate lattice defects and increase grain size, etc.; cooling for a period of time after annealing, and after the heat treatment is completed, the wafer is taken out for subsequent processing steps.

[0042] For example, the aforementioned low-temperature heat treatment is performed on wafers at certain fixed stages of the process, such as after ion implantation, after thin film deposition, after barrier layer deposition, and during metal silicide formation. However, due to the limited capacity of each furnace tube, only a fixed number of wafers can be processed at a time. When a large number of wafers need to be batch-processed at low temperatures, a large number of wafers may accumulate at a certain process stage in the furnace tube equipment processing station, preventing these wafers from proceeding to the next processing step and thus affecting the overall production efficiency of the product line.

[0043] To address the aforementioned shortcomings, this invention provides a method for manufacturing an image sensor, comprising at least four processing steps: high-temperature annealing of the well region, formation of a gate oxide layer and a polysilicon layer on the substrate surface, ion implantation of the well region to form source and drain electrodes on the substrate, and annealing of the source and drain electrodes. Starting with the high-temperature annealing of the well region, after each of the above processing steps, it is sequentially determined whether to perform a low-temperature heat treatment step on the substrate: if the number of substrates currently to be processed in the low-temperature heat treatment equipment is less than or equal to a set threshold, then the substrate is subjected to low-temperature heat treatment in the low-temperature heat treatment equipment; if the number of substrates currently to be processed in the low-temperature heat treatment equipment is greater than the set threshold, then the substrate directly proceeds to the next processing step. By setting this logical judgment, the position for performing low-temperature heat treatment on the substrate can be dynamically adjusted, avoiding the stockpiling problem caused by performing low-temperature heat treatment at a fixed process stage, and improving production efficiency while improving white pixels.

[0044] like Figure 1 As shown, the present invention provides a method for manufacturing an image sensor, comprising at least the following processing steps:

[0045] Step S1: Provide a plurality of substrates, perform ion implantation on the substrates to form a first well region and a second well region on the substrates, and perform high-temperature annealing on the first well region and the second well region.

[0046] In the fabrication of CMOS image sensors, the first step is typically to prepare and process the semiconductor substrate, typically a silicon substrate, which forms the basis for all subsequent structures. Before the process begins, pretreatment steps are also included on the silicon substrate, such as cleaning, oxidation, or other surface treatments, to ensure that the silicon substrate surface is suitable for subsequent processing steps.

[0047] In semiconductor manufacturing, well ion implantation (Well IMP) is a crucial step used to form well regions with different electrical properties to achieve device isolation and construct specific device structures. The purpose of Well IMP is to create N-type or P-type well regions, which serve as isolation regions or as part of transistors. For example, implanting P-type elements onto a P-type substrate forms a P-well, and implanting N-type elements onto an N-type substrate forms an N-well. The first well region in this invention can be either an N-well or a P-well, and the second well region can be either a P-well or an N-well.

[0048] After forming the P-well and N-well regions, high-temperature annealing is performed on them to activate the implanted dopant elements (such as boron and phosphorus) in the silicon lattice, thereby altering the electrical properties of silicon. This also promotes the diffusion of dopant elements in silicon, contributing to a more uniform doping distribution, which is crucial for adjusting transistor characteristics and optimizing device performance. In some embodiments, the high-temperature annealing temperature is 600°C to 1000°C.

[0049] After high-temperature annealing of the P-well and N-well regions, a pad oxide layer is formed on the substrate surface. The pad oxide layer can serve as a stress buffer layer to prevent other layers deposited in subsequent processes from damaging the silicon surface. It also helps to control the etching depth and sidewall angle, which is crucial for forming a uniform and precise STI structure.

[0050] Step S2: A gate oxide layer and a polysilicon layer are sequentially formed on the surface of the substrate.

[0051] A gate oxide layer and a polysilicon layer are sequentially deposited in a predetermined area using chemical vapor deposition (CVD). A desired pattern is transferred onto the polysilicon layer using photolithography. The polysilicon portions not protected by photoresist are etched away, forming a specific shape for the polysilicon gate. A thin oxide layer is deposited on both sides of the polysilicon gate. By coating with photoresist, exposure, and development, a desired pattern is formed on the oxide layer. The oxide portions not covered by the photoresist are etched away, leaving the oxide layer beneath the photoresist-patterned area. Sidewall structures are formed on both sides of the remaining oxide layer. After forming the sidewalls on both sides of the polysilicon gate, the pad oxide layer is precisely removed using diluted hydrofluoric acid and hot phosphoric acid. By controlling the reaction time and concentration of these solutions, the pad oxide layer is prepared for subsequent processing steps.

[0052] Step S3: Ion implantation is performed into the first well region and the second well region to form the source and drain on the substrate.

[0053] After forming P-well and N-well regions on the aforementioned substrate, NMOS and PMOS transistors are constructed. Ion implantation is performed into the P-well and N-well regions, wherein the ions contain at least one or more of phosphorus, arsenic, and boron. Source and drain electrodes are formed on the substrate through heavy doping.

[0054] Step S4: Anneal the source and drain electrodes.

[0055] After the source and drain are formed, the substrate is annealed at at least 950°C. During the annealing process, the injected impurity atoms migrate from the interstitial spaces to the lattice sites, forming effective doping. Annealing can also make the internal arrangement of the material more orderly and improve the structure, thereby improving the overall performance and reliability of the device.

[0056] Starting from step S1, after each processing step, it is determined sequentially whether to perform a low-temperature heat treatment step on the substrate:

[0057] When the number of substrates to be processed in the low-temperature heat treatment equipment is less than or equal to a set threshold, the substrates are subjected to low-temperature heat treatment in the low-temperature heat treatment equipment.

[0058] When the number of substrates to be processed in the low-temperature heat treatment equipment is greater than the set threshold, the next processing step is performed on the substrates.

[0059] Low-temperature heat treatment of the substrate can significantly improve the white pixel problem in image sensors. While improving the white pixel problem, to avoid substrate buildup in the heat treatment equipment and thus affecting production efficiency, logical judgments are added to the processing steps. By determining whether low-temperature heat treatment is needed after each processing step, the processing position of the low-temperature heat treatment can be dynamically adjusted, thereby improving production efficiency. In some embodiments, the temperature of the low-temperature heat treatment is 550℃~650℃, and the duration of the low-temperature heat treatment is 1h~10h.

[0060] Understandably, at the beginning of substrate processing, i.e. after the high-temperature annealing of the first and second well regions, it is determined whether a low-temperature heat treatment step is required for the substrate. If the number of substrates to be processed by the heat treatment equipment is less than or equal to a set threshold, then the substrate is subjected to low-temperature heat treatment after this step is completed. If the number of substrates to be processed by the heat treatment equipment is greater than the set threshold, then the substrate is not subjected to low-temperature heat treatment after this step is completed, but the next processing step is directly performed on the substrate, i.e., the gate oxide layer and polysilicon layer are formed sequentially on the substrate surface. After the gate oxide layer and polysilicon layer are formed, the same logic judgment is performed again, and the judgment is performed sequentially until all processing steps are completed.

[0061] To further improve production efficiency, after any of the above processing steps, the substrate undergoes a low-temperature heat treatment, and then the next processing step is performed directly without further evaluation to determine whether a further low-temperature heat treatment is needed. It is understood that the substrate only needs to undergo one low-temperature heat treatment step throughout the entire product line, without the need for multiple treatments. This single low-temperature heat treatment accelerates the diffusion rate of metal impurity ions, and the numerous grain boundaries in the polycrystalline silicon layer adsorb metal impurity ions from the photodiode region into the polycrystalline silicon layer, significantly reducing metal impurity contamination in the photodiode region and thus improving the white pixel performance of the image sensor.

[0062] To prevent the number of substrates to be processed in the low-temperature heat treatment equipment from exceeding a set threshold after each processing step, thus preventing the substrates from undergoing low-temperature heat treatment, a mechanism is established that after steps S1 to S3, if the number of substrates to be processed in the low-temperature heat treatment equipment exceeds the set threshold, then after step S4, logical judgment will not continue, and the substrates will be forcibly subjected to low-temperature heat treatment. This ensures that the substrates undergo at least one low-temperature heat treatment throughout the entire product line.

[0063] The aforementioned low-temperature heat treatment equipment refers to devices capable of providing precise temperature control, which can perform heat treatment on substrates at low temperatures to improve their performance. It is understood that different low-temperature heat treatment devices have different maximum capacities; therefore, the specific value of the set threshold mentioned in this invention is determined based on the actual low-temperature heat treatment equipment used. In some embodiments, the low-temperature heat treatment equipment includes at least a rapid heat treatment furnace or furnace tubes. In this invention, horizontal or vertical furnace tubes are used.

[0064] Example

[0065] This embodiment provides a method for manufacturing an image sensor, comprising the following processing steps:

[0066] 1. Prepare 100 silicon substrates, wherein the silicon substrates contain n-type substrates and p-type substrates. Boron ions are implanted into the n-type substrates to form P-well regions, and phosphorus ions and arsenic ions are implanted into the p-type substrates to form N-well regions. The P-well regions and N-well regions are subjected to high-temperature annealing at a temperature of 800°C.

[0067] 2. A silicon dioxide layer is formed on the surface of a silicon substrate through a thermal oxidation process, and a polycrystalline silicon layer is formed on the surface of the silicon dioxide layer through a chemical vapor deposition process.

[0068] 3. N-type doped ions, such as phosphorus ions and arsenic ions, are implanted onto the silicon substrate to form the source and drain of the NMOS.

[0069] 4. Anneal the source and drain electrodes at a temperature of 950℃.

[0070] In this embodiment, the furnace tube's capacity (set threshold) is 25 silicon substrates. After step 1, there are 30 silicon substrates to be processed in the furnace tube, so the silicon substrates are transferred to the next processing step (step 2). After step 2, there are 40 silicon substrates to be processed in the furnace tube, so the silicon substrates are transferred to the next processing step (step 3). After step 3, there are 10 silicon substrates to be processed in the furnace tube. The furnace tube's heat treatment temperature is set to 580℃ and the heat treatment time is set to 1 hour. The silicon substrates are then transferred into the furnace tube and heated to the set temperature and held for a period of time to repair lattice damage and activate impurities. After the low-temperature heat treatment is completed, the silicon substrates are slowly cooled and removed from the furnace tube to continue to the next processing step (step 4).

[0071] like Figure 2 As shown, after performing low-temperature thermal treatment on the silicon substrate in the above steps, the white pixel count (WP) decreased by 30%, while the full-well capacity (FWC) only decreased by 5 DN. Therefore, without affecting the full-well capacity of the image sensor, this manufacturing method can improve the white pixel problem of the image sensor and also increase the production efficiency of the entire product line.

[0072] In summary, this invention provides a method for manufacturing an image sensor. A logical judgment function is added to the processing steps to determine whether to perform low-temperature heat treatment on the substrate in that step based on the maximum capacity of the current low-temperature heat treatment equipment: if the number of substrates currently awaiting processing in the low-temperature heat treatment equipment is less than or equal to the maximum capacity, it indicates that there is no substrate backlog at the heat treatment station, and low-temperature heat treatment is performed on the substrates; if the number of substrates currently awaiting processing in the low-temperature heat treatment equipment is greater than the maximum capacity, it indicates that there is substrate backlog at the heat treatment station, and low-temperature heat treatment is skipped, and the substrates proceed directly to the next processing step. This method avoids the backlog problem caused by performing low-temperature heat treatment on substrates in a fixed process flow. By dynamically adjusting the order of low-temperature heat treatment in different processing steps using logical judgment, it improves the white pixels in the image while significantly increasing the overall production efficiency of the product line.

[0073] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A method for manufacturing an image sensor, characterized in that, It should include at least the following processing steps: Step S1: Provide a plurality of substrates, perform ion implantation on the substrates to form a first well region and a second well region on the substrates, and perform high-temperature annealing on the first well region and the second well region. Step S2: A gate oxide layer and a polysilicon layer are sequentially formed on the surface of the substrate; Step S3: Ion implantation is performed into the first well region and the second well region to form the source and drain on the substrate; Step S4: Anneal the source and drain electrodes. Starting from step S1, after each processing step, it is determined sequentially whether to perform a low-temperature heat treatment step on the substrate: When the number of substrates to be processed in the low-temperature heat treatment equipment is less than or equal to a set threshold, the substrates are subjected to low-temperature heat treatment in the low-temperature heat treatment equipment. When the number of substrates to be processed in the low-temperature heat treatment equipment is greater than the set threshold, the next processing step is performed on the substrates.

2. The manufacturing method as described in claim 1, characterized in that, After the substrate undergoes low-temperature heat treatment, the next processing step is performed directly without further determination of whether the substrate needs to undergo low-temperature heat treatment.

3. The manufacturing method as described in claim 2, characterized in that, After all processing steps are completed, the substrate undergoes a single low-temperature heat treatment step.

4. The manufacturing method as described in claim 1, characterized in that, After steps S1 to S3 are completed, if the number of substrates to be processed in the low-temperature heat treatment equipment is greater than the set threshold, then after step S4 is completed, the substrates are subjected to low-temperature heat treatment in the low-temperature heat treatment equipment.

5. The manufacturing method as described in claim 1, characterized in that, The temperature of the low-temperature heat treatment is 550℃~650℃, and the time of the low-temperature heat treatment is 1h~10h.

6. The manufacturing method as described in claim 1, characterized in that, The low-temperature heat treatment equipment includes at least a rapid heat treatment furnace or furnace tubes.

7. The manufacturing method as described in claim 6, characterized in that, The furnace tubes are either horizontal or vertical.

8. The manufacturing method as described in claim 1, characterized in that, Also includes: After step S1 ends and before step S2 begins, a pad oxide layer is formed on the substrate surface.

9. The manufacturing method as described in claim 8, characterized in that, Also includes: After step S2 ends and before step S3 begins, the polysilicon layer is etched using an etching process to form a polysilicon gate, and sidewalls are formed on both sides of the polysilicon gate.

10. The manufacturing method as described in claim 9, characterized in that, Also includes: After sidewalls are formed on both sides of the polysilicon gate, the pad oxide layer is removed using a wet etching process.

11. The manufacturing method as described in claim 1, characterized in that, In step S1, the first well region is an N-well region or a P-well region, and the second well region is a P-well region or an N-well region.

12. The manufacturing method as described in claim 1, characterized in that, In step S1, the high-temperature annealing temperature is 600℃~1000℃.

13. The manufacturing method as described in claim 1, characterized in that, In step S3, the ion contains at least one or more of phosphorus, arsenic, and boron.

14. The manufacturing method as described in claim 1, characterized in that, In step S4, the annealing temperature is at least 950°C.

15. An image sensor, characterized in that, The image sensor is formed using the manufacturing method described in any one of claims 1 to 14.

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