Stacked battery and method for manufacturing the same, photovoltaic module

Abstract

This application relates to a tandem solar cell, its fabrication method, and a photovoltaic module. The tandem solar cell includes a first cell structure and a second cell structure stacked together. The first cell structure includes: a semiconductor substrate having a first surface and a second surface disposed opposite to each other, and a first side surface connected to the first surface and the second surface; a tunneling layer and a first doped semiconductor layer stacked on the first surface and the first side surface; an intrinsic semiconductor layer and a second doped semiconductor layer stacked on the second surface and the first side surface; the surface of the semiconductor substrate has an overlapping region, the overlapping region being at least located on the first side surface, and a portion of the tunneling layer, a portion of the first doped semiconductor layer, a portion of the intrinsic semiconductor layer, and a portion of the second doped semiconductor layer stacked in the overlapping region along a direction away from the semiconductor substrate. Therefore, the tandem solar cell, its fabrication method, and the photovoltaic module provided in this application can improve the passivation effect of the tandem solar cell.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to tandem cells and their preparation methods, and photovoltaic modules. Background Technology

[0002] Solar cells, also known as photovoltaic cells, are semiconductor devices that directly convert sunlight into electrical energy. Because they are green and environmentally friendly products that do not cause pollution, and because solar energy is a renewable resource, solar cells are a new type of battery with broad development prospects.

[0003] Among related technologies, tandem solar cells, made with solar cell materials whose bandgap widths match different spectral bands, can maximize the conversion of solar energy into electrical energy and are widely recognized as an effective way to further improve cell efficiency. Because perovskite materials possess characteristics such as high light absorption, adjustable bandgap, and complementary absorption regions of the solar spectrum to silicon cells, tandem cell structures using perovskite as the top cell and crystalline silicon as the bottom cell have received widespread attention and research.

[0004] However, the passivation effect of the aforementioned solar tandem cells needs to be improved. Summary of the Invention

[0005] Therefore, it is necessary to provide a tandem solar cell, its preparation method, and a photovoltaic module, which can improve the passivation effect of the tandem solar cell.

[0006] In a first aspect, embodiments of this application provide a stacked battery, which includes a first battery structure and a second battery structure stacked together; the first battery structure includes:

[0007] A semiconductor substrate has a first surface and a second surface disposed opposite to each other, and a first side surface connected to the first surface and the second surface;

[0008] A tunnel layer is provided on the first face and the first side face.

[0009] A first doped semiconductor layer is disposed on a first surface and a first side surface, and is disposed on the side of the tunneling layer away from the semiconductor substrate;

[0010] An intrinsic semiconductor layer is disposed on the second side and the first side;

[0011] The second doped semiconductor layer is disposed on the second side and the first side, and is disposed on the side of the intrinsic semiconductor layer away from the semiconductor substrate;

[0012] The semiconductor substrate has an overlapping region on its surface, which is located at least on the first side. A portion of the tunneling layer, a portion of the first doped semiconductor layer, a portion of the intrinsic semiconductor layer, and a portion of the second doped semiconductor layer are stacked in the overlapping region along a direction away from the semiconductor substrate.

[0013] In one embodiment, the first side surface includes a first sub-side surface and a second sub-side surface connected together. The first sub-side surface is connected to the first surface, and the second sub-side surface is connected to the second surface. The orthogonal projection of the tunneling layer and the first doped semiconductor layer on the plane where the first side surface is located overlaps with the first sub-side surface but does not overlap with the second sub-side surface. At least part of the overlapping area is located on the first sub-side surface.

[0014] In one embodiment, the dimension of the first sub-side along the thickness direction of the semiconductor substrate is greater than the dimension of the second sub-side along the thickness direction of the semiconductor substrate.

[0015] In one embodiment, the intrinsic semiconductor layer is in contact with the second sub-side.

[0016] In one embodiment, the overlapping area includes a first sub-overlapping area and a second sub-overlapping area, the first sub-overlapping area being located on a first side surface and the second sub-overlapping area being located at the edge of the first side surface;

[0017] Both the intrinsic semiconductor layer and the second doped semiconductor layer are located in the second sub-overlap region.

[0018] In one embodiment, the size of the second sub-overlapping region along the center to edge direction of the first surface is less than or equal to 300 μm.

[0019] In one embodiment, the intrinsic semiconductor layer includes a third surface facing the semiconductor substrate and a fourth surface away from the semiconductor substrate, as well as a second side surface connecting the third surface and the fourth surface.

[0020] The second doped semiconductor layer is flush with the second side surface; or...

[0021] A second doped semiconductor layer covers the second side surface.

[0022] In one embodiment, the first battery structure includes a first conductive layer and a second conductive layer disposed at intervals. The first conductive layer is disposed on a first surface and on the side of the first doped semiconductor layer away from the semiconductor substrate, and the second conductive layer is disposed on a second surface and on the side of the second doped semiconductor layer away from the semiconductor substrate.

[0023] In one embodiment, one of the first conductive layer and the second conductive layer is located between the second battery structure and the semiconductor substrate, and is disposed on the side of the second doped semiconductor layer located in the overlapping region away from the semiconductor substrate.

[0024] In one embodiment, the second battery structure is disposed on the side of the first surface opposite to the second surface, and the first conductive layer is located between the second battery structure and the semiconductor substrate, and is located on the first side surface.

[0025] In one embodiment, the second doped semiconductor layer located in the overlapping region is spaced apart from the second conductive layer.

[0026] In one embodiment, the outer contour of the second conductive layer as an orthographic projection on the plane where the second surface is located is disposed at intervals within the outer contour of the second surface.

[0027] In one embodiment, the second battery structure is disposed on the side of the second surface opposite to the first surface, and the second conductive layer is located between the second battery structure and the semiconductor substrate, and is located on the first side surface.

[0028] In one embodiment, the overlapping region includes a second sub-overlapping region located at the edge of the first surface, and a second conductive layer is disposed in the second sub-overlapping region.

[0029] In one embodiment, the first doped semiconductor layer located in the overlapping region is spaced apart from the first conductive layer; and / or,

[0030] The intrinsic semiconductor layer and the second doped semiconductor layer are both spaced apart from the first conductive layer.

[0031] In one embodiment, the outer contour of the first conductive layer projected onto the plane of the first surface is spaced out within the outer contour of the first surface.

[0032] In one embodiment, a portion of the second battery structure is disposed on the first side and located outside the first battery structure.

[0033] In one embodiment, the first battery structure includes an insulating layer disposed between a first doped semiconductor layer and an intrinsic semiconductor layer located in an overlapping region.

[0034] In one embodiment, the material of the first doped semiconductor layer includes polycrystalline silicon; and / or,

[0035] The insulating layer material includes borosilicate glass or phosphosilicate glass; and / or,

[0036] The material of the second doped semiconductor layer includes microcrystalline silicon or amorphous silicon.

[0037] Secondly, embodiments of this application provide a method for fabricating a stacked battery, the method comprising forming a first battery structure and a second battery structure stacked together; forming the first battery structure includes:

[0038] A semiconductor substrate is provided; the semiconductor substrate has a first surface and a second surface disposed opposite to each other, and a first side surface connected to the first surface and the second surface;

[0039] A tunneling layer and a first doped semiconductor layer are formed on both the first surface and the first side surface; the first doped semiconductor layer is disposed on the side of the tunneling layer opposite to the semiconductor substrate.

[0040] An intrinsic semiconductor layer and a second doped semiconductor layer are formed on both the second and first sides; the second doped semiconductor layer is disposed on the side of the intrinsic semiconductor layer that is away from the semiconductor substrate.

[0041] The semiconductor substrate has an overlapping region on its surface, which is located at least on the first side. A portion of the tunneling layer, a portion of the first doped semiconductor layer, a portion of the intrinsic semiconductor layer, and a portion of the second doped semiconductor layer are stacked in the overlapping region along a direction away from the semiconductor substrate.

[0042] In one embodiment, forming a tunneling layer and a first doped semiconductor layer on both the first surface and the first side surface includes:

[0043] A tunneling material layer is formed on the first surface, the second surface, and the first side surface;

[0044] A first doped semiconductor material layer and an insulating material layer are formed on the side of the tunneling material layer away from the semiconductor substrate; the first doped semiconductor material layer and the insulating material layer are both located on the first surface, the second surface, and the first side surface;

[0045] At least the insulating material layer on the second side is removed; the insulating material layer on the first side and at least part of the first side surface is retained;

[0046] Using the retained insulating material layer as a mask, the first doped semiconductor material layer and the tunneling material layer exposed outside the mask are removed, and the retained first doped semiconductor material layer and tunneling material layer are respectively formed into the first doped semiconductor layer and the tunneling layer.

[0047] In one embodiment, before forming an intrinsic semiconductor layer and a second doped semiconductor layer on both the second side and the first side, the process includes: removing an insulating material layer;

[0048] Alternatively, during the process of forming an intrinsic semiconductor layer and a second doped semiconductor layer on both the second side and the first side, the process further includes: forming an intrinsic semiconductor layer and a second doped semiconductor layer on at least the side of the insulating material layer located in the overlapping region that faces away from the semiconductor substrate.

[0049] After forming an intrinsic semiconductor layer and a second doped semiconductor layer on both the second and first sides, the process includes removing the insulating material layer located outside the overlapping region, retaining the insulating material layer located in the overlapping region, and forming an insulating layer.

[0050] In one embodiment, after forming an intrinsic semiconductor layer and a second doped semiconductor layer on both the second and first sides, the process includes:

[0051] A first conductive layer and a second conductive layer are formed at intervals; the first conductive layer is disposed on a first surface and on the side of the first doped semiconductor layer away from the semiconductor substrate, and the second conductive layer is disposed on a second surface and on the side of the second doped semiconductor layer away from the semiconductor substrate.

[0052] Thirdly, embodiments of this application provide a photovoltaic module, including a tandem cell prepared by the method of the first aspect or the second aspect.

[0053] The tandem battery and its fabrication method, as well as the photovoltaic module provided in this application embodiment, achieve full surface passivation of the semiconductor substrate by overlapping the tunneling layer and the intrinsic semiconductor layer in the overlapping area, thereby improving the conversion efficiency of the first battery structure. In addition, overlapping the first doped semiconductor layer and the second doped semiconductor layer on the first side provides better protection for the tunneling layer and the intrinsic semiconductor layer. Attached Figure Description

[0054] Figure 1 This is a cross-sectional view of a stacked battery provided in an embodiment of this application.

[0055] Figure 2 Another cross-sectional view of the stacked battery provided in an embodiment of this application.

[0056] Figure 3 Another cross-sectional view of the stacked battery provided in an embodiment of this application.

[0057] Figure 4 Another cross-sectional view of the stacked battery provided in an embodiment of this application.

[0058] Figure 5 Another cross-sectional view of the stacked battery provided in an embodiment of this application.

[0059] Figure 6 Another cross-sectional view of the stacked battery provided in an embodiment of this application.

[0060] Figure 7 Another cross-sectional view of the stacked battery provided in an embodiment of this application.

[0061] Figure 8 This is a schematic diagram of the structure after providing a semiconductor substrate, as provided in an embodiment of this application.

[0062] Figure 9 This is a schematic diagram of the structure after the tunneling layer is formed, as provided in an embodiment of this application.

[0063] Figure 10 This is a schematic diagram of the structure after the formation of the insulating material layer, provided in an embodiment of this application.

[0064] Figure 11 This is a schematic diagram of the structure after removing the insulating material layer on the second surface, as provided in an embodiment of this application.

[0065] Figure 12 This is a schematic diagram of the structure after removing the first doped semiconductor material layer and the tunneling material layer exposed outside the mask, as provided in an embodiment of this application.

[0066] Figure 13 This is a schematic diagram of a structure with all insulating material layers removed, provided as an embodiment of this application.

[0067] Figure 14 This is a schematic diagram of the structure after forming the intrinsic semiconductor layer and the second doped semiconductor layer, provided in an embodiment of this application.

[0068] Figure 15 This is a schematic diagram of the structure for forming the first conductive layer and the second conductive layer, provided in an embodiment of this application.

[0069] Figure 16 This is another schematic diagram of the structure after forming the intrinsic semiconductor layer and the second doped semiconductor layer, provided for an embodiment of this application.

[0070] Figure 17 This is another structural schematic diagram of the formation of the first conductive layer and the second conductive layer provided in an embodiment of this application.

[0071] Figure 18 This is another schematic diagram of the structure after forming the intrinsic semiconductor layer and the second doped semiconductor layer, provided for an embodiment of this application.

[0072] Figure 19 This is a schematic diagram of the structure after removing the intrinsic semiconductor layer and the second doped semiconductor layer that are wound around the first surface, as provided in an embodiment of this application.

[0073] Figure 20 This is a schematic diagram of the structure for removing the insulating material layer located outside the overlapping area, provided in an embodiment of this application.

[0074] Figure 21 This is another structural schematic diagram of the formation of the first conductive layer and the second conductive layer provided in an embodiment of this application.

[0075] Figure 22 This is another structural schematic diagram of removing the insulating material layer on the second side, provided as an embodiment of this application.

[0076] Figure 23 This is a schematic diagram of the structure after removing the first doped semiconductor material layer and the tunneling material layer exposed outside the mask, as provided in an embodiment of this application.

[0077] Figure 24This is a schematic diagram of a structure with all insulating material layers removed, provided as an embodiment of this application.

[0078] Figure 25 This is a schematic diagram of the structure after forming the intrinsic semiconductor layer and the second doped semiconductor layer, provided in an embodiment of this application.

[0079] Figure 26 This is another structural schematic diagram of the formation of the first conductive layer and the second conductive layer provided in an embodiment of this application.

[0080] Figure 27 This is a schematic flowchart illustrating the fabrication method of the stacked battery provided in the embodiments of this application.

[0081] Explanation of reference numerals in the attached figures:

[0082] 10. Stacked battery; 11. First battery structure; 12. Second battery structure; 110. First doped semiconductor layer; 110e. First doped semiconductor material layer; 120. Second doped semiconductor layer; 130. Third doped semiconductor layer; 140. Semiconductor substrate; 140a. Overlapping region; 140a1. First sub-overlapping region; 140a2. Second sub-overlapping region; 141. First surface; 142. Second surface; 143. First side surface; 1431. First sub-side surface; 1432. Second sub-side surface; 150. Tunneling layer; 150e. Tunneling material layer; 160. Intrinsic semiconductor layer; 162. Second side surface; 171. First conductive layer; 1711. First sub-layer; 1712. Second sub-layer; 172. Second conductive layer; 181. First electrode; 182. Second electrode; 191. Insulating layer; 191e. Insulating material layer. Detailed Implementation

[0083] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0084] In the description of this application, it should be understood that if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0085] Furthermore, where the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0086] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0087] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0088] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.

[0089] In related technologies, a solar cell includes a semiconductor substrate having a first surface and a second surface opposite to each other, and a side surface connecting the first surface and the second surface. A first passivation layer and a first doped semiconductor layer are sequentially disposed on the first surface, and a second passivation layer and a second doped semiconductor layer are sequentially disposed on the second surface.

[0090] However, since the sides of the semiconductor substrate are exposed outside the first and second passivation layers and are not passivated, edge defects in the semiconductor substrate exacerbate carrier recombination, thereby adversely affecting the conversion efficiency of the solar cell. Therefore, the passivation effect of the solar cell needs to be improved.

[0091] To address the aforementioned issues, this application provides a tandem solar cell, its fabrication method, and a photovoltaic module, which can improve the passivation effect of the tandem solar cell.

[0092] The following will combine Figures 1-27 The tandem solar cells, their preparation methods, and photovoltaic modules provided in the embodiments of this application are described.

[0093] See Figure 1 This application provides a stacked battery 10, which includes a first battery structure 11 and a second battery structure 12 stacked together. The stacked battery 10 utilizes semiconductor materials with different bandgap widths in the first battery structure 11 and the second battery structure 12 respectively to absorb light of different wavelengths in the solar spectrum, thereby improving the efficiency of the stacked battery 10.

[0094] For example, the tandem cell 10 can be any one of perovskite / crystalline silicon tandem cells, III-V compound / crystalline silicon tandem cells, perovskite / perovskite tandem cells, crystalline silicon / crystalline silicon tandem cells, perovskite / copper indium gallium selenide tandem cells, etc. This application uses a perovskite / crystalline silicon tandem cell as an example for illustration.

[0095] For example, one of the first battery structure 11 and the second battery structure 12 is a perovskite battery, and the other is a crystalline silicon battery. This embodiment of the application uses a perovskite battery as the second battery structure 12 and a crystalline silicon battery as the first battery structure 11 as an example. One of the first battery structure 11 and the second battery structure 12 can be a top battery, and the other can be a bottom battery. This embodiment of the application uses a top battery structure 12 and a bottom battery structure 11 as an example for illustration. For example, the top battery can be the layer of the stacked battery 10 that directly faces the incident sunlight.

[0096] See Figure 1 The first battery structure 11 includes a semiconductor substrate 140, which can provide support for subsequently formed film layers. The semiconductor substrate 140 can be used to receive incident light and generate photogenerated carriers. The semiconductor substrate 140 may have a first surface 141 and a second surface 142 disposed opposite to each other along the thickness direction (direction Z) of the semiconductor substrate 140, and a first side surface 143 connected to the first surface 141 and the second surface 142.

[0097] See Figure 1 The first battery structure 11 includes a tunneling layer 150 disposed on the first surface 141 and the first side surface 143. Majority carriers (e.g., electrons) can pass through the tunneling layer 150 through the tunneling effect, while the tunneling layer 150 can block minority carriers (e.g., holes), thereby achieving selective collection of carriers, preventing electron-hole recombination, reducing the surface recombination rate, and increasing the open-circuit voltage. The first battery structure 11 also includes a first doped semiconductor layer 110 disposed on the first surface 141 and the first side surface 143, and the first doped semiconductor layer 110 is located on the side of the tunneling layer 150 facing away from the semiconductor substrate 140. The first doped semiconductor layer 110 has low resistance, effectively reducing current loss and increasing conductivity.

[0098] For example, the material of the tunneling layer 150 may include a tunneling oxide. For instance, the material of the tunneling layer 150 may include at least one of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0099] For example, the material of the first doped semiconductor layer 110 may include doped polycrystalline silicon, doped amorphous silicon, or doped microcrystalline silicon. This application embodiment uses doped polycrystalline silicon as an example to illustrate the material of the first doped semiconductor layer 110.

[0100] See Figure 1The first battery structure 11 includes an intrinsic semiconductor layer 160, which is disposed on the second surface 142 and the first side surface 143. The intrinsic semiconductor layer 160 achieves efficient and stable passivation of the surface of the semiconductor substrate 140 through its unique material properties, thereby reducing carrier recombination losses and improving the photoelectric conversion efficiency of the battery.

[0101] For example, the material of the intrinsic semiconductor layer 160 may include intrinsic amorphous silicon or intrinsic microcrystalline silicon.

[0102] See Figure 1 The first battery structure 11 includes a second doped semiconductor layer 120, which is disposed on a second surface 142 and a first side surface 143, and is also disposed on the side of the intrinsic semiconductor layer 160 facing away from the semiconductor substrate 140. The second doped semiconductor layer 120 has a low resistance, which can effectively reduce current loss and increase conductivity.

[0103] For example, the material of the second doped semiconductor layer 120 may include doped microcrystalline silicon or doped amorphous silicon.

[0104] See Figure 1 The surface of the semiconductor substrate 140 has an overlapping region 140a, which is located at least on the first side surface 143. A portion of the tunneling layer 150, a portion of the first doped semiconductor layer 110, a portion of the intrinsic semiconductor layer 160, and a portion of the second doped semiconductor layer 120 are stacked in the overlapping region 140a in a direction away from the semiconductor substrate 140. In this way, the tunneling layer 150 and the intrinsic semiconductor layer 160 overlap each other in the overlapping region 140a, so that the tunneling layer 150 and the intrinsic semiconductor layer 160 can jointly and completely cover all surfaces of the semiconductor substrate 140, thereby achieving full surface passivation of the semiconductor substrate 140, which is beneficial to improving the conversion efficiency of the first battery structure 11. In addition, the overlap of the first doped semiconductor layer 110 and the second doped semiconductor layer 120 on the first side surface 143 is beneficial to providing better protection for the tunneling layer 150 and the intrinsic semiconductor layer 160.

[0105] It should be noted that in the embodiment where the first doped semiconductor layer 110 is doped polysilicon, the tunneling layer 150 and / or the first doped semiconductor layer 110 are prepared by a high-temperature process, which is higher than the preparation temperature of the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120. In the overlapping region 140a, the tunneling layer 150 and the first doped semiconductor layer 110 are located closer to the semiconductor substrate 140, i.e., on the inner side, while the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 are located further away from the semiconductor substrate 140, i.e., on the outer side. Therefore, it is beneficial to prepare the tunneling layer 150 and the first doped semiconductor layer 110 first, and then prepare the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120, in order to prevent the adverse effects of the high-temperature preparation process of the tunneling layer 150 and the first doped semiconductor layer 110 on the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120.

[0106] See Figure 1 In some embodiments, the first side surface 143 includes a first sub-side surface 1431 and a second sub-side surface 1432 connected together. The first sub-side surface 1431 is connected to the first surface 141, and the second sub-side surface 1432 is connected to the second surface 142. The orthographic projections of the tunneling layer 150 and the first doped semiconductor layer 110 on the plane of the first side surface 143 both overlap with the first sub-side surface 1431, and the orthographic projections of the tunneling layer 150 and the first doped semiconductor layer 110 on the plane of the first side surface 143 do not overlap with the second sub-side surface 1432. That is, the tunneling layer 150 and the first doped semiconductor layer 110 are both located on the first sub-side surface 1431 and neither extends to the second sub-side surface 1432. At least a partial overlapping region 140a may be located on the first sub-side surface 1431. Thus, by placing both the tunneling layer 150 and the first doped semiconductor layer 110 on the first sub-side surface 1431, at least a portion of the overlapping area 140a can be located on the first sub-side surface 1431. This prevents the area of ​​the dead zone on one side of the first surface 141 from being too large if all the overlapping areas 140a are placed on the first surface 141. This ensures a large overlapping area 140a while improving the effective light-receiving area of ​​the first battery structure 11.

[0107] For example, the area of ​​the first doped semiconductor layer 110 covered by the second doped semiconductor layer 120 and the intrinsic semiconductor layer 160 is smaller than the area of ​​the first doped semiconductor layer 110 not covered by the second doped semiconductor layer 120 and the intrinsic semiconductor layer 160. That is, the second doped semiconductor layer 120 and the intrinsic semiconductor layer 160 cover a small portion of the first doped semiconductor layer 110.

[0108] See Figure 1In some embodiments, the dimension of the first sub-side surface 1431 along the thickness direction of the semiconductor substrate 140 is larger than the dimension of the second sub-side surface 1432 along the thickness direction of the semiconductor substrate 140. This makes the area of ​​the first side surface 143 covered by the tunneling layer 150 and the first doped semiconductor layer 110 larger than the area of ​​the first side surface 143 not covered by the tunneling layer 150 and the first doped semiconductor layer 110. The tunneling layer 150 and the first doped semiconductor layer 110 are prepared before the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120. Their earlier preparation can better reduce passivation damage to the first side surface 143 of the semiconductor substrate 140 during the process. In addition, for example, the thickness of the first doped semiconductor layer 110 can be greater than the thickness of the second doped semiconductor layer 120. By placing the thicker first doped semiconductor layer 110 on the inside and covering a larger area of ​​the first side surface 143, the passivation damage to the first side surface 143 of the semiconductor substrate 140 during the process can be further reduced. In other embodiments, the first side 143 may be completely covered by the tunneling layer 150 and the first doped semiconductor layer 110.

[0109] In at least some embodiments, the passivation effect of the intrinsic semiconductor layer 160 is higher than that of the tunneling layer 150. The intrinsic semiconductor layer 160 contacts the second sub-side surface 1432 and extends from the second surface 142 to the second sub-side surface 1432 through the intrinsic semiconductor layer 160. Compared with only the intrinsic semiconductor layer 160 being disposed on the second surface 142, the area covered by the intrinsic semiconductor layer 160 is larger, which can improve the passivation effect on the surface of the semiconductor substrate 140.

[0110] See Figure 2 In some embodiments, the overlapping region 140a is located only on the first side surface 143 and does not extend to the first surface 141. The overlapping region 140a may only include the first sub-overlapping region 140a1. This prevents dead zones caused by the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 being deposited around the edge of the first surface 141, thereby increasing the effective light-receiving area of ​​the first battery structure 11 and improving its conversion efficiency. For example, the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 not being deposited around the first surface 141 can be achieved by using an optimized PECVD substrate design, or by using a low-winding deposition method such as hot-wire CVD, or by using a single-sided wet etching process after deposition.

[0111] See Figure 1In other embodiments, the overlapping region 140a includes a first sub-overlapping region 140a1 and a second sub-overlapping region 140a2. The first sub-overlapping region 140a1 is located on the first side surface 143, and the second sub-overlapping region 140a2 is located at the edge of the first surface 141. A portion of the intrinsic semiconductor layer 160 and a portion of the second doped semiconductor layer 120 are both located in the second sub-overlapping region 140a2. Thus, by extending the overlapping region 140a from the first side 143 to the first surface 141, the area of ​​the overlapping region 140a is made larger, which is beneficial to better ensure the full-area passivation of the surface of the semiconductor substrate 140 by the tunneling layer 150 and the intrinsic semiconductor layer 160. In addition, when forming the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120, a process with a winding can be used so that the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 are wrapped around the edge of the first surface 141 from the second surface 142 of the semiconductor substrate 140. By retaining the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 located at the edge of the first surface 141, it is not necessary to remove the wrapped intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 formed in this process, thus avoiding damage to the tunneling layer 150 and the first doped semiconductor layer 110 during the removal process.

[0112] In some embodiments, the dimension of the second sub-overlapping region 140a2 along the direction from the center to the edge of the first surface 141 is less than or equal to 300 μm. This smaller dimension helps to reduce the dead zone area caused by at least one of the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 deposited around the first surface 141, thereby increasing the effective light-receiving area of ​​the first battery structure 11 and improving its conversion efficiency. Exemplarily, this dimension can be any value of 100 μm, 200 μm, 300 μm, or less than 300 μm.

[0113] It should be noted that the region where the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 are located on the first surface 141 becomes a "dead zone". The intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 are plated around the edge, which destroys the selective collection function of the carriers at the edge of the first surface 141, so that the photogenerated carriers cannot be effectively collected and are recombinated, and the region cannot output effective current normally.

[0114] For example, the doping type of the first doped semiconductor layer 110 is the same as or opposite to the doping type of the semiconductor substrate 140. The doping type of the second doped semiconductor layer 120 is opposite to the doping type of the first doped semiconductor layer 110. One of the first doped semiconductor layer 110 and the second doped semiconductor layer 120 can be N-type doped, and the other can be P-type doped.

[0115] See Figure 2 and Figure 4In some embodiments, the intrinsic semiconductor layer 160 includes a third surface facing the semiconductor substrate 140 and a fourth surface away from the semiconductor substrate 140, as well as a second side surface 162 connecting the third and fourth surfaces. See also Figure 2 In some examples, the second doped semiconductor layer 120 is flush with the second side surface 162. This helps prevent lateral leakage caused by the second doped semiconductor layer 120 bypassing the second side surface 162 and contacting the first doped semiconductor layer 110. See also Figure 4 In other examples, the second doped semiconductor layer 120 covers the second side surface 162. This allows for more complete coverage of the intrinsic semiconductor layer 160, improving protection of the intrinsic semiconductor layer 160 and ensuring passivation. In this case, the second doped semiconductor layer 120 may come into contact with the first doped semiconductor layer 110, leading to lateral leakage. The thinner thickness of the second doped semiconductor layer 120 covering the second side surface 162 results in a smaller contact area between the second doped semiconductor layer 120 and the first doped semiconductor layer 110, thus reducing leakage. Furthermore, the leakage is lateral and has a minimal impact on the battery.

[0116] The semiconductor substrate 140 provided in the embodiments of this application will be described below.

[0117] In some embodiments, the semiconductor substrate 140 may be a silicon substrate, and the material of the silicon substrate may include at least one of monocrystalline silicon and polycrystalline silicon. This application uses monocrystalline silicon as an example for illustration.

[0118] For example, the semiconductor substrate 140 can be doped with N-type ions, which can be at least one of phosphorus, arsenic, and antimony. Alternatively, the semiconductor substrate 140 can be doped with P-type ions, which can be at least one of aluminum and boron. This application embodiment uses N-type doping of the semiconductor substrate 140 as an example for illustration.

[0119] In some embodiments, at least a portion of at least one of the first surface 141 and the second surface 142 may have a textured surface. The textured surface may be a pyramidal textured surface, a pitted textured surface, etc. The textured surface has a low reflectivity to incident light, thus resulting in a high absorption and utilization rate of incident light, leading to a high photoelectric conversion efficiency of the first battery structure 11. In other embodiments, at least a portion of at least one of the first surface 141 and the second surface 142 may not have a textured surface.

[0120] The first conductive layer 171 and the second conductive layer 172 provided in the embodiments of this application will be described below.

[0121] See Figure 1 In some embodiments, the first battery structure 11 includes a first conductive layer 171 and a second conductive layer 172 spaced apart. The first conductive layer 171 and the second conductive layer 172 have high conductivity, enabling timely removal of collected charge carriers and reducing carrier recombination losses. Additionally, the first conductive layer 171 and the second conductive layer 172 can serve as an anti-reflection film to improve the light absorption rate of the first battery structure 11. The first conductive layer 171 is disposed on the first surface 141 and on the side of the first doped semiconductor layer 110 facing away from the semiconductor substrate 140. The second conductive layer 172 is disposed on the second surface 142 and on the side of the second doped semiconductor layer 120 facing away from the semiconductor substrate 140.

[0122] See Figure 1 and Figure 5 In some embodiments, one of the first conductive layer 171 and the second conductive layer 172 is located between the second battery structure 12 and the semiconductor substrate 140, and the conductive layer located between the second battery structure 12 and the semiconductor substrate 140 is disposed on the side of the second doped semiconductor layer 120 located in the overlapping region 140a away from the semiconductor substrate 140. In this way, by disposing the conductive layer located between the second battery structure 12 and the semiconductor substrate 140 in the overlapping region 140a, the films in the overlapping region 140a are protected, which helps to prevent damage to the films in the overlapping region 140a by subsequent fabrication processes and helps to ensure the passivation effect.

[0123] See Figure 1 and Figure 2 In some embodiments, the second battery structure 12 is disposed on the side of the first surface 141 facing away from the second surface 142, and the first conductive layer 171 is located between the second battery structure 12 and the semiconductor substrate 140, and the first conductive layer 171 is located on the first side surface 143. Thus, by extending the first conductive layer 171 from the first surface 141 to the first side surface 143, the first conductive layer 171 can protect each film layer located inside it and on the first side surface 143, which is beneficial to reducing the impact of the second battery structure 12 on the passivation of the first side surface 143 during the fabrication process, and is beneficial to ensuring the passivation effect of the first side surface 143. In addition, compared with extending the second conductive layer 172 to the first side surface 143, by extending the first conductive layer 171 to the first side surface 143, the first conductive layer 171 can form a continuous isolation effect between the second battery structure 12 located on the first surface 141 and the second battery structure 12 located on the first side surface 143, so as to better prevent the adverse effects of the second battery structure 12 on the first battery structure 11 from different sides.

[0124] See Figure 1In the embodiment where the second battery structure 12 is disposed on the side of the first surface 141 away from the second surface 142, the first surface 141 is the light-facing surface and the second surface 142 is the backlight surface. When the first doped semiconductor layer 110 is doped polysilicon, the conductivity of the doped polysilicon is better, which is beneficial to the current transmission between the first battery structure 11 and the second battery structure 12. In addition, the first doped semiconductor layer 110 doped with polysilicon can be made relatively thick. For example, the thickness of the first doped semiconductor layer 110 can be greater than the thickness of the second doped semiconductor layer 120, so as to improve the process window for subsequent fabrication of the second battery structure 12 and reduce the degree of damage to the second doped semiconductor layer 120 caused by the high-temperature process.

[0125] See Figure 1 In the embodiment where the second battery structure 12 is disposed on the side of the first surface 141 opposite to the second surface 142, the second doped semiconductor layer 120 located in the overlap region 140a is spaced apart from the second conductive layer 172. This results in a greater distance between the second conductive layer 172 and the first conductive layer 171 located in the overlap region, which helps to prevent the second conductive layer 172 and the first conductive layer 171 from easily contacting each other and short-circuiting when both are located in the overlap region 140a.

[0126] See Figure 1 In the embodiment where the second battery structure 12 is disposed on the side of the first surface 141 opposite to the second surface 142, the outer contour of the second conductive layer 172 projected onto the plane of the second surface 142 is spaced within the outer contour of the second surface 142. Thus, by not disposing of the second conductive layer 172 at the edge of the second surface 142, it is beneficial to further increase the distance between the second conductive layer 172 and the first conductive layer 171, which helps to prevent short circuits. In addition, compared to the second conductive layer 172 being flush with the first side surface 143 and just completely covering the second surface 142, it is easier to achieve the goal of not disposing of the second conductive layer 172 at the edge of the second surface 142.

[0127] In another embodiment, the second conductive layer 172 may extend to a portion of the second sub-side surface 1432. In other embodiments, the second conductive layer 172 is flush with the first side surface 143 and just completely covers the second surface 142.

[0128] See Figure 1 In some embodiments, the intrinsic semiconductor layer 160 located on the second side 142 and the intrinsic semiconductor layer 160 located on the second sub-side 1432 are both in contact with the semiconductor substrate 140, and the portion of the intrinsic semiconductor layer 160 in contact with the semiconductor substrate 140 is configured as a first portion, and the second conductive layer 172 covers the portion of the first portion of the intrinsic semiconductor layer 160.

[0129] See Figure 5 and Figure 7In another embodiment, the second battery structure 12 is disposed on the side of the second surface 142 facing away from the first surface 141, and the second conductive layer 172 is located between the second battery structure 12 and the semiconductor substrate 140, and the second conductive layer 172 is located on the first side surface 143. Thus, by extending the second conductive layer 172 from the second surface 142 to the first side surface 143, the second conductive layer 172 can protect the films located inside it and on the first side surface 143, which helps to reduce the impact of the second battery structure 12 fabrication process on the passivation of the first side surface 143, and helps to ensure the passivation effect of the first side surface 143. Furthermore, compared to extending the first conductive layer 171 to the first side surface 143, by extending the second conductive layer 172 to the first side surface 143, the second conductive layer 172 can form a continuous isolation effect between the second battery structure 12 located on the second surface 142 and the second battery structure 12 located on the first side surface 143, so as to better prevent the adverse effects of the second battery structures 12 on the first battery structure 11 from different sides.

[0130] It should be noted that in the embodiment where the first doped semiconductor layer 110 is doped polycrystalline silicon and the second doped semiconductor layer 120 is amorphous silicon or microcrystalline silicon, the parasitic absorption of light by polycrystalline silicon is greater than that by amorphous silicon and microcrystalline silicon, that is, the parasitic absorption of the first doped semiconductor layer 110 is greater than that of the second doped semiconductor layer 120.

[0131] In the embodiment where the second battery structure 12 is disposed on the side of the second surface 142 away from the first surface 141, the second surface 142 is used as the light-facing surface and the first surface 141 is used as the back-light surface. The first doped semiconductor layer 110 of polycrystalline silicon is disposed on the back-light surface, which helps to alleviate the problem of reduced conversion efficiency caused by the large parasitic absorption of light by the first doped semiconductor layer 110 of polycrystalline silicon.

[0132] See Figure 5 In an embodiment where the second battery structure 12 is disposed on the side of the second surface 142 opposite to the first surface 141, the overlapping region 140a includes a second sub-overlapping region 140a2 located at the edge of the first surface 141, and the second conductive layer 172 is disposed in the second sub-overlapping region 140a2. Thus, the second conductive layer 172 extends from the second surface 142 to the edge of the first surface 141 and overlaps with the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 located at the edge of the first surface 141, making the coverage of the second conductive layer 172 wider. This is beneficial to improving the protection effect of the second conductive layer 172 on the inner film layers, ensuring the passivation effect, and also helps to ensure that the second battery structure 12 is isolated outside the second conductive layer 172.

[0133] See Figure 5In an embodiment where the second battery structure 12 is disposed on the side of the second surface 142 away from the first surface 141, the first doped semiconductor layer 110 located in the overlapping region 140a is spaced apart from the first conductive layer 171. This spaced arrangement between the second conductive layer 172 and the first conductive layer 171 in the overlapping region helps to prevent the second conductive layer 172 and the first conductive layer 171 from being easily short-circuited due to both being located in the overlapping region 140a.

[0134] See Figure 5 In the embodiment where the second battery structure 12 is disposed on the side of the second surface 142 opposite to the first surface 141, the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 are both disposed at a distance from the first conductive layer 171. In this way, the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 do not contact or overlap with the first conductive layer 171, which can prevent the second doped semiconductor layer 120 from contacting the first conductive layer 171.

[0135] See Figure 5 In the embodiment where the second battery structure 12 is disposed on the side of the second surface 142 opposite to the first surface 141, the outer contour of the first conductive layer 171 projected onto the plane of the first surface 141 is spaced within the outer contour of the first surface 141. Thus, the absence of the first conductive layer 171 at the edge of the first surface 141 helps to prevent the first conductive layer 171 and the second conductive layer 172 from coming into contact and short-circuiting. In addition, compared to the first conductive layer 171 being flush with the first side surface 143 and just completely covering the first surface 141, it is easier to achieve the goal of not disposing of the first conductive layer 171 at the edge of the first surface 141.

[0136] In other embodiments, the first conductive layer 171 is flush with the first side surface 143 and just completely covers the first side surface 141.

[0137] See Figure 6 In an embodiment where the second battery structure 12 is disposed on the side of the second surface 142 opposite to the first surface 141, the first conductive layer 171 includes a first sub-layer 1711 and a second sub-layer 1712 stacked along a direction away from the semiconductor substrate 140. The outer contour of the orthographic projection of the second sub-layer 1712 on the first surface 141 is spaced within the outer contour of the orthographic projection of the first sub-layer 1711 on the first surface 141. This results in a smaller area for the second sub-layer 1712, which helps to increase the distance between the second sub-layer 1712 and the second conductive layer 172 and / or the second doped semiconductor layer 120 located on the first surface 141, preventing the second sub-layer 1712 from contacting the second conductive layer 172 and / or the second doped semiconductor layer 120 located on the first surface 141. In addition, the larger area for the first sub-layer 1711 helps to increase the coverage area of ​​the first conductive layer 171 and improve the collection and transport capability of the first conductive layer 171 for charge carriers.

[0138] For example, the first conductive layer 171 is an integral structure, so the first sublayer 1711 and the second sublayer 1712 can be prepared simultaneously, which can simplify the preparation process of the first sublayer 1711 and the second sublayer 1712.

[0139] See Figure 6 For example, the intrinsic semiconductor layer 160 located in the second sub-overlapping region 140a2 has a fifth surface on the side facing away from the first surface 141. The distance between the fifth surface and the first doped semiconductor layer 110 along the thickness direction of the semiconductor substrate 140 is greater than or equal to the thickness of the first sub-layer 1711. This makes the thickness of the first sub-layer 1711 smaller. It is horizontally offset from the second doped semiconductor layer 120 and / or the second conductive layer 172 located on the first surface 141. This can reduce the risk of the first sub-layer 1711 contacting the second doped semiconductor layer 120 and / or the second conductive layer 172 while setting the area of ​​the first sub-layer 1711 to be larger.

[0140] For example, the material of at least one of the first conductive layer 171 and the second conductive layer 172 may include a transparent conductive oxide, such as one or more of zinc oxide, indium oxide, and tin oxide. The doping elements in the conductive layers include one or more of gallium (Ga), tin (Sn), titanium (Ti), zirconium (Zr), molybdenum (Mo), cerium (Ce), fluorine (F), tungsten (W), and aluminum (Al).

[0141] It should be noted that the photogenerated holes generated by the top cell and the photogenerated electrons generated by the bottom cell meet and recombine at the recombination junction between the top and bottom cells. Simultaneously, the photogenerated electrons from the top cell continuously move towards the top electrode, and the photogenerated holes from the bottom cell continuously move towards the bottom electrode. This process is equivalent to current flowing from the top cell to the bottom cell through the recombination junction, achieving current continuity in the series-connected structure of the top and bottom cells. Therefore, the recombination junction facilitates charge transfer and reduces recombination resistance, significantly impacting current transmission efficiency.

[0142] See Figure 6In one embodiment where the second battery structure 12 is disposed on the side of the second surface 142 opposite to the first surface 141, the first battery structure 11 includes a third doped semiconductor layer 130. The third doped semiconductor layer 130 is located at least on the second surface 142 and is situated on the side of the second doped semiconductor layer 120 opposite to the semiconductor substrate 140. The doping type of the third doped semiconductor layer 130 is opposite to that of the second doped semiconductor layer 120, and the third doped semiconductor layer 130 and the second doped semiconductor layer 120 are in contact with each other. Thus, a homogeneous composite junction can be formed between the third doped semiconductor layer 130 and the second doped semiconductor layer 120. Compared to forming a heterogeneous composite junction between the top and bottom batteries, the homogeneous composite junction can better promote charge transfer, thereby improving the current transport efficiency of the top and bottom batteries.

[0143] See Figure 5 In another embodiment where the second battery structure 12 is disposed on the side of the second surface 142 opposite to the first surface 141, a second doped semiconductor layer 120 may be disposed without a third doped semiconductor layer 130. In this case, a composite junction of heterogeneous materials is formed between the second conductive layer 172 and the second doped semiconductor layer 120.

[0144] For example, the material of the third doped semiconductor layer 130 includes doped microcrystalline silicon or doped amorphous silicon.

[0145] See Figure 1 and Figure 5 In some embodiments, a portion of the second battery structure 12 is disposed on the first side 143, and this portion of the second battery structure 12 is located outside the first battery structure 11. In this way, the portion of the second battery structure 12 can protect the film layer on the first side 143 of the first battery structure 11. In addition, it is beneficial to increase the contact area between the first battery structure 11 and the second battery structure 12, thereby improving the connection stability. Secondly, during the formation of the second battery structure 12, a portion of the film layer of the second battery structure 12 is formed on the first side 143 due to process reasons. Retaining this portion of the film layer formed on the first side 143 without removing it simplifies the manufacturing process and avoids damage to the first battery structure 11 that may be caused by removing this portion of the film layer.

[0146] See Figure 3 In some embodiments, the first battery structure 11 includes an insulating layer 191 disposed between the first doped semiconductor layer 110 and the intrinsic semiconductor layer 160 located in the overlap region 140a. Thus, by providing the insulating layer 191 in the overlap region 140a, the insulation effect between the first doped semiconductor layer 110 and the second doped semiconductor layer 120 can be improved, which is beneficial to prevent leakage.

[0147] In embodiments where the material of the first doped semiconductor layer 110 includes polycrystalline silicon, the material of the insulating layer 191 includes doped silicon glass, such as borosilicate glass or phosphosilicate glass. The insulating layer 191 and the first doped semiconductor layer 110 can be formed in the same process. During the formation of the first doped semiconductor layer 110 of polycrystalline silicon, a portion of the silicon near the surface can be oxidized to form the insulating layer 191, thereby simplifying the fabrication process of the first doped semiconductor layer 110 and the insulating layer 191.

[0148] The first electrode 181 and the second electrode 182 provided in the embodiments of this application will be described below.

[0149] See Figure 1 In an embodiment where the second battery structure 12 is located on the side of the first surface 141 facing away from the second surface 142, the stacked battery 10 includes a first electrode 181 and a second electrode 182. The first electrode 181 is located on the side of the second battery structure 12 facing away from the first surface 141, and the second electrode 182 is located on the side of the second conductive layer 172 facing away from the first surface 141. The first electrode 181 and the second electrode 182 can collect and transport charge carriers.

[0150] See Figure 5 In an embodiment where the second battery structure 12 is located on the side of the second surface 142 away from the first surface 141, the stacked battery 10 includes a first electrode 181 and a second electrode 182. The first electrode 181 is located on the side of the first conductive layer 171 away from the first surface 141, and the second electrode 182 is located on the side of the second battery structure 12 away from the second surface 142.

[0151] For example, at least one of the first electrode 181 and the second electrode 182 may be made of conductive metals such as silver, copper, and tin.

[0152] For example, the first electrode 181 and the second electrode 182 can be prepared using a low-temperature process to reduce the impact on the tandem battery 10.

[0153] The following describes the preparation method of the stacked battery 10 provided in the embodiments of this application.

[0154] This application provides a method for fabricating a stacked battery 10. This method is used to fabricate the stacked battery 10 described in the above embodiments. The fabrication method includes forming a first battery structure 11 and a second battery structure 12 stacked together. See also... Figure 27 The formation of the first battery structure 11 may include:

[0155] Step S100: Provide a semiconductor substrate; the semiconductor substrate has a first surface and a second surface disposed opposite to each other, and a first side surface connected to the first surface and the second surface.

[0156] See Figure 8 First, a semiconductor substrate 140 is provided. The semiconductor substrate 140 may have a first surface 141 and a second surface 142 disposed opposite to each other along the thickness direction of the semiconductor substrate 140, and a first side surface 143 connected to the first surface 141 and the second surface 142. The semiconductor substrate 140 can provide support for the film layer subsequently formed.

[0157] Step S200: A tunneling layer and a first doped semiconductor layer are formed on both the first surface and the first side surface; the first doped semiconductor layer is disposed on the side of the tunneling layer away from the semiconductor substrate.

[0158] See Figure 13 and Figure 24 After providing the semiconductor substrate 140, a tunneling layer 150 and a first doped semiconductor layer 110 may be formed on a first surface 141 and a first side surface 143, wherein the first doped semiconductor layer 110 is disposed on the side of the tunneling layer 150 opposite to the semiconductor substrate 140.

[0159] For example, a deposition process can be used to form the first doped semiconductor layer 110.

[0160] For example, the deposition process may include atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or reactive plasma deposition (RPD), etc. Other structural layers in the embodiments of this disclosure may also be formed by deposition, which will not be described in detail here.

[0161] Step S300: An intrinsic semiconductor layer and a second doped semiconductor layer are formed on both the second side and the first side. The second doped semiconductor layer is disposed on the side of the intrinsic semiconductor layer away from the semiconductor substrate. The surface of the semiconductor substrate has an overlapping region, which is located at least on the first side. A portion of the tunneling layer, a portion of the first doped semiconductor layer, a portion of the intrinsic semiconductor layer, and a portion of the second doped semiconductor layer are stacked in the overlapping region along a direction away from the semiconductor substrate.

[0162] See Figure 14 , Figure 16 and Figure 25After forming a tunneling layer 150 and a first doped semiconductor layer 110 on both the first surface 141 and the first side surface 143, the system may include forming an intrinsic semiconductor layer 160 and a second doped semiconductor layer 120 on both the second surface 142 and the first side surface 143. The second doped semiconductor layer 120 is disposed on the side of the intrinsic semiconductor layer 160 away from the semiconductor substrate 140. The surface of the semiconductor substrate 140 has an overlapping region 140a, which is located at least on the first side surface 143. A portion of the tunneling layer 150, a portion of the first doped semiconductor layer 110, a portion of the intrinsic semiconductor layer 160, and a portion of the second doped semiconductor layer 120 are stacked in the overlapping region 140a in a direction away from the semiconductor substrate 140. In this way, the tunneling layer 150 and the intrinsic semiconductor layer 160 overlap in the overlapping region 140a, allowing the tunneling layer 150 and the intrinsic semiconductor layer 160 to jointly and completely cover all surfaces of the semiconductor substrate 140. This achieves full-surface passivation of the semiconductor substrate 140, which is beneficial to improving the conversion efficiency of the first battery structure 11. In addition, covering the first doped semiconductor layer 110 and the second doped semiconductor layer 120 on the first side 143 provides better protection for the tunneling layer 150 and the intrinsic semiconductor layer 160, preventing damage to the passivation layers such as the tunneling layer 150 and the intrinsic semiconductor layer 160, and ensuring that the tunneling layer 150 and the intrinsic semiconductor layer 160 jointly passivate the entire surface of the semiconductor substrate 140.

[0163] In some embodiments, the formation of a tunneling layer 150 and a first doped semiconductor layer 110 on both the first side surface 141 and the first side surface 143 may include, see, Figure 9 A tunneling material layer 150e is formed on the first surface 141, the second surface 142, and the first side surface 143; then, see... Figure 10 A first doped semiconductor material layer 110e and an insulating material layer 191e are formed on the side of the tunneling material layer 150e facing away from the semiconductor substrate 140; the first doped semiconductor material layer 110e and the insulating material layer 191e are both located on the first surface 141, the second surface 142, and the first side surface 143; then, see... Figure 11 and Figure 22 At least the insulating material layer 191e located on the second surface 142 is removed; the insulating material layer 191e located on the first surface 141 and at least part of the first side surface 143 is retained; then, see Figure 12 and Figure 23Using the retained insulating material layer 191e as a mask, the first doped semiconductor material layer 110e and tunneling material layer 150e exposed outside the mask are removed. The retained first doped semiconductor material layer 110e and tunneling material layer 150e are then used to form the first doped semiconductor layer 110 and tunneling layer 150, respectively. Thus, the first doped semiconductor material layer 110e and insulating material layer 191e can be formed in the same process, eliminating the need for separate steps to form them, which simplifies the fabrication process. Furthermore, by using the insulating material layer 191e as a mask, during the removal of the first doped semiconductor material layer 110e and tunneling material layer 150e exposed outside the mask, it is not necessary to additionally prepare a mask to protect the retained first doped semiconductor material layer 110e and tunneling material layer 150e.

[0164] In some embodiments, see Figure 13 and Figure 24 Before the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 are formed on both the second side 142 and the first side 143, the process includes: removing all insulating material layers 191e to expose the first doped semiconductor layer 110 so that the first doped semiconductor layer 110 can contact the subsequently formed first conductive layer 171.

[0165] For example, during the process of removing all insulating material layers 191e, the semiconductor substrate 140 can be cleaned and texturized simultaneously, which helps to simplify the manufacturing process of the display panel.

[0166] In other embodiments, see Figure 12 and Figure 18 During the process of forming the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 on both the second side 142 and the first side 143, the process further includes: forming the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 on at least the side of the insulating material layer 191e located in the overlapping region 140a that faces away from the semiconductor substrate 140; correspondingly, see Figure 19After forming the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 on both the second side 142 and the first side 143, the process includes removing the insulating material layer 191e located outside the overlap region 140a, retaining the insulating material layer 191e located in the overlap region 140a, and forming an insulating layer 191. Thus, before the step of removing the insulating material layer 191e located outside the overlap region 140a, the retained insulating material layer 191e provides good coverage of the film layer on the first side 141 of the first battery structure 11, preventing damage to the first doped semiconductor layer 110 and the tunneling layer 150 caused by impacts during the fabrication of the first battery structure 11. Furthermore, by retaining the insulating layer 191 in the overlap region 140a, the insulation effect between the first doped semiconductor layer 110 and the second doped semiconductor layer 120 can be improved, which is beneficial for preventing leakage.

[0167] For example, see Figure 18 A process with a winding feature can be employed, such that the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 are deposited around the edge of the first surface 141 of the semiconductor substrate 140 from the second surface 142. Then, see... Figure 19 The intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 deposited around the edge of the first surface 141 can be removed, see [link to relevant documentation]. Figure 20 Remove the insulating material layer 191e outside the overlapping area so that the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 are not deposited around the first surface 141.

[0168] See Figure 15 , Figure 17 , Figure 21 and Figure 26 In some embodiments, after the intrinsic semiconductor layer 160 and the second doped semiconductor layer 120 are formed on both the second side 142 and the first side 143, the following may be included: forming a first conductive layer 171 and a second conductive layer 172 spaced apart; the first conductive layer 171 is disposed on the first side 141 and on the side of the first doped semiconductor layer 110 facing away from the semiconductor substrate 140, and the second conductive layer 172 is disposed on the second side 142 and on the side of the second doped semiconductor layer 120 facing away from the semiconductor substrate 140.

[0169] In some embodiments, after forming the spaced-apart first conductive layer 171 and second conductive layer 172, the following may be included: (See below) Figure 1 A second battery structure 12 is formed on the first surface 141, or see [other details]. Figure 5 A second battery structure 12 is formed on the second surface 142.

[0170] In some embodiments, after forming the first conductive layer 171 and the second conductive layer 172 that are spaced apart, the process may further include forming a first electrode 181 and a second electrode 182.

[0171] It should be noted that, Figures 8-21 The first surface 141 is shown facing the second battery structure 12. Figures 22-26 The second surface 142 is shown facing the second battery structure 12.

[0172] The photovoltaic modules provided in the embodiments of this application are described below.

[0173] This application also provides a photovoltaic module, which may include the tandem cell 10 described in the above embodiments. There may be at least one tandem cell 10 in the photovoltaic module. This application describes an example where there are multiple tandem cells 10 in the photovoltaic module, with multiple tandem cells 10 collectively forming a battery string.

[0174] In some embodiments, the photovoltaic module may include a first encapsulation and a second encapsulation located on both sides of the cell string layer, which encapsulate the cell string layer to protect it. The first and second encapsulations may include an encapsulating adhesive layer and a cover plate, with the encapsulating adhesive layer located on the side of the cover plate facing the cell string layer. The cover plate protects the cell string layer, and the encapsulating adhesive layer connects the cover plate and the cell string layer.

[0175] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0176] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A stacked battery, characterized in that, The stacked battery includes a first battery structure and a second battery structure stacked together; the first battery structure includes: A semiconductor substrate has a first surface and a second surface disposed opposite to each other, and a first side surface connected to the first surface and the second surface; A tunneling layer is disposed on the first surface and the first side surface. A first doped semiconductor layer is disposed on the first surface and the first side surface, and is disposed on the side of the tunneling layer opposite to the semiconductor substrate; An intrinsic semiconductor layer is disposed on the second side and the first side; A second doped semiconductor layer is disposed on the second surface and the first side surface, and is disposed on the side of the intrinsic semiconductor layer opposite to the semiconductor substrate; The semiconductor substrate has an overlapping region on its surface, which is located at least on the first side. A portion of the tunneling layer, a portion of the first doped semiconductor layer, a portion of the intrinsic semiconductor layer, and a portion of the second doped semiconductor layer are stacked in the overlapping region in a direction away from the semiconductor substrate.

2. The stacked battery according to claim 1, characterized in that, The first side surface includes a first sub-side surface and a second sub-side surface connected together. The first sub-side surface is connected to the first surface, and the second sub-side surface is connected to the second surface. The orthographic projection of the tunneling layer and the first doped semiconductor layer on the plane where the first side surface is located overlaps with the first sub-side surface but does not overlap with the second sub-side surface. At least a portion of the overlapping area is located on the first sub-side surface.

3. The stacked battery according to claim 2, characterized in that, The dimension of the first sub-side along the thickness direction of the semiconductor substrate is greater than the dimension of the second sub-side along the thickness direction of the semiconductor substrate.

4. The stacked battery according to claim 2, characterized in that, The intrinsic semiconductor layer is in contact with the second sub-side surface.

5. The stacked battery according to any one of claims 1-4, characterized in that, The overlapping area includes a first sub-overlapping area and a second sub-overlapping area, wherein the first sub-overlapping area is located on the first side surface and the second sub-overlapping area is located on the edge of the first side surface; Both a portion of the intrinsic semiconductor layer and a portion of the second doped semiconductor layer are located in the second sub-overlap region.

6. The stacked battery according to claim 5, characterized in that, The second sub-overlapping region has a dimension of less than or equal to 300 μm along the direction from the center to the edge of the first surface.

7. The stacked battery according to any one of claims 1-4, characterized in that, The intrinsic semiconductor layer includes a third surface facing the semiconductor substrate and a fourth surface away from the semiconductor substrate, as well as a second side surface connecting the third surface and the fourth surface; The second doped semiconductor layer is flush with the second side surface; or, The second doped semiconductor layer covers the second side surface.

8. The stacked battery according to any one of claims 1-4, characterized in that, The first battery structure includes a first conductive layer and a second conductive layer disposed at intervals. The first conductive layer is disposed on the first surface and on the side of the first doped semiconductor layer away from the semiconductor substrate. The second conductive layer is disposed on the second surface and on the side of the second doped semiconductor layer away from the semiconductor substrate.

9. The stacked battery according to claim 8, characterized in that, One of the first conductive layer and the second conductive layer is located between the second battery structure and the semiconductor substrate, and is disposed on the side of the second doped semiconductor layer located in the overlapping region away from the semiconductor substrate.

10. The stacked battery according to claim 9, characterized in that, The second battery structure is disposed on the side of the first surface opposite to the second surface, and the first conductive layer is located between the second battery structure and the semiconductor substrate, and is located on the first side surface.

11. The stacked battery according to claim 10, characterized in that, The second doped semiconductor layer located in the overlapping region is disposed at a distance from the second conductive layer.

12. The stacked battery according to claim 10, characterized in that, The outer contour of the second conductive layer as an orthographic projection on the plane containing the second surface is disposed at intervals within the outer contour of the second surface.

13. The stacked battery according to claim 9, characterized in that, The second battery structure is disposed on the side of the second surface opposite to the first surface, and the second conductive layer is located between the second battery structure and the semiconductor substrate, and is located on the first side surface.

14. The stacked battery according to claim 13, characterized in that, The overlapping area includes a second sub-overlapping area located at the edge of the first surface, and the second conductive layer is disposed in the second sub-overlapping area.

15. The stacked battery according to claim 13, characterized in that, The first doped semiconductor layer located in the overlapping region is disposed at a distance from the first conductive layer; and / or, Both the intrinsic semiconductor layer and the second doped semiconductor layer are spaced apart from the first conductive layer.

16. The stacked battery according to claim 13, characterized in that, The outer contour of the first conductive layer as an orthographic projection on the plane containing the first surface is spaced out within the outer contour of the first surface.

17. The stacked battery according to any one of claims 1-4, characterized in that, A portion of the second battery structure is disposed on the first side and located outside the first battery structure.

18. The stacked battery according to any one of claims 1-4, characterized in that, The first battery structure includes an insulating layer disposed between the first doped semiconductor layer and the intrinsic semiconductor layer located in the overlapping region.

19. The stacked battery according to claim 18, characterized in that, The material of the first doped semiconductor layer includes polycrystalline silicon; and / or, The insulating layer is made of borosilicate glass or phosphosilicate glass; and / or, The material of the second doped semiconductor layer includes microcrystalline silicon or amorphous silicon.

20. A method for preparing a tandem battery, characterized in that, The preparation method includes forming a first battery structure and a second battery structure stacked together. The formation of the first battery structure includes: A semiconductor substrate is provided; the semiconductor substrate has a first surface and a second surface disposed opposite to each other, and a first side surface connected to the first surface and the second surface; A tunneling layer and a first doped semiconductor layer are formed on both the first surface and the first side surface; the first doped semiconductor layer is disposed on the side of the tunneling layer opposite to the semiconductor substrate; An intrinsic semiconductor layer and a second doped semiconductor layer are formed on both the second side and the first side; the second doped semiconductor layer is disposed on the side of the intrinsic semiconductor layer opposite to the semiconductor substrate; The semiconductor substrate has an overlapping region on its surface, which is located at least on the first side. A portion of the tunneling layer, a portion of the first doped semiconductor layer, a portion of the intrinsic semiconductor layer, and a portion of the second doped semiconductor layer are stacked in the overlapping region in a direction away from the semiconductor substrate.

21. The method for preparing a stacked battery according to claim 20, characterized in that, The formation of a tunneling layer and a first doped semiconductor layer on both the first surface and the first side surface includes: A tunneling material layer is formed on the first surface, the second surface, and the first side surface; A first doped semiconductor material layer and an insulating material layer are formed on the side of the tunneling material layer facing away from the semiconductor substrate; the first doped semiconductor material layer and the insulating material layer are both located on the first surface, the second surface, and the first side surface; At least the insulating material layer located on the second surface is removed; the insulating material layer located on the first surface and at least a portion of the first side surface is retained; Using the retained insulating material layer as a mask, the first doped semiconductor material layer and the tunneling material layer exposed outside the mask are removed, and the retained first doped semiconductor material layer and the tunneling material layer respectively form the first doped semiconductor layer and the tunneling layer.

22. The method for preparing a stacked battery according to claim 21, characterized in that, Before forming an intrinsic semiconductor layer and a second doped semiconductor layer on both the second side and the first side, the method includes: removing the insulating material layer; Alternatively, the process of forming an intrinsic semiconductor layer and a second doped semiconductor layer on both the second side and the first side further includes: forming the intrinsic semiconductor layer and the second doped semiconductor layer on at least one side of the insulating material layer located in the overlapping region away from the semiconductor substrate; After forming an intrinsic semiconductor layer and a second doped semiconductor layer on both the second side and the first side, the process includes removing the insulating material layer located outside the overlapping region, retaining the insulating material layer located in the overlapping region, and forming an insulating layer.

23. The method for preparing a stacked battery according to claim 20, characterized in that, After forming an intrinsic semiconductor layer and a second doped semiconductor layer on both the second side and the first side, the process includes: A first conductive layer and a second conductive layer are formed at intervals; the first conductive layer is disposed on the first surface and on the side of the first doped semiconductor layer away from the semiconductor substrate, and the second conductive layer is disposed on the second surface and on the side of the second doped semiconductor layer away from the semiconductor substrate.

24. A photovoltaic module, characterized in that, The stacked battery includes the stacked battery prepared by any of the methods described in claims 1-19 or claims 20-23.

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