A low-power fft chip for real-time frequency spectrum analysis of electroencephalogram signals and a method of using the same

Abstract

This invention discloses a low-power FFT chip for real-time spectrum analysis of electroencephalogram (EEG) signals and its usage method. The chip includes an analog front-end module, a digital processing module, an interface and control module, and a low-power management and clock control module. The analog front-end module amplifies, filters, performs power frequency notch filtering, and performs analog-to-digital conversion on the input microvolt-level analog EEG signals. This invention integrates a low-noise analog front-end, a dedicated digital processing module, and a fine-grained power management module into a single chip, constructing a dual anti-interference link that combines analog and digital processing. While ensuring signal purity, the digital processing module accelerates real-time processing speed, and the overall power consumption is controlled through fully custom circuitry and dynamic power management. This solves the three major problems of poor real-time performance, high power consumption, and weak noise immunity in general-purpose processor solutions for EEG spectrum analysis, thus meeting the demanding requirements of wearable devices.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a low-power FFT chip for real-time spectrum analysis of electroencephalogram (EEG) signals and its usage method. Background Technology

[0002] In the field of EEG signal processing, using a general-purpose processor combined with peripheral discrete circuits for EEG spectrum analysis is a common traditional approach. First, in terms of real-time performance, the software-implemented Fast Fourier Transform (FFT) algorithm has a large computational load and high processing latency, making it difficult to meet the real-time feedback requirements of brain-computer interface applications. Second, in terms of power consumption, in order to maintain general computing power, the architecture and working mode of general-purpose processors often result in overall power consumption of up to milliwatts or even higher, which severely limits the device's battery life. Therefore, this solution proposes a low-power FFT chip for real-time spectrum analysis of EEG signals and its usage method to solve the above problems. Summary of the Invention

[0003] The purpose of this invention is to provide a low-power FFT chip for real-time spectrum analysis of electroencephalogram (EEG) signals and its usage method, so as to solve the problems mentioned in the background art.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a low-power FFT chip for real-time spectrum analysis of electroencephalogram (EEG) signals, comprising: The analog front-end module is used to amplify, filter, perform power frequency notch filtering, and convert analog to digital signals at the input microvolt level. A digital processing module, electrically connected to the output of the analog front-end module, is used to perform fast Fourier transform, power spectrum calculation, and feature extraction on the digital signal from the analog front-end module. An interface and control module is electrically connected to the input terminals of the analog front-end module and the digital processing module, and is used to receive external configuration parameters and output the processed spectrum data or characteristic parameters. A low-power management and clock control module is electrically connected to the control terminals of the analog front-end module, digital processing module, and interface and control module. It is used to synchronize the operation of each module of the chip and perform dynamic power consumption management.

[0005] Preferably, the simulated front-end module includes the following executed sequentially: A low-noise amplifier, employing a folded common-source common-gate structure and operating in the subthreshold region, is used for preliminary amplification of input EEG signals; A bandpass filter, electrically connected to the output of a low-noise amplifier, has a fourth-order Chebyshev response and is used to filter out noise outside the frequency band of the EEG signal. An adaptive power frequency notch filter is electrically connected to the output of a bandpass filter to suppress 50Hz power frequency interference. An analog-to-digital converter, electrically connected to the output of an adaptive power frequency notch filter, is used to convert the filtered analog signal into a digital signal.

[0006] Preferably, the digital processing module includes: The Fast Fourier Transform (FFT) computation unit adopts an 8-stage pipeline structure, with each stage containing a parallel butterfly operation unit, used to perform Fast Fourier Transform on digital signals, converting time-domain signals into frequency-domain data; The post-processing unit is electrically connected to the output of the fast Fourier transform calculation unit and is used to perform power spectrum calculation, secondary power frequency suppression, and feature extraction on the fast Fourier transform calculation results.

[0007] Preferably, the fast Fourier transform calculation unit integrates a coordinate rotation digital calculation algorithm unit for real-time calculation of the rotation factor required for butterfly operations.

[0008] Preferably, the Fast Fourier Transform (FFT) calculation unit utilizes the symmetry of the real signal to convert the total number of points N in the sequence into an N / 2-point complex sequence through zero-padding and conjugate symmetry processing, and then performs FFT calculation.

[0009] Preferably, the post-processing unit includes the following executed sequentially: The power spectrum calculation unit is used to calculate the square of the spectrum amplitude. The secondary power frequency suppression unit is used to digitally filter specific narrowband power frequency interference that remains in the power spectrum. The feature extraction unit is used to calculate the power ratio of signals in multiple frequency bands as output features.

[0010] Preferably, the interface and control module includes: The configuration interface is used to receive configuration parameters sent from the outside and to send the configuration parameters to the digital processing module and the analog front-end module. The data output interface is used to output the feature parameters obtained by the feature extraction unit or the spectrum data obtained by the power spectrum calculation unit.

[0011] A method for using a low-power FFT chip for real-time spectrum analysis of electroencephalogram (EEG) signals, comprising the following steps: S1, receive external configuration parameters through the interface and control module to set the chip's operating mode; S2 provides clocks to each functional module through the low-power management and clock control module, and initiates dynamic power management; S3, the EEG analog signal is input into the analog front-end module, and then passes through low-noise amplification, bandpass filtering, power frequency notch filtering and analog-to-digital conversion in sequence to obtain a 14-bit digital signal; S4, the digital signal is sent to the digital processing module and sequentially undergoes optimized fast Fourier transform calculation, power spectrum calculation, second power frequency suppression and feature extraction; S5, the final obtained EEG rhythm characteristic parameters or spectrum data are output to the external host through the interface and control module.

[0012] Preferably, obtaining the 14-bit digital signal includes the following steps: S301, low-noise amplifier, performs preliminary amplification of the input EEG signal through a low-noise amplifier; S302, bandpass filter, filters out noise outside the frequency band of the amplified EEG signal; S303, power frequency notch filter, suppresses 50Hz power frequency interference in EEG signals after noise filtering through an adaptive power frequency notch filter. S304, Analog-to-Digital Converter, converts an analog signal after interference suppression into a digital signal using an analog-to-digital converter.

[0013] Preferably, the fast Fourier transform calculation includes the following steps: S401, padding with zeros to form a complex sequence, padding N-point real sequence data from analog-to-digital conversion with zeros to construct an N / 2-point complex sequence; S402, Execute the fast Fourier transform calculation of the N / 2 point complex sequence, and call the coordinate rotation digital calculation algorithm unit to generate the rotation factor in real time; S403 ultimately outputs the complete N-point spectrum. By utilizing the conjugate symmetry of the real sequence spectrum, the complete N-point real sequence spectrum is separated and output from the calculation results.

[0014] The technical effects and advantages of this invention are as follows: This invention integrates a low-noise analog front-end, a dedicated digital processing module, and a fine power management module into a single chip, constructing a dual anti-interference link that combines analog and digital technologies. While ensuring signal purity, it utilizes the digital processing module to accelerate real-time processing speed, and controls overall power consumption through fully customized circuitry and dynamic power management. This solves the three major problems of poor real-time performance, high power consumption, and weak noise immunity in general-purpose processor solutions for EEG spectrum analysis, thus meeting the demanding requirements of wearable devices. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the chip process of the present invention.

[0016] Figure 2This is a flowchart of the chip usage method of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Example 1: The present invention provides as follows Figure 1 The low-power FFT chip for real-time spectrum analysis of EEG signals shown includes: The analog front-end module is used to amplify, filter, perform power frequency notch filtering, and convert analog to digital signals at the input microvolt level. The digital processing module is electrically connected to the output of the analog front-end module and is used to perform fast Fourier transform, power spectrum calculation and feature extraction on the digital signal from the analog front-end module. The interface and control module is electrically connected to the input terminals of the analog front-end module and the digital processing module. It is used to receive external configuration parameters and output the processed spectrum data or characteristic parameters. The low-power management and clock control module is electrically connected to the control terminals of the analog front-end module, digital processing module, and interface and control module. It is used to synchronize the operation of each module of the chip and perform dynamic power consumption management.

[0019] Specifically, the simulated front-end module includes the following executed sequentially: A low-noise amplifier, employing a folded common-source common-gate structure and operating in the subthreshold region, is used for preliminary amplification of input EEG signals; A bandpass filter is electrically connected to the output of a low-noise amplifier. The bandpass filter has a fourth-order Chebyshev response and is used to filter out noise outside the frequency band of the EEG signal. An adaptive power frequency notch filter is electrically connected to the output of a bandpass filter to suppress 50Hz power frequency interference. An analog-to-digital converter (ADC) is electrically connected to the output of an adaptive power frequency notch filter to convert the filtered analog signal into a digital signal.

[0020] It should be noted that the analog front-end module is the fundamental signal conditioning link that ensures system performance and power consumption. It performs high-precision, low-noise signal amplification, filtering, and conversion sequentially in a cascaded manner. This module first uses a low-noise amplifier to initially amplify the input microvolt-level EEG signal. Then, the amplified signal is sent to a bandpass filter electrically connected to its output. This filter has a fourth-order Chebyshev frequency response, which can accurately filter out environmental noise and device-inherent noise outside the EEG signal band with a steep roll-off characteristic, thereby effectively extracting useful physiological signal components. Next, the bandpass-filtered signal... The signal then enters the adaptive power frequency notch filter, a unit specifically designed to dynamically monitor and powerfully suppress 50Hz power frequency interference, ensuring stable suppression under various conditions. Together with the secondary suppression in the subsequent digital processing stage, it forms a robust anti-interference system. Finally, the amplified, filtered, and notch-processed analog signal is sent to the analog-to-digital converter electrically connected to the notch filter output. This converter employs a 14-bit high-precision design to digitize the pure analog EEG signal with sufficient resolution, providing a data source for the subsequent digital processing module and laying a solid analog circuit foundation for the chip's total power consumption of less than 50μW.

[0021] Specifically, the digital processing module includes: The Fast Fourier Transform (FFT) computation unit adopts an 8-stage pipeline structure, with each stage containing a parallel butterfly operation unit, used to perform Fast Fourier Transform on digital signals, converting time-domain signals into frequency-domain data; The post-processing unit is electrically connected to the output of the fast Fourier transform calculation unit and is used to perform power spectrum calculation, secondary power frequency suppression, and feature extraction on the fast Fourier transform calculation results.

[0022] Specifically, the Fast Fourier Transform calculation unit integrates a coordinate rotation digital calculation algorithm unit, which is used to calculate the rotation factor required for butterfly operations in real time.

[0023] Specifically, the Fast Fourier Transform (FFT) calculation unit utilizes the symmetry of the real signal to convert the total number of points N in the sequence into an N / 2-point complex sequence through zero-padding and conjugate symmetry processing, and then performs FFT calculations.

[0024] Specifically, the post-processing unit includes the following executed sequentially: The power spectrum calculation unit is used to calculate the square of the spectrum amplitude. The secondary power frequency suppression unit is used to digitally filter specific narrowband power frequency interference that remains in the power spectrum. The feature extraction unit is used to calculate the power ratio of signals in multiple frequency bands as output features.

[0025] It should be noted that the Fast Fourier Transform (FFT) computation unit adopts a highly parallelized 8-stage pipeline hardware structure. Each stage of the pipeline integrates multiple butterfly operation units that can perform operations simultaneously, enabling data to be processed at high speed in a step-by-step, streamlined manner, much like on an industrial assembly line. This improves data throughput and real-time performance, laying a speed foundation for subsequent analysis. At the algorithm level, this module integrates two key innovations to optimize energy efficiency and area. First, it incorporates a coordinate rotation digital computation algorithm unit to generate the rotation factors necessary for butterfly operations in real time. This design eliminates the reliance on large-scale read-only memory lookup tables in traditional solutions, saving chip area and reducing related static power consumption while ensuring computational accuracy. Second, it conducts in-depth algorithm-hardware co-optimization based on the inherent characteristics of EEG signals as real sequences. Utilizing the symmetry of real signals, it optimizes the computational path of a 256-point real sequence FFT into a 128-point complex sequence FFT. This optimized path cleverly utilizes mathematical symmetry, directly reducing computational complexity by approximately 50% while ensuring the integrity of spectral information.

[0026] The frequency domain complex results obtained after processing by the Fast Fourier Transform (FFT) calculation unit are transmitted in real time to the post-processing unit directly electrically connected to it. This module is responsible for performing a series of detailed subsequent analyses to extract stable, interference-resistant, and physiologically significant features from the original spectrum. The processing flow is progressive: first, the power spectrum calculation unit performs amplitude square operation on the complex spectrum results, clearly presenting the signal energy distribution in the form of a power spectrum, which is the foundation of all frequency domain analyses. Next, the secondary power frequency suppression unit performs precise digital filtering on any residual specific narrowband power frequencies and their harmonic interference in the power spectrum. This, together with the power frequency notch filter at the analog front end, forms a dual anti-interference defense line of "analog suppression + digital elimination," ensuring the purity of the spectrum data. Finally, the feature extraction unit calculates and outputs a direct and reliable input basis for intelligent interpretation based on the purified power spectrum and preset EEG rhythms.

[0027] Specifically, the interface and control modules include: The configuration interface is used to receive configuration parameters sent from the outside and to send the configuration parameters to the digital processing module and the analog front-end module. The data output interface is used to output the feature parameters obtained by the feature extraction unit or the spectrum data obtained by the power spectrum calculation unit.

[0028] Example 2: The present invention provides as follows Figure 2 The method of using a low-power FFT chip for real-time spectrum analysis of EEG signals, as shown above, includes the following steps: S1 receives external configuration parameters through the interface and control module to set the chip's operating mode; S2, the low-power management and clock control module, provides clocks for each functional module and initiates dynamic power management; S3, the analog front-end module for inputting EEG analog signals, sequentially passes through low-noise amplification, bandpass filtering, power frequency notch filtering, and analog-to-digital conversion to obtain a 14-bit digital signal; S4, the digital signal is sent to the digital processing module, and then undergoes optimized fast Fourier transform calculation, power spectrum calculation, second power frequency suppression and feature extraction in sequence. S5, the final obtained EEG rhythm characteristic parameters or spectrum data, is output to the external host through the interface and control module.

[0029] Specifically, obtaining the 14-bit digital signal includes the following steps: S301, low-noise amplifier, performs preliminary amplification of the input EEG signal through a low-noise amplifier; S302, bandpass filter, filters out noise outside the frequency band of the amplified EEG signal; S303, power frequency notch filter, suppresses 50Hz power frequency interference in EEG signals after noise filtering through an adaptive power frequency notch filter. S304, Analog-to-Digital Converter, converts an analog signal after interference suppression into a digital signal using an analog-to-digital converter.

[0030] Furthermore, firstly, a low-noise amplifier with a folded cascode structure and operating in the subthreshold region is used to perform high-gain, low-noise preliminary amplification of the input microvolt-level EEG signal. Subsequently, the amplified signal is passed through a bandpass filter with a fourth-order Chebyshev response, which precisely filters out noise outside the effective EEG frequency band with a steep roll-off characteristic. Then, an adaptive power frequency notch filter dynamically monitors and strongly suppresses the 50Hz power frequency, forming the first anti-interference barrier. Finally, the processed clean analog signal is sent to a 14-bit high-precision analog-to-digital converter to be converted into a high-quality digital signal, laying the foundation for subsequent digital processing.

[0031] Specifically, the Fast Fourier Transform calculation includes the following steps: S401, padding with zeros to form a complex sequence, padding N-point real sequence data from analog-to-digital conversion with zeros to construct an N / 2-point complex sequence; S402, Execute the fast Fourier transform calculation of the N / 2 point complex sequence, and call the coordinate rotation digital calculation algorithm unit to generate the rotation factor in real time; S403 ultimately outputs the complete N-point spectrum. By utilizing the conjugate symmetry of the real sequence spectrum, the complete N-point real sequence spectrum is separated and output from the calculation results.

[0032] Furthermore, firstly, the N-point real sequence data from the analog-to-digital converter is padded with zeros to reconstruct an N / 2-point complex sequence, thus laying the data structure foundation for subsequent simplified calculations. Next, the system calls the integrated coordinate rotation digital calculation algorithm unit to generate the rotation factor required for the butterfly operation in real time. This completely eliminates the reliance on traditional ROM lookup tables, becoming key to reducing chip area. Subsequently, the N / 2-point complex sequence is sent to a dedicated 8-stage pipelined butterfly operation unit for core transformation. In this process, the data flows through a highly efficient pipeline. The N / 2-point complex fast Fourier transform is performed by processing the data step-by-step at high speed through multiple parallel butterfly operation units at each stage. Finally, the algorithm utilizes the mathematical essence of the conjugate symmetry of the spectrum of the real sequence to accurately separate the real and imaginary parts from the above complex transform results and reconstruct the complete N-point real sequence spectrum. The entire process reduces the theoretical computational load by 50% without losing any spectral information by transforming the complete N-point real sequence FFT into an N / 2-point complex FFT calculation. This is a core algorithmic innovation for achieving high real-time performance and ultra-low power consumption in the chip.

[0033] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-power FFT chip for real-time spectral analysis of electroencephalogram (EEG) signals, characterized in that, include: The analog front-end module is used to amplify, filter, perform power frequency notch filtering, and convert analog to digital signals at the input microvolt level. A digital processing module, electrically connected to the output of the analog front-end module, is used to perform fast Fourier transform, power spectrum calculation, and feature extraction on the digital signal from the analog front-end module. An interface and control module is electrically connected to the input terminals of the analog front-end module and the digital processing module, and is used to receive external configuration parameters and output the processed spectrum data or characteristic parameters. A low-power management and clock control module is electrically connected to the control terminals of the analog front-end module, digital processing module, and interface and control module. It is used to synchronize the operation of each module of the chip and perform dynamic power consumption management.

2. The low-power FFT chip for real-time spectrum analysis of EEG signals according to claim 1, characterized in that, The simulated front-end module includes the following components that are executed sequentially: A low-noise amplifier, employing a folded common-source common-gate structure and operating in the subthreshold region, is used for preliminary amplification of input EEG signals; A bandpass filter, electrically connected to the output of a low-noise amplifier, has a fourth-order Chebyshev response and is used to filter out noise outside the frequency band of the EEG signal. An adaptive power frequency notch filter is electrically connected to the output of a bandpass filter to suppress 50Hz power frequency interference. An analog-to-digital converter, electrically connected to the output of an adaptive power frequency notch filter, is used to convert the filtered analog signal into a digital signal.

3. The low-power FFT chip for real-time spectrum analysis of EEG signals according to claim 1, characterized in that, The digital processing module includes: The Fast Fourier Transform (FFT) computation unit adopts an 8-stage pipeline structure, with each stage containing a parallel butterfly operation unit, used to perform Fast Fourier Transform on digital signals, converting time-domain signals into frequency-domain data; The post-processing unit is electrically connected to the output of the fast Fourier transform calculation unit and is used to perform power spectrum calculation, secondary power frequency suppression, and feature extraction on the fast Fourier transform calculation results.

4. The low-power FFT chip for real-time spectrum analysis of EEG signals according to claim 3, characterized in that, The Fast Fourier Transform calculation unit integrates a coordinate rotation digital calculation algorithm unit, which is used to calculate the rotation factor required for butterfly operations in real time.

5. A low-power FFT chip for real-time spectrum analysis of electroencephalogram (EEG) signals according to claim 3, characterized in that, The Fast Fourier Transform (FFT) calculation unit utilizes the symmetry of the real signal to convert the total number of points N in the sequence into an N / 2-point complex sequence through zero-padding and conjugate symmetry processing, and then performs FFT calculations.

6. The low-power FFT chip for real-time spectrum analysis of EEG signals according to claim 1, characterized in that, The post-processing unit includes the following components executed sequentially: The power spectrum calculation unit is used to calculate the square of the spectrum amplitude. The secondary power frequency suppression unit is used to digitally filter specific narrowband power frequency interference that remains in the power spectrum. The feature extraction unit is used to calculate the power ratio of signals in multiple frequency bands as output features.

7. A low-power FFT chip for real-time spectrum analysis of electroencephalogram (EEG) signals according to claim 6, characterized in that, The interface and control module include: The configuration interface is used to receive configuration parameters sent from the outside and to send the configuration parameters to the digital processing module and the analog front-end module. The data output interface is used to output the feature parameters obtained by the feature extraction unit or the spectrum data obtained by the power spectrum calculation unit.

8. A method for using a low-power FFT chip for real-time spectrum analysis of electroencephalogram (EEG) signals, characterized in that, The method of using a low-power FFT chip for real-time spectrum analysis of electroencephalogram (EEG) signals as described in any one of claims 1 to 7 includes the following steps: S1, receive external configuration parameters through the interface and control module to set the chip's operating mode; S2 provides clocks to each functional module through a low-power management and clock control module, and initiates dynamic power management; S3, the brainwave analog signal is input into the analog front-end module to obtain a 14-bit digital signal; S4, the digital signal is sent to the digital processing module and sequentially undergoes optimized fast Fourier transform calculation, power spectrum calculation, second power frequency suppression and feature extraction; S5, the final obtained EEG rhythm characteristic parameters or spectrum data are output to the external host through the interface and control module.

9. The method of using a low-power FFT chip for real-time spectrum analysis of electroencephalogram (EEG) signals according to claim 8, characterized in that, Obtaining the 14-bit digital signal involves the following steps: S301, low-noise amplifier, performs preliminary amplification of the input EEG signal through a low-noise amplifier; S302, bandpass filter, filters out noise outside the frequency band of the amplified EEG signal; S303, power frequency notch filter, suppresses 50Hz power frequency interference in EEG signals after noise filtering through an adaptive power frequency notch filter. S304, Analog-to-Digital Converter, converts an analog signal after interference suppression into a digital signal using an analog-to-digital converter.

10. The method of using a low-power FFT chip for real-time spectrum analysis of electroencephalogram (EEG) signals according to claim 8, characterized in that, The Fast Fourier Transform calculation includes the following steps: S401, zero-padding to form a complex sequence, zero-padding the N-point real sequence data from the analog-to-digital conversion to construct an N / 2-point complex sequence; S402, Execute the fast Fourier transform calculation of the N / 2 point complex sequence, and call the coordinate rotation digital calculation algorithm unit to generate the rotation factor in real time; S403 ultimately outputs the complete N-point spectrum. By utilizing the conjugate symmetry of the real sequence spectrum, the complete N-point real sequence spectrum is separated and output from the calculation results.

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