Soft reset circuit for analog neurons
By controlling the charging and discharging of the membrane capacitor and the reset capacitor, and coordinating with switching elements, combined with adaptive isolation and resting potential reset, the high power consumption problem of the simulated neuron soft reset circuit is solved, achieving a low power soft reset effect and meeting the needs of large-scale neural networks.
Patent Information
- Application Number
- CN202411934046.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2026-06-26
AI Technical Summary
Existing soft reset circuits for simulating neurons suffer from excessive power consumption during implementation, failing to meet the requirements of large-scale neural networks.
By controlling the charging and discharging of the membrane capacitor and the reset capacitor and the switching elements, a soft reset module is used to achieve low-power discharge of the membrane capacitor. Combined with an adaptive isolation unit and a resting potential reset module, the soft reset effect of the membrane potential is ensured.
It achieves soft reset of simulated neurons with extremely low power consumption, meets the needs of large-scale neural networks, avoids information loss, and improves the inference accuracy of neural networks.
Smart Images
Figure CN122287737A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of neuron circuits, and more particularly to a soft reset circuit for simulating neurons. Background Technology
[0002] Spiking Neural Networks (SNNs) contain neurons with temporal dynamics, possessing powerful spatiotemporal information representation and asynchronous event processing capabilities, and are considered third-generation neural networks. Synapses in SNNs are the connections between spiking neurons used for information transmission. Neurons in SNNs are not activated in every iteration, but rather when their membrane potential reaches a specific value. When a neuron is activated, it generates a signal that is transmitted to other neurons, raising or lowering their membrane potentials. The membrane potential of the activated neuron itself needs to be reset.
[0003] There are two membrane potential reset strategies: directly pulling the membrane potential down to the reset voltage, which is called hard reset; and subtracting a certain value from the membrane potential, which is called soft reset.
[0004] In spiking neural networks, the charge on the membrane potential represents the information transmitted to the neuron via synapsis. When the membrane potential is reset, a hard reset directly pulls the membrane potential down to the reset voltage, losing the portion of the charge exceeding the threshold. This is equivalent to losing some information and affects the inference accuracy of the spiking neural network. A soft reset, however, retains the portion of the charge exceeding the threshold during the reset operation, preventing information loss.
[0005] Figure 5 This illustrates the difference in membrane potential trends between hard reset and soft reset methods. Figure 5 As shown, in hard reset mode, the membrane potential will be reset to a certain fixed level regardless of how much it exceeds the threshold voltage. In soft reset mode, the portion of the membrane potential that exceeds the threshold will be retained, and the membrane potential will only decrease by a certain value each time it is reset.
[0006] There are two types of circuit implementations for neurons: digital and analog. Digital circuits are relatively simple to implement soft-reset subtraction, but digital neurons have problems such as large area and high power consumption. In the current implementation of analog neurons, there are still technical challenges in how to implement soft-reset subtraction at a lower cost. The current implementation methods consume too much power and cannot meet the needs of large-scale neural networks. Summary of the Invention
[0007] This disclosure was made to solve the aforementioned problems in the prior art, and its purpose is to provide a soft reset circuit for simulating neurons, which can realize the soft reset function of simulating neurons with extremely low power consumption, thus meeting the needs of large-scale neural networks.
[0008] According to an exemplary embodiment of the present disclosure, a soft reset circuit for simulating a neuron is provided, comprising:
[0009] A membrane potential accumulation module, which includes a membrane capacitor, is used to accumulate input signals representing information input to neurons to generate membrane potential signals.
[0010] A pulse generation module receives the membrane potential signal from the membrane potential accumulation module and generates a pulse signal based on whether the membrane potential signal exceeds a predetermined threshold voltage.
[0011] A reset signal generation module receives the pulse signal from the pulse generation module and generates a reset signal with a pulse width greater than or equal to the pulse signal based on the pulse signal; and
[0012] A soft reset module includes a reset capacitor connected in series with the membrane capacitor, a first switching element connected between the membrane capacitor and the reset capacitor, and a second switching element connected in parallel with the reset capacitor.
[0013] The soft reset module receives the reset signal from the reset signal generation module.
[0014] When the reset signal is at the first level, the soft reset module turns off the first switching element and turns on the second switching element.
[0015] When the reset signal is at the second level, the soft reset module turns on the first switching element and turns off the second switching element, thereby causing the membrane capacitor to discharge to the reset capacitor. When the voltage across the reset capacitor exceeds a specified value, the first switching element is turned off, stopping the discharge of the membrane capacitor.
[0016] Optionally, in the soft reset circuit for simulating neurons described above, the membrane potential accumulation module further includes an adaptive isolation unit. The adaptive isolation unit is turned on when the reset signal is at a first level, providing the membrane potential signal to the input terminal of the pulse generation module, and turned off when the reset signal is at a second level, isolating the membrane potential signal from the input terminal of the pulse generation module.
[0017] Optionally, in the soft reset circuit for simulating neurons described above, the adaptive isolation unit is a transmission gate structure.
[0018] Optionally, the soft reset circuit for simulating neurons described above also includes a resting potential reset module, which resets the input terminal of the pulse generation module to the resting potential when the reset signal is at the second level.
[0019] Optionally, in the soft reset circuit for simulating neurons described above, the reset signal generation module receives a bias voltage signal from the outside and adjusts the pulse width of the reset signal based on the bias voltage signal.
[0020] Optionally, in the soft reset circuit for simulating neurons described above, the soft reset module further includes a reset level conversion unit, which generates a reset level conversion signal with a voltage amplitude below the power supply voltage based on the reset signal and provides it to the first switching element.
[0021] Optionally, in the soft reset circuit for simulating neurons described above, the membrane potential accumulation module further includes a leakage unit, which, when there is no input signal, uses a leakage voltage signal received from the outside to leak the membrane potential signal to the resting potential.
[0022] Optionally, in the soft reset circuit for simulating neurons described above, the ratio of the capacitance values of the membrane capacitor to the reset capacitor is determined based on the amount of charge that the membrane capacitor needs to discharge to the reset capacitor.
[0023] According to the soft reset circuit for simulating neurons disclosed herein, by utilizing the charging and discharging between the membrane capacitor and the reset capacitor and the switching control of the switching element, the discharge of the membrane capacitor to the reset capacitor can be controlled, thereby achieving the soft reset function of simulating neurons with extremely low power consumption, meeting the needs of large-scale neural networks. Attached Figure Description
[0024] This disclosure can be better understood by describing exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, in which:
[0025] Figure 1 To illustrate the structural block diagram of the soft reset circuit for simulating neurons according to the embodiments of this disclosure;
[0026] Figure 2 A schematic diagram illustrating an example of the soft reset circuit for simulating neurons disclosed herein;
[0027] Figure 3 A schematic diagram illustrating another example of the soft reset circuit for simulating neurons disclosed herein;
[0028] Figure 4 To show Figure 3The waveforms of each signal in the soft reset circuit used to simulate a neuron are shown below.
[0029] Figure 5 A graph illustrating the difference in membrane potential trends during hard reset and soft reset. Detailed Implementation
[0030] The following describes specific embodiments of this disclosure. It should be noted that, in order to maintain brevity, this specification cannot provide a detailed description of all features of the actual embodiments. It should be understood that, in the actual implementation of any embodiment, just as in any engineering or design project, various specific decisions are often made to achieve the developer's specific goals and to meet system-related or business-related constraints, and this can change from one embodiment to another. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content of this disclosure, changes in design, manufacturing, or production based on the technical content disclosed herein are merely conventional technical means and should not be construed as insufficient content of this disclosure.
[0031] Unless otherwise defined, the technical or scientific terms used in the claims and description shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this patent application description and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. The terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the element or object preceding “comprising” or “including” encompasses the element or object listed following “comprising” or “including” and its equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, nor are they limited to direct or indirect connections.
[0032] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0033] Unless otherwise specified, all embodiments and preferred embodiments mentioned herein can be combined to form new technical solutions. Similarly, unless otherwise specified, all technical features and preferred features mentioned herein can be combined to form new technical solutions.
[0034] The embodiments of this disclosure will now be described with reference to the accompanying drawings. It should be understood that the embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.
[0035] use Figures 1-2 The structure of the soft reset circuit for simulating neurons according to the embodiments of this disclosure will be described. Figure 1 To illustrate the structural block diagram of the soft reset circuit 10 for simulating neurons according to an embodiment of this disclosure, Figure 2 This is a schematic diagram illustrating an example of a soft reset circuit 10 used to simulate a neuron.
[0036] like Figure 1 As shown, the soft reset circuit 10 used to simulate a neuron may include a membrane potential accumulation module 11, a pulse generation module 12, a reset signal generation module 13, and a soft reset module 14.
[0037] Reference Figure 2 As shown in the structure, the membrane potential accumulation module 11 may include a membrane capacitor Cm, which is used to accumulate the input signal representing the information input to the neuron to generate a membrane potential signal Vm.
[0038] The membrane potential signal Vm is the voltage across the membrane capacitance Cm. In the initial state, the membrane potential signal Vm is usually the resting potential Vrest. The resting potential Vrest refers to the membrane potential of nerve or muscle cells in a resting, inactive state. This potential is caused by the uneven distribution of ions inside and outside the cell. In non-excited cells and excitable cells in the baseline state, this resting potential usually remains relatively stable.
[0039] Figure 2In the example shown, during the inference operation of the spiking neural network (SNN), the synaptic current Iin, which serves as the input signal, is injected into one end of the membrane capacitor Cm and accumulated, causing the membrane potential signal Vm to rise. The other end of the membrane capacitor Cm is grounded.
[0040] The pulse generation module 12 can receive the membrane potential signal Vm from the membrane potential accumulation module 11 and generate a pulse signal Vspike based on whether the membrane potential signal Vm exceeds the specified threshold voltage Vth.
[0041] exist Figure 2 In the example shown, the pulse generation module 12 may include an inverter composed of a PMOS transistor M6 and an NMOS transistor M7, and an inverter composed of a PMOS transistor M8 and an NMOS transistor M9.
[0042] The gates of both PMOS transistor M6 and NMOS transistor M7 are connected to the input terminal of pulse generation module 12, and the potential signal at the input terminal is Vm_in. The source of PMOS transistor M6 is connected to the power supply voltage V. DD The drain is connected to the drain of NMOS transistor M7, and the source of NMOS transistor M7 is grounded.
[0043] The connection point between the drain of PMOS transistor M6 and the drain of NMOS transistor M7 is connected to the gates of PMOS transistor M8 and NMOS transistor M9. The source of PMOS transistor M8 is connected to the power supply voltage V. DD The drain of PMOS transistor M8 is connected to the drain of NMOS transistor M9, and the source of NMOS transistor M9 is grounded. A pulse signal Vspike is output from the connection point between the drain of PMOS transistor M8 and the drain of NMOS transistor M9.
[0044] Of course, the above-described circuit structure of the pulse generation module 12 is only an example, and this disclosure is not limited to it. Any circuit structure that can generate a pulse signal based on whether the membrane potential signal exceeds a specified threshold voltage is acceptable.
[0045] The reset signal generation module 13 receives the pulse signal Vspike from the pulse generation module 12 and generates a reset signal Vrfr with a pulse width greater than or equal to that of the pulse signal Vspike. That is, the pulse width of the reset signal Vrfr can be greater than or equal to the pulse width of the pulse signal Vspike. For example, in some embodiments of this disclosure, the pulse width of the pulse signal Vspike is a few milliseconds (ms), and the pulse width of the reset signal Vrfr can be tens of milliseconds (ms).
[0046] exist Figure 2In the example shown, the reset signal generation module 13 may include an inverter composed of PMOS transistor M10, PMOS transistor M11, and NMOS transistor M12, and an inverter composed of PMOS transistor M13 and NMOS transistor M14.
[0047] The gate input of PMOS transistor M10 has an external bias voltage signal Vbias, and its source is connected to the power supply voltage V. DD The drain of the PMOS transistor M11 is connected to the source of the NMOS transistor M12. The gates of both the PMOS transistor M11 and the NMOS transistor M12 are connected to the output of the pulse generation module 12 to receive the pulse signal Vspike. The drain of the PMOS transistor M11 is connected to the drain of the NMOS transistor M12, and the source of the NMOS transistor M12 is grounded.
[0048] The connection point between the drain of PMOS transistor M11 and the drain of NMOS transistor M12 is connected to the gates of PMOS transistor M13 and NMOS transistor M14. The source of PMOS transistor M13 is connected to the power supply voltage V. DD The drain of PMOS transistor M13 is connected to the drain of NMOS transistor M14, and the source of NMOS transistor M14 is grounded. A reset signal Vrfr is output from the connection point between the drain of PMOS transistor M13 and the drain of NMOS transistor M14.
[0049] According to the above structure, the reset signal generation module 13 can receive a bias voltage signal Vbias from the outside and adjust the pulse width of the reset signal Vrfr based on the bias voltage signal Vbias. The pulse duration of the reset signal Vrfr is related to the refractory period. The refractory period refers to the relatively long period of time during which a single neuron cannot trigger an action potential again after generating an action potential. The refractory period can also be set to be non-existent. When there is no refractory period, the pulse width of the reset signal Vrfr is adjusted to the shortest possible value through the bias voltage signal Vbias, and the pulse width of the reset signal Vrfr is approximately equal to the pulse width of the pulse signal Vspike. Vbias and the refractory period are key factors in controlling the temporal rhythm of neuronal activity in the design of spiking neural networks (SNNs). Changes in Vbias affect the activation threshold of neurons, thereby affecting the length of the refractory period. Vbias and the refractory period play an important role in dynamically evolving spiking neural networks and can optimize neural network performance. In some embodiments of this disclosure, Vbias can be greater than the power supply voltage V. DD It's several hundred millivolts lower.
[0050] Of course, the above-described circuit structure of the reset signal generation module 13 is only an example, and this disclosure is not limited to it. Any circuit structure that can generate a reset signal with a pulse width greater than or equal to a pulse signal based on a pulse signal is acceptable.
[0051] like Figure 2 As shown, the soft reset module 14 may include a reset capacitor Csr connected in series with the membrane capacitor Cm, a first switching element M1 connected between the membrane capacitor Cm and the reset capacitor Csr, and a second switching element M2 connected in parallel with the reset capacitor Csr.
[0052] The soft reset module 14 receives the reset signal Vrfr from the reset signal generation module 13. When the reset signal Vrfr is at the first level, the soft reset module 14 turns off the first switching element M1 and turns on the second switching element M2.
[0053] When the reset signal Vrfr is at the second level, the soft reset module 14 turns on the first switching element M1 and turns off the second switching element M2, thereby causing the membrane capacitor Cm to discharge to the reset capacitor Csr. When the voltage Vsr across the reset capacitor Csr exceeds a specified value, the first switching element M1 turns off, stopping the discharge of the membrane capacitor Cm. The capacitance ratio of the membrane capacitor Cm to the reset capacitor Csr can be determined based on the amount of charge that the membrane capacitor Cm needs to discharge to the reset capacitor Csr.
[0054] In addition, Figure 2 In the example shown, the first level of the reset signal Vrfr is low, and the second level is high; that is, the reset signal Vrfr is valid when it is high, initiating the reset. Of course, this disclosure is not limited to this; alternatively, the first level of the reset signal Vrfr can be set to high, and the second level to low, meaning the reset signal Vrfr is valid when it is low, initiating the reset.
[0055] Furthermore, the first switching element M1 and the second switching element M2 can be power semiconductor switching elements such as IGBT transistors and MOS transistors. Figure 2 In the example shown, both the first switching element M1 and the second switching element M2 are NMOS transistors. The gate input of NMOS transistor M1 has a reset signal Vrfr, its drain is connected to one end of the film capacitor Cm, and its source is connected to the drain of NMOS transistor M2 and one end of the reset capacitor Csr. The other end of the reset capacitor Csr is grounded. The gate input of NMOS transistor M2 has an inverted signal Vrfrb of the reset signal Vrfr, and its source is grounded.
[0056] In the membrane potential accumulation module 11, since the synaptic current Iin, which serves as the input signal, is injected into one end of the membrane capacitor Cm, parasitic capacitance is generated at the synapse (see below). Figure 3The parasitic capacitance (Cpa) in the circuit can affect the operating speed of the circuit. Furthermore, in the soft reset method, the membrane potential only decreases by a fixed value. If the membrane potential before reset is particularly high, it may still be higher than the specified threshold voltage Vth after reset, resulting in the pulse signal not ending and an excessively long pulse width.
[0057] Based on the above problems, in some embodiments of this disclosure, such as Figure 2 As shown, the membrane potential accumulation module 11 may also include an adaptive isolation unit 111. The adaptive isolation unit 111 is turned on when the reset signal Vrfr is at the first level, providing the membrane potential signal Vm to the input terminal of the pulse generation module 12, and turned off when the reset signal is at the second level, isolating the membrane potential signal Vm from the input terminal of the pulse generation module 12.
[0058] By setting an adaptive isolation unit, isolation can be performed after the reset starts. The voltage at the input of the pulse generation module can be quickly pulled down, and the pulse will have a sharp downward sliding shape instead of a slowly sliding ramp shape, thus obtaining a more ideal pulse signal. At the same time, it can also avoid the pulse width being too long due to the pulse not ending.
[0059] exist Figure 2 In the example shown, the adaptive isolation unit 111 is a transmission gate structure composed of a PMOS transistor M3 and an NMOS transistor M4 connected in parallel. The gate input of the PMOS transistor M3 has a reset signal Vrfr as a control signal, and the gate input of the NMOS transistor M4 has an inverted signal Vrfrb of the reset signal Vrfr as a control signal. Of course, the structure of the adaptive isolation unit 111 is not limited to this, and other isolation circuit structures can also be used.
[0060] When the adaptive isolation unit 111 is provided, the soft reset circuit 10 for simulating neurons may further include a resting potential reset module 15. When the reset signal Vrfr is at the second level, the resting potential reset module 15 resets the input terminal of the pulse generation module 12 to the resting potential Vrest, which can quickly pull down the voltage at the input terminal of the pulse generation module 12.
[0061] like Figure 2 As shown, the resting potential reset module 15 can be implemented using an NMOS transistor M15. The gate input of the NMOS transistor M15 has a reset signal Vrfr, the drain is connected to the input terminal of the pulse generation module 12, and the source is connected to the resting potential Vrest.
[0062] Furthermore, in some embodiments of this disclosure, such as Figure 2As shown, the membrane potential accumulation module 11 may further include a leakage unit 112. The leakage unit 112 can use the leakage voltage signal Vleak received from the outside to leak the membrane potential signal Vm to the resting potential Vrest when there is no input signal.
[0063] like Figure 2 As shown, the leakage unit 112 can be implemented using an NMOS transistor M5. The gate input of the NMOS transistor M5 has a leakage voltage signal Vleak, the drain is connected to the input terminal of the pulse generation module 12, and the source is connected to the resting potential Vrest.
[0064] Figure 3 The diagram shows the structure of another example of the soft reset circuit for simulating neurons disclosed herein. Figure 3 Examples and Figure 2 The differences are as follows: 1) The membrane potential accumulation module 11 shows the parasitic capacitance Cpa generated by the synapse, and the leakage unit 112 is removed; 2) The pulse generation module 12 is implemented by a Schmitt trigger composed of PMOS transistor M6, NMOS transistor M7, PMOS transistor M8, NMOS transistor M9, and NMOS transistor M20; 3) The soft reset module 14 shows an inverter composed of PMOS transistor M16 and NMOS transistor M17, which is used to obtain the inverted signal Vrfrb of the reset signal Vrfr and provide it to the gate of NMOS transistor M2, which is the second switching element; 4) The soft reset module 14 also includes a reset level conversion unit 141. The reset level conversion unit 141 generates a voltage amplitude V based on the reset signal Vrfr, which is equal to the power supply voltage V. DD The following reset level conversion signal Vrfr_ls is provided to the gate of the NMOS transistor M1, which serves as the first switching element.
[0065] exist Figure 3 In the example shown, the reset level conversion unit 141 is implemented by an inverter composed of a PMOS transistor M18 and an NMOS transistor M19. The gates of both the PMOS transistor M18 and the NMOS transistor M19 are input with the inverted signal Vrfrb of the reset signal Vrfr. The source of the PMOS transistor M18 is connected to the voltage Vreset, and its drain is connected to the drain of the NMOS transistor M12. The source of the NMOS transistor M12 is grounded. The voltage Vreset is set to the power supply voltage V. DD For example, the voltage Vreset can be higher than the supply voltage V. DD It is several hundred millivolts (mV) lower.
[0066] Based on the above structure, the voltage amplitude of the reset level conversion signal Vrfr_ls becomes the voltage Vreset, which is the power supply voltage V. DD the following.
[0067] In a soft-reset circuit used to simulate a neuron, it is desirable that the voltage Vsr on the reset capacitor Csr after the reset is completed does not exceed the resting potential Vrest of the membrane capacitor Cm. Figure 2 In the structure shown, a reset signal Vrfr is provided to the gate of the NMOS transistor M1, which serves as the first switching element, and its voltage amplitude is equal to the power supply voltage V. DD Therefore, if the power supply voltage V DD If it is too large, the power supply voltage V DD Even after subtracting the threshold voltage Vthn of the NMOS transistor M1, it may still be too large, causing the voltage Vsr on the reset capacitor Csr to exceed the resting potential Vrest after the reset is completed.
[0068] Therefore, by setting the reset level conversion unit 141, the voltage amplitude is converted to the power supply voltage V. DD The following reset level conversion signal Vrfr_ls is provided to the gate of NMOS transistor M1 to prevent the voltage Vsr on the reset capacitor Csr from exceeding the resting potential Vrest of the film capacitor Cm after the reset is completed.
[0069] Figure 4 To show Figure 3 The diagram shows the waveforms of various signals in the soft-reset circuit used to simulate a neuron. (See diagram for example.) Figure 4 As shown, Iin represents the input synaptic current signal, Vm represents the membrane potential signal, Vm_in represents the potential signal at the input terminal of the pulse generation module 12, Vspike represents the pulse signal, Vrfr represents the reset signal, Vrfr_ls represents the reset level conversion signal, and Vsr represents the voltage signal of the reset capacitor Csr.
[0070] exist Figure 4 In the waveform diagram shown, the time period from time t1 to time t2 is the integration phase, the time period from time t2 to time t3 is the ignition phase, and the time period from time t3 to time t4 is the reset phase.
[0071] When the membrane potential Vm is higher than the specified threshold voltage Vth, the spiking neuron is considered to have ignited. This ignition process is similar to the generation of nerve impulses in biological neurons, while in spiking neural networks (SNNs), this process is simulated to realize the transmission and processing of information.
[0072] In the initial state, the membrane potential Vm of the membrane capacitor Cm is the resting value Vrest, the pulse signal Vspike is low, the reset signal Vrfr is low, the inverted signal Vrfrb of the reset signal is high, transistor M1 is off, transistor M2 is on, and the voltage signal Vsr of the reset capacitor Csr is 0.
[0073] During inference operations in the spiking neural network (SNN), synaptic current Iin is injected into the membrane capacitor Cm. When the voltage across the membrane capacitor Cm rises above the specified threshold voltage Vth, the two inverters composed of transistors M2, M3, M4, and M5 in the pulse generation module 12 flip and emit pulses. The pulse signal Vspike rises from a low level to a high level. Similarly, in the reset signal generation circuit 13, the reset signal Vrfr rises from a low level to a high level (the voltage amplitude is equal to the power supply voltage V). DD The inverted signal Vrfrb of the reset signal Vrfr is pulled low from high level to low level, and the reset level conversion signal Vrfr 1s is raised from low level to high level (the voltage amplitude is the power supply voltage V). DD The following voltage (Vreset) is used. At this time, the adaptive isolation unit 111 composed of transistors M3 and M4 is turned off, transistor M1 is turned on, and the charge in the film capacitor Cm is transferred to the reset capacitor Csr. When the voltage Vsr across the reset capacitor Csr rises to a certain value, the gate-source voltage of transistor M1 cannot reach the threshold voltage Vthn of transistor M1, transistor M1 enters the cutoff region, and charge transfer stops. Therefore, by controlling the ratio of the capacitance values of the film capacitor Cm and the reset capacitor Csr, precise control of the amount of transferred charge can be achieved, thereby controlling the change of the voltage across the film capacitor Cm, i.e., the film potential Vm, retaining the charge exceeding the threshold, and realizing soft reset.
[0074] Among them, the amount of charge ΔQ discharged from the membrane capacitor Cm to the reset capacitor Csr and the change in membrane potential Vm ΔV n It satisfies the following formulas (1) and (2).
[0075] ΔQ=c sr (V reset -V thn (1)
[0076]
[0077] Among them, c m Let Cm be the capacitance value of the film capacitor, and c be the capacitance value of the film capacitor. sr This is the capacitance value of the reset capacitor Csr.
[0078] According to the soft reset circuit for simulating neurons disclosed herein, by utilizing the charging and discharging between the membrane capacitor and the reset capacitor and the switching control of the switching element, the discharge of the membrane capacitor to the reset capacitor can be controlled, thereby achieving the soft reset function of simulating neurons with extremely low power consumption, meeting the needs of large-scale neural networks.
[0079] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or aspects thereof) can be used in combination with each other. Furthermore, many modifications can be made to adapt particular situations or materials to the teachings of the various embodiments of this disclosure without departing from the scope of this disclosure. While the dimensions and types of materials described herein are used to define parameters of the various embodiments of this disclosure, the embodiments are not intended to be restrictive but are exemplary. Many other embodiments will become apparent to those skilled in the art upon reading the above description. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims and the full scope of their equivalents.
Claims
1. A soft reset circuit for simulating neurons, characterized in that, include: A membrane potential accumulation module, which includes a membrane capacitor, is used to accumulate input signals representing information input to neurons to generate membrane potential signals. A pulse generation module receives the membrane potential signal from the membrane potential accumulation module and generates a pulse signal based on whether the membrane potential signal exceeds a predetermined threshold voltage. A reset signal generation module receives the pulse signal from the pulse generation module and generates a reset signal with a pulse width greater than or equal to the pulse signal based on the pulse signal. and A soft reset module includes a reset capacitor connected in series with the membrane capacitor, a first switching element connected between the membrane capacitor and the reset capacitor, and a second switching element connected in parallel with the reset capacitor. The soft reset module receives the reset signal from the reset signal generation module. When the reset signal is at the first level, the soft reset module turns off the first switching element and turns on the second switching element. When the reset signal is at the second level, the soft reset module turns on the first switching element and turns off the second switching element, thereby causing the membrane capacitor to discharge to the reset capacitor. When the voltage across the reset capacitor exceeds a specified value, the first switching element is turned off, stopping the discharge of the membrane capacitor.
2. The soft reset circuit for simulating neurons as described in claim 1, characterized in that, The membrane potential accumulation module also includes an adaptive isolation unit. The adaptive isolation unit is turned on when the reset signal is at the first level, providing the membrane potential signal to the input terminal of the pulse generation module, and turned off when the reset signal is at the second level, isolating the membrane potential signal from the input terminal of the pulse generation module.
3. The soft reset circuit for simulating neurons as described in claim 2, characterized in that, The adaptive isolation unit is a transmission gate structure.
4. The soft reset circuit for simulating neurons as described in claim 2, characterized in that, It also includes a resting potential reset module, which resets the input terminal of the pulse generation module to the resting potential when the reset signal is at the second level.
5. The soft reset circuit for simulating neurons as described in any one of claims 1 to 4, characterized in that, The reset signal generation module receives a bias voltage signal from the outside and adjusts the pulse width of the reset signal based on the bias voltage signal.
6. The soft reset circuit for simulating neurons as described in any one of claims 1 to 4, characterized in that, The soft reset module further includes a reset level conversion unit, which generates a reset level conversion signal with a voltage amplitude below the power supply voltage based on the reset signal and provides it to the first switching element.
7. The soft reset circuit for simulating neurons as described in any one of claims 1 to 4, characterized in that, The membrane potential accumulation module also includes a leakage unit, which, when there is no input signal, uses a leakage voltage signal received from the outside to leak the membrane potential signal to the resting potential.
8. The soft reset circuit for simulating neurons as described in any one of claims 1 to 3, characterized in that, The ratio of the capacitance values of the membrane capacitor to the reset capacitor is determined based on the amount of charge that the membrane capacitor needs to discharge to the reset capacitor.