Semiconductor device

Abstract

A semiconductor device includes: a substrate; a transistor structure located on the substrate; an interlayer insulating layer covering the transistor structure; and a wiring structure located on the interlayer insulating layer, wherein the wiring structure includes: a plurality of wiring layers spaced apart from each other in a first direction, wherein the first direction is parallel to a surface of the substrate; a separator structure located between pairs of adjacent wiring layers in the plurality of wiring layers, wherein the separator structure includes a lower separator pattern and an upper separator pattern, wherein the upper separator pattern is located above the lower separator pattern; and a contact passage located on a first wiring layer in the pairs of adjacent wiring layers, wherein the upper surface of the lower separator pattern includes a recessed region curved toward the upper surface of the interlayer insulating layer, and wherein the upper separator pattern is located within a recess formed by the recessed region.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] Semiconductor devices include integrated circuits composed of MOS field-effect transistors (FETs). As the size of semiconductor devices continues to shrink and design rules become increasingly restrictive, the scaling down of MOS FETs and signal wiring is also accelerating. However, as the size of MOS FETs and signal wiring shrinks, the operating characteristics of semiconductor devices may degrade. Therefore, various methods are being investigated to overcome the challenges of semiconductor device integration and to fabricate semiconductor devices with superior performance. Summary of the Invention

[0003] Some aspects of this disclosure provide semiconductor devices with improved reliability.

[0004] A semiconductor device according to some embodiments may include: a substrate; a transistor structure located on the substrate; an interlayer insulating layer covering the transistor structure; and a wiring structure located on the interlayer insulating layer, wherein the wiring structure includes: a plurality of wiring layers spaced apart from each other in a first direction, wherein the first direction is parallel to a surface of the substrate; a separation structure located between pairs of adjacent wiring layers in the plurality of wiring layers, wherein the separation structure includes a lower separation pattern and an upper separation pattern, wherein the upper separation pattern is located above the lower separation pattern; and a contact passage located on a first wiring layer in the pair of adjacent wiring layers, wherein the upper surface of the lower separation pattern includes a recessed region curved toward the upper surface of the interlayer insulating layer, and wherein the upper separation pattern is located within a recess formed by the recessed region.

[0005] A semiconductor device according to some embodiments may include: a substrate; a transistor structure located on the substrate; an interlayer insulating layer covering the transistor structure; and a wiring structure located on the interlayer insulating layer, wherein the wiring structure includes: a plurality of wiring layers spaced apart from each other in a first direction, wherein the first direction is parallel to a surface of the substrate; a separator structure located between pairs of adjacent wiring layers; an air gap located between the interlayer insulating layer and the separator structure; and an insulating pad located between the air gap and the separator structure, wherein the surface of the insulating pad in contact with the air gap is at the same height as or higher than the upper surface of the first wiring layer in the pair of adjacent wiring layers.

[0006] A semiconductor device according to some embodiments may include: a substrate; a transistor structure located on the substrate; a first interlayer insulating layer covering the transistor structure; and a wiring structure located on the first interlayer insulating layer, wherein the wiring structure includes: a plurality of wiring layers spaced apart from each other in a first direction, wherein the first direction is parallel to a surface of the substrate; a separator structure located between pairs of adjacent wiring layers in the plurality of wiring layers, wherein the separator structure includes a lower separator pattern and an upper separator pattern located on the lower separator pattern, and wherein the upper surface of the separator structure is at a height higher than the upper surface of the first wiring layer in the pair of adjacent wiring layers; an insulating pad covering the side surface and lower surface of the lower separator pattern; and a second interlayer insulating layer covering the first wiring layer. At least a portion of the upper surface and at least a portion of each of the upper surface and side surface of the partition structure; a contact path extending in the second interlayer insulation layer and electrically connected to the first wiring layer, wherein the width of the contact path along the first direction at a height higher than the upper surface of the partition structure is greater than the width of the first wiring layer along the first direction, and wherein the contact path covers at least a portion of the upper surface of the first wiring layer and at least a portion of the upper surface of the partition structure; and a barrier layer covering the side surface and lower surface of the contact path, wherein an air gap is located between the lower surface of the partition structure and the first interlayer insulation layer, wherein the upper surface of the lower partition pattern includes a recessed region, wherein the recessed region bends toward the upper surface of the first interlayer insulation layer, and wherein the upper partition pattern is located within a recess formed by the recessed region.

[0007] A method of manufacturing a semiconductor device according to some embodiments may include: forming a transistor structure on a substrate; forming an interlayer insulating layer covering the transistor structure; and forming a wiring structure on the interlayer insulating layer, wherein forming the wiring structure includes: forming wiring layers spaced apart from each other in a first direction parallel to a surface of the substrate; forming a partition structure between the wiring layers, the partition structure including a lower partition pattern and an upper partition pattern on the lower partition pattern; and forming contact vias on the wiring layers, wherein forming the partition structure includes forming a recessed region on the upper surface of the lower partition pattern that bends toward the upper surface of the interlayer insulating layer; and forming the upper partition pattern in the recessed region.

[0008] In the manufacturing method of the semiconductor device, forming the separation structure may include selectively forming the upper separation pattern on the lower separation pattern.

[0009] The method of manufacturing the semiconductor device may further include forming a hard mask pattern on the wiring layer, and wherein selectively forming the upper separator pattern on the lower separator pattern may further include forming a deposition prevention layer on the hard mask pattern.

[0010] In the manufacturing method of the semiconductor device, the interface between the lower surface of the upper separator pattern and the upper surface of the lower separator pattern may be located at a height higher than the upper surface of the wiring layer.

[0011] In the manufacturing method of the semiconductor device, the upper surface of the separator structure may be located at a height higher than the upper surface of the wiring layer.

[0012] The method of manufacturing the semiconductor device may further include forming an air gap between the interlayer insulating layer and the separation structure.

[0013] In the manufacturing method of the semiconductor device, forming the air gap may include forming a sacrificial layer between the wiring layers, forming an insulating pad on the sacrificial layer, and removing the sacrificial layer.

[0014] In the manufacturing method of the semiconductor device, the surface of the insulating pad that contacts the air gap may be located at a height equal to or higher than the upper surface of the wiring layer.

[0015] Based on the above and / or other characteristics described herein, the reliability of semiconductor devices can be improved. Attached Figure Description

[0016] Figure 1 This is a cross-sectional view showing an example of a semiconductor device.

[0017] Figure 2 It is shown Figure 1 Enlarged cross-sectional view of region 'A'.

[0018] Figure 3 It is shown Figure 2 Enlarged cross-sectional view of region 'B'.

[0019] Figure 4 This is a cross-sectional view showing an example of a semiconductor device.

[0020] Figure 5 This is a cross-sectional view showing an example of a semiconductor device.

[0021] Figure 6 This is a cross-sectional view showing an example of a semiconductor device.

[0022] Figure 7 This is a cross-sectional view showing an example of a semiconductor device.

[0023] Figure 8 This is a cross-sectional view showing an example of a semiconductor device.

[0024] Figure 9 This is a cross-sectional view showing an example of a semiconductor device.

[0025] Figures 10 to 22 This is a process cross-sectional view illustrating an example of a semiconductor device manufacturing method.

[0026] Figures 23 to 30 This is a process cross-sectional view illustrating an example of a semiconductor device manufacturing method. Detailed Implementation

[0027] As will be understood by those skilled in the art, the examples described below can be modified in various ways without departing from the spirit or scope of this disclosure.

[0028] In the full text of the specification, descriptions of some well-known parts have been omitted, and the same reference numerals denote the same elements.

[0029] Furthermore, since the dimensions and thicknesses of the constituent components shown in the accompanying drawings can be arbitrarily given for better understanding and ease of description, this disclosure is not limited to the dimensions and thicknesses shown. In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity.

[0030] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there may be intermediate elements present. In contrast, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Furthermore, in the specification, the terms "on" or "above" refer to relative positioning and do not necessarily imply that it is located on the upper side of the object based on the direction of gravity.

[0031] In addition, unless explicitly stated otherwise, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply inclusion of the elements stated, but not to exclude any other elements.

[0032] Furthermore, in the instruction manual, the phrase "on a plane" means when viewing a portion of the object from above, and the phrase "on a cross section" means when viewing a cross section taken by vertically cutting the portion of the object from the side.

[0033] Figures 1 to 3 This is an accompanying drawing illustrating an example of a semiconductor device. In detail, Figure 1 This is a cross-sectional view showing an example of a semiconductor device. Figure 2 yes Figure 1 Enlarged cross-sectional view of region 'A'. Figure 3 yes Figure 2 Enlarged cross-sectional view of region 'B'.

[0034] First, refer to Figure 1 and Figure 2 The semiconductor device may include a transistor structure 100 located on a substrate 10 and a wiring structure 200 connected to the transistor structure 100. In some embodiments, the wiring structure 200 may include wiring layers 291, a separation structure 250 located between wiring layers 291, and contact passages 293 located on and connected to the wiring layers 291.

[0035] The substrate 10 may be silicon-on-insulator (SOI) or bulk silicon. As another example, the substrate 10 may be a silicon substrate, or may include other materials such as silicon germanium (SiGe), silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0036] The substrate 10 may include an upper surface and a lower surface. The upper and lower surfaces of the substrate 10 may be formed as planes parallel to a first direction D1 and a second direction D2 intersecting the first direction D1. The upper surface of the substrate 10 may be a surface opposite the lower surface of the substrate 10 in a third direction D3. The upper surface of the substrate 10 may be referred to as the front side. The lower surface of the substrate 10 may be referred to as the back side.

[0037] Transistor structure 100 may be located on substrate 10. Transistor structure 100 may include various microelectronic devices formed in a front-end (FEOL) process, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), system-on-large-scale integration (LSI), image sensors such as CMOS imaging sensors (CIS), microelectromechanical systems (MEMS), active components, passive components, etc. For example, transistor structure 100 may include planar MOSFETs, FinFETs, multi-bridge channel field-effect transistors (MBCFETs), or three-dimensional stacked FETs (3DSFETs). Hereinafter, transistor structure 100 will be described as an example including MBCFETs, but the semiconductor device is not limited thereto. For example, in the semiconductor devices described herein, transistor structure 100 may include planar MOSFETs, FinFETs, or 3DSFETs.

[0038] The transistor structure 100 may include a channel pattern 140, a gate structure 160 surrounding the channel pattern 140, and source / drain patterns 150 located on both sides of the channel pattern 140.

[0039] The channel pattern 140 may be located on the upper surface of the substrate 10. The channel patterns 140 may be arranged to be spaced apart on the substrate 10 in a first direction D1. Each channel pattern 140 may have a sheet shape. Each channel pattern 140 may be a nanosheet with a thickness of a few nanometers along a third direction D3.

[0040] Channel pattern 140 provides a path for current to flow between source / drain patterns 150, as described below. (Reference) Figure 1 The channel pattern 140 is arranged between the source / drain pattern 150, allowing it to connect to the source / drain pattern 150. Figure 1 In the diagram, four channel patterns 140 are shown arranged at intervals on a third direction D3, but the number is not limited to this, and the number of channel patterns 140 stacked can be varied in various ways.

[0041] The channel pattern 140 may include a semiconductor material. For example, the channel pattern 140 may include group IV semiconductors, group III-V compound semiconductors, group II-VI compound semiconductors, etc., such as Si and Ge.

[0042] Gate structure 160 may be located on substrate 10. Gate structure 160 may extend on substrate 10 in a second direction D2. Gate structures 160 may be arranged to be spaced apart from each other in a first direction D1. Gate structure 160 may include sub-gate structure 161 and main gate structure 163.

[0043] The sub-gate structure 161 and the channel pattern 140 can be alternately stacked on the third-direction D3. Figure 1 In this design, three sub-gate structures 161 are depicted as being spaced apart on a third-direction D3, but the number of spaced-apart sub-gate structures 161 is not limited thereto. For example, gate structure 160 may include four sub-gate structures 161.

[0044] The sub-gate structure 161 may include a sub-gate electrode 161a and a sub-gate insulating layer 161b surrounding it. The sub-gate electrode 161a may be located on the substrate 10. A plurality of sub-gate electrodes 161a may be positioned spaced apart from each other on the substrate 10. The plurality of sub-gate electrodes 161a and a plurality of channel patterns 140 may be stacked alternately and repeatedly.

[0045] The sub-gate electrode 161a may include at least one of the following: metal, metal alloy, metal silicide, doped semiconductor material, conductive metal oxide, or conductive metal nitride. The sub-gate electrode 161a may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), and tungsten (W). Aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or at least one combination thereof, but not limited thereto.

[0046] The sub-gate insulating layer 161b can be positioned circumferentially along the plurality of channel patterns 140. The sub-gate insulating layer 161b can be inserted between the plurality of channel patterns 140 and the sub-gate electrode 161a. The sub-gate insulating layer 161b can include various insulating materials.

[0047] The sub-gate insulating layer 161b is depicted as a single film, but its structure is not limited to this. For example, the sub-gate insulating layer 161b may consist of multiple layers including silicon oxide (SiO2) and a high-dielectric-constant material. The high-dielectric-constant material may include materials with a higher dielectric constant than silicon oxide (SiO2), such as hafnium oxide (HfO) and aluminum oxide (AlO2). x ) or tantalum oxide (TaO).

[0048] The main gate structure 163 may be located above the sub-gate structure 161 and the plurality of channel patterns 140. The main gate structure 163 may be located on the upper surface of the uppermost channel pattern 140 among the plurality of channel patterns 140.

[0049] The main gate structure 163 may include a main gate electrode 163a and a main gate insulating layer 163b.

[0050] The main gate electrode 163a may be located on the sub-gate structure 161 and a plurality of channel patterns 110a, 110b, 110c, 110d. At least a portion of the main gate electrode 163a may be located on a structure in which the sub-gate electrode 161a and the plurality of channel patterns 110a, 110b, 110c, 110d are alternately stacked. The remaining portion of the main gate electrode 163a may cover the sides of the structure in which the sub-gate electrode 161a and the plurality of channel patterns 110a, 110b, 110c, 110d are alternately stacked. Each of the plurality of channel patterns 110a, 110b, 110c, 110d may be surrounded by the sub-gate electrode 161a and / or the main gate electrode 163a.

[0051] The main gate electrode 163a may include the same material as the sub-gate electrode 161a. For example, the main gate electrode 163a may include at least one of a metal, a metal alloy, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal nitride.

[0052] The main gate insulating layer 163b may extend along the side of the main gate electrode 163a. ​​The main gate insulating layer 163b may extend along the side of the gate spacer 142 described below. The main gate insulating layer 163b may comprise various insulating materials. The main gate insulating layer 163b may comprise the same material as the sub-gate insulating layer 161b.

[0053] The main gate insulating layer 163b is depicted as a single film, but its structure is not limited to this. For example, the main gate insulating layer 163b may consist of multiple layers including silicon oxide (SiO2) and a high dielectric constant material. The high dielectric constant material may include materials with a higher dielectric constant than silicon oxide (SiO2), such as hafnium oxide (HfO) and aluminum oxide (AlO2). x ) or tantalum oxide (TaO).

[0054] The transistor structure 100 may also include a capping layer 141 and a gate spacer 142.

[0055] Gate spacer 142 may be located on the side of main gate electrode 163a. ​​Gate spacer 142 may be located above channel pattern 140. Gate spacer 142 may not be located on the side surface of sub-gate electrode 161a. Gate spacer 142 may not be located on each side of channel pattern 140. Gate spacer 142 may not be located between multiple channel patterns 140. Gate spacer 142 may not be located between multiple adjacent channel patterns 140 on third-direction D3. Gate spacer 142 is described as a single layer, but this is only for better understanding and ease of description, and its structure is not limited thereto.

[0056] Gate spacer 142 may include, for example, silicon nitride (SiN). X At least one of the following: silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbon oxynitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbon oxynitride (SiOC), or combinations thereof.

[0057] The capping layer 141 may be located on the main gate structure 163 and the gate spacer 142. In some embodiments, the capping layer 141 may also be located between the gate spacers 142.

[0058] The capping layer 141 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), or combinations thereof.

[0059] Source / drain patterns 150 may be located on the upper surface of substrate 10. Channel patterns 140 and gate structures 160 may be located between source / drain patterns 150. Multiple source / drain patterns 150 and multiple channel patterns 140 may be arranged alternately along a first direction D1.

[0060] The source / drain pattern 150 can be located on either side of the channel pattern 140 or the sub-gate structure 161. The two source / drain patterns 150 can be arranged spaced apart in the first direction D1, with the channel pattern 140 and / or the sub-gate structure 161 located between the two source / drain patterns 150. The source / drain pattern 150 can be in direct contact with the channel pattern 140 or the sub-gate structure 161. The source / drain pattern 150 can be in direct contact with the sub-gate insulating layer 161b of the sub-gate structure 161.

[0061] The source / drain pattern 150 may consist of an epitaxial layer formed by selective epitaxial growth (SEG). The source / drain pattern 150 may be formed by removing at least some regions of the channel pattern stacked on the substrate 10 and then selectively epitaxially growing material in the corresponding regions.

[0062] The source / drain pattern 150 may include a semiconductor material. The source / drain pattern 150 may include, for example, silicon (Si) or germanium (Ge). As another example, the source / drain pattern 150 may include a binary or ternary compound comprising, for example, carbon (C), silicon (Si), germanium (Ge), or tin (Sn). For example, the source / drain pattern 150 may include silicon (Si), silicon-germanium (SiGe), germanium (Ge), silicon carbide (SiC), etc., but is not limited thereto.

[0063] The semiconductor device may also include an interlayer insulating layer 177, a contact electrode 191, and a contact passage 193.

[0064] The interlayer insulating layer 177 may cover the source / drain pattern 150, the gate structure 160, the capping layer 141, and the gate spacer 142.

[0065] Interlayer insulation layer 177 may include an insulating material. Interlayer insulation layer 177 may include at least one of, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a low dielectric constant material. Low dielectric constant materials include, for example, tetraethyl fluorinated orthosilicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), tonil silazane (TOSZ), fluorosilicate glass (FSG), polyimide nanofoams such as polypropylene oxide, carbon-doped silica (CDO), organosilicon glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica dry gel, mesoporous silica, or combinations thereof, but are not limited thereto.

[0066] Contact electrode 191 may be located on source / drain pattern 150. Contact passage 193 may be located on contact electrode 191. Contact passage 193 may be connected to wiring structure 200, which will be described later. Contact electrode 191 and contact passage 193 are connected to source / drain pattern 150 and may provide externally supplied electrical signals or power supply voltages to source / drain pattern 150.

[0067] The contact electrode 191 and the contact passage 193 may include at least one of metal, metal alloy, metal silicide, doped semiconductor material, conductive metal oxide or conductive metal nitride.

[0068] Wiring structure 200 may be located on interlayer insulating layer 177. Wiring structure 200 may include various wirings, pathways, and / or insulating layers formed in back-to-end (BEOL) processes. Wiring structure 200 may be used to apply electrical signals to transistor structure 100 or for internal signal routing. Wiring structure 200 may include wiring layers 291, separation structures 250 located between wiring layers 291, and contact pathways 293 located above wiring layers 291 and connected to wiring layers 291.

[0069] Wiring layer 291 may be located above transistor structure 100. Wiring layer 291 may be electrically connected to transistor structure 100. Wiring layer 291 may be electrically connected to transistor structure 100 through contact path 193 and contact electrode 191. Figure 1 and Figure 2 In this context, wiring layer 291 is described as being connected to source / drain pattern 150, but is not limited thereto. For example, wiring layer 291 can be connected to gate structure 160 via structures such as contact electrode 191 and contact passage 193.

[0070] At least a portion of the wiring layer 291 may have a line shape extending in one direction. For example, the wiring layer 291 may have a line shape extending in a second direction D2. In another cross-section, the wiring layer 291 may extend in a first direction D1.

[0071] The semiconductor device may include multiple wiring layers 291. The multiple wiring layers 291 may be positioned spaced apart from each other along a first direction D1. Each of the multiple wiring layers 291 may be applied with a different electrical signal. (Reference) Figure 1 and Figure 2 Although wiring layer 291 is depicted as being directly above interlayer insulation layer 177, in some embodiments, multiple other wiring layers may be located between wiring layer 291 and interlayer insulation layer 177.

[0072] Wiring layer 291 may include a conductive material. For example, wiring layer 291 may include at least one of a metal, a metal alloy, a conductive metal carbide, a conductive metal oxide, a conductive metal nitride, and a two-dimensional (2D) material. In some embodiments, wiring layer 291 may include a conductive material suitable for subtractive patterning processes, but is not limited thereto. For example, wiring layer 291 may include at least one of Ru, Al, W, Mo, Ti, Cr, or Ni. However, the material is not limited thereto, and wiring layer 291 may also include, for example, Cu.

[0073] The adhesive layer 281 may be located between the wiring layer 291 and the interlayer insulating layer 177 and / or between the wiring layer 291 and the contact passage 193. The adhesive layer 281 may be formed between the wiring layer 291 and the interlayer insulating layer 177 or between the wiring layer 291 and the contact passage 193 to enhance the adhesion of the wiring layer 291 to other layers during the process of forming the wiring layer 291. The adhesive layer 281 may include a conductive material. For example, the adhesive layer 281 may include TaN, TiN, WN, TaO, TiO, MnN, MnO, or combinations thereof, but is not limited thereto.

[0074] In some embodiments, the semiconductor device may not include the adhesive layer 281. In this case, the wiring layer 291 may contact the contact passage 193. The lower surface of the wiring layer 291 may contact the upper surface of the contact passage 193. In some embodiments, the wiring layer 291 may comprise the same material as the contact passage 193. In this case, the boundary between the wiring layer 291 and the contact passage 193 may not be discernible.

[0075] The first insulating pad 285 may be located on at least some areas of the side surface of the wiring layer 291 and at least some areas of the upper surface of the interlayer insulating layer 177. The first insulating pad 285 may be used to enhance the adhesion between the wiring layer 291 and other layers and to prevent oxidation of the wiring layer 291. In some embodiments, the first insulating pad 285 may comprise various insulating materials, such as silicon oxide (SiO2), silicon nitride (SiN2), etc. X ), silicon oxynitride (SiON) or silicon oxycarbonate (SiOC).

[0076] The partition structure 250 may be located between wiring layers 291. The partition structure 250 may include a lower partition pattern 251 and an upper partition pattern 253 located on the lower partition pattern 251. The partition structure 250 is located between two adjacent wiring layers 291, thereby physically and electrically separating the wiring layers 291 from each other.

[0077] In some embodiments, the upper surface of the separator 250 may be located at a height higher than the upper surface of the wiring layer 291. The upper surface of the separator 250 may be positioned further from the upper surface of the substrate 10 than the upper surface of the wiring layer 291. For example, the difference between the height of the upper surface of the separator 250 and the height of the upper surface of the wiring layer 291 may be greater than approximately 0 nm and less than or equal to approximately 10 nm. For example, the upper surface of the separator 250 may be located between the upper surface of the wiring layer 291 and the upper surface of the interlayer insulating layer 277, which will be described later. For example, refer to... Figure 3The ratio of the distance L2 between the height of the upper surface of the partition structure 250 and the height of the upper surface of the wiring layer 291 to the distance L1 between the upper surface of the wiring layer 291 and the upper surface of the interlayer insulation layer 277 can be greater than or equal to about 0.1 and less than or equal to about 0.5.

[0078] In some embodiments, the ratio of the maximum distance L3 between the upper and lower surfaces of the upper partition pattern 253 in the third direction D3 to the distance L2 between the height of the upper surface of the partition structure 250 and the height of the upper surface of the wiring layer 291 can be greater than or equal to about 0.3 and less than or equal to about 1.0.

[0079] In some embodiments, the separator structure 250 may have a "dielectric-on-dielectric (DoD)" structure. The separator structure 250 may include a lower separator pattern 251 and an upper separator pattern 253 located above the lower separator pattern 251.

[0080] The lower separator pattern 251 may be located on the interlayer insulating layer 177. In some embodiments, a portion of the lower separator pattern 251 may be in the horizontal direction (e.g., Figure 1 and Figure 2 The lower separator pattern 251 overlaps with the wiring layer 291 in either the first direction D1 or the second direction D2. In some embodiments, the upper surface of the lower separator pattern 251 may be located at a height higher than the upper surface of the wiring layer 291. In some embodiments, the lower surface of the lower separator pattern 251 may be located at a height between the upper and lower surfaces of the wiring layer 291.

[0081] refer to Figure 1 and Figure 2 Only some areas of wiring layer 291 can be in the horizontal direction (e.g., in Figure 1 and Figure 2 In the first direction D1 or the second direction D2, the upper and lower separating patterns 251 overlap, but are not limited thereto. In an embodiment, the air gap AG may be located between the lower separating pattern 251 and the interlayer insulating layer 177. This will be explained later.

[0082] In some embodiments, the lower separator pattern 251 may include a dishing region located on the upper surface (the upper surface may include a dishing region). The dishing region may be formed by polishing the upper surface of the lower separator pattern 251 under predetermined process conditions, for example, using a chemical mechanical polishing (CMP) process during the formation of the lower separator pattern 251. However, the manufacturing process is not limited to this, and the dishing region may be formed using various known etching, polishing, or photolithography processes. Reference Figure 1 and Figure 2The lower separator pattern 251 may have a shape, such as a concave shape, in which its upper surface curves toward the upper surface of the interlayer insulating layer 177. Compared to the two opposing lateral ends of the upper surface of the lower separator pattern 251, the central portion of the upper surface of the lower separator pattern 251 may be positioned closer to the upper surface of the interlayer insulating layer 177. The upper surface of the lower separator pattern 251 may have a surface profile in which the distance to the upper surface of the interlayer insulating layer 177, when viewed in cross-section, gradually decreases from both ends toward the center.

[0083] The lower separator pattern 251 may include an insulating material. For example, the lower separator pattern 251 may include silicon oxide (SiO2) or silicon nitride (SiN). X It may be at least one of silicon oxynitride (SiON) and silicon oxycarbide (SiOC). However, the material is not limited to this, and the lower partition pattern 251 may include various insulating materials.

[0084] In some embodiments, the separator 250 may further include a second insulating pad 257. The second insulating pad 257 may be located on at least some areas of the lower surface and side surfaces of the lower separator pattern 251. In some embodiments, the second insulating pad 257 may be used to form an air gap AG between the separator 250 and the interlayer insulation layer 177. The second insulating pad 257 may cover at least some areas of the lower surface and side surfaces of the lower separator pattern 251. The second insulating pad 257 may not be located on the upper surface of the lower separator pattern 251.

[0085] The second insulating pad 257 may comprise an insulating material. In some embodiments, the second insulating pad 257 may comprise a low-k material. For example, the second insulating pad 257 may comprise an insulating material having a lower dielectric constant than silicon oxide (SiO2). For example, the second insulating pad 257 may comprise aluminum oxide (Al2O3) or silicon carbide (SiOC). However, the material is not limited to these, and the second insulating pad 257 may comprise materials such as silicon oxide (SiO2), silicon nitride (SiN). X Various insulating materials, such as silicon oxynitride (SiON), may be used. In some embodiments, the separator 250 may not include the second insulating pad 257.

[0086] The upper dividing pattern 253 may be located on the lower dividing pattern 251. The upper dividing pattern 253 may fill the recessed area formed on the upper surface of the lower dividing pattern 251. In some embodiments, the upper dividing pattern 253 may be located within a recess formed by the recessed area. The upper dividing pattern 253 may have its lower surface facing downward (in the direction of downward). Figure 1 and Figure 2The upper partition pattern 253 has a convex shape (in the direction towards the upper surface of the interlayer insulating layer 177). Compared with the two opposite lateral ends of the lower surface of the upper partition pattern 253, the upper partition pattern 253 can position the central portion of the lower surface of the upper partition pattern 253 closer to the upper surface of the interlayer insulating layer 177.

[0087] The lower surface of the upper separating pattern 253 may have a surface profile in which the distance to the upper surface of the interlayer insulating layer 177, when viewed in cross section, gradually decreases from both ends toward the center.

[0088] In some embodiments, the lower surface of the upper separator pattern 253 may contact the upper surface of the lower separator pattern 251. In some embodiments, the interface between the lower surface of the upper separator pattern 253 and the upper surface of the lower separator pattern 251 may be located at a height higher than the upper surface of the wiring layer 291. In some embodiments, the interface between the lower surface of the upper separator pattern 253 and the upper surface of the lower separator pattern 251 may be located at substantially the same height as the upper surface of the wiring layer 291, or may be located at a height lower than the upper surface of the wiring layer 291. For example, the lowermost part of the entire interface between the lower surface of the upper separator pattern 253 and the upper surface of the lower separator pattern 251 may be located at substantially the same height as the upper surface of the wiring layer 291, or may be located at a height lower than the upper surface of the wiring layer 291.

[0089] In some embodiments, the upper surface of the upper dividing pattern 253 may have a flat shape. However, it is not limited to this, and the upper dividing pattern 253 may have an upwardly convex or downwardly convex shape.

[0090] In some embodiments, the upper dividing pattern 253 may be in the thickness direction (e.g., Figure 1 and Figure 2 The upper partition pattern 253 may overlap with the lower partition pattern 251 in the third direction (D3, such as the vertical direction), but may not overlap with the wiring layer 291 in the thickness direction. The upper partition pattern 253 may not be included in the area that overlaps with the wiring layer 291 in the direction perpendicular to the upper surface of the wiring layer 291.

[0091] In some embodiments, during the process of forming the upper separator pattern 253, the upper separator pattern 253 may be formed only on the upper surface of the lower separator pattern 251, and may not be formed in the region overlapping with the wiring layer 291 along the third direction D3. This may be due to process characteristics in which the upper separator pattern 253 is formed while filling the recessed region formed on the upper surface of the lower separator pattern 251 during the process of forming the upper separator pattern 253. For example, during the process of forming the upper separator pattern 253, the opposite lateral ends of the recessed region may prevent the upper separator pattern 253 from growing or being deposited beyond or substantially beyond the region overlapping with the lower separator pattern 251, the second insulating pad 257, and / or the first insulating pad 285 in the third direction D3, for example, preventing growth into the region overlapping with the wiring layer 291 in the third direction D3. Therefore, in some embodiments, the upper partition pattern 253 may be stably formed only in the region where it overlaps with the lower partition pattern 251, the second insulating pad 257 and / or the first insulating pad 285 along the third direction D3.

[0092] The upper separator pattern 253 may include an insulating material. For example, the upper separator pattern 253 may include silicon carbide (SiOC) or silicon oxide (SiO). X ), aluminum oxide (AlO) x ), alumina silicon (AlSiO) X ), hafnium oxide (HfO) X ) and zirconium oxide (ZrO) X At least one of the following. However, the material is not limited to this, and the upper partition pattern 253 may include silicon nitride (SiN). X Various insulating materials, including silicon oxynitride (SiON), may be used. In some embodiments, the upper separating pattern 253 may include an insulating material having a lower dielectric constant than silicon oxide (SiO2).

[0093] In some embodiments of the semiconductor device, an air gap AG may be located in at least a portion of the region between wiring layers 291. An air gap AG can refer to an empty space between one layer and another. For example, an air gap AG may comprise air or a gas used in the manufacturing process of the semiconductor device. Multiple wiring layers 291 may be positioned horizontally separated from each other by air gaps AG and / or separator structures 250 inserted therebetween. In some embodiments, a second insulating pad 257 may be located between the air gap AG and the lower separator pattern 251. Reference Figure 2 The surface of the second insulating pad 257 that contacts the air gap AG may be located at a lower height than the upper surface of the wiring layer 291. However, the arrangement is not limited to this, and the surface of the second insulating pad 257 that contacts the air gap AG may be located at a higher height than the upper surface of the wiring layer 291 or at substantially the same height.

[0094] refer to Figure 1 and Figure 2 The air gap AG can be located between the wiring layers 291 and between the separation structure 250 and the interlayer insulation layer 177. In some embodiments, the wiring layers 291 can at least partially overlap with the air gap AG in the horizontal direction.

[0095] In some embodiments, the air gap AG can have a lower permittivity compared to the insulating layer and the insulating pattern surrounding it, which includes one or more insulating materials. For example, the air gap AG can have a relatively low permittivity compared to the interlayer insulating layers 177 and 277, the insulating pads 257 and 285, and the separation structure 250. For example, the air gap AG can be filled with air, and the permittivity of air can be approximately 1. Semiconductor devices can internally include the air gap AG to reduce parasitic capacitance within the device and improve its electrical characteristics.

[0096] The semiconductor device may also include an etch stop layer 286 covering portions of the upper surface of the wiring layer 291 and the upper surface and side surfaces of the partition structure 250. The etch stop layer 286 prevents the wiring layer 291 and / or the partition structure 250 from being damaged by etchants or the like during the process of forming the contact path 293, which will be described later.

[0097] The etch stop layer 286 may cover the entire upper surface of the wiring layer 291. The etch stop layer 286 may cover at least a portion of the region of the separator structure 250 located at a height higher than the upper surface of the wiring layer 291. The etch stop layer 286 may cover the side surfaces of the separator structure 250 located at a height higher than the upper surface of the wiring layer 291. The etch stop layer 286 may cover at least a portion of the upper surface of the separator structure 250. The etch stop layer 286 may not be located in the region where the wiring layer 291 and the separator structure 250 overlap with the contact path 293 and the barrier layer 289 in the third direction D3. In some embodiments, the etch stop layer 286 may be omitted.

[0098] The etch stop layer 286 may include an insulating material. The etch stop layer 286 may include an insulating material that has etch selectivity relative to the interlayer insulating layer 277. In some embodiments, the etch stop layer 286 may include alumina (Al₂O₃). x (e.g., aluminum nitride (AlN), but not limited to these).

[0099] The semiconductor device may also include an interlayer insulating layer 277 covering the wiring layer 291 and the separation structure 250.

[0100] Interlayer insulation 277 may be located on wiring layer 291 and separator 250. Interlayer insulation 277 may cover the entire upper surface of wiring layer 291. (See reference) Figure 1 and Figure 2 The etch stop layer 286 can be inserted between the lower surface of the interlayer insulating layer 277 and the upper surface of the wiring layer 291.

[0101] Interlayer insulation layer 277 may cover at least a portion of the area of ​​separator 250 located at a height higher than the upper surface of wiring layer 291. Interlayer insulation layer 277 may cover the side surfaces of separator 250 located at a height higher than the upper surface of wiring layer 291. Interlayer insulation layer 277 may cover at least a portion of the upper surface area of ​​separator 250. (See reference) Figure 1 and Figure 2 The etch stop layer 286 can be inserted between the interlayer insulating layer 277 and the lower separator pattern 251 or between the interlayer insulating layer 277 and the upper separator pattern 253.

[0102] Interlayer insulating layer 277 may include an insulating material. For example, interlayer insulating layer 277 may include the same insulating material as interlayer insulating layer 177, but is not limited thereto. Interlayer insulating layer 277 may include, for example, silicon oxide (SiO2) or silicon nitride (SiN). x It is at least one of silicon oxycarbonate (SiOC), silicon oxynitride (SiON), or a low dielectric constant material.

[0103] Contact path 293 can be connected to wiring layer 291. For example, the semiconductor device may also include multiple wiring layers located above interlayer insulating layer 277. In some embodiments, contact path 293 can connect wiring layer 291 located below interlayer insulating layer 277 to at least one other wiring layer located on interlayer insulating layer 277.

[0104] Contact path 293 can penetrate a region of interlayer insulation layer 277. Contact path 293 can overlap with one or more regions of wiring layer 291 in the third direction D3. In some embodiments, the width of contact path 293 along the first direction D1 may not be constant. (See reference...) Figure 3The contact path 293 may have a first width W1 at a height lower than the upper surface of the partition structure 250, and a second width W2 at a height higher than the upper surface of the partition structure 250, which is wider than the first width W1. In some embodiments, the first width W1 may be substantially the same as the width of the wiring layer 291 along the first direction D1. In some embodiments, the second width W2 may be wider than the width of the wiring layer 291 along the first direction D1. In some embodiments, the contact path 293 may cover at least a portion of the upper surface of the wiring layer 291 and at least a portion of the upper surface of the partition structure 250. The upper surface of the edge of the partition structure 250 adjacent to the wiring layer 291 may be covered by the contact path 293.

[0105] like Figures 1 to 3 As shown, since the upper surface of the partition structure 250 is at a higher height than the upper surface of the wiring layer 291, the contact path 293 may include a bent portion or a stepped portion due to the width difference at the interface with the upper surface of the partition structure 250.

[0106] Contact path 293 may include a conductive material. For example, contact path 293 may include at least one of a metal, a metal alloy, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal nitride. For example, contact path 293 may include Cu, Al, Ru, Co, W, and Mo, or combinations thereof. However, the material is not limited to these, and contact path 293 may include various conductive materials.

[0107] The semiconductor device may also include a barrier layer 289 surrounding the contact path 293. For example, the barrier layer 289 may be located between the contact path 293 and the interlayer insulating layer 277, between the contact path 293 and the separator 250, and / or between the contact path 293 and the wiring layer 291. The barrier layer 289 may be in direct contact with the wiring layer 291, the separator 250, and the interlayer insulating layer 277. The barrier layer 289 may improve the adhesion properties between the contact path 293 and the interlayer insulating layer 277, between the contact path 293 and the separator 250, and / or between the contact path 293 and the wiring layer 291. The barrier layer 289 may prevent material included in the contact path 293 from diffusing into the interlayer insulating layer 277 and / or the separator 250. In some embodiments, at least some areas of the barrier layer 289 may be omitted. In some embodiments, the barrier layer 289 may not be located between the upper surface of the wiring layer 291 and the lower surface of the contact path 293.

[0108] The barrier layer 289 may include a conductive material. For example, the barrier layer 289 may include, but is not limited to, TaN, TiN, WN, TaO, TiO, MnN, MnO, or combinations thereof.

[0109] like Figures 1 to 3 As shown, since the upper surface of the partition structure 250 is at a higher height than the upper surface of the wiring layer 291, the surface of the contact path 293 adjacent to the upper surface of the partition structure 250 can be at a higher height than the surface of the contact path 293 adjacent to the upper surface of the wiring layer 291. In this case, compared to the case where the upper surface of the partition structure 250 and the upper surface of the wiring layer 291 are at the same height, the distance between the contact path 293 and its adjacent wiring layer (i.e., the wiring layer adjacent to the wiring layer connected to the contact path 293) is increased. In some embodiments, based on this positioning, edge placement error (EPE) in the patterning process can be reduced, thereby reducing process complexity, and time-dependent dielectric breakdown (TDDB) can be reduced, thereby improving the reliability of the semiconductor device.

[0110] Figure 4 This is a cross-sectional view showing an example of a semiconductor device. Figure 4 The semiconductor device shown has the same characteristics as Figures 1 to 3 The parts shown are the same or similar to many other parts, so the following description focuses on the differences from the previous description. Figure 4 The semiconductor device shown may differ from the previous semiconductor device in some respects, specifically in that it does not include the air gap AG described previously.

[0111] refer to Figure 4 In a semiconductor device, the separator structure 250 can be located between wiring layers 291. Specifically, with reference to... Figures 1 to 3 Compared to the described semiconductor device, the lower separator pattern 251 can be located in the air gap AG. Figures 1 to 3 The location of the semiconductor device. The semiconductor device may not include the second insulating pad 257 located on the side surface and the lower surface of the lower partition pattern 251.

[0112] refer to Figure 4 The lower surface of the lower separator pattern 251 may contact the upper surface of the interlayer insulating layer 177. In some embodiments, the lower separator pattern 251 may be located between wiring layers 291. In some embodiments, the wiring layer 291 may completely overlap with the lower separator pattern 251 in the horizontal direction (e.g., a first direction D1 or a second direction D2).

[0113] Figure 5 This is a cross-sectional view showing an example of a semiconductor device. Figure 5 The semiconductor device shown has many parts that are the same as or similar to those in the previous example, so the following description focuses on the differences from the previous example. Figure 5 The semiconductor device shown can be used in some aspects with Figures 1 to 4The implementation of the semiconductor device differs in some ways, specifically in that the lower separating pattern 251 includes two layers.

[0114] refer to Figure 5 In some embodiments, the lower dividing pattern 251 may include a first lower dividing pattern 251a and a second lower dividing pattern 251b located on the first lower dividing pattern 251a. The first lower dividing pattern 251a may be located in the air gap AG at the reference Figures 1 to 3 The location described is within the semiconductor device. In some embodiments, the upper surface of the first lower separator pattern 251a may contact the lower surface of the second lower separator pattern 251b. In some embodiments, the interface between the first lower separator pattern 251a and the second lower separator pattern 251b may be located between the upper and lower surfaces of the wiring layer 291. Figure 5 In the middle, the lower partition pattern 251 is depicted as consisting of two layers (i.e., the first lower partition pattern 251a and the second lower partition pattern 251b), but the lower partition pattern 251 may include three or more layers.

[0115] In some embodiments, the first lower separator pattern 251a may include an insulating material. In some embodiments, the first lower separator pattern 251a may have a lower dielectric constant compared to the second lower separator pattern 251b. In some embodiments, the first lower separator pattern 251a may include a low-k insulating material. For example, the first lower separator pattern 251a may include an insulating material having a lower dielectric constant than silicon oxide (SiO2). In some embodiments, the first lower separator pattern 251a may include Al2O3. However, the material is not limited to this, and the second insulating pad 257 may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). X Various insulating materials, such as silicon oxynitride (SiON).

[0116] Figure 6 This is a cross-sectional view showing an example of a semiconductor device. Figure 6 The semiconductor device shown has the same characteristics as the reference. Figures 1 to 5 The semiconductor devices described have many identical or similar parts, so the following description focuses on the differences between them. Figure 6 The semiconductor device shown may differ from some embodiments of the previously described examples in some respects, specifically in the location where the contact passage 293 is formed. For example, Figure 6 A semiconductor device in which the photomask was not precisely aligned during the process of etching a portion of the interlayer insulating layer 277 to form the contact path 293 can be shown.

[0117] refer to Figure 6The contact path 293 may cover only a portion of the upper surface of the wiring layer 291. In some embodiments, the contact path 293 may be located only on the upper surface of one of the two partition structures 250 located on either side of the wiring layer 291.

[0118] In some implementations, even if the contact path 293 is formed when the photomask is not precisely aligned above the substrate 10, the contact path 293 can be adequately separated from the adjacent wiring layer (i.e., another wiring layer adjacent to the wiring layer connected to the contact path 293) by the separation structure 250.

[0119] Figure 7 and Figure 8 This is a cross-sectional view showing an example of a semiconductor device. Figure 7 and Figure 8 The semiconductor device shown has the same characteristics as... Figures 1 to 6 The examples described have many parts that are the same or similar, so the following description focuses primarily on the differences from the previous examples. Figure 7 and Figure 8 The position of the air gap AG in the semiconductor device shown may differ from that in the previous example.

[0120] For example, such as Figure 7 and Figure 8 As shown, the air gap AG can overlap with the entire wiring layer 291 in the horizontal direction (e.g., the first direction D1 or the second direction D2).

[0121] refer to Figure 7 The surface of the second insulating pad 257 that contacts the air gap AG can be located on the same plane as the upper surface of the wiring layer 291. (See reference) Figure 8 The surface of the second insulating pad 257 that contacts the air gap AG can be located at a height higher than the upper surface of the wiring layer 291. Therefore, the air gap AG can overlap the entire area of ​​the wiring layer 291 in the horizontal direction (e.g., the first direction D1 or the second direction D2), thereby reducing the parasitic capacitance around the wiring layer 291 and thus improving the electrical characteristics of the semiconductor device.

[0122] Figure 9 This is a cross-sectional view showing an example of a semiconductor device. Figure 9 The semiconductor device shown has the same characteristics as... Figures 1 to 8 The examples described have many parts that are the same or similar, so the following description focuses on the differences from the previous examples. Figure 9 The semiconductor device shown may differ from some of the embodiments in the previous examples, specifically in that it also includes an insulating pattern 255 located above the interlayer insulating layer 177.

[0123] In some embodiments, the insulating pattern 255 may be located between wiring layers 291. (See reference...) Figure 9 The insulating pattern 255 may be located between the air gap AG and the interlayer insulation layer 177. The lower surface of the insulating pattern 255 may contact the interlayer insulation layer 177, and the upper surface may contact the air gap AG. The insulating pattern 255 may be formed by, but is not limited to, some of the insulating material included in the lower partition pattern 251 passing through the second insulating pad 257 and depositing on the interlayer insulation layer 177 during the process of forming the lower partition pattern 251.

[0124] The insulating pattern 255 may include an insulating material. In some embodiments, the insulating pattern 255 may include the same insulating material as the lower separating pattern 251, but is not limited thereto. The insulating pattern 255 may include, for example, silicon oxide (SiO2) or silicon nitride (SiN). X At least one of silicon oxynitride (SiON).

[0125] Figures 10 to 21 This is a cross-sectional view illustrating an example of a semiconductor device manufacturing method. Specifically, Figures 10 to 21 Is with Figure 1 The cross-sectional view corresponding to region 'A'. Figures 10 to 21 A process diagram showing an intermediate stage of the manufacturing process.

[0126] like Figure 10 As shown, multiple wiring layers 291 and a sacrificial layer 220 covering the wiring layers 291 can be formed on a substrate that has undergone a front-end (FEOL) process. The front-end (FEOL) process can be included in the reference... Figures 1 to 3 The steps described are forming a transistor structure 100, a contact electrode 191, and a contact path 193 on a substrate 10, and forming an interlayer insulating layer 177 covering them.

[0127] First, a conductive layer comprising a conductive material is deposited on an interlayer insulating layer 177 including contact pathways 193, and then the conductive layer is patterned to form an adhesive layer 281 and a wiring layer 291 located on the adhesive layer 281. In some embodiments, the conductive material deposited on the interlayer insulating layer 177 may include a conductive material suitable for a subtractive patterning process. For example, the conductive material may include at least one of Ru, Al, W, Mo, Ti, Cr, and Ni.

[0128] For example, a conductive layer comprising a conductive material can be deposited on the interlayer insulating layer 177, and a conductive layer such as... can be formed on portions of the conductive layer. Figure 10 The hard mask pattern 283a is shown. For example, the hard mask pattern 283a may include silicon nitride (SiN). X However, it is not limited to this.

[0129] Next, by using a hard mask pattern 283a as an etching mask to etch portions of the conductive layer formed on the interlayer insulating layer 177, a structure such as... Figure 10 The adhesive layer 281 and wiring layer 291 are shown. Following this, a first insulating pad 285 can be formed to conformally cover the top and side surfaces of the hard mask pattern 283a, the upper surface of the interlayer insulating layer 177, and the side surfaces of the adhesive layer 281 and wiring layer 291. Next, a sacrificial layer 220 can be completely deposited on the upper surface of the first insulating pad 285 and the upper surface of the interlayer insulating layer 177. At this time, the sacrificial layer 220 can be deposited to a height higher than the upper surface of the hard mask pattern 283a, such that the sacrificial layer 220 covers the entire area of ​​the adhesive layer 281, wiring layer 291, hard mask pattern 283a, and first insulating pad 285.

[0130] like Figure 11 As shown, a portion of the sacrificial layer 220 can be etched. For example, as... Figure 11 As shown, a portion of the sacrificial layer 220 can be etched such that the upper surface of the sacrificial layer 220 is located at a height between the upper and lower surfaces of the wiring layer 291. Therefore, the sacrificial layer 220 located in the region overlapping with the wiring layer 291 on the third direction D3 is completely etched, and the sacrificial layer 220 can be located in some regions between the wiring layers 291. The sacrificial layer 220 can be formed at the location where the air gap AG will be generated in subsequent processes.

[0131] In some implementations, the sacrificial layer 220 may have the same characteristics as... Figure 11 The thicknesses shown are of different types. For example, in Figure 11 In this embodiment, the sacrificial layer 220 is formed such that its upper surface is located between the upper and lower surfaces of the wiring layer 291; however, in some embodiments, the sacrificial layer 220 may be formed such that its upper surface is at the same height as the upper surface of the wiring layer 291. As another example, the sacrificial layer 220 may be formed such that its upper surface is located between the upper surface of the wiring layer 291 and the upper surface of the hard mask pattern 283a.

[0132] In some implementations, in the case of Figure 10 and Figure 11 In the process modification, the sacrificial layer 220 can be deposited from the beginning such that the upper surface of the sacrificial layer 220 is located at a specific height between the upper and lower surfaces of the wiring layer 291. For this purpose, a process can be added to form a deposition prevention layer (275, see below) on the upper surface of the first insulating pad 285, which will be described later. Figure 16 The first insulating pad 285 overlaps with the wiring layer 291 on the third-direction D3. In this case, it can be omitted as shown in the reference. Figure 11 The process described is for etching a portion of the sacrificial layer 220.

[0133] like Figure 12 As shown, a second insulating pad 257 can be formed on the sacrificial layer 220. The second insulating pad 257 can be formed to cover the upper surface of the sacrificial layer 220 formed between the wiring layers 291.

[0134] The second insulating pad 257 may cover the first insulating pad 285 located on the top and side surfaces of the hard mask pattern 283a. The second insulating pad 257 may cover the first insulating pad 285 located on a portion of the side region of the wiring layer 291.

[0135] The second insulating pad 257 may include an insulating material. The second insulating pad 257 may contain aluminum oxide (Al2O3). However, the material is not limited to this; the second insulating pad 257 may include materials such as silicon oxide (SiO2) or silicon nitride (SiN). X Various insulating materials, such as silicon oxynitride (SiON).

[0136] Next, as Figure 13 As shown, the sacrificial layer 220 located between the second insulating pad 257 and the interlayer insulating layer 177 can be removed. In some embodiments, the sacrificial layer 220 can be removed by various methods. For example, the sacrificial layer 220 can be decomposed by performing heat treatment (annealing), ultraviolet irradiation, or plasma treatment. However, the methods are not limited to these, and the sacrificial layer 220 can also be etched by wet etching or dry etching, for example. In some embodiments, the layers constituting the second insulating pad 257 can be formed with a sufficiently low density to allow the sacrificial layer 220 to decompose and be released during the process of removing the sacrificial layer 220. As the sacrificial layer 220 is removed, an air gap AG can be formed between the interlayer insulating layer 177 and the second insulating pad 257.

[0137] like Figure 14 As shown, an upper insulating layer 259 can be formed above the second insulating pad 257. The upper insulating layer 259 can cover the second insulating pad 257. (See reference) Figure 14 The upper insulating layer 259 may fill at least some areas between the plurality of wiring layers 291. The upper insulating layer 259 may be formed above the second insulating pad 257 between the plurality of wiring layers 291.

[0138] The upper insulating layer 259 may not be formed inside the air gap AG. During the process of depositing the upper insulating layer 259, the second insulating pad 257 can prevent the upper insulating layer 259 from penetrating into the air gap AG. In some embodiments, the second insulating pad 257 may be further pretreated, such as by heat treatment, before the upper insulating layer 259 is deposited, to prevent the upper insulating layer 259 from penetrating into the air gap AG.

[0139] like Figure 15 As shown, a portion of the upper insulating layer 259 located at a height higher than the upper surface of the hard mask pattern 283a can be removed to form the lower separating pattern 251. In some embodiments, the removal of the portion of the upper insulating layer 259 can be performed using a chemical mechanical polishing (CMP) process. The CMP process can be performed until the upper surface of the upper insulating layer 259 is at substantially the same height as the upper surface of the hard mask pattern 283a. In the CMP process, an etchant material with higher etch selectivity for the upper insulating layer 259 than that for the hard mask pattern 283a can be used. (See reference...) Figure 15 The portions of the first insulating pad 285 and the second insulating pad 257, which are located at a height higher than the upper surface of the hard mask pattern 283a, can be removed by chemical mechanical polishing together with the upper insulating layer 259.

[0140] In some embodiments, recessed regions DS can be formed on the upper surface of the lower separating pattern 251, the upper surface of the first insulating pad 285, and the upper surface of the second insulating pad 257 by a chemical mechanical polishing process. (See reference...) Figure 15 The lower separator pattern 251 may have a shape in which its upper surface curves toward the upper surface of the interlayer insulating layer 177. The upper surface of the lower separator pattern 251 may have a surface profile in which the distance from the upper surface of the interlayer insulating layer 177, when viewed in cross-section, becomes closer from both ends to the center.

[0141] In some embodiments, process variables of the chemical mechanical polishing process can be controlled to give the recessed region DS a predetermined depth. For example, the type and flow rate of the slurry used in the chemical mechanical polishing process, the process temperature, the process time, etc., can be adjusted to give the recessed region DS a predetermined depth. For example, the recessed region DS can have a depth greater than approximately one-third of the thickness of the hard mask pattern 283a. For example, the recessed region DS can have a depth shallower than the thickness of the hard mask pattern 283a. However, the depth is not limited to these, and the recessed region DS can be designed to have various depths.

[0142] like Figure 16 and Figure 17 As shown, the upper separator pattern 253 can be selectively formed over the lower separator pattern 251, the first insulating pad 285, and the second insulating pad 257. In some embodiments, the process of forming the upper separator pattern 253 can be performed by area-selective deposition (ASD). Area-selective deposition can be a process that selectively deposits a desired thin film on a specific area of ​​a substrate.

[0143] First, such as Figure 16As shown, a deposition prevention layer 275 can be formed on the hard mask pattern 283a. The deposition prevention layer 275 can be formed using a material that can be selectively deposited only on the surface of a specific film. The deposition prevention layer 275 can be formed using inhibitors such as, for example, self-assembled monolayers (SAMs) or small molecule inhibitors (SMIs). Figure 16 As shown, the deposition prevention layer 275 can be selectively formed only on the upper surface of the hard mask pattern 283a. The deposition prevention layer 275 may not be formed on the surface of the lower separating pattern 251, the surface of the first insulating pad 285, or the surface of the second insulating pad 257.

[0144] Next, as Figure 17 As shown, the upper partition pattern 253 can be selectively formed on the upper surface of the lower partition pattern 251, the upper surface of the first insulating pad 285, and the upper surface of the second insulating pad 257. In some embodiments, the upper partition pattern 253 may not be formed on the deposition prevention layer 275. In some embodiments, the semiconductor device may not include the first insulating pad 285 and the second insulating pad 257, in which case the upper partition pattern 253 may be selectively formed only on the lower partition pattern 251.

[0145] In some embodiments, the process of forming the upper separating pattern 253 can be performed using a precursor material that has no or very low chemical affinity to the surface of the deposited barrier layer 275, but has relatively high chemical affinity to the surface of the lower separating pattern 251, the surface of the first insulating pad 285, and the surface of the second insulating pad 257.

[0146] For example, the lower separator pattern 251, the first insulating pad 285, and the second insulating pad 257 may comprise silicon carbide (SiOC), in which case a precursor material with a higher chemical affinity for SiOC compared to the material included in the deposition barrier layer 275 can be used to perform the region-selective deposition process. In some embodiments, the upper separator pattern 253 may be selectively formed only on the lower separator pattern 251, the first insulating pad 285, and the second insulating pad 257 by a region-selective deposition process. In some embodiments, the upper separator pattern 253 may not be formed on the deposition barrier layer 275.

[0147] In some embodiments, the upper separator pattern 253 may fill the recessed region DS. In some embodiments, since the upper separator pattern 253 is formed by filling the recessed region DS formed to a predetermined depth, the recessed region DS can prevent the upper separator pattern 253 from growing or depositing beyond the region overlapping with the lower separator pattern 251 in the third direction D3 to the region overlapping with the wiring layer 291 in the third direction D3. Therefore, the upper separator pattern 253 can be stably formed only in the region overlapping with a specific pattern / layer (e.g., the lower separator pattern 251) along the third direction D3, for example, and may not overlap with the wiring layer 291.

[0148] like Figure 18 As shown, the deposition prevention layer 275 and the hard mask pattern 283a can be removed. The removal of the hard mask pattern 283a can be performed, for example, by a dry etching process. At this time, the upper region of the upper separating pattern 253 can also be partially removed. (See reference...) Figure 18 Following the dry etching process, the upper separating pattern 253 is depicted as having a flat shape on the upper surface, but the shape is not limited to this. In some embodiments, the removal of the hard mask pattern 283a can be performed by, for example, dry etching, wet etching, or cleaning processes.

[0149] By completely removing the hard mask pattern 283a, the upper surface of the wiring layer 291 can be exposed, and a step can be formed between the upper surface of the wiring layer 291 and the upper surface of the upper partition pattern 253.

[0150] like Figure 19 As shown, an etch stop layer 286 and an interlayer insulating layer 277 can be sequentially formed on the wiring layer 291, the separator structure 250, and the first insulating pad 285. First, the etch stop layer 286 can be conformally deposited on the upper surface of the wiring layer 291, the upper surface of the separator structure 250, and the side surface of the first insulating pad 285. Next, an interlayer insulating layer 277 that completely covers the etch stop layer 286 can be formed.

[0151] like Figure 20 As shown, portions of the interlayer insulating layer 277, including the portion overlapping the wiring layer 291 on the third direction D3, can be etched, and then portions of the etch stop layer 286 can be etched to form a recess RC exposing the upper surface of the wiring layer 291. Next, a barrier layer 289 can be conformally formed on the upper surface of the interlayer insulating layer 277 and on the lower and side surfaces inside the recess RC. The barrier layer 289 may include a conductive material. The barrier layer 289 can prevent the material included in the contact path 293 to be formed subsequently from diffusing into the interlayer insulating layer 277 and / or the separation structure 250. In some embodiments, the process of forming the barrier layer 289 may be omitted.

[0152] like Figure 21 and Figure 22 As shown, the interior of the recess RC can be filled with a conductive material to form a contact path 293. First, as... Figure 21 As shown, conductive material can be formed inside the recess RC and on the upper surface of the interlayer insulating layer 277. Afterward, a chemical mechanical polishing process is performed to remove portions of the contact passage 293 located at a height higher than the upper surface of the interlayer insulating layer 277, as well as portions of the barrier layer 289, thereby forming... Figure 22 The contact path 293 is shown.

[0153] The semiconductor device may include multiple wiring structures 200 stacked on a third-direction D3. For example, a wiring structure including wiring layers and interlayer insulating layers surrounding the wiring layers (see...) Figure 2 Another wiring structure is positioned on the 200). In this case, the contact path 293 included in the wiring structure 200 and the wiring layer included in the other wiring structure can be formed simultaneously. In this case, with reference Figure 21 and Figure 22 Depending on the content described, a chemical mechanical polishing process can be performed to retain the barrier layer 289 and the conductive material on the upper surface of the interlayer insulating layer 277. In this case, the conductive material and the barrier layer 289 retained on the upper surface of the interlayer insulating layer 277 can form part of another wiring structure located on the wiring structure 200.

[0154] Figures 23 to 30 This is a cross-sectional view illustrating an example of a semiconductor device manufacturing method. Specifically, Figures 23 to 30 Is with Figure 1 The cross-sectional view corresponding to region 'A' shows a method for manufacturing a semiconductor device according to an embodiment. Aspects of this method are... Figures 10 to 21 The methods are the same or similar in aspect, and will be referenced below. Figures 10 to 21 The comparison of semiconductor device manufacturing methods mainly describes the differences.

[0155] First, such as Figure 23 As shown, multiple wiring layers 291, a hard mask pattern 283a, a first insulating pad 285, a second insulating pad 257, and an upper insulating layer 259 can be formed on the interlayer insulating layer 177. In some embodiments, air gaps AG may be located in some areas between the wiring layers 291.

[0156] like Figure 24 As shown, a portion of the upper insulating layer 259, located at a height higher than the upper surface of the wiring layer 291, can be removed to form the lower separating pattern 251. (And...) Figure 15The manufacturing method shown is different; the upper surface of the wiring layer 291 can be used as a reference to remove the upper insulating layer 259, which is located at a height higher than the upper surface of the wiring layer 291, by a chemical mechanical polishing process. The hard mask pattern 283a located on the upper surface of the wiring layer 291 can also be removed during the chemical mechanical polishing process.

[0157] A chemical mechanical polishing (CMP) process can be performed until the upper surface of the upper insulating layer 259 is at substantially the same height as the upper surface of the wiring layer 291. In the CMP process, an etching material with higher etch selectivity for the upper insulating layer 259 and the hard mask pattern 283a compared to the wiring layer 291 can be used. (Reference) Figure 24 The portions of the first insulating pad 285 and the second insulating pad 257, which are located at a height higher than the upper surface of the wiring layer 291, as well as the hard mask pattern 283a, can be removed together by a chemical mechanical polishing process.

[0158] In some embodiments, recessed regions DS can be formed on the upper surface of the lower dividing pattern 251, the upper surface of the first insulating pad 285, and the upper surface of the second insulating pad 257 by a chemical mechanical polishing process.

[0159] Next, as Figure 25 and Figure 26 As shown, the upper partition pattern 253 can be selectively formed on the lower partition pattern 251, the first insulating pad 285, and the second insulating pad 257. In some embodiments, the process of forming the upper partition pattern 253 can be performed by a region-selective deposition process.

[0160] First, such as Figure 25 As shown, a deposition prevention layer 275 can be formed on the upper surface of the wiring layer 291. The deposition prevention layer 275 can be selectively formed only on the upper surface of the wiring layer 291. The deposition prevention layer 275 may not be formed on the surface of the lower separating pattern 251, the surface of the first insulating pad 285, and the surface of the second insulating pad 257.

[0161] Next, as Figure 26As shown, the upper partition pattern 253 can be selectively formed on the upper surface of the lower partition pattern 251, the upper surface of the first insulating pad 285, and the upper surface of the second insulating pad 257. In some embodiments, the upper partition pattern 253 can fill the recessed region DS. In some embodiments, the upper partition pattern 253 may not be formed above the deposition prevention layer 275. In some embodiments, the process of forming the upper partition pattern 253 can be performed using a precursor material that has no or relatively low chemical affinity to the surface of the deposition barrier layer 275, but has relatively high chemical affinity to the surfaces of the lower partition pattern 251, the first insulating pad 285, and the second insulating pad 257.

[0162] like Figure 27 As shown, a step can be formed between the partition structure 250 and the wiring layer 291 by removing a portion of the wiring layer 291. The removal of the wiring layer 291 can be performed, for example, by a dry etching process. In this case, the upper partition pattern 253 can be used as a hard mask. During the etching process of the wiring layer 291, some areas of the upper partition pattern 253 can also be removed.

[0163] like Figure 28 As shown, an etch stop layer 286 and an interlayer insulating layer 277 can be sequentially formed on the wiring layer 291, the separator structure 250, and the first insulating pad 285.

[0164] Next, as Figure 29 As shown, a portion of the interlayer insulating layer 277 is etched, including the portion overlapping the wiring layer 291 on the third direction D3, and then a portion of the etch stop layer 286 is etched to form a recess RC exposing the upper surface of the wiring layer 291. Next, a barrier layer 289 can be conformally formed on the upper surface of the interlayer insulating layer 277 and on the lower and side surfaces inside the recess RC.

[0165] Next, as Figure 30 As shown, a conductive material is formed inside the recess RC and on the upper surface of the interlayer insulating layer 277, and then a chemical mechanical polishing process is performed to remove a portion of the contact passage 293 located at a height higher than the upper surface of the interlayer insulating layer 277 and a portion of the barrier layer 289, thereby forming the contact passage 293.

[0166] While this disclosure contains numerous details of specific implementations, these should not be construed as limiting the scope of any claims that may be made. Certain features described in this disclosure in the context of a single implementation can also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation can also be implemented individually in multiple implementations or in any suitable sub-combination. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination can be removed from that combination in some cases, and the combination may be for sub-combinations or variations thereof.

[0167] Although examples have been described in detail above, the scope of this disclosure is not limited thereto, and various modifications and improvements made by those skilled in the art also fall within the scope of this disclosure.

Claims

1. A semiconductor device, the semiconductor device comprising: Substrate; A transistor structure located on the substrate; An interlayer insulating layer that covers the transistor structure; as well as A wiring structure located on the interlayer insulation layer. The wiring structure includes: A plurality of wiring layers, the plurality of wiring layers being spaced apart from each other in a first direction, wherein the first direction is parallel to the surface of the substrate; A separation structure located between pairs of adjacent wiring layers in the plurality of wiring layers, wherein the separation structure includes a lower separation pattern and an upper separation pattern, wherein the upper separation pattern is located above the lower separation pattern; and A contact path, the contact path being located on the first wiring layer of the pair of adjacent wiring layers. The upper surface of the lower separating pattern includes a recessed region that curves toward the upper surface of the interlayer insulating layer, and The upper dividing pattern is located within the recess formed by the recessed area.

2. The semiconductor device according to claim 1, wherein, The interface between the lower surface of the upper dividing pattern and the upper surface of the lower dividing pattern is located at a height higher than the upper surface of the first wiring layer.

3. The semiconductor device according to claim 1, wherein, The upper separating pattern and the paired adjacent wiring layers do not overlap each other in a direction perpendicular to the upper surface of the interlayer insulation layer.

4. The semiconductor device according to claim 1, wherein the semiconductor device further comprises an air gap located between the interlayer insulating layer and the separation structure.

5. The semiconductor device of claim 4, further comprising an insulating pad located between the air gap and the lower separation pattern.

6. The semiconductor device according to claim 5, wherein, The surface of the insulating pad that contacts the air gap is located at the same height as the upper surface of the first wiring layer or at a height higher than the upper surface of the first wiring layer.

7. The semiconductor device according to claim 1, wherein, The upper surface of the partition structure is located at a height higher than the upper surface of the first wiring layer.

8. The semiconductor device according to claim 1, wherein, (i) The difference between the vertical height of the upper surface of the first wiring layer and the vertical height of the upper surface of the separation structure is greater than 0 nm and less than or equal to 10 nm.

9. The semiconductor device according to claim 1, wherein, The contact path covers: At least a portion of the upper surface of the first wiring layer, and At least a portion of the upper surface of the partition structure.

10. The semiconductor device according to claim 1, wherein, The width of the contact path along the first direction at a height higher than the upper surface of the separator structure is greater than the width of the first wiring layer along the first direction.

11. The semiconductor device according to claim 1, wherein, The upper separating pattern comprises an insulating material with a dielectric constant lower than that of SiO2.

12. The semiconductor device according to claim 1, wherein, The upper separating pattern includes SiOC and SiO. X AlO X AlSiO X or ZrO X At least one of them.

13. The semiconductor device according to claim 1, wherein, The lower dividing pattern includes: A first lower dividing pattern, the first lower dividing pattern being located on the interlayer insulating layer; and The second lower dividing pattern is located between the first lower dividing pattern and the upper dividing pattern. The first lower dividing pattern comprises an insulating material with a dielectric constant lower than that of SiO2.

14. The semiconductor device according to claim 1, wherein, The paired adjacent wiring layers include at least one of Ru, W, or Mo.

15. The semiconductor device according to claim 1, wherein, (i) The ratio of the maximum distance between the upper surface of the upper partition pattern and the lower surface of the upper partition pattern in a vertical direction perpendicular to the upper surface of the interlayer insulation layer to (ii) the distance between the upper surface of the upper partition pattern and the upper surface of the first wiring layer is in the range of 0.3 to 1.

0.

16. A semiconductor device, the semiconductor device comprising: Substrate; A transistor structure located on the substrate; An interlayer insulating layer that covers the transistor structure; as well as A wiring structure located on the interlayer insulation layer. The wiring structure includes: A plurality of wiring layers, the plurality of wiring layers being spaced apart from each other in a first direction, wherein the first direction is parallel to the surface of the substrate; A separation structure, wherein the separation structure is located between pairs of adjacent wiring layers in the plurality of wiring layers; An air gap, the air gap being located between the interlayer insulation layer and the separation structure; and An insulating pad is located between the air gap and the partition structure. Wherein, the surface of the insulating pad that contacts the air gap is at the same height as or higher than the upper surface of the first wiring layer in the pair of adjacent wiring layers.

17. The semiconductor device according to claim 16, wherein: The dividing structure includes a lower dividing pattern and an upper dividing pattern, wherein the upper dividing pattern is located above the lower dividing pattern. The upper surface of the lower dividing pattern includes a recessed region, wherein the recessed region curves toward the upper surface of the interlayer insulating layer, and The upper dividing pattern is located within the recess formed by the recessed area.

18. The semiconductor device according to claim 17, wherein, The upper separating pattern and the paired adjacent wiring layers do not overlap in a direction perpendicular to the upper surface of the interlayer insulation layer.

19. The semiconductor device of claim 16, further comprising a contact passage located on and covering the first wiring layer: At least a portion of the upper surface of the first wiring layer, and At least a portion of the upper surface of the partition structure.

20. A semiconductor device, the semiconductor device comprising: Substrate; A transistor structure located on the substrate; A first interlayer insulating layer covers the transistor structure; as well as A wiring structure located on the first interlayer insulation layer. The wiring structure includes: A plurality of wiring layers, the plurality of wiring layers being spaced apart from each other in a first direction, wherein the first direction is parallel to the surface of the substrate; A partition structure is located between pairs of adjacent wiring layers in the plurality of wiring layers, wherein the partition structure includes a lower partition pattern and an upper partition pattern located on the lower partition pattern, and wherein the upper surface of the partition structure is located at a height higher than the upper surface of the first wiring layer in the pair of adjacent wiring layers; An insulating pad that covers the side and lower surfaces of the lower dividing pattern; A second interlayer insulating layer covers at least a portion of the upper surface of the first wiring layer, and at least a portion of each of the upper surface and side surface of the separation structure; A contact path extending in the second interlayer insulation layer and electrically connected to the first wiring layer, wherein the width of the contact path along the first direction at a height higher than the upper surface of the separator structure is greater than the width of the first wiring layer along the first direction, and wherein the contact path covers at least a portion of the upper surface of the first wiring layer and at least a portion of the upper surface of the separator structure; and A barrier layer covering the side and bottom surfaces of the contact path. The air gap is located between the lower surface of the partition structure and the first interlayer insulation layer. The upper surface of the lower dividing pattern includes a recessed area, wherein the recessed area curves toward the upper surface of the first interlayer insulating layer, and The upper dividing pattern is located within the recess formed by the recessed area.

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