Display device

Abstract

According to one aspect of this disclosure, a display device includes: a substrate, the substrate including a display area, a first non-display area surrounding the display area, a curved area extending from the first non-display area, and a second non-display area extending from the curved area; a first planarization layer disposed on the substrate in the first non-display area, the curved area, and the second non-display area; a plurality of connecting lines located on the first planarization layer in the first non-display area, the curved area, and the second non-display area; and a second planarization layer located on the plurality of connecting lines in the first non-display area, the curved area, and the second non-display area, and in cross-section, the plurality of connecting lines are configured to be closer to the substrate in the central portion of the curved area than at the boundary between the first non-display area or the second non-display area and the curved area.

Description

[0001] Cross-reference to related applications This application claims priority to Korean Patent Application No. 10-2024-0196863, filed with the Korean Intellectual Property Office on December 26, 2024, the disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device, and more particularly to a display device capable of minimizing cracks generated in curved regions. Background Technology

[0003] With the advent of the information age, the field of display devices that visually express electrical information signals has developed rapidly, and research continues to be conducted to improve the performance of various display devices, such as thinness, light weight, and low power consumption.

[0004] Representative display devices may include liquid crystal displays (LCDs), field emission displays (FEDs), electrowetting displays (EWDs), and organic light-emitting displays (OLEDs).

[0005] Electroluminescent displays, represented by organic light-emitting diodes (OLEDs), are self-emissive and therefore do not require a separate light source, unlike liquid crystal displays (LCDs). Consequently, electroluminescent displays can be manufactured with light weight and thin profiles. Furthermore, electroluminescent displays are expected to find applications in various fields due to their advantages not only in power consumption (due to low-voltage operation) but also in color reproduction, response speed, viewing angle, and contrast ratio (CR). Summary of the Invention

[0006] One objective of this disclosure is to provide a display device that minimizes damage to connecting wires caused by tensile stress in curved regions.

[0007] Another objective of this disclosure is to provide a display device that minimizes cracks generated in curved regions.

[0008] Another objective of this disclosure is to provide a low-power display device that improves its lifespan and reduces power consumption by enhancing the reliability of the display device.

[0009] The purpose of this disclosure is not limited to the above-described purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0010] According to one aspect of this disclosure, a display device includes: a substrate, the substrate including a display area, a first non-display area surrounding the display area, a curved area extending from the first non-display area, and a second non-display area extending from the curved area; a first planarization layer disposed on the substrate in the first non-display area, the curved area, and the second non-display area; a plurality of connecting lines located on the first planarization layer in the first non-display area, the curved area, and the second non-display area; and a second planarization layer located on the plurality of connecting lines in the first non-display area, the curved area, and the second non-display area, and in cross-section, the plurality of connecting lines are configured to be closer to the substrate in the central portion of the curved area than at the boundary between the first non-display area or the second non-display area and the curved area.

[0011] According to another aspect of this disclosure, a display device includes: a substrate, the substrate including a display area, a first non-display area surrounding the display area, a curved area extending from the first non-display area, and a second non-display area extending from the curved area; a first planarization layer, the first planarization layer being located on the substrate, and in the curved area, the first planarization layer thins as it moves from the first non-display area toward a central portion of the curved area, and thickens as it moves from the central portion of the curved area toward a second non-display area; a plurality of connecting lines, the plurality of connecting lines being located on the first planarization layer in the curved area, and in the curved area, the plurality of connecting lines being closest to the substrate in the central portion of the curved area; and a second planarization layer, the second planarization layer being located on the plurality of connecting lines in the curved area.

[0012] Further details of the exemplary embodiments are included in the detailed description and the accompanying drawings.

[0013] In the display device of this disclosure, damage to the connecting wires caused by tensile stress during bending is minimized.

[0014] In the display device disclosed herein, cracks generated in the bending region are minimized to improve the reliability of the display device.

[0015] In the display device according to this disclosure, cracks generated in the bending region are minimized to improve the reliability and service life of the display device, thereby realizing a low-power display device with reduced power consumption.

[0016] The effects of this disclosure are not limited to those illustrated above, and this specification includes many more effects. Attached Figure Description

[0017] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following specific embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic plan view of a display device according to exemplary embodiments of the present disclosure; Figure 2 This is a cross-sectional view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure; Figure 3 This is a cross-sectional view showing a bent state of a display device according to an exemplary embodiment of the present disclosure; Figure 4 It is along Figure 1 A sectional view taken along line IV-IV'; and Figure 5 This is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Detailed Implementation

[0018] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosure and scope of this disclosure.

[0019] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless expressly stated otherwise, any reference to the singular may include the plural.

[0020] Even without explicit explanation, components are interpreted as including a normal tolerance range.

[0021] When using terms such as “on,” “above,” “below,” and “beside” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “immediately” or “directly.”

[0022] When one element or layer is positioned "on" another element or layer, another layer or element can be directly inserted onto or between that other element.

[0023] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from others. Therefore, in the technical concept of this disclosure, the first component referred to below can be the second component.

[0024] Throughout the specification, the same reference numerals generally denote the same elements.

[0025] For ease of description, the dimensions and thickness of each component shown in the accompanying drawings are illustrated, and this disclosure is not limited to the dimensions and thickness of the components shown.

[0026] The features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole and may be linked and operated in various technical ways, and the embodiments may be performed independently or in association with each other.

[0027] This disclosure will be described in detail below with reference to the accompanying drawings.

[0028] Figure 1 This is a schematic plan view of a display device according to exemplary embodiments of the present disclosure. Figure 1 For ease of description, among the various components of the display device 100, only the display panel PN, multiple pads PAD, multiple connection lines LNK, multiple scan lines SL, and gate driver GD are shown.

[0029] Reference Figure 1 The display device 100 according to this disclosure includes a display panel PN, a plurality of pads PAD, a plurality of connection lines LNK, a plurality of scan lines SL and a gate driver GD.

[0030] The display panel PN is a panel used to display images to a user. The display panel PN may include light-emitting diodes (LEDs) for displaying images, driving elements for driving the LEDs, and wiring for transmitting various signals to the LEDs and driving elements. Therefore, the display panel PN may include a substrate for supporting various components of the display device 100.

[0031] Light-emitting diodes (LEDs) can be defined in different ways depending on the type of the display panel PN. For example, when the display panel PN is an organic light-emitting display panel PN, the LED can be an organic light-emitting diode that includes an anode, an organic light-emitting layer, and a cathode. For example, when the display panel PN is a liquid crystal display panel, the LED can be a liquid crystal display element. In the following text, even if the display panel PN is assumed to be an organic light-emitting display panel, the display panel PN is not limited to organic light-emitting display panels.

[0032] The display panel PN may include the display area AA and the non-display area NA.

[0033] The display area AA is the area in the display panel PN where the image is displayed. Within the display area AA, multiple sub-pixels SP, which constitute multiple pixels, and driving circuitry for driving the multiple sub-pixels SP can be provided.

[0034] Multiple sub-pixels (SPs) are the smallest units constituting the display area (AA), and light-emitting diodes (LEDs) can be disposed in each of the multiple sub-pixels (SPs). For example, an organic light-emitting diode (OLED) comprising an anode, an organic light-emitting layer, and a cathode can be disposed in each of the multiple sub-pixels (SPs), but is not limited thereto. Furthermore, the driving circuit for driving the multiple sub-pixels (SPs) can include driving elements and wiring. For example, the driving circuit can be constructed from thin-film transistors, storage capacitors, gate lines, and data lines, but is not limited thereto.

[0035] The non-display area NA is the area where no image is displayed. The non-display area NA may refer to the outer periphery of the display panel PN surrounding the display area AA. Various wiring and circuitry for driving the organic light-emitting diodes (OLEDs) of the display area AA are provided in the non-display area NA. For example, a gate driver (GD), a data driver, multiple connection lines (LNK), and multiple pads (PAD) may be provided in the non-display area. The non-display area NA where no image is displayed may be a border area, but the exemplary embodiments of this disclosure are not limited thereto.

[0036] The non-display area NA includes the first non-display area NA1, the curved area BA, and the second non-display area NA2.

[0037] The first non-display area NA1 is the area surrounding and extending from the display area AA. The curved area BA can extend from one side of the first non-display area NA1 and can be within the area formed by... Figure 1 The direction indicated by the arrow is curved. The second non-display area NA2 extends from the curved area BA and is located below the display area AA. Meanwhile, like the display panel PN, the substrate may include the display area AA, a first non-display area NA1 surrounding the display area AA, a curved area BA extending from the first non-display area NA1, and a second non-display area NA2 extending from the curved area BA.

[0038] The first non-display area NA1 is the area surrounding the curved area BA and the display area AA, and can be provided with multiple connection lines LNK such as gate connection line GLL, power connection line VLL, and data connection line DLL, as well as a gate driver GD. That is, the first non-display area NA1 is used to send signals from multiple pads PAD to the display area AA. When the display panel PN includes an irregular corner area, the first non-display area NA1 can have a shape corresponding to the shape of the display panel PN and the display area AA.

[0039] The gate driver GD supplies multiple scan signals to multiple scan lines SL based on multiple gate control signals supplied from the timing controller. Although in Figure 1 The diagram shows two gate drivers (GDs) spaced apart from each other on either side of the display panel PN, but the number of gate drivers (GDs) and their arrangement are not limited to this.

[0040] In the second non-display area NA2, multiple pads can be set. These pads include those that connect to various interconnects and flexible films or printed circuit boards.

[0041] The multiple pads (PADs) may include multiple first pads (PAD1), multiple second pads (PAD2), and multiple third pads (PAD3). The multiple first pads (PAD1) are located on both sides of the display panel (PN) in the second non-display area (NA2), and the multiple second pads (PAD2) are located in the center of the display panel (PN) in the second non-display area (NA2). For example, the multiple second pads (PAD2) may be located between the multiple first pads (PAD1), and the multiple third pads (PAD3) may be located between the multiple second pads (PAD2).

[0042] Multiple first pads PAD1 are electrically connected to multiple gate connection lines GLL in multiple connection lines LNK. The multiple gate connection lines GLL can be connection lines connected to gate driver GD.

[0043] Multiple second pads PAD2 are electrically connected to multiple power connection lines VLL in multiple connection lines LNK. These multiple power connection lines VLL can be connection lines that are set in the power supply line of the display area AA.

[0044] Multiple third pads (PAD3) are electrically connected to multiple data connection lines (DLLs) within multiple connection lines (LNK). These multiple data connection lines (DLLs) can be connection lines connected to data lines located in the display area (AA).

[0045] In the following text, we will refer to... Figure 2 The cross-sectional structure of the display area AA of the display device 100 is described in more detail.

[0046] Figure 2 This is a cross-sectional view showing a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0047] Reference Figure 2The display device 100 according to an exemplary embodiment of the present disclosure may include a substrate 110, a first buffer layer 111, a first thin film transistor TR1, a second thin film transistor TR2, a first gate insulating layer 112a, a first interlayer insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, a second interlayer insulating layer 113b, a first connection electrode CE1, a light-shielding layer LS, a first planarization layer 115a, a second planarization layer 115b, a second connection electrode CE2, a dam unit 116, a light-emitting diode 120, a packaging unit 117, and a touch sensing unit.

[0048] The substrate 110 is used to support and protect the components of the display device 100 disposed on the substrate 110.

[0049] The substrate 110 is a component used to support various components included in the display device 100, and may be formed of an insulating material. The substrate 110 may include a first substrate 110a, a second substrate 110b, and an insulating film 110c. The insulating film 110c may be disposed between the first substrate 110a and the second substrate 110b. As described above, the substrate 110 is constructed from the first substrate 110a, the second substrate 110b, and the insulating film 110c to suppress moisture penetration. For example, the first substrate 110a and the second substrate 110b may be polyimide (PI) substrates, and the insulating film 110c may be made of silicon nitride (SiN). x ) or silicon dioxide (SiO) x It is formed in single or multiple layers.

[0050] The insulating film 110c may include at least one patterned region. For example, the insulating film 110c may include an opening in the curved region BA.

[0051] A first buffer layer 111 is disposed on the substrate 110. The first buffer layer 111 is disposed below the first thin film transistor TR1 to delay the diffusion of moisture and oxygen that have penetrated into the substrate 110 to the first thin film transistor TR1.

[0052] The first buffer layer 111 may include a multi-buffer layer 111a and a display buffer layer 111b. The first buffer layer 111 may be formed from multiple layers including the multi-buffer layer 111a and the display buffer layer 111b. Therefore, even though the first buffer layer 111 may be referred to as a multi-buffer layer, the first buffer layer 111 may also be formed from a single layer or from multiple layers other than two layers, but is not limited thereto.

[0053] For example, the multi-buffer layer 111a can be made of amorphous silicon (a-Si), silicon nitride (SiN) x ) and silicon dioxide (SiO) x It can be formed in a single layer or multiple layers of any of the following, but is not limited thereto.

[0054] For example, the buffer layer 111b can be made of amorphous silicon (a-Si) or silicon nitride (SiN). x ) and silicon dioxide (SiO) x It can be formed in a single layer or multiple layers of any of the following, but is not limited thereto.

[0055] The first thin-film transistor TR1 can be disposed on the first buffer layer 111. The first thin-film transistor TR1 may include a first display layer A1, a first gate G1, a first source S1, and a first drain D1. Here, depending on the design of the pixel circuit, the first source S1 can be used as the first drain, and the first drain D1 can be used as the first source.

[0056] The first display layer A1 can be disposed on the first buffer layer 111 and overlap with the light-shielding layer LS. The first display layer A1 can contain amorphous silicon or polycrystalline silicon.

[0057] For example, the first display layer A1 may comprise low-temperature polycrystalline silicon (LTPS). For instance, polycrystalline silicon materials have high mobility (100 cm⁻¹). 2 ( / Vs or more), resulting in low power consumption and excellent reliability. Therefore, according to an exemplary embodiment, polycrystalline silicon material can be applied to the gate driver and / or multiplexer (MUX) of the driving element of the thin-film transistor for driving the display element, and also to the display layer A1 of the driving thin-film transistor of the display device 100, but is not limited thereto.

[0058] For example, depending on the characteristics of the display device 100, polycrystalline silicon material can also be used as the display layer A2 of the switching thin-film transistor. Amorphous silicon (a-Si) material is deposited on the first buffer layer 111, and a dehydrogenation process and a crystallization process are performed to form polycrystalline silicon, and the polycrystalline silicon is patterned to form the first display layer A1. Here, the first display layer A1 may include a first channel region in which a channel is formed when the first thin-film transistor TR1 is driven, and a first source region and a first drain region on both sides of the first channel region. The first source region refers to the portion of the first display layer A1 connected to the first source S1, and the first drain region refers to the portion of the first display layer A1 connected to the first drain D1. For example, the first source region and the first drain region can be formed by ion doping (impurity doping) of the first display layer A1. The first source region and the first drain region can be generated by doping ions into the polycrystalline silicon material, and the first channel region can refer to the portion in which no ions are doped and the polycrystalline silicon material remains.

[0059] The first gate insulating layer 112a can be disposed on the first display layer A1. It can be made of silicon nitride (SiN). x ) or silicon dioxide (SiO) xThe first gate insulating layer 112a may be formed by a single layer or multiple layers of the first gate insulating layer 112a. Contact holes may be formed in the first gate insulating layer 112a, through which the first source S1 and the first drain D1 of the first thin film transistor TR1 are respectively connected to the first source region and the first drain region of the first display layer A1 of the first thin film transistor TR1.

[0060] The first gate G1 of the first thin-film transistor TR1 and the first capacitor electrode C1 of the storage capacitor Cst can be disposed on the first gate insulating layer 112a.

[0061] At this time, the first gate G1 and the first capacitor electrode C1 can be formed by a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) or their alloys. The first gate G1 can be formed on the first gate insulating layer 112a and overlap with the first channel region of the first display layer A1 of the first thin film transistor TR1.

[0062] Based on the driving characteristics of the display device 100 and the structure and type of the thin-film transistor, the first capacitor electrode C1 can be omitted. The first gate G1 and the first capacitor electrode C1 can be formed using the same process. Furthermore, the first gate G1 and the first capacitor electrode C1 can be formed on the same layer using the same material.

[0063] The first interlayer insulating layer 113a can be disposed above the first gate insulating layer 112a, the first gate G1, and the first capacitor electrode C1. The first interlayer insulating layer 113a can be made of silicon nitride (SiN). x ) or silicon dioxide (SiO) x It may be composed of a single layer or multiple layers. In the first interlayer insulating layer 113a, contact holes may be formed for exposing the first source region and the first drain region of the first display layer A1 of the first thin film transistor TR1.

[0064] The second capacitor electrode C2 of the storage capacitor Cst can be disposed on the first interlayer insulating layer 113a. The second capacitor electrode C2 can be formed by a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or their alloys. The second capacitor electrode C2 can be formed on the first interlayer insulating layer 113a and overlap with the first capacitor electrode C1. Furthermore, the second capacitor electrode C2 can be formed of the same material as the first capacitor electrode C1. Based on the driving characteristics of the display device 100 and the structure and type of the thin-film transistor, the second capacitor electrode C2 can be omitted.

[0065] The second buffer layer 114 can be disposed on the first interlayer insulating layer 113a and the second capacitor electrode C2. The second buffer layer 114 can be made of silicon nitride (SiN). x ) or silicon dioxide (SiO) x It may be composed of a single layer or multiple layers. Contact holes may be formed in the second buffer layer 114 for exposing the first source region and the first drain region of the first display layer A1 of the first thin-film transistor TR1. Furthermore, contact holes may be formed in the second buffer layer 114 for exposing the second capacitor electrode C2 of the storage capacitor Cst.

[0066] The second buffer layer 114 can be formed from multiple layers, but is not limited to this.

[0067] The second display layer A2 of the second thin-film transistor TR2 can be disposed on the second buffer layer 114. Here, the second thin-film transistor TR2 may include the second display layer A2, the second gate insulating layer 112b, the second gate G2, the second source S2, and the second drain D2. Here, depending on the pixel circuit design, the second source S2 can be used as the drain, and the second drain D2 can be used as the source.

[0068] Furthermore, the second display layer A2 may include a second channel region in which a channel is formed when the second thin-film transistor TR2 is driven, and a second source region and a second drain region on both sides of the second channel region. The second source region may refer to the portion of the second display layer A2 connected to the second source S2, and the second drain region may refer to the portion of the second display layer A2 connected to the second drain D2.

[0069] The second display layer A2 can be formed of oxide semiconductor. Oxide semiconductor materials have a larger band gap than silicon materials, preventing electrons from jumping across the band gap in the off-state. Therefore, oxide semiconductor materials have a low cutoff current. Thus, a thin-film transistor including a display layer formed of oxide semiconductor can be used as a switching thin-film transistor that maintains a short on-time and a long off-time, but is not limited thereto. Based on the characteristics of the display device 100, it can be used as a driving thin-film transistor. Furthermore, due to the small cutoff current, the amplitude of the auxiliary capacitor can be reduced, making oxide semiconductor suitable for high-resolution display elements. For example, the second display layer A2 can be formed of metal oxide, and for example, it can be formed of various metal oxides such as indium gallium zinc oxide (IGZO). Here, the description assumes that the second display layer A2 of the second thin-film transistor TR2 is composed of IGZO among various metal oxides, but is not limited thereto. Therefore, the second display layer can be formed of another metal oxide such as indium zinc oxide (IZO), indium gallium tin oxide (IGTO), or indium gallium oxide (IGO) instead of IGZO.

[0070] The second display layer A2 can be formed by depositing a metal oxide on the second buffer layer 114, performing a heat treatment to stabilize it, and then patterning the metal oxide.

[0071] The second gate insulating layer 112b can be disposed on the entire substrate 110 including the second display layer A2. For example, it can be made of silicon nitride (SiN). x ) or silicon dioxide (SiO) x The second gate insulating layer 112b is formed by a single layer or multiple layers of ).

[0072] The second gate G2 can be disposed on the second gate insulating layer 112b.

[0073] The second gate G2 can be formed by a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) or their alloys.

[0074] For example, a metal material is formed on the second gate insulating layer 112b, a photoresist pattern is formed on the metal material, and then the photoresist pattern is used as a mask to wet etch the metal material to form the second gate G2. As a wet etchant for etching the metal material, a material or alloy thereof that selectively etches molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) constituting the metal material can be used, but not the insulating material.

[0075] The second interlayer insulating layer 113b can be disposed on the second gate insulating layer 112b and the second gate G2. Contact holes for exposing the first display layer A1 of the first thin-film transistor TR1 and the second display layer A2 of the second thin-film transistor TR2 can be formed in the second interlayer insulating layer 113b. For example, contact holes for exposing the first source region and the first drain region of the first display layer A1 of the first thin-film transistor TR1 can be formed in the second interlayer insulating layer 113b. Contact holes for exposing the second source region and the second drain region of the second display layer A2 of the second thin-film transistor TR2 can be formed in the second interlayer insulating layer 113b.

[0076] The second interlayer insulating layer 113b can be configured as silicon nitride (SiN). x ) or silicon dioxide (SiO) x ( ) a single layer or multiple layers.

[0077] The first connection electrode CE1, the first source S1 and the first drain D1 of the first thin film transistor TR1, and the second source S2 and the second drain D2 of the second thin film transistor TR2 can be disposed on the second interlayer insulating layer 113b.

[0078] The first connection electrode CE1 can be electrically connected to the second drain D2 of the second thin-film transistor TR2. Furthermore, the first connection electrode CE1 can be electrically connected to the second capacitor electrode C2 of the storage capacitor Cst through contact holes formed in the second buffer layer 114 and the second interlayer insulating layer 113b. In other words, the first connection electrode CE1 can be used to electrically connect the second capacitor electrode C2 of the storage capacitor Cst to the second drain D2 of the second thin-film transistor TR2.

[0079] Here, the first source S1 and the first drain D1 of the first thin film transistor TR1 can be connected to the first display layer A1 of the first thin film transistor TR1 through contact holes formed in the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114 and the second interlayer insulating layer 113b.

[0080] The second source S2 and the second drain D2 of the second thin-film transistor TR2 can be connected to the second display layer A2 through contact holes formed in the second interlayer insulating layer 113b.

[0081] The first connection electrode CE1, the first source S1 and the first drain D1 of the first thin film transistor TR1, and the second source S2 and the second drain D2 of the second thin film transistor TR2 can be formed from the same material using the same process.

[0082] For example, the first connection electrode CE1, the first source S1, and the first drain D1 of the first thin-film transistor TR1, and the second source S2 and the second drain D2 of the second thin-film transistor TR2 can be formed by a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or their alloys. For example, the first connection electrode CE1, the first source S1, and the first drain D1 of the first thin-film transistor TR1, and the second source S2 and the second drain D2 of the second thin-film transistor TR2 can be formed by a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but are not limited thereto.

[0083] The first connection electrode CE1 may be integrally formed with and connected to the second drain D2 of the second thin film transistor TR2, but is not limited thereto.

[0084] In the first thin-film transistor TR1 and the second thin-film transistor TR2, a light-shielding layer LS is disposed below the first display layer A1 and the second display layer A2, respectively. The light-shielding layer LS can be configured to overlap with the first display layer A1 and be located between the substrate 110 and the first buffer layer 111, and it can also be configured to overlap with the second display layer A2 and be located between the first interlayer insulating layer 113a and the second buffer layer 114. Therefore, the light-shielding layer LS can be insulated from the first display layer A1 and the second display layer A2.

[0085] The light-shielding layer LS can be formed of a metallic material with low light transmittance, and reflects light incident on the first display layer A1 and the second display layer A2 from below the second display layer A2. The light-shielding layer LS can block light incident on the first display layer A1 and the second display layer A2, and protect the first display layer A1 and the second display layer A2.

[0086] For example, the light-shielding layer LS can be referred to as a bottom shielding metal (BSM), but is not limited to this. Specifically, the light-shielding layer LS can be formed by a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) or their alloys, but is not limited to this.

[0087] The first planarization layer 115a may be disposed above the first connection electrode CE1, the first source S1 and the first drain D1 of the first thin film transistor TR1, the second source S2 and the second drain D2 of the second thin film transistor TR2, and the second interlayer insulating layer 113b.

[0088] The first planarization layer 115a may be an organic layer that planarizes and protects the upper parts of the first thin-film transistor TR1 and the second thin-film transistor TR2. For example, the first planarization layer 115a may be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0089] The second connection electrode CE2 can be disposed on the first planarization layer 115a. The second connection electrode CE2 can be connected to the second drain D2 of the second thin-film transistor TR2 through the contact holes of the first planarization layer 115a. The second connection electrode CE2 can be used to electrically connect the second thin-film transistor TR2 and the anode 121 to each other. The second connection electrode CE2 can be formed by a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) or their alloys.

[0090] The second planarization layer 115b may be disposed above the second connecting electrode CE2 and the first planarization layer 115a. For example, the second planarization layer 115b may be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0091] The light-emitting diode 120 can be disposed on the second planarization layer 115b. That is, the light-emitting diode 120 can be formed by an anode 121, a light-emitting layer 122, and a cathode 123.

[0092] The anode 121 can be disposed on the second planarization layer 115b. In this case, the anode 121 can be electrically connected to the second connecting electrode CE2 through a contact hole disposed in the second planarization layer 115b. The anode 121 can be formed of a metallic material.

[0093] When the display device 100 is a top-emitting type in which light emitted from the light-emitting diode 120 is emitted onto the substrate 110 on which the light-emitting diode 120 is disposed, the anode 121 may further include a transparent conductive layer and a reflective layer located on the transparent conductive layer. The transparent conductive layer may be formed of a transparent conductive oxide such as ITO or IZO, and the reflective layer may be formed of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or alloys thereof.

[0094] Dike unit 116 can be disposed on anode 121. Dike unit 116 includes dike layer 116a and spacer 116b.

[0095] The dam layer 116a can be configured to cover the end of the anode 121. The portion of the dam layer 116a corresponding to the light-emitting area of ​​the sub-pixel SP can be open. A portion of the anode 121 can be exposed through the open portion of the dam layer 116a (hereinafter referred to as the open area). In this case, the dam layer 116a can be made of an inorganic insulating material (such as silicon nitride (SiN)). x ) or silicon dioxide (SiO) x It may be formed from organic insulating materials (such as benzocyclobutene resin, acrylic resin or imide resin), but is not limited thereto.

[0096] Spacer 116b may be disposed on the embankment 116a. Spacer 116b serves to maintain a predetermined gap such that the mask does not contact the substrate during the fabrication process of the light-emitting layer 122 formed from organic materials. For example, spacer 116b may be made of an inorganic insulating material (such as silicon nitride (SiN)). x ) or silicon dioxide (SiO) x It may be formed from organic insulating materials (such as benzocyclobutene resin, acrylic resin or imide resin), but is not limited thereto.

[0097] The light-emitting layer 122 can be disposed in the opening region of the dam layer 116a and on its front side. Therefore, the light-emitting layer 122 can be disposed on the anode 121 exposed through the opening region of the dam layer 116a.

[0098] The light-emitting layer 122 may include multiple organic material layers. For example, the light-emitting layer 122 may include organic material layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Furthermore, when the light-emitting layer 122 emits white light, the light emitted from the light-emitting layer 122 can be converted into light of various colors through multiple color filters, but is not limited to these.

[0099] The cathode 123 can be disposed on the light-emitting layer 122. The cathode 123 supplies electrons to the light-emitting layer 122, therefore the cathode can be formed of a conductive material with a low work function. The cathode 123 can be formed as a single layer across multiple sub-pixels SP. That is, the cathodes 123 of multiple sub-pixels SP are connected and formed integrally.

[0100] For example, the cathode 123 may be formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO) or ytterbium (Yb) alloy, and may also include a metal doped layer, but is not limited thereto.

[0101] The packaging unit 117 can be located on the aforementioned light-emitting diode 120.

[0102] The packaging unit 117 may have a single-layer structure or a multi-layer structure. For example, the packaging unit 117 may include a first packaging layer 117a, a second packaging layer 117b, and a third packaging layer 117c.

[0103] At this point, the first encapsulation layer 117a and the third encapsulation layer 117c are formed by inorganic layers, and the second encapsulation layer 117b can be formed by organic layers. Among the first encapsulation layer 117a, the second encapsulation layer 117b, and the third encapsulation layer 117c, the second encapsulation layer 117b is the thickest and can be used as a planarization layer.

[0104] The first encapsulation layer 117a can be disposed on the cathode 123 and positioned adjacent to the light-emitting diode 120. The first encapsulation layer 117a can be formed of an inorganic insulating material to which low-temperature deposition can be performed. For example, it can be made of silicon nitride (SiN). x ), silicon dioxide (SiO) x The first encapsulation layer 117a is formed of silicon oxynitride (SiON) or aluminum oxide (Al2O3). The first encapsulation layer 117a is deposited in a low-temperature atmosphere, so that damage to the light-emitting layer 122, which contains organic materials that are susceptible to high-temperature atmospheres, can be suppressed during the deposition process.

[0105] The second encapsulation layer 117b can be formed to have an area smaller than that of the first encapsulation layer 117a. In this case, the second encapsulation layer 117b can be formed to expose both ends of the first encapsulation layer 117a. The second encapsulation layer 117b can serve as a buffer to reduce interlayer stress caused by bending of the display device and improve planarization performance.

[0106] For example, the second encapsulation layer 117b can be formed of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or siloxycarbon (SiOC). For example, the second encapsulation layer 117b can be formed by an inkjet printing method, but is not limited thereto.

[0107] The third encapsulation layer 117c can be formed above the substrate 110 on which the second encapsulation layer 117b is formed, to cover the upper and side surfaces of the second encapsulation layer 117b and the upper and side surfaces of the first encapsulation layer 117a. In this case, the third encapsulation layer 117c can minimize or block the penetration of external moisture or oxygen into the first and second encapsulation layers 117a and 117b. For example, it can be made of materials such as silicon nitride (SiN). x ), silicon dioxide (SiO) x The third encapsulation layer 117c is composed of inorganic insulating materials such as silicon oxynitride (SiON) or aluminum oxide (Al2O3).

[0108] The touch sensing unit can be disposed on the packaging unit 117. The touch sensing unit may include a touch electrode unit TE and a touch insulating layer. The touch electrode unit TE includes a touch sensor metal TS and a bridging metal BM. The touch insulating layer includes a touch buffer layer 118a, a touch interlayer insulating layer 118b and a touch planarization layer 118c.

[0109] For example, the touch buffer layer 118a can be disposed on the third encapsulation layer 117c, and the touch electrode unit TE can be disposed on the touch buffer layer 118a.

[0110] The touch electrode unit TE may include a touch sensor metal TS and a bridging metal BM located on different layers. The interlayer insulation layer 118b may be disposed between the touch sensor metal TS and the bridging metal BM.

[0111] The touch buffer layer 118a and the inter-layer insulating layer 118b can be configured to remove the step at the location where the touch electrode unit TE is disposed and to be electrically insulated. Therefore, the touch buffer layer 118a and the inter-layer insulating layer 118b can be formed of inorganic materials, and for example, can be made of silicon nitride (SiN). x ) or silicon dioxide (SiO) x It consists of a single layer or multiple layers.

[0112] A touch planarization layer 118c is disposed on the interlayer insulating layer 118b and the touch sensor metal TS. The touch planarization layer 118c can be an organic layer that planarizes and protects the upper part of the interlayer insulating layer 118b. For example, the touch planarization layer 118c can be formed from organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The touch electrode unit TE can be formed in a mesh type.

[0113] Figure 3 This is a cross-sectional view showing a bent state of a display device according to an exemplary embodiment of the present disclosure. Meanwhile, in Figure 3 For ease of description, only the substrate 110 of the display panel PN, the first planarization layer 115a, the multiple connecting lines LNK, the second planarization layer 115b and the dam unit 116, the polarizing plate POL, the micro-coating MCL, the back plate 130, the buffer strip 140 and the additional back plate 130A are shown in the components of the display device 100.

[0114] Reference Figure 1 and Figure 3 The display device 100 according to an exemplary embodiment of the present disclosure may include a polarizing plate POL and a micro-coating MCL disposed on a display panel PN, as well as a back plate 130, a buffer strip 140 and an additional back plate 130A disposed below the display panel PN.

[0115] Reference Figure 3 A polarizing plate POL is disposed on the display panel PN. The polarizing plate POL is disposed in the display area AA and the first non-display area NA1 of the display panel PN. The polarizing plate POL is disposed on the dam unit 116 in the first non-display area NA1. The polarizing plate POL selectively transmits light to reduce the reflection of external light incident on the display panel PN. Specifically, the display panel PN contains various metallic materials used in semiconductor elements, wiring, and organic light-emitting diodes. Therefore, external light incident on the display panel PN can be reflected from the metallic materials, potentially reducing the visibility of the display device 100 due to the reflection of external light. In contrast, when the polarizing plate POL is disposed, it suppresses the reflection of external light, thereby increasing the outdoor visibility of the display device 100. However, according to embodiments of the display device 100, the polarizing plate POL may be omitted, but is not limited thereto.

[0116] An adhesive layer can be disposed between the polarizer POL and the display panel PN. The adhesive layer can bond the polarizer POL and the display panel PN. Therefore, the adhesive layer can be formed as a transparent adhesive layer so that the image on the display panel PN is visible. For example, the adhesive layer can be formed of optically clear adhesive (OCA) or pressure-sensitive adhesive (PSA), but is not limited to these.

[0117] A backplate 130 is disposed below the display panel PN. The backplate 130 can be configured to support the display panel PN. For example, when the substrate 110 of the display panel PN is formed of a plastic material such as polyimide, due to its flexibility, a separate component may be needed to support the substrate. Therefore, a support substrate formed of glass is disposed below the substrate 110 to perform the manufacturing process of the display device 100, and the support substrate can be separated and released after the manufacturing process is completed. However, even after the support substrate is released, the component for supporting the substrate 110 is still necessary, so the backplate 130 for supporting the substrate 110 can be disposed below the display panel PN.

[0118] The back panel 130 may comprise a plastic material. For example, the back panel 130 may be formed from a plastic film made of a combination of polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), or polymers.

[0119] A buffer strip 140 is disposed below the back panel 130. The buffer strip 140 protects the components of the display device 100 from external impacts. That is, when an external force is applied, the buffer strip 140 is compressed to absorb the impact. Specifically, the buffer strip 140 may include multiple air bubbles, and the multiple air bubbles can effectively absorb the physical impact applied to the display device 100. For example, the buffer strip 140 may be formed of acrylic foam, but is not limited thereto.

[0120] The additional backplate 130A corresponds to the first non-display area NA1 and is located below the buffer strip 140.

[0121] The additional backplate 130A can enhance the rigidity of the second non-display area NA2 of the display panel PN. Simultaneously, the additional backplate 130A can be configured not to overlap with the curved area BA. Therefore, the thickness of the configuration disposed in the curved area BA can be minimized, and the neutral surface of the curved area BA can be easily controlled to ensure the flexibility of the curved area BA. The additional backplate 130A can be formed from the same material as the backplate 130. For example, the additional backplate 130A can comprise a plastic material and be formed by a plastic film formed from a combination of polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), or polymers, but is not limited thereto.

[0122] The adhesive layer can be disposed between the display panel PN and the back plate 130, between the back plate 130 and the buffer strip 140, and between the buffer strip 140 and the additional back plate 130A. The adhesive layer can bond the display panel PN, the back plate 130, the buffer strip 140, and the additional back plate 130A to each other. For example, the adhesive layer can be formed of optically clear adhesive (OCA) or pressure-sensitive adhesive (PSA), but is not limited thereto.

[0123] The second non-display area NA2 of the display panel PN is disposed below the additional back plate 130A. In addition, an adhesive layer is also disposed between the additional back plate 130A and the second non-display area NA2 of the display panel PN to bond the additional back plate 130A and the second non-display area NA2 of the display panel PN to each other.

[0124] The micro-coating MCL is disposed on the first non-display area NA1, the second non-display area NA2, and the bending area BA of the display panel PN. Since the multiple connecting lines LNK disposed on the substrate 110 are subjected to tensile stress during bending, causing micro-cracks, the micro-coating MCL can be formed by coating resin to a thin thickness at the bending location to protect the multiple connecting lines LNK. For example, the micro-coating MCL can be composed of resin, acrylic material, or polyurethane acrylate, but is not limited to these.

[0125] Multiple connection lines LNK are disposed in the curved region BA between the first planarization layer 115a and the second planarization layer 115b located on the substrate 110. In this case, the multiple connection lines LNK can be disposed on the first planarization layer 115a and positioned closest to the substrate 110 in the central portion of the curved region BA. That is, in cross-section, the multiple connection lines LNK are positioned closer to the substrate 110 in the central portion of the curved region BA than the boundary between the first non-display region NA1 or the second non-display region NA2 and the curved region BA. For example, the multiple connection lines LNK can be disposed in the curved region BA between... Figure 2 The second connecting electrode CE2 shown is formed on the same layer.

[0126] At this point, the curvature of the multiple connecting lines LNK in the central portion of the curved region BA can be less than the curvature at the boundary between the first non-display area NA1 or the second non-display area NA2 and the curved region BA. That is, within the curved region BA, the curvature of the multiple connecting lines LNK decreases as they approach the center of the curved region BA from the boundary of the first non-display area NA1, and increases as they approach the boundary of the second non-display area NA2 from the center of the curved region BA. Therefore, the curvature of the multiple connecting lines LNK is minimized in the central portion of the curved region BA relative to the boundary points of the first non-display area NA1 and the second non-display area NA2.

[0127] In the curved region BA, the first planarization layer 115a becomes thinner as it approaches the center of the curved region BA, starting from the first non-display region NA1, and the first planarization layer 115a becomes thicker as it approaches the second non-display region NA2, starting from the center of the curved region BA.

[0128] In the curved region BA, the second planarization layer 115b becomes thicker as it approaches the center of the curved region BA, starting from the first non-display region NA1, and thinner as it approaches the second non-display region NA2, starting from the center of the curved region BA, on the multiple connecting lines LNK.

[0129] A dam unit 116 is disposed on the second planarization layer 115b. In this case, the dam unit 116 can be disposed on the second planarization layer 115b and is thicker in the curved region BA than in the first non-display region NA1 or the second non-display region NA2. Therefore, the dam unit 116 can planarize and protect the upper part of the second planarization layer 115b in the curved region BA.

[0130] In the following text, we will refer to... Figure 4 The cross-sectional structure of the curved region BA of the display device 100 is described in more detail.

[0131] Figure 4 It is along Figure 1 The sectional view taken by line IV-IV', and Figure 4 This is a cross-sectional view showing the curved region BA of the display device 100 in its unfolded state according to an exemplary embodiment of the present disclosure. Figure 4 In the display device 100, only the following components are shown: substrate 110, first buffer layer 111, first gate insulating layer 112a, first interlayer insulating layer 113a, second buffer layer 114, second gate insulating layer 112b, second interlayer insulating layer 113b, first planarization layer 115a, second planarization layer 115b, multiple connection lines LNK, dam unit 116, touch buffer layer 118a, touch interlayer insulating layer 118b, touch planarization layer 118c, polarizing plate POL, and microcoating MCL.

[0132] Reference Figure 2 and Figure 4 In the display device 100 according to an exemplary embodiment of the present disclosure, a first planarization layer 115a, a plurality of connecting lines LNK, a second planarization layer 115b, a dam unit 116 and a micro-coating MCL are provided in the curved region BA extending from the first non-display region NA1 and the second non-display region NA2 of the display panel PN.

[0133] In the first non-display area NA1, the ends of the first buffer layer 111, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b are provided. Meanwhile, the first buffer layer 111, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b are likely to break during bending, therefore they are not provided in the bending area BA.

[0134] The multiple connecting lines LNK include the first connecting line LNK1 and the second connecting line LNK2.

[0135] In the first non-display area NA1, a first connecting line LNK1 is disposed on the second interlayer insulating layer 113b. The first connecting line LNK1 can be formed of the same material as one of the various conductive components formed in the display area AA. For example, the first connecting line LNK1 can be formed of the same material using the same process as the first connecting electrode CE1 on the second interlayer insulating layer 113b. That is, the first connecting line LNK1 can be formed of a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or their alloys. Furthermore, the second connecting line LNK2 can be formed of a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but is not limited thereto.

[0136] In the first non-display area NA1, a second connection line LNK2 is disposed on the first connection line LNK1 and the first planarization layer 115a. The second connection line LNK2 can be electrically connected to the first connection line LNK1 through the contact holes of the first planarization layer 115a.

[0137] The second connecting line LNK2 can be disposed along the curved region BA extending from the first non-display region NA1 to the second non-display region NA2. In this case, the height H1 of the second connecting line LNK2 from the substrate 110 at the boundary between the first non-display region NA1 and the curved region BA can be higher than the height H2 of the second connecting line LNK2 from the substrate 110 in the central portion of the curved region BA. That is, the height H2 of the second connecting line LNK2 from the substrate 110 in the central portion of the curved region BA is lower than the height H1 of the second connecting line LNK2 from the substrate 110 at the boundary between the first non-display region NA1 and the curved region BA. Therefore, in the central portion of the curved region BA, the second connecting line LNK2 can be positioned closest to the substrate 110.

[0138] At this point, the curvature of the multiple second connecting lines LNK2 in the central portion of the curved region BA can be less than the curvature at the boundary between the first non-display region NA1 or the second non-display region NA2 and the curved region BA. That is, in the curved region BA, the curvature of the second connecting lines LNK2 decreases as they approach the center of the curved region BA from the boundary of the first non-display region NA1, and the curvature increases as they approach the boundary of the second non-display region NA2 from the center of the curved region BA. Therefore, the curvature of the second connecting lines LNK2 can be minimized in the central portion of the curved region BA relative to the boundary points of the first non-display region NA1 and the second non-display region NA2. The second connecting lines LNK2 can be formed from the same material as one of the various conductive components formed in the display region AA. For example, the second connecting lines LNK2 can be formed from the same material using the same process as the second connecting electrode CE2 on the first planarization layer 115a. In other words, the second connecting line LNK2 can be formed by a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or their alloys. Furthermore, the second connecting line LNK2 can be formed by a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but is not limited to this.

[0139] Meanwhile, the neutral plane NP in the curved region BA can be located in the second substrate 110b of the substrate 110. Therefore, the second connecting line LNK2 can be configured to be closer to the neutral plane in the central portion of the curved region BA than at the boundary between the first non-display region NA1 or the second non-display region NA2 and the curved region BA.

[0140] In the curved region BA, a first planarization layer 115a is disposed on the substrate 110. At this time, starting from the first non-display region NA1, the thickness of the first planarization layer 115a decreases as it approaches the center of the curved region BA, and the thickness of the first planarization layer 115a increases as it approaches the second non-display region NA2 as it approaches the center of the curved region BA. That is, the thickness D1c of the first planarization layer 115a in the center of the curved region BA is less than the thickness D1a at the interface between the first non-display region NA1 and the curved region BA, and the thickness D1b at the interface between the second non-display region NA2 and the curved region BA. Therefore, in the center of the curved region BA, the second connecting line LNK2 can be positioned to be closest to the substrate 110 based on the thickness of the first planarization layer 115a.

[0141] Such a first planarization layer 115a can have a stepped shape in cross-section. For example, the first planarization layer 115a can be formed into a stepped shape using slit shapes and / or halftone masks. In this case, the steepness of the slope of the concave shape of the first planarization layer 115a can be adjusted according to the slit spacing of the mask, and the straightness can be smoothed using a halftone mask. For example, the smaller the slit spacing of the mask, the gentler the slope, and the larger the slit spacing, the steeper the slope. In this case, a flat surface is formed between the slopes using a halftone mask to form the stepped shape.

[0142] In the curved region BA, a second planarization layer 115b is disposed on the second connecting line LNK2. At this time, starting from the first non-display region NA1, the thickness of the second planarization layer 115b increases towards the center of the curved region BA, and the thickness decreases towards the second non-display region NA2. That is, the thickness D2c of the second planarization layer 115b in the center of the curved region BA is greater than the thickness D2a at the interface between the first non-display region NA1 and the curved region BA, and the thickness D2b at the interface between the second non-display region NA2 and the curved region BA. Therefore, in the center of the curved region BA, the second planarization layer 115b can be configured to fill the upper part of the second connecting line LNK2.

[0143] Reference Figure 4 A dam unit 116 is disposed on the second planarization layer 115b. In the curved region BA, the dam unit 116 planarizes the upper part of the second planarization layer 115b, thereby planarizing the entire upper part of the curved region BA on the substrate 110. At this time, the thickness of the dam unit 116 in the curved region BA can be greater than the thickness in the first non-display region NA1 or the second non-display region NA2. Therefore, the dam unit 116 can fill the upper part of the second planarization layer 115b in the curved region BA to completely planarize the upper part of the curved region BA.

[0144] When a substrate is bent to reduce the bezel area in a display device, it is necessary to ensure not only the flexibility of the substrate itself, but also the flexibility of the various insulating layers formed on the substrate and the connecting lines made of metallic materials. In the case of connecting lines, when the substrate is bent, stress concentrates on the connecting lines located in the bending area, causing cracks in the connecting lines. When a connecting line breaks, signals cannot be transmitted normally, causing thin-film transistors or light-emitting diodes to malfunction. Therefore, uniform bending stress acts on the bending area of ​​the display panel, leading to problems such as display panel damage or easy degradation of the display panel's quality.

[0145] Furthermore, when the display device is repeatedly heated and cooled, the components of the display panel expand and contract. If this process is repeated, stress is also generated on the display panel in the bending areas, which causes cracks to form in the display panel PN and results in defects in the display device due to these cracks.

[0146] In the display device 100 according to an exemplary embodiment of the present disclosure, in the bending region BA, a plurality of connecting lines LNK are arranged closer to the substrate 110 at the center portion of the bending region BA than at the interface between the bending region BA and the first non-display region NA1 or the second non-display region NA2. Therefore, damage to the connecting lines due to tensile stress during bending can be minimized.

[0147] Specifically, in the display device 100 according to an exemplary embodiment of the present disclosure, in the curved region BA, the first planarization layer 115a is thinner towards the center of the curved region BA, starting from the first non-display region NA1, and thicker towards the second non-display region NA2, starting from the center of the curved region BA. That is, in the curved region BA, the first planarization layer 115a is positioned closer to the substrate 110 in the center of the curved region BA than in either the first non-display region NA1 or the second non-display region NA2. Therefore, the second connection line LNK2 is disposed on the first planarization layer 115a and is closest to the substrate 110 in the center of the curved region BA. At this time, the neutral surface of the curved region BA is located in the substrate 110. Therefore, in the center of the curved region BA, the second connection line LNK2 is positioned close to the substrate 110 to minimize stress concentration due to bending. In the display device 100 according to an exemplary embodiment of the present disclosure, in the bending region BA, a plurality of connecting lines LNK are arranged to be closer to the substrate 110 at the center portion of the bending region BA than at the interface between the bending region BA and the first non-display region NA1 or the second non-display region NA2. By doing so, damage to the connecting lines due to tensile stress during bending can be minimized, and the reliability of the display device 100 can be improved.

[0148] Furthermore, even in Figure 4 As not shown, the substrate 110 may also exclude the insulating film 110c in a portion of the bending region BA. For example, the insulating film 110c may be patterned in the bending region BA. In the bending region BA, the insulating film 110c, which contains inorganic material, is patterned to minimize stress concentration caused by bending.

[0149] Furthermore, in the display device 100 according to the exemplary embodiments of the present disclosure, cracks generated in the bending region BA are minimized to improve the reliability and service life of the display device 100, thereby realizing a low-power display device with reduced power consumption.

[0150] Figure 5 This is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Figure 5 The display device 200 and Figures 1 to 4 The differences between the display devices 100 are only in the first planarization layer 215a, the second connection line LNK2, and the second planarization layer 215b, while the other configurations are the same, so redundant descriptions will be omitted.

[0151] Reference Figure 5 In the curved region BA, the first planarization layer 215a has a recessed shape. For example, as seen in the cross-section, the first planarization layer 215a is formed by a recessed curved surface. Therefore, the thickness of the first planarization layer 215a at the center of the curved region BA can be thinner than its thickness near the interface between the first non-display region NA1 and the curved region BA. In this case, the first planarization layer 215a can have a recessed curved shape using a slit-type mask. The steepness of the slope of the recessed shape of the first planarization layer 215a can be adjusted according to the slit spacing of the mask. For example, the narrower the slit spacing of the mask, the gentler the slope; the wider the slit spacing, the steeper the slope, thus forming a recessed curved shape.

[0152] In the curved region BA, the second connecting line LNK2 is disposed above the first planarization layer 215a. That is, in the curved region BA, the second connecting line LNK2 can be disposed in a concave curved shape along the concave curved shape of the first planarization layer 215a. In other words, the height H1 of the second connecting line LNK2 from the substrate 110 at the boundary between the first non-display region NA1 and the curved region BA can be higher than the height H2 of the second connecting line LNK2 from the substrate 110 in the central portion of the curved region BA. Therefore, the height H2 of the second connecting line LNK2 from the substrate 110 in the central portion of the curved region BA is lower than the height H1 of the second connecting line LNK2 from the substrate 110 at the boundary between the first non-display region NA1 and the curved region BA. Furthermore, in the central portion of the curved region BA, the second connecting line LNK2 can be positioned closest to the substrate 110.

[0153] Meanwhile, the neutral plane NP in the curved region BA can be located in the second substrate 110b of the substrate 110. Therefore, the second connecting line LNK2 can be configured to be closer to the neutral plane in the central portion of the curved region BA than the boundary between the first non-display region NA1 or the second non-display region NA2 and the curved region BA.

[0154] In the curved region BA, the second planarization layer 215b is disposed on the second connecting line LNK2 in a concave curved shape. At this time, starting from the first non-display region NA1, the thickness of the second planarization layer 215b increases towards the center of the curved region BA, and the thickness decreases towards the second non-display region NA2. That is, the thickness D2c of the second planarization layer 215b in the center of the curved region BA is greater than the thickness D2a at the interface between the first non-display region NA1 and the curved region BA, and the thickness D2b at the interface between the second non-display region NA2 and the curved region BA. Therefore, in the center of the curved region BA, the second planarization layer 215b can be configured to fill the upper part of the second connecting line LNK2.

[0155] In a display device 200 according to another exemplary embodiment of the present disclosure, in the bending region BA, a plurality of second connecting lines LNK2 are arranged such that the central portion of the bending region BA is closest to the substrate 110 than the interface between the bending region BA and the first non-display region NA1 or the second non-display region NA2. Therefore, damage to the second connecting lines LNK2 due to tensile stress during bending can be minimized.

[0156] Therefore, in a display device 200 according to another exemplary embodiment of the present disclosure, cracks generated in the bending region are minimized to improve the reliability of the display device 200, thereby increasing its service life and providing a low-power display device with reduced power consumption.

[0157] Exemplary embodiments of this disclosure can also be described as follows: According to one aspect of this disclosure, a display device includes: a substrate, the substrate including a display area, a first non-display area surrounding the display area, a curved area extending from the first non-display area, and a second non-display area extending from the curved area; a first planarization layer disposed on the substrate in the first non-display area, the curved area, and the second non-display area; a plurality of connecting lines located on the first planarization layer in the first non-display area, the curved area, and the second non-display area; and a second planarization layer located on the plurality of connecting lines in the first non-display area, the curved area, and the second non-display area. In cross-section, the plurality of connecting lines are arranged to be closer to the substrate in the central portion of the curved area than at the boundary between the first non-display area or the second non-display area and the curved area.

[0158] In the curved region, the thickness of the first planarization layer can be smaller as it approaches the center of the curved region, starting from the first non-display region, and the thickness of the first planarization layer can be larger as it approaches the second non-display region, starting from the center of the curved region.

[0159] The first planarization layer can have a stepped shape in the cross-section.

[0160] The first planarization layer can have a concave shape in the cross-section.

[0161] In the curved region, the thickness of the second planarization layer can be greater as it approaches the center of the curved region, starting from the first non-display region, and the thickness of the second planarization layer can be smaller as it approaches the second non-display region, starting from the center of the curved region.

[0162] The display device may also include a dam unit that flattens the upper part of the second planarization layer in the curved region. In cross-section, the thickness of the dam unit in the curved region may be greater than the thickness in the first non-display region or the second non-display region.

[0163] The substrate may include a first substrate, an insulating film on the first substrate, and a second substrate on the insulating film. The neutral plane may be located in the second substrate.

[0164] Multiple connecting lines can be configured to be closer to the neutral plane at the center of the curved area than at the boundary between the first or second non-display area and the curved area.

[0165] In the curved region, the curvature of multiple connecting lines in the central part of the curved region can be less than the curvature at the boundary between the first non-display region or the second non-display region and the curved region.

[0166] According to another aspect of this disclosure, a display device includes: a substrate, the substrate including a display area, a first non-display area surrounding the display area, a curved area extending from the first non-display area, and a second non-display area extending from the curved area; a first planarization layer, the first planarization layer being located on the substrate, and in the curved area, the first planarization layer thinning as it moves from the first non-display area toward the center portion of the curved area, and thickening as it moves from the center portion of the curved area toward the second non-display area; a plurality of connecting lines, the plurality of connecting lines being located on the first planarization layer in the curved area, and in the curved area, the plurality of connecting lines being closest to the substrate in the center portion of the curved area; and a second planarization layer, the second planarization layer being located on the plurality of connecting lines in the curved area.

[0167] The first planarization layer can have a stepped shape in the cross-section.

[0168] The first planarization layer can have a concave shape in the cross-section.

[0169] The substrate may include a first substrate, an insulating film on the first substrate, and a second substrate on the insulating film. The neutral plane may be located in the second substrate.

[0170] Multiple connecting lines can be configured to be closer to the neutral plane at the center of the curved area than at the boundary between the first or second non-display area and the curved area.

[0171] In the curved region, the thickness of the second planarization layer can be greater as it approaches the center of the curved region, starting from the first non-display region, and the thickness of the second planarization layer can be smaller as it approaches the second non-display region, starting from the center of the curved region.

[0172] The display device may also include embankment units located on a second planarization layer in the curved region.

[0173] In the cross-section, the thickness of the embankment unit in the curved region can be greater than the thickness in the first non-display region or the second non-display region.

[0174] In the curved region, the curvature of multiple connecting lines in the central part of the curved region can be less than the curvature at the boundary between the first non-display area or the second non-display area and the curved region.

[0175] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: A substrate, the substrate including a display area, a first non-display area surrounding the display area, a curved area extending from the first non-display area, and a second non-display area extending from the curved area; A first planarization layer is disposed on the substrate in the first non-display area, the curved area, and the second non-display area; Multiple connecting lines are located on the first planarization layer in the first non-display area, the curved area, and the second non-display area; as well as A second planarization layer is located on the plurality of connecting lines in the first non-display area, the curved area, and the second non-display area. In the cross-section, the plurality of connecting lines are positioned closer to the substrate in the central portion of the curved region than at the boundary between the first non-display region or the second non-display region and the curved region.

2. The display device according to claim 1, wherein, In the curved region, the thickness of the first planarization layer decreases as it approaches the center of the curved region from the first non-display region, and the thickness of the first planarization layer increases as it approaches the second non-display region from the center of the curved region.

3. The display device according to claim 2, wherein, The first planarization layer has a stepped shape in the cross-section.

4. The display device according to claim 2, wherein, The first planarization layer has a recessed shape in the cross-section.

5. The display device according to claim 1, wherein, In the curved region, the thickness of the second planarization layer increases as it approaches the center of the curved region from the first non-display region, and the thickness of the second planarization layer decreases as it approaches the second non-display region from the center of the curved region.

6. The display device according to claim 5, further comprising: A dike unit that flattens the upper portion of the second flattening layer in the curved region. In the cross-section, the thickness of the embankment unit in the curved region is greater than its thickness in the first non-display region or the second non-display region.

7. The display device according to claim 1, wherein, The substrate includes: First substrate; An insulating film, the insulating film being located on the first substrate; and The second substrate is located on the insulating film. The neutral plane is located in the second substrate.

8. The display device according to claim 7, wherein, The plurality of connecting lines are configured such that the central portion of the curved region is closer to the neutral surface than at the boundary between the first non-display region or the second non-display region and the curved region.

9. The display device according to claim 1, wherein, In the curved region, the curvature of the plurality of connecting lines in the central portion of the curved region is less than the curvature at the boundary between the first non-display region or the second non-display region and the curved region.

10. A display device, comprising: A substrate, the substrate including a display area, a first non-display area surrounding the display area, a curved area extending from the first non-display area, and a second non-display area extending from the curved area; A first planarization layer is located on the substrate, and in the curved region, the first planarization layer thins as it moves from the first non-display area toward the center portion of the curved region, and thickens as it moves from the center portion of the curved region toward the second non-display area. Multiple connecting lines are located on the first planarization layer in the curved region, and in the curved region, the multiple connecting lines are closest to the substrate in the central portion of the curved region; as well as A second planarization layer is located on the plurality of connecting lines in the curved region.

11. The display device according to claim 10, wherein, The first planarization layer has a stepped shape in cross-section.

12. The display device according to claim 10, wherein, The first planarization layer has a concave shape in cross-section.

13. The display device according to claim 10, wherein, The substrate includes: First substrate; An insulating film, the insulating film being located on the first substrate; and The second substrate is located on the insulating film. The neutral plane is located in the second substrate.

14. The display device according to claim 13, wherein, The plurality of connecting lines are configured such that the central portion of the curved region is closer to the neutral surface than at the boundary between the first non-display region or the second non-display region and the curved region.

15. The display device according to claim 10, wherein, In the curved region, the thickness of the second planarization layer increases as it approaches the center of the curved region from the first non-display region, and the thickness of the second planarization layer decreases as it approaches the second non-display region from the center of the curved region.

16. The display device according to claim 15, further comprising: A dam unit, which is located on the second planarization layer in the curved region.

17. The display device according to claim 16, wherein, In the cross-section, the thickness of the embankment unit in the curved region is greater than its thickness in the first non-display region or the second non-display region.

18. The display device according to claim 10, wherein, In the curved region, the curvature of the plurality of connecting lines in the central portion of the curved region is less than the curvature at the boundary between the first non-display region or the second non-display region and the curved region.

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