System for high energy-efficient bit-serial storage-multiplication and 5-3 compressor circuit
By reconstructing the full adder core and applying a mirror adder, the problems of large area overhead and long latency in traditional 5-3 compressor designs are solved, and high-efficiency bit-serial in-memory multiplication is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NAT UNIV OF DEFENSE TECH
- Filing Date
- 2026-06-01
- Publication Date
- 2026-08-04
AI Technical Summary
Traditional 5-3 compressor designs have large area overhead and long latency, which cannot meet the needs of high-performance computing.
A reconstructed 5-3 compressor circuit is adopted, which decomposes the full adder core into independent carry generation modules and sum generation modules, reduces the number of inverters, and achieves a critical path delay of 4 transistors through a mirror adder.
It reduces area overhead, increases multiplier speed, and achieves the same latency performance as a single 3-2 compressor.
Smart Images
Figure CN122331860B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit design technology and relates to a system for high-efficiency bit-serial in-memory multiplication and a 5-3 compressor circuit. Background Technology
[0002] In modern microprocessors, digital signal processors, and dedicated hardware accelerators, multipliers are critical execution units, and their performance directly impacts the overall system's throughput and energy efficiency. The core step of multiplication is generating and accumulating multiple partial products. How to efficiently and quickly add these reduced partial products to the final product remains a key design challenge. Traditional cascaded accumulation using ripple carry adders has excessive latency, failing to meet the demands of high-performance computing. Therefore, employing a compressor tree structure (such as a Wallace tree or Dadda tree) to compress multiple partial products into two operands in parallel, and then obtaining the final result through a fast carry-propagating adder, has become a common design approach.
[0003] The basic unit of a compressor is a full adder, also known as a 3-2 compressor, which compresses three input bits with equal weights into a sum bit (with equal weights) and a carry bit (with a higher weight). To improve the efficiency of single-stage compression, more efficient compressor units have been proposed, such as the 5-3 compressor.
[0004] The 5-3 compressor is a core component of high-performance multipliers and multiply-accumulator units. It is used in high-performance multipliers such as Booth to process the 5-3 compression at the end of each partial product. However, traditional 5-3 compressor designs typically use two cascaded 3-2 compressors (full adders). This structure not only has a large area overhead, but its output delay is also significantly longer than that of ordinary 3-2 compressors, which slows down the overall operating speed of the multiplier and reduces the main frequency of the entire device. Summary of the Invention
[0005] To address the problems existing in the aforementioned traditional methods, this invention proposes a system and a 5-3 compressor circuit for high-efficiency bit-serial in-memory multiplication. This system integrates the area advantages of bit-serial processing, the partial product reduction advantages of Booth encoding, and the high-speed advantages of carry-preserving addition, while eliminating the speed bottleneck at the end of the accumulation phase through an innovative 5-3 compressor circuit.
[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On one hand, a 5-3 compressor circuit is provided, the circuit including: two mirror adders ADD1 and ADD2 with the inverters of the carry output terminal and the output terminal removed; the mirror adder includes a C module for generating the carry output and an S module for generating and outputting; the C module and the S module are respectively the circuit parts before and after the inverted carry output in the mirror adder.
[0007] The three inputs of ADD1's C module receive the carry signal Cin, signal A0, and signal B0 from the previous stage, respectively. The output of ADD1's C module outputs the inverted carry signal from the first stage. The four inputs of the ADD1 S module receive the carry signal Cin from the previous stage and the inverted carry signal from the first stage, respectively. Signals A0 and B0, the output terminal of the S module of ADD1 outputs the inverted low-order sum signal. .
[0008] The three inputs of ADD2's C module receive the inverted first-stage carry signal. The inverted signals A1 and B1 are used to input the carry signal C1 from the C module of ADD2; the four inputs of the S module of ADD2 receive the inverted first-stage carry signal. The carry signal C1, the inverted signal of signal A1, and the inverted signal of signal B1; the output terminal of the S module of ADD2 outputs the high bit and signal S1.
[0009] In one embodiment, the circuit further includes a first inverter and a second inverter. After passing through the first inverter and the second inverter, signals A1 and B1 are respectively inverted to obtain the inverted signals of signal A1 and B1.
[0010] In one embodiment, the circuit further includes a third inverter to invert the low-order bit and the signal. The low-order bit signal is output after passing through the third inverter. .
[0011] In one embodiment, the inverted signals of signal A1 and B1 are obtained by reading the signals A1 and B1 inverted.
[0012] In one embodiment, the inverted low bit and signal Write the corresponding bit into the SRAM cell in reverse order.
[0013] In one embodiment, the circuit includes a fourth inverter, a fifth inverter, and a sixth inverter.
[0014] Signals A1 and B1 are passed through the fourth inverter and the fifth inverter, respectively, to obtain the inverted signals of signal A1 and B1.
[0015] Inverted low bit and signal The low-order bit signal is output after passing through the sixth inverter. .
[0016] On the other hand, a system for high-efficiency bit-serial in-memory multiplication is provided, the system comprising: a multiplicand buffer, a Booth encoder, a partial product generator, and a carry-holding accumulator module.
[0017] Multiplicand cache is used to store the multiplicand.
[0018] The Booth encoder is used to receive the multiplier serially, with 2 bits input per cycle. These bits, together with 1 bit of historical value stored internally, generate the Booth code for the current cycle.
[0019] A partial product generator is used to select, combine, or invert values from a cache storing the multiplicands, based on Booth encoding control, to generate an n+2-bit partial product and a 1-bit sign suffix.
[0020] The carry-retaining accumulation module includes: a first accumulation buffer, a second accumulation buffer, a sign suffix delay buffer, multiple full adders, and the aforementioned 5-3 compressor circuit; the first and second accumulation buffers are used to store intermediate accumulation results in carry-retaining format; the sign suffix delay buffer is used to cache the sign suffix generated in the previous cycle; the multiple full adders are used to compress the main bits of the partial product of the current cycle and the high bits of the first and second accumulation buffers; the 5-3 compressor circuit is used to perform 5-3 compression on the lowest two bits of the first and second accumulation buffers and the output of the sign suffix delay buffer, and output the low bits of the product result.
[0021] In one embodiment, the workflow of the carry-holding accumulation module includes an iteration phase and a drain phase: During the iteration phase, the partial product generation, carry retention accumulation, and result output are repeatedly executed over N cycles, and an N-bit product is output; N is half the multiplier bit width plus one.
[0022] During the emptying phase, the partial product is fixed to 0, and the accumulation and output continue. The first and second accumulation buffers are shifted to the left. After N cycles, the remaining N-bit product is output, thus completing the 2N-bit multiplication operation.
[0023] In one embodiment, a 5-3 compressor circuit for 5-3 compression of the outputs of the first accumulator buffer, the lowest two bits of the second accumulator buffer, and the sign suffix delay buffer has a critical path delay of 4 transistors.
[0024] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned 5-3 compressor circuit includes two mirror adders. This circuit reconstructs the full adder core, decomposing it into independent carry generation and sum generation modules. The output of the carry generation module depends entirely on the initial input, while the output of the sum generation module depends not only on the initial input but also on the output of the carry generation module. The reconstructed adders reduce area overhead. By using the two reconstructed adders to form the 5-3 compressor circuit, the critical path of the 5-3 compressor circuit contains only 4 stages of transistor delay, intersecting with the conventional implementation of two cascaded 3-2 compressors (6 stages of delay in total). This circuit reduces the area overhead of two inverters (4T) and achieves the same delay overhead as a single 3-2 compressor. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 This is a schematic diagram of the compressor circuit structure in one embodiment (5-3). Figure 2 This is a schematic diagram of a mirror adder structure (I) in one embodiment; Figure 3 This is a schematic diagram of a mirror adder structure (II) in one embodiment; Figure 4 This is a schematic diagram of the compressor circuit structure (I) of 5-3 in one embodiment; Figure 5 This is a schematic diagram of the compressor circuit structure (II) of 5-3 in one embodiment; Figure 6 This is a schematic diagram of a high-efficiency bit-serial in-memory multiplication system in one embodiment. Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0029] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.
[0030] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0031] In one embodiment, such as Figure 1 As shown, a 5-3 compressor circuit is provided, including: The two mirror adders ADD1 and ADD2 have their carry-out and output inverters removed; the mirror adders include a C module for generating the carry-out and an S module for generating and outputting; the C module and the S module are the circuit parts before and after the inverted carry-out in the mirror adder, respectively.
[0032] The three inputs of ADD1's C module receive the carry signal Cin, signal A0, and signal B0 from the previous stage, respectively. The output of ADD1's C module outputs the inverted carry signal from the first stage. The four inputs of the ADD1 S module receive the carry signal Cin from the previous stage and the inverted carry signal from the first stage, respectively. Signals A0 and B0, the output terminal of the S module of ADD1 outputs the inverted low-order sum signal. .
[0033] The three inputs of ADD2's C module receive the inverted first-stage carry signal. The inverted signals A1 and B1 are used to input the carry signal C1 from the C module of ADD2; the four inputs of the S module of ADD2 receive the inverted first-stage carry signal. The carry signal C1, the inverted signal of signal A1, and the inverted signal of signal B1; the output terminal of the S module of ADD2 outputs the high bit and signal S1.
[0034] Specifically, in this connection, if inputs A1 and B1 come from SRAM that can provide inverted readout, and the output... If it can be written to SRAM in reverse, then Figure 1 The structure shown can realize a zero inverter, requiring only 48 transistors, and the critical path (A0, B0, Cin → C module of ADD1 → C module of ADD2 → C1) has a delay of only 4 stages of transistors.
[0035] To efficiently achieve the final 5-3 compression of Booth multiplication, this design does not employ the traditional method of cascading two 3-2 compressors (i.e., full adders) to form a 5-3 compressor. Instead, the full adder kernel is restructured, decomposing it into independent carry generation (C) modules and sum generation (S) modules.
[0036] like Figure 2 The diagram shows a standard 28T full adder implementation. Removing the inverters from its two output ports reduces the area overhead to 24T. The first half of the circuit outputs... The path serves as a boundary, logically dividing the circuit into two parts. These two parts are then configured as a C module to generate carry output and an S module to generate and output, respectively, as follows: Figure 3 As shown.
[0037] Figure 3 The C module contains five groups of CMOS transistors, where the first PMOS transistor P1 to the fifth PMOS transistor P5 are complementary to the first NMOS transistor N1 to the fifth NMOS transistor N5, respectively. The connection relationship of the five groups of CMOS transistors is as follows: The first PMOS transistor P1 has its gate configured to receive control signal A, its source connected to the power supply terminal of the module, and its drain connected to the source of the third PMOS transistor P3.
[0038] The second PMOS transistor P2 has its gate configured to receive the control signal B, its source connected to the power supply terminal of the module, and its drain connected to the source of the third PMOS transistor P3.
[0039] The third PMOS transistor P3 has its gate configured to receive the control signal Cin, its source connected to the drains of the first PMOS transistor P1 and the second PMOS transistor P2, and its drain connected to the drain of the first NMOS transistor N1 and the output of the C module. end.
[0040] The fourth PMOS transistor P4 has its gate configured to receive control signal A, its source connected to the power supply terminal of the module, and its drain connected to the source of the fifth PMOS transistor P5.
[0041] The fifth PMOS transistor P5 has its gate configured to receive the control signal B, its source connected to the drain of the fourth PMOS transistor P4, and its drain connected to the drain of the third PMOS transistor P3 and the output of the C module. end.
[0042] The connection relationships of the first NMOS transistor N1 to the fifth NMOS transistor N5 correspond one-to-one with the connection relationships of the first PMOS transistor P1 to the fifth PMOS transistor P5.
[0043] The connected module C contains three input ports to receive control signals A, B, and Cin respectively, and one output port to output the calculation results of the module. Signal.
[0044] Figure 3 The S module contains seven groups of CMOS transistors, namely, groups six through twelfth CMOS transistors. The sixth PMOS transistor (P6) through the twelfth PMOS transistor (P12) are complementary to the sixth NMOS transistor (N6) through the twelfth NMOS transistor (N12), respectively. The connection relationship of the seven groups of CMOS transistors is as follows: The sixth PMOS transistor, P6, has its gate configured to receive the control signal output from module C. Its source is connected to the drain of the seventh, eighth, and ninth PMOS transistors, and its drain is connected to the drain of the tenth PMOS transistor P10 and the output signal of the S module. .
[0045] The seventh PMOS transistor P7 has its gate configured to receive control signal A, its source connected to the power supply terminal of the module, and its drain connected to the source of the sixth PMOS transistor P6.
[0046] The eighth PMOS transistor P8 has its gate configured to receive the control signal B, its source connected to the power supply terminal of the module, and its drain connected to the source of the sixth PMOS transistor P6.
[0047] The ninth PMOS transistor P9 has its gate configured to receive the control signal Cin output by the C module, its source connected to the power supply terminal of the module, and its drain connected to the source of the sixth PMOS transistor P6.
[0048] The tenth PMOS transistor P10 has its gate configured to receive the control signal Cin output from the C module. Its source is connected to the drain of the eleventh PMOS transistor P11, and its drain is connected to the drain of the sixth PMOS transistor P6 and the output signal of the S module. .
[0049] The eleventh PMOS transistor P11 has its gate configured to receive the control signal B, its source is connected to the drain of the twelfth PMOS transistor P12, and its drain is connected to the source of the tenth PMOS transistor P10.
[0050] The twelfth PMOS transistor P12 has its gate configured to receive control signal A, its source connected to the power supply terminal of the module, and its drain connected to the source of the eleventh PMOS transistor P11.
[0051] The connection relationships of the sixth NMOS transistor N6 to the twelfth NMOS transistor N12 correspond one-to-one with the connection relationships of the sixth PMOS transistor P6 to the twelfth PMOS transistor P12.
[0052] The S-module formed by this connection has four input ports, which respectively receive input control signals A, B, Cin and input signals from module C. It includes an output port for outputting the calculation results of this module. Signal.
[0053] from Figure 3 You can see the output of the C module. The output of module S depends entirely on the initial inputs A, B, and Cin, while the output of module S depends not only on the initial inputs but also on the output of module C. This indicates that in subsequent circuit connections, the input direction of the S module requires at least one C module to be paired with it.
[0054] like Figure 1 The 5-3 compressor circuit structure shown contains two sets of... Figure 3 The connection relationship between the C module and the S module shown is as follows: The three input ports of the C module in section ADD1 receive control signals A0, B0, and Cin respectively, and its output port... Simultaneously with the ADD1 part of the S module Connect the input terminals, the Cin input terminal of the C module in the ADD2 section, and the Cin input terminal of the S module in the ADD2 section.
[0055] The four input ports of the S module in the ADD1 section receive control signals A0, B0, Cin, and the output signal from the C module in the ADD1 section, respectively. Its output port As the output terminal of the 5-3 compressor circuit .
[0056] The three input ports of the C module in the ADD2 section receive control signals respectively. , and the output signal from the C module of ADD1 section Its output signal C1 is connected to the S module of the ADD2 section. The input port also serves as the output terminal C1 of the 5-3 compressor circuit.
[0057] The four input ports of the S-module in the ADD2 section receive control signals respectively. , Output signals from the C module of ADD1 section And the output signal C1 from module C of section ADD2. Its output port S1 serves as the output terminal S1 of this 5-3 compressor circuit.
[0058] The 5-3 compressor circuit formed by this connection includes five input ports, which receive input control signals A0, B0, Cin, A1, and B1 respectively, and three output ports, which are used to output the calculation results of this module. S1 and C1 signals.
[0059] Its key advantage lies in the fact that the critical path of the 5-3 compressor contains only 4 stages of transistor delay. Compared to the conventional implementation of cascading two 3-2 compressors (a total of 6 stages of delay), this design not only reduces the area overhead of two inverters (4T) compared to the cascaded design, but also achieves the same delay overhead as a single 3-2 compressor. Compared to the scheme of cascading two stages of 3-2 compressors, this further improves the overall operation speed of the multiplier.
[0060] This design is based on the self-duality principle of addition: (The ADD logic here remains unchanged. For general logic without self-duality, such as AND logic, according to De Morgan's law, this expression would become...) (Here, AND logic becomes OR logic.) That is, for an adder, inverting all inputs is directly equivalent to inverting all outputs (this does not mean that addition logic does not follow De Morgan's law, but that the logical expression of addition will return to itself after De Morgan's transformation). This principle also applies to the adder submodules C and S.
[0061] Only devices possessing self-dual properties can be designed as mirror (symmetric) structures. This is the origin of mirror-structure adders (and explains why NAND gates and NOR gates use dual structures instead of symmetric structures; based on this, it can also be argued that the mirror configuration of a mirror-structured device possesses self-dual properties). Figure 3 The structure shown has been verified by simulation. Reducing the number of NOT gates not only reduces the area but also makes the waveform more stable.
[0062] Because SRAM can provide both forward and reverse data, and can also be written in both forward and reverse directions, if a bubble is pushed to the beginning or end of the device, it can be directly discarded. Based on this principle, we can obtain... Figure 1The diagram shows a 5-3 compression circuit containing 0 inverters. In this structure, the output S0 is inverted and written to the corresponding bit of the SRAM cell, and the signals A1 and B1 are inverted to read the corresponding bit data, with a capacity of only 48T.
[0063] The aforementioned 5-3 compressor circuit includes two mirror adders. This circuit reconstructs the full adder core, decomposing it into independent carry generation and sum generation modules. The output of the carry generation module depends entirely on the initial input, while the output of the sum generation module depends not only on the initial input but also on the output of the carry generation module. The reconstructed adders reduce area overhead. By using the two reconstructed adders to form the 5-3 compressor circuit, the critical path of the 5-3 compressor circuit contains only 4 stages of transistor delay, intersecting with the conventional implementation of two cascaded 3-2 compressors (6 stages of delay in total). This circuit reduces the area overhead of two inverters (4T) and achieves the same delay overhead as a single 3-2 compressor.
[0064] In one embodiment, the circuit further includes a first inverter and a second inverter. After passing through the first inverter and the second inverter, signals A1 and B1 are respectively inverted to obtain the inverted signals of signal A1 and B1.
[0065] Specifically, in practical applications, the inputs of signals A1 and B1 come from the partial product generation circuit in the circuit rather than directly from the SRAM bitcell. Therefore, the input inverters at signals A1 and B1 cannot be directly eliminated, forming the final 5-3 compressor circuit schematic as shown below. Figure 4 As shown, a total of 52T transistors are used.
[0066] In one embodiment, the circuit further includes a third inverter to invert the low-order bit and the signal. The low-order bit signal is output after passing through the third inverter. .
[0067] In one embodiment, the inverted signals of signal A1 and B1 are obtained by reading the signals A1 and B1 inverted.
[0068] In one embodiment, the inverted low bit and signal Write the corresponding bit into the SRAM cell in reverse order.
[0069] In one embodiment, such as Figure 5 As shown, the circuit also includes a fourth inverter, a fifth inverter, and a sixth inverter.
[0070] Signals A1 and B1 are passed through the fourth inverter and the fifth inverter, respectively, to obtain the inverted signals of signal A1 and B1.
[0071] Inverted low bit and signal The low-order bit signal is output after passing through the sixth inverter. .
[0072] In one embodiment, a system for high-efficiency bit-serial in-memory multiplication is also provided, the system comprising: a multiplicand buffer, a Booth encoder, a partial product generator, and a carry-holding accumulator module.
[0073] Multiplicand cache is used to store the multiplicand.
[0074] The Booth encoder is used to receive the multiplier serially, with 2 bits input per cycle. These bits, together with 1 bit of historical value stored internally, generate the Booth code for the current cycle.
[0075] The partial product generator is used to select, combine, or invert values from the cache storing the multiplicands, according to the control of Booth encoding, to generate an n+2-bit partial product (PP) and a 1-bit sign suffix (hsig).
[0076] The carry-retaining accumulation module includes: a first accumulation buffer, a second accumulation buffer, a sign suffix delay buffer, multiple full adders, and the aforementioned 5-3 compressor circuit; the first and second accumulation buffers are used to store intermediate accumulation results in carry-retaining format; the sign suffix delay buffer is used to cache the sign suffix generated in the previous cycle; the multiple full adders are used to compress the main bits of the partial product of the current cycle and the high bits of the first and second accumulation buffers; the 5-3 compressor circuit is used to perform 5-3 compression on the lowest two bits of the first and second accumulation buffers and the output of the sign suffix delay buffer, and output the low bits of the product result.
[0077] The aforementioned system for high-efficiency bit-serial in-memory multiplication achieves a balance between area, speed, and energy efficiency at the algorithm level by integrating bit-serial processing. Its bit-serial characteristics significantly reduce data path width and cache area; Booth encoding reduces the number of partial products; and carry-preserving addition decouples accumulation latency from operand bit width. The system integrates bit-serial processing, Booth encoding, and carry-preserving accumulation, completing multiplication through a two-stage process of iteration and emptying, resulting in a small area and speed independent of bit width.
[0078] In one embodiment, the workflow of the carry-holding accumulation module includes an iteration phase and a drain phase: During the iteration phase, the partial product generation, carry retention accumulation, and result output are repeatedly executed over N cycles, and an N-bit product is output; N is half the multiplier bit width plus one.
[0079] During the emptying phase, the partial product is fixed to 0, and the accumulation and output continue. The first and second accumulation buffers are shifted to the left. After N cycles, the remaining N-bit product is output, thus completing the 2N-bit multiplication operation.
[0080] In one embodiment, a 5-3 compressor circuit performs 5-3 compression on the outputs of the first accumulator buffer, the lowest two bits of the second accumulator buffer, and the sign suffix delay buffer, with a critical path delay of 4 transistors.
[0081] Specifically, in combination Figure 6 Describe this high-energy-efficiency bit-sequential in-memory multiplication system. For example... Figure 6 As shown, the high-efficiency bit-sequential in-memory multiplication system includes: a multiplicand buffer, a Booth encoder, a partial product generator, and a carry-retaining accumulator module. The Booth encoder and partial product generator employ a typical current design. The multiplier W is serially input to the encoder starting from the least significant bit, with 2 bits input per cycle. This input, along with a 1-bit historical value stored internally, generates the Booth code for the current cycle. This code controls the partial product generation circuit to select, combine, or invert the value of the multiplicand Q from the buffer, generating an n+2-bit partial product (PP) and a 1-bit sign suffix (hsig).
[0082] The carry-preserving accumulator module includes two accumulator caches, hca and hsu, a sign suffix delay cache, hsig, a 3-2 compressor array consisting of full adders (FAs), and a 5-3 compressor as described above. hca and hsu are initialized to specific values, and the caches used to store hca, hsu, hsig, and W are all standard SRAM cells.
[0083] The cumulative operations for each work cycle are as follows: Step (1) Cache initialization: Load the multiplier Q (n bits) into the cache. Initialize the accumulator caches hca and hsu, setting the highest bit of hca and hsu to "1" and clearing the remaining bits to zero. Initialize the sign suffix delay cache hsig to "0"; Step (2) Booth encoding generation: The multiplicand W (n bits) is padded with one "0" in the low bits and two "0"s in the high bits to expand it. Starting from the least significant bit, every 3 bits are overlapped into a group, and the Booth encoding is generated sequentially in a bit-serial manner; (the number of groups is "bit width divided by 2 and rounded up by 1"). Step (3) Partial product generation: The Booth code generated in the current clock cycle is operated with the multiplier Q to generate an n+2 bit partial product and a 1 bit sign suffix; Step (4) Carry-hold Accumulator (CSA), Result Output and Write-back: Compress the lower n-1 bits of the current partial product with the higher n-1 bits of hca and hsu in a 3:2 ratio, and write the result back to hca[n-1:1] (n:0) and hsu[51:0]. Compress the lowest 2 bits of hca and hsu with hsig in a 5:3 ratio; write the carry bit generated by the 5:3 compression back to the lowest bit of hca (hca[0]), and output the two sum bits (lower 2 bits) as the final product result; Add 1 to the nth bit of the current partial product, write the sum back to hsu[n-1], and write the carry bit back to hca[n]. Write the (n+1)th bit of the current partial product directly back into hsu[n]; Step (5) Iteration: Repeat steps (2) to (4) for a total of 27 clock cycles until all bits (partial products) of W are involved in the calculation. At this point, the n+1 bit product result has been output, but there is still residual data in hca and hsu, which needs to be emptied.
[0084] Step (6) Emptying stage: Control Booth encoding output to 0, so that the partial product is 0. Under this condition, continue with steps (4) and (5); accumulate hca and hsu in each cycle using CSA and shift left by 2 bits, and output the final product result of 2 bits.
[0085] Step (7) Emptying the iteration: Continue step (6) for a total of (n+1) / 2 cycles, empty all the data in hca and hsu, and output the product result of n+1 bits. At this point, the calculation is complete, and a total of 2n+2 bits of complete product are output.
[0086] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0087] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and all such modifications and improvements fall within the scope of protection of this application.
Claims
1. A 5-3 compressor circuit, characterized in that, include: Two mirror adders, ADD1 and ADD2, have their carry-out and output inverters removed; each mirror adder includes a C module for generating the carry-out and an S module for generating and outputting the carry-out; the C module and S module are respectively the circuit sections before and after the inverted carry-out in the mirror adder. The three inputs of ADD1's C module receive the carry signal Cin, signal A0, and signal B0 from the previous stage, respectively. The output of ADD1's C module outputs the inverted carry signal from the first stage. The four inputs of the ADD1 S module receive the carry signal Cin from the previous stage and the inverted carry signal from the first stage, respectively. Signals A0 and B0, the output terminal of the S module of ADD1 outputs the inverted low-order sum signal. ; The three inputs of ADD2's C module receive the inverted first-stage carry signal. The inverted signals A1 and B1 are used to input the carry signal C1 from the C module of ADD2; the four inputs of the S module of ADD2 receive the inverted first-stage carry signal. The carry signal C1, the inverted signal of signal A1, and the inverted signal of signal B1; the output terminal of the S module of ADD2 outputs the high bit and signal S1.
2. The 5-3 compressor circuit according to claim 1, characterized in that, The circuit further includes a first inverter and a second inverter. After passing through the first inverter and the second inverter, respectively, the inverted signals of signal A1 and B1 are obtained.
3. The 5-3 compressor circuit according to claim 1, characterized in that, The circuit also includes a third inverter to invert the low-order bit and the signal. The low-order bit signal is output after passing through the third inverter. .
4. The 5-3 compressor circuit according to claim 1, characterized in that, The inverted signals of signal A1 and signal B1 are obtained by reading the inverted signals A1 and B1.
5. The 5-3 compressor circuit according to claim 1, characterized in that, The inverted low bit and signal Write the corresponding bit into the SRAM cell in reverse order.
6. The 5-3 compressor circuit according to claim 1, characterized in that, The circuit includes a fourth inverter, a fifth inverter, and a sixth inverter; The signals A1 and B1 are respectively passed through the fourth inverter and the fifth inverter to obtain the inverted signals of signal A1 and B1. Inverted low bit and signal The low-order bit signal is output after passing through the sixth inverter. .
7. A system for high-efficiency bit-serial in-memory multiplication, characterized in that, include: Multiplicand buffer, Booth encoder, partial product generator and carry-preserving accumulator module; The multiplicand cache is used to store the multiplicand; The Booth encoder is used to receive the multiplier serially, inputting 2 bits per cycle, which together with the 1-bit historical value stored internally to generate the Booth code for the current cycle. The partial product generator is used to select, combine, or invert values from the cache storing the multiplicands, according to the control of the Booth encoding, to generate an n+2-bit partial product and a 1-bit sign suffix. The carry-holding accumulation module includes: a first accumulation buffer, a second accumulation buffer, a sign suffix delay buffer, multiple full adders, and a 5-3 compressor circuit as described in any one of claims 1 to 6; The first and second accumulation buffers are used to store intermediate accumulation results in a carry-preserving format; the sign suffix delay buffer is used to cache the sign suffix generated in the previous cycle; the multiple full adders are used to compress the main bits of the partial product of the current cycle and the high bits of the first and second accumulation buffers; the 5-3 compressor circuit is used to perform 5-3 compression on the lowest two bits of the first and second accumulation buffers and the output of the sign suffix delay buffer, and output the low bits of the product.
8. The system for high-efficiency bit-serial in-memory multiplication according to claim 7, characterized in that, The workflow of the carry-retaining accumulation module includes an iteration phase and a drain phase: During the iteration phase, the partial product generation, carry retention accumulation, and result output are repeatedly executed for N cycles, and an N-bit product is output; N is half the multiplier bit width plus one. During the emptying phase, the partial product is fixed to 0, and the accumulation and output continue. The first and second accumulation buffers are shifted to the left. After N cycles, the remaining N-bit product is output, thus completing the 2N-bit multiplication operation.
9. The system for high-efficiency bit-serial in-memory multiplication according to claim 7, characterized in that, A 5-3 compressor circuit is used to perform 5-3 compression on the outputs of the first accumulator buffer, the lowest two bits of the second accumulator buffer, and the symbol suffix delay buffer, with a critical path delay of 4 transistors.