Embedded flash memory and methods of forming the same
By etching the SRAM polysilicon layer simultaneously with the sidewall material layer of the flash memory region, the problems of large leakage current in the straight-head structure and small process window in the bent-head structure of the SRAM polysilicon layer are solved. This achieves effective transistor disconnection and process window stability, avoiding additional photomasks and process steps.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-04-27
- Publication Date
- 2026-07-10
Smart Images
Figure CN122373329A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to an embedded flash memory and a method for forming the same. Background Technology
[0002] SRAM (Static Random Access Memory) is a type of volatile memory that uses bistable trigger circuits to store each bit of data. It relies on the steady-state latching of the circuit, rather than capacitor charge, to latch the data, thus eliminating the need for periodic refreshing like DRAM. It boasts extremely fast read / write speeds, simple interface timings, and high reliability, making it ideal for applications with extremely high speed and stability requirements.
[0003] SRAM polysilicon layers typically employ a straight-end structure. However, the polylineend of a small polysilicon layer in a straight-end structure is prone to photoresist shrinkage, resulting in poor channel control and high leakage current.
[0004] Reducing SRAM area is one of the core goals in advanced process technology, CPU cache, MCU, and SoC design, directly affecting chip cost, power consumption, and integration.
[0005] To reduce the SRAM area, a polysilicon layer elbow structure was designed. However, the polysilicon layer elbow structure results in a small process window. Figure 1 This is an SEM image of the shorted-out SRAM polysilicon layer elbow structure in existing technology. (Example:) Figure 1 As shown, a large critical dimension in the SRAM polysilicon layer makes it prone to scum short circuits. A small critical dimension in the polysilicon layer results in rapid shrinkage at the bends of the polysilicon layer's elbow structure, leading to abnormal short-channel leakage. Furthermore, the elbow structure may cause ion implantation blocking or shadowing effects, resulting in a small ion implantation process window. Summary of the Invention
[0006] The purpose of this invention is to provide an embedded flash memory and a method for forming the same, in order to solve at least one of the following problems: poor channel control capability due to line end shrinkage in the straight-end structure of SRAM polysilicon layer, large leakage current, or small process window due to the bent-end structure of SRAM polysilicon layer.
[0007] To address the aforementioned technical problems, the present invention provides a method for forming embedded flash memory, comprising:
[0008] A substrate is provided, the substrate including a flash memory region and an SRAM region, the flash memory region including a first gate structure located on the substrate;
[0009] A sidewall material layer is formed, which covers the top and sidewalls of the first gate structure and the substrate of the flash memory region;
[0010] A polysilicon layer is formed on the substrate of the SRAM region;
[0011] An etching process is performed to etch the sidewall material layer of the flash memory region to form the sidewall of the first gate structure, while the polysilicon layer of the SRAM region is etched to form the first transistor and the second transistor with the target spacing in the SRAM region.
[0012] Optionally, the polysilicon layer of the SRAM region is a first transistor and a second transistor with a bend structure, and the bend structures of the first transistor and the second transistor are adjacent to each other.
[0013] Optionally, etching the polysilicon layer of the SRAM region includes etching the gap region between the bend structure of the first transistor and the bend structure of the second transistor and / or a portion of the bend structure of the first transistor and a portion of the bend structure of the second transistor, so that the bend structure of the first transistor and the bend structure of the second transistor meet the target spacing.
[0014] Optionally, the polysilicon layer of the SRAM region is a first transistor and a second transistor with straight-head structures, and the lengths of the straight-head structures of the first transistor and the second transistor are greater than the target length.
[0015] Optionally, etching the polysilicon layer of the SRAM region includes etching the gap region between the straight head structure of the first transistor and the straight head structure of the second transistor and / or a portion of the straight head structure of the first transistor and a portion of the straight head structure of the second transistor, so that the straight head structure of the first transistor and the straight head structure of the second transistor meet the target spacing.
[0016] Optionally, the polysilicon layer of the SRAM region is a continuous polysilicon layer that is greater than the sum of the target lengths of the first transistor and the second transistor.
[0017] Optionally, etching the polysilicon layer of the SRAM region includes etching the spacing region between the first transistor and the second transistor to ensure that the straight head structure of the first transistor and the straight head structure of the second transistor meet the target spacing.
[0018] Optionally, the substrate further includes a logic region, the logic region including a second gate structure located on the substrate.
[0019] Optionally, etching the sidewall material layer of the flash memory region includes etching the top sidewall material layer of the first gate structure and the sidewall material layer on the substrate of the flash memory region, while retaining the sidewall material layer on the sidewall of the first gate structure to form the sidewall of the first gate structure.
[0020] Based on the same inventive concept, the present invention also provides an embedded flash memory, which is prepared by the embedded flash memory forming method described in any of the above claims.
[0021] In the embedded flash memory formation method provided by this invention, during the process of etching the sidewall material layer of the flash memory region to form the sidewalls of the first gate structure, the polysilicon layer of the SRAM region is simultaneously etched to form the first transistor and the second transistor with a target pitch in the SRAM region. This invention, through different layers—that is, by simultaneously using the sidewall etching process in the flash memory region to etch away the polysilicon layer of the SRAM region—ultimately creates the first and second transistors of the SRAM region with straight-end structures that do not shrink, or adjacent bend structures that are not short-circuited. The etching process of this invention does not require additional photomasks or process steps, and reduces process weaknesses without increasing the area by combining preceding and following layers. Attached Figure Description
[0022] Figure 1 This is an SEM image of the short circuit in the SRAM polysilicon layer elbow structure in the existing technology.
[0023] Figure 2 This is a flowchart of a method for forming an embedded flash memory according to an embodiment of the present invention.
[0024] Figure 3 This is a schematic diagram of the embedded flash memory structure after the sidewall material layer is formed according to an embodiment of the present invention.
[0025] Figure 4 This is a schematic diagram of the embedded flash memory structure after the formation of the second gate structure and the polysilicon layer according to an embodiment of the present invention.
[0026] Figure 5 This is a schematic diagram of the embedded flash memory structure after the formation of a patterned photoresist layer according to an embodiment of the present invention.
[0027] Figure 6 This is a schematic diagram of the embedded flash memory structure after the sidewalls and the first transistor and the second transistor are formed simultaneously according to an embodiment of the present invention.
[0028] Figure 7 This is a top view schematic diagram of an embedded flash memory with an SRAM polysilicon layer bend structure according to an embodiment of the present invention.
[0029] Figure 8This is a top view schematic diagram of an embedded flash memory with a straight SRAM polysilicon layer structure and left and right connections, according to an embodiment of the present invention.
[0030] Figure 9 This is a top view schematic diagram of the embedded flash memory structure with the opening position of the SRAM polysilicon layer cut off according to an embodiment of the present invention.
[0031] Figure 10 This is a top view of the embedded flash memory structure after the SRAM polysilicon layer is cut off, according to an embodiment of the present invention.
[0032] Figure 11 This is a SEM image of the first and second transistors in the SRAM region of an embodiment of the present invention.
[0033] In the figure: 10-substrate; 10a-flash memory region; 10b-SRAM region; 10c-logic region; 11-shallow trench isolation structure; 12-first gate structure; 12a-word line; 12b-floating gate; 13-sidewall material layer; 13a-sidewall; 14-polysilicon layer; 14a-first transistor; 14b-second transistor; 15-second gate structure; 16-third gate structure; 17-patterned photoresist layer. Detailed Implementation
[0034] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the present application. Repeated reference numerals may be used in the various embodiments; these repeated reference numerals are for simplicity and clarity only and do not indicate a relationship between the various embodiments.
[0035] Furthermore, in this application, spatial relationship terms such as "below," "under," "above," and "over" can be used to describe the relationship between one element and another in the accompanying drawings. In addition to the orientations shown in the drawings, these spatial relationship terms may also include different orientations of the device / structure during use (e.g., rotation of 90 degrees). The interpretation of the aforementioned spatial relationship terms should be adjusted accordingly for these different orientations.
[0036] In the description of this application, the term "connection" or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. For example, in this application, the formation of a first feature over a second feature can include direct or indirect contact between the first and second features.
[0037] In the embodiments described in this application, the term "about" or a term with an equivalent meaning can refer to a given number of values that vary within, for example, 10% of the value. It is understood that for numerical values not defined by terms such as "about" in this application, the numerical value may also have a certain range of fluctuation, provided that the desired technical effect of the embodiments of this application can be achieved, and the numerical values described in the embodiments are merely exemplary.
[0038] Figure 2 This is a flowchart illustrating a method for forming an embedded flash memory according to an embodiment of the present invention. Figure 2 As shown, this embodiment provides a method for forming embedded flash memory, including:
[0039] Step S10: A substrate is provided, the substrate including a flash memory region and an SRAM region, the flash memory region including a first gate structure located on the substrate;
[0040] Step S20: Form a sidewall material layer, the sidewall material layer covering the top and sidewalls of the first gate structure and the substrate of the flash memory region;
[0041] Step S30: Form a polysilicon layer, the polysilicon layer being located on the substrate of the SRAM region;
[0042] Step S40: Perform an etching process to etch the sidewall material layer of the flash memory region to form the sidewall of the first gate structure, and simultaneously etch the polysilicon layer of the SRAM region to form the first transistor and the second transistor with the target spacing in the SRAM region.
[0043] Figures 3 to 6 This is a schematic diagram showing the structural steps corresponding to the formation method of embedded flash memory according to an embodiment of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 3 to 6 Specific embodiments of the present invention will be described in detail below.
[0044] Figure 3 This is a schematic diagram of the embedded flash memory structure after the sidewall material layer is formed according to an embodiment of the present invention. Figure 3As shown, a substrate 10 is provided, the substrate 10 including a flash memory region 10a and an SRAM region 10b, a shallow trench isolation structure 11 is disposed between the flash memory region 10a and the SRAM region 10b, the shallow trench isolation structure 11 is used to isolate the flash memory region 10a and the SRAM region 10b. In some embodiments, the substrate 10 further includes a logic region 10c, the shallow trench isolation structure 11 is disposed between the flash memory region 10a, the SRAM region 10b and the logic region 10c, the shallow trench isolation structure 11 is used to isolate the flash memory region 10a, the SRAM region 10b and the logic region 10c. The flash memory region (flash cell) includes a first gate structure 12 located on the substrate 10, the first gate structure 12 including a word line 12a and a floating gate 12b, an isolation layer is formed between the word line 12a and the floating gate 12b.
[0045] Please continue to refer to this. Figure 3 A sidewall material layer 13 is formed, which covers the top and sidewalls of the first gate structure 12 and the substrate of the flash memory region. In some embodiments, the top and sidewalls of the first gate structure 12 are formed with a first sidewall (not shown in the figure), and the sidewall material layer 13 covers the first sidewall. The sidewall material layer 13 is used to form a second sidewall. The material of the first sidewall is, for example, silicon oxide, and the material of the sidewall material layer 13 is, for example, silicon nitride. The sidewall material layer 13 can be formed using a chemical vapor deposition process. Further, the sidewall material layer 13 is formed, which covers the top and sidewalls of the first gate structure 12 and the substrates of the flash memory region 10a, SRAM region 10b, and logic region 10c. Then, an etching process is performed to remove the sidewall material layer 13 on the substrates of the SRAM region 10b and logic region 10c, leaving only the top and sidewalls of the first gate structure 12 and the sidewall material layer 13 on the substrate of the flash memory region.
[0046] Figure 4 This is a schematic diagram of the embedded flash memory structure after forming the second gate structure and the polysilicon layer according to an embodiment of the present invention. Figure 4As shown, a polysilicon layer 14 is formed on the substrate of the SRAM region 10b. In some embodiments, the substrate 10 further includes a logic region 10c. During the formation of the polysilicon layer 14, a second gate structure 15 is simultaneously formed on the substrate of the logic region 10c. The second gate structure 15 is made of polysilicon and can be formed using a chemical vapor deposition process. In some embodiments, a third gate structure 16 is also formed on the substrate of the SRAM region 10b. The third gate structure 16 is made of polysilicon and can be formed using a chemical vapor deposition process. The third gate structure 16 can be a pull-down transistor or a memory transistor. That is, if the polysilicon layer 14 is subsequently used to form a pull-up transistor, then the third gate structure 16 can be a pull-down transistor or a memory transistor. If the polysilicon layer 14 is subsequently used to form a pull-down transistor, then the third gate structure 16 can be a memory transistor.
[0047] Figure 7 This is a top view schematic diagram of an embedded flash memory with an SRAM polysilicon layer bend structure according to an embodiment of the present invention. Figure 8 This is a top view schematic diagram of an embedded flash memory with a straight SRAM polysilicon layer structure and left-right connections, according to an embodiment of the present invention. Figure 7 As shown, the polysilicon layer 14 of the SRAM region comprises a first transistor 14a and a second transistor 14b with bent structures, and the bent structures of the first transistor 14a and the second transistor 14b are adjacent. In some processes, the bent structures of the adjacent first transistor 14a and the second transistor 14b may be short-circuited. For example... Figure 8 As shown, the polysilicon layer 14 of the SRAM region comprises a first transistor 14a and a second transistor 14b with straight-head structures, and the lengths of the straight-head structures of the first transistor 14a and the second transistor 14b are greater than the target length. The line ends of the straight-head structures of the first transistor 14a and the second transistor 14b are prone to photoresist shrinkage; therefore, the lengths of adjacent straight-head structures of the first transistor 14a and the second transistor 14b are pre-compensated (the compensation size is the subsequent shrinkage portion of the straight-head structure). In some embodiments, even adjacent straight-head structures of the first transistor 14a and the second transistor 14b are connected left and right. That is, the polysilicon layer 14 of the SRAM region is a continuous polysilicon layer greater than the sum of the target lengths of the first transistor 14a and the second transistor 14b. In this embodiment, the first transistor 14a and the second transistor 14b can both be pull-up transistors; in some embodiments, the first transistor 14a and the second transistor 14b can both be pull-down transistors.
[0048] Figure 5This is a schematic diagram of the embedded flash memory structure after forming a patterned photoresist layer according to an embodiment of the present invention. Figure 5 As shown, a patterned photoresist layer 17 is formed, which covers a portion of the polysilicon layer 14 of the SRAM region, the third gate structure 16, and the second gate structure 15 of the logic region 10c, and exposes a portion of the polysilicon layer 14 of the SRAM region, that is, exposes the polysilicon layer 14 of the SRAM region in the spacer region between the first transistor 14a and the second transistor 14b.
[0049] Figure 6 This is a schematic diagram of the embedded flash memory structure after simultaneously forming sidewalls and the first and second transistors according to an embodiment of the present invention. Figure 6 As shown, an etching process is performed to etch the sidewall material layer 13 of the flash memory region to form the sidewall 13a of the first gate structure. Simultaneously, the polysilicon layer 14 of the SRAM region is etched to form the first transistor 14a and the second transistor 14b with a target spacing in the SRAM region. The target spacing between the first transistor 14a and the second transistor 14b ensures that the first transistor 14a and the second transistor 14b are effectively disconnected and do not short-circuit. Etching the sidewall material layer 13 of the flash memory region includes etching the sidewall material layer on top of the first gate structure and the sidewall material layer 13 on the substrate of the flash memory region, while retaining the sidewall material layer 13 on the sidewall of the first gate structure 12 to form the sidewall 13a of the first gate structure.
[0050] Figure 9 This is a top view schematic diagram of the embedded flash memory structure with the opening position of the SRAM polysilicon layer cut off according to an embodiment of the present invention. Figure 10 This is a top view of the embedded flash memory structure after the SRAM polysilicon layer has been cut, according to an embodiment of the present invention. Figure 10 and Figure 6As shown. In the process of forming sidewall 13a by etching the sidewall material layer 13 of the flash memory region, the gap region between the first transistor 14a and the second transistor 14b of the SRAM region is simultaneously etched. Even if there is a short circuit in the bend structure of the first transistor 14a and the bend structure of the second transistor 14b of the SRAM region, the etching process is performed to etch the gap region between the bend structure of the first transistor 14a and the bend structure of the second transistor 14b and / or part of the bend structure of the first transistor 14a and part of the bend structure of the second transistor 14b, removing (breaking) the short circuit. Alternatively, the straight-head structure of the first transistor 14a and the straight-head structure of the second transistor 14b in the SRAM region can be connected left and right. An etching process is then performed to etch the gap area between the straight-head structures of the first transistor 14a and the second transistor 14b and / or a portion of the straight-head structure of the first transistor 14a and a portion of the straight-head structure of the second transistor 14b, so that the straight-head structures of the first transistor and the second transistor meet the target spacing, ensuring the isolation between the first transistor 14a and the second transistor 14b in the SRAM region. This avoids the problem of severe shrinkage of the straight-head structures of the first transistor 14a and the second transistor 14b in the SRAM region, and also avoids problems such as shrinkage of the bent structure and ion implantation shielding of the bent structure. The lengths of the straight-head structures of the first transistor 14a and the second transistor 14b in the SRAM region are greater than the target length, increasing the lengths of the straight-head structures of the first transistor 14a and the second transistor 14b in the SRAM region (the photoresist shrinkage portion of the straight-head structure is compensated for in advance during the formation of the polysilicon layer). After etching, the straight-head structures of the first transistor and the second transistor meet the target spacing, ensuring the isolation of the first transistor 14a and the second transistor 14b in the SRAM region. This avoids the problem of severe shrinkage of the straight-head structures of the first transistor 14a and the second transistor 14b in the SRAM region, and also avoids problems such as shrinkage of the bent structure and ion implantation shielding of the bent structure. In the prior art, the first transistor 14a and the second transistor 14b in the SRAM region are defined by a single photomask layer or by two separate photomasks. In this embodiment, the original single photomask layer is used, along with the photomask of the polysilicon layer originally defined for the word lines in the flash memory region 10a. In other words, the etching process in this embodiment does not require adding a mask or additional process steps. By combining front and back layers, the process weakness points are reduced without increasing the area.
[0051] Figure 11 This is a SEM image of two transistors in the SRAM region of an embodiment of the present invention. Figure 11As shown, the embedded flash memory formation method of this embodiment forms an SRAM region where the two transistors meet the target spacing, ensuring effective disconnection between the pull-up and pull-down transistors. This avoids the severe shrinkage problems of the straight-head structure of the first transistor 14a and the straight-head structure of the second transistor 14b in the SRAM region, and also avoids the shrinkage of the bent structure and the ion implantation shielding problems of the bent structure. Furthermore, the etching process in this embodiment does not require an additional mask or process steps. By combining front and back layers, it reduces process weaknesses without increasing the area.
[0052] Please continue to refer to this. Figure 6 This embodiment also provides an embedded flash memory, which is fabricated using the embedded flash memory formation method described in any of the above claims, including:
[0053] Substrate 10, the substrate 10 including flash memory region 10a, SRAM region 10b and logic region 10c;
[0054] Shallow trench isolation structure 11 is used to isolate flash memory region 10a, SRAM region 10b and logic region 10c;
[0055] A first gate structure 12 is located on the substrate of the flash memory region 10a. The first gate structure 12 includes a word line 12a and a floating gate 12b, and an isolation layer is formed between the word line 12a and the floating gate 12b.
[0056] Sidewall 13a, sidewall 13a covers the sidewall of the first gate structure 12;
[0057] The second gate structure 15 is located on the substrate of the logic region 10c;
[0058] The first transistor 14a is located on the substrate of the SRAM region 10b;
[0059] The second transistor 14b is located on the substrate of the SRAM region 10b and satisfies the target spacing with the first transistor 14a.
[0060] In summary, in the embedded flash memory formation method provided by this invention, during the process of etching the sidewall material layer of the flash memory region to form the sidewalls of the first gate structure, the polysilicon layer of the SRAM region is simultaneously etched to form the first transistor and the second transistor with a target pitch in the SRAM region. This invention, through different layers—that is, using the sidewall etching process currently employed in the flash memory region—simultaneously etches away the polysilicon layer of the SRAM region, ultimately creating the first and second transistors of the SRAM region with straight-end structures that do not shrink, or adjacent bend structures that are not short-circuited. The etching process of this invention does not require additional photomasks or process steps, and by combining preceding and following layers, it reduces process weaknesses without increasing the area.
[0061] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.
[0062] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for forming an embedded flash memory, characterized in that, include: A substrate is provided, the substrate including a flash memory region and an SRAM region, the flash memory region including a first gate structure located on the substrate; A sidewall material layer is formed, which covers the top and sidewalls of the first gate structure and the substrate of the flash memory region; A polysilicon layer is formed on the substrate of the SRAM region; An etching process is performed to etch the sidewall material layer of the flash memory region to form the sidewall of the first gate structure, while the polysilicon layer of the SRAM region is etched to form the first transistor and the second transistor with the target spacing in the SRAM region.
2. The method for forming embedded flash memory as described in claim 1, characterized in that, The polysilicon layer of the SRAM region consists of a first transistor and a second transistor with bend structures, and the bend structures of the first transistor and the second transistor are adjacent to each other.
3. The method for forming embedded flash memory as described in claim 2, characterized in that, Etching the polysilicon layer of the SRAM region includes etching the gap region between the bend structure of the first transistor and the bend structure of the second transistor and / or a portion of the bend structure of the first transistor and a portion of the bend structure of the second transistor, so that the bend structure of the first transistor and the bend structure of the second transistor meet the target spacing.
4. The method for forming embedded flash memory as described in claim 1, characterized in that, The polysilicon layer of the SRAM region consists of a first transistor and a second transistor with straight-head structures, and the lengths of the straight-head structures of the first transistor and the second transistor are greater than the target length.
5. The method for forming embedded flash memory as described in claim 4, characterized in that, Etching the polysilicon layer of the SRAM region includes etching the gap region between the straight head structure of the first transistor and the straight head structure of the second transistor and / or a portion of the straight head structure of the first transistor and a portion of the straight head structure of the second transistor, so that the straight head structure of the first transistor and the straight head structure of the second transistor meet the target spacing.
6. The method for forming embedded flash memory as described in claim 1, characterized in that, The polysilicon layer of the SRAM region is a continuous polysilicon layer that is greater than the sum of the target lengths of the first transistor and the second transistor.
7. The method for forming embedded flash memory as described in claim 6, characterized in that, Etching the polysilicon layer of the SRAM region includes etching the spacing region between the first transistor and the second transistor to ensure that the straight head structure of the first transistor and the straight head structure of the second transistor meet the target spacing.
8. The method for forming embedded flash memory as described in claim 1, characterized in that, The substrate further includes a logic region, which includes a second gate structure located on the substrate.
9. The method for forming embedded flash memory as described in claim 1, characterized in that, Etching the sidewall material layer of the flash memory region includes etching the top sidewall material layer of the first gate structure and the sidewall material layer on the substrate of the flash memory region, while retaining the sidewall material layer on the sidewall of the first gate structure to form the sidewall of the first gate structure.
10. An embedded flash memory, characterized in that, It is prepared by the method for forming embedded flash memory as described in any one of claims 1 to 9.