Semiconductor memory device

Abstract

A semiconductor memory device is provided having a full wrap-around gate structure in which a first channel layer at least partially surrounds a second channel layer.

Description

Technical Field

[0001] This invention relates to a semiconductor memory device. More specifically, this invention relates to a semiconductor memory device comprising a gate-all-around (GAA) structure. Background Technology

[0002] With the advancement of electronic technology, the miniaturization of semiconductor devices is progressing rapidly. Therefore, there is a need for miniaturization of memory cells, and existing memory cells may have limitations in maintaining high integration and reliability. Consequently, research has been conducted to develop semiconductor memory devices with structures that facilitate the miniaturization and high integration of memory cells. Summary of the Invention

[0003] Embodiments of the present invention provide a semiconductor memory device with a structure that promotes miniaturization and high integration of memory cells.

[0004] Furthermore, the inventive concept is not limited to the embodiments disclosed herein, and those skilled in the art can clearly understand the inventive concept from the following description.

[0005] Furthermore, the present invention provides a method for manufacturing a semiconductor memory device.

[0006] According to one aspect of the present invention, a semiconductor memory device is provided, the semiconductor memory device comprising: a memory cell disposed three-dimensionally on a substrate along a first direction, a second direction orthogonal to the first direction, and a third direction, the memory cell including a first transistor having a first channel layer and a second transistor having a second channel layer; a bit line electrically connected to a first end of the first channel layer and extending upward in the third direction; a select line electrically connected to a second end of the first channel layer and extending upward in the third direction; a memory node directly contacting a first surface of the second channel layer and adjacent to the first channel layer; and a word line located between the bit line and the select line, at least partially surrounding a second end of the first channel layer in the first and second directions, and extending in the first direction, wherein the word line has a cross-section in an annular shape surrounding the second end of the first channel layer and the second channel layer in a plane defined by the first and third directions, the first channel layer having a "C" shape in the plane defined by the second and third directions, and the memory node and the second channel layer being disposed within the "C" shape of the first channel layer.

[0007] According to another aspect of the present invention, a semiconductor memory device is provided, the semiconductor memory device comprising: a bit line extending on a substrate along a second direction intersecting a first direction; a first channel layer having a "U" shape in a plane defined by the second direction and a third direction perpendicular to an upper surface of the substrate, the first channel layer including a horizontally extending portion directly contacting an upper surface of the bit line and a vertically extending portion extending from an end of the horizontally extending portion along the third direction; and a second channel layer located within the "U" shape of the first channel layer, the second channel layer including a portion of the upper surface of the vertically extending portion... A coplanar upper surface and a lower surface opposite the upper surface; a storage node, the storage node including a first surface and a second surface opposite the first surface, wherein the first surface directly contacts the upper surface of the horizontal extension of the first channel layer, and the second surface directly contacts the lower surface of the second channel layer; a word line extending in a first direction and at least partially surrounding the side surface of the vertical extension of the first channel layer in an annular shape in both the first and second directions; and a select line directly contacting the upper surface of the second channel layer and overlapping the bit line in the third direction.

[0008] According to another aspect of the present invention, a semiconductor memory device is provided, the semiconductor memory device comprising: a plurality of memory cells arranged three-dimensionally on a substrate along a first direction, a second direction orthogonal to the first direction, and a third direction, each of the plurality of memory cells including a first transistor and a second transistor; a plurality of bit lines, each of the plurality of bit lines extending upward in the third direction; a plurality of select lines, each of the plurality of select lines extending upward in the third direction; a first channel layer included in the first transistor; a second channel layer included in the second transistor; and a memory node, wherein the first channel layer includes: a vertically extending portion extending upward in the third direction and directly contacting one of the plurality of bit lines, and a horizontally extending portion extending from both ends of the vertically extending portion along the second direction toward one of the plurality of select lines, and the horizontally extending portion... An extension portion is electrically connected to the select line, wherein the second channel layer is at least partially surrounded by the horizontal extension portion of the first channel layer and includes a first surface directly contacting the select line and a second surface facing the vertical extension portion of the first channel layer, wherein the memory node is at least partially surrounded by the horizontal extension portion of the first channel layer and includes a first surface directly contacting the second surface of the second channel layer and a second surface facing the vertical extension portion of the first channel layer, wherein the semiconductor memory device further includes a word line located between the bit line and the select line, at least partially surrounding the horizontal extension portion of the first channel layer in the first and second directions, and extending in the first direction, and wherein the word line has a cross-section in an annular shape surrounding the horizontal extension portion of the first channel layer and the second channel layer in a plane defined by the first and third directions.

[0009] According to another aspect of the present invention, a method of manufacturing a semiconductor memory device is provided, the method comprising: forming a trench in a molding layer disposed on a substrate, the trench including a protruding portion extending in a first direction and projecting in a second direction intersecting a first horizontal direction; forming a pad on a sidewall of the trench; forming a first channel layer conformally deposited along the sidewall of the protruding portion, the first channel layer including a horizontally extending portion extending in the second direction and a vertically extending portion extending upward in a third direction perpendicular to the first and second directions; forming a memory node that at least partially fills a portion of a region at least partially surrounded by the vertically extending portion and the horizontally extending portion of the first channel layer; A second channel layer is formed in the remaining portion of the region at least partially surrounded by the vertical extension and the horizontal extension of the first channel layer; a selection line is formed on the exposed surface of the second channel layer, and the selection line extends upward in the third direction; a word line is formed at least partially surrounding the horizontal extension of the first channel layer in the first direction and the second horizontal direction, and the word line extends in the first direction; and a bit line is formed on the vertical extension of the first channel layer, and the bit line extends upward in the third direction; wherein the vertical extension and the horizontal extension of the first channel layer have a "C" shape in a plane defined by the second direction and the third direction. Attached Figure Description

[0010] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A and Figure 8B This is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment; Figure 9A , Figure 9B , Figure 10A and Figure 10B This is a cross-sectional view showing a portion of a method for manufacturing a semiconductor memory device according to an embodiment; Figure 11 This is a perspective view showing a semiconductor memory device according to an embodiment; Figure 12 This is an equivalent circuit diagram showing a cell array of a semiconductor memory device according to an embodiment; Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A and Figure 16B This is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment. Detailed Implementation

[0011] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Throughout the drawings, the same reference numerals will be used to refer to the same or similar parts, and repeated descriptions of them are omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. It should be noted that, although no specific related description is provided, aspects described with respect to one embodiment may be incorporated into different embodiments. That is, features of all and / or any embodiment may be combined in any manner and / or combination.

[0012] The embodiments can be modified in various ways and have many different embodiments, and specific embodiments are shown in the accompanying drawings and specifically described in the detailed description of the embodiments. However, this is not intended to limit the scope of the inventive concept to the specific embodiments, and it should be understood to include various modifications, variations, equivalents, and substitutions within the spirit or scope of the disclosed inventive concept. In describing the embodiments, detailed descriptions of related known technologies are omitted unless specifically and explicitly necessary.

[0013] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A and Figure 8B This is a cross-sectional view sequentially illustrating a method for manufacturing a semiconductor memory device 100 according to an embodiment. Specifically, Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A They are along Figure 2B, Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B The horizontal cross-section diagram taken by line B-B', and Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B They are along Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A The vertical cross-section diagram taken by line A-A'.

[0014] refer to Figure 1A and Figure 1B A substrate insulating layer 112 can be formed on the substrate 110, and a first molding layer 114p and a second molding layer 116p can be alternately stacked on the substrate insulating layer 112 in a direction perpendicular to the substrate 110 (i.e., the Z direction or a third direction). In some embodiments, the first molding layer 114p may comprise an oxide, and the second molding layer 116p may comprise SiN. In some embodiments, the structure formed by stacking a plurality of first molding layers 114p and a plurality of second molding layers 116p can be referred to as a molding structure.

[0015] although Figure 1B The molded structure shown includes three first molding layers 114p spaced apart from each other in the vertical direction (Z direction) and two second molding layers 116p spaced apart from each other in the vertical direction (Z direction), but this is merely an example and embodiments of the inventive concept are not limited thereto.

[0016] Substrate 110 may include, for example, silicon (Si), such as crystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments, substrate 110 may include a semiconductor element such as germanium (Ge), or at least one compound semiconductor selected from silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and / or indium phosphide (InP). In other embodiments, substrate 110 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. Substrate 110 may include conductive regions, such as impurity-doped wells or impurity-doped structures.

[0017] The substrate insulating layer 112 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The substrate insulating layer 112 may include, for example, SiCN.

[0018] refer to Figure 2A and Figure 2B A first groove (not shown) may be formed that penetrates or extends into the molding structure in the vertical direction (Z direction). In some embodiments, after the first groove is formed, the first groove may be at least partially filled with a material similar to... Figure 1A and Figure 1B The first molding layer 114p shown is made of the same material. According to the above process, as... Figure 1A and Figure 1B Each of the second molding layers 116p shown can be divided into multiple second molding patterns 116 spaced apart from each other in an island shape at the same vertical (Z direction) height.

[0019] The second molded patterns 116 may be spaced apart from each other in a first horizontal direction (X direction or first direction) and may also be spaced apart from each other in a second horizontal direction (Y direction or second direction) orthogonal to the first horizontal direction (X direction). The distance between the second molded patterns 116 in the first horizontal direction (X direction) may be the same as or different from the distance between the second molded patterns 116 in the second horizontal direction (Y direction). The first molded pattern 114 may at least partially fill the space between the spaced-apart second molded patterns 116.

[0020] refer to Figure 3A and Figure 3B It can form a penetration or extension in the vertical direction (Z direction). Figure 2A and Figure 2B The second trench T2 in the resulting structure. In some embodiments, the second molding pattern 116 may be removed in the process of forming the second trench T2. In some embodiments, the SiN included in the second molding pattern 116 may be removed by a pull-back process. After the removal of the second molding pattern 116, a molding liner 116L that is at least partially conformally surrounding the sidewalls of the second trench T2 and has a thickness may be formed. The term “around” (or “encircle” or similar terms) as used herein is intended to refer generally to an element, structure, or layer that surrounds, encloses, surrounds, or encloses another element, structure, or layer extension on all sides, but gaps or gaps may also be present. Thus, for example, a material layer having voids or gaps may still “around” the other layer it surrounds. In some other embodiments, a portion of the second molding pattern 116 may not be removed in the pull-back process and may be retained as part of the molding liner 116L. Although for ease of illustration Figure 3A The text is omitted, but please refer to it. Figure 3B A molded insulating film 118 can be formed on the molded pad 116L.

[0021] The second trench T2 may be formed to extend along a first horizontal direction (X direction) and may be formed to have a plurality of protruding portions projecting in a second horizontal direction (Y direction). The protruding portions may be formed in a bilaterally symmetrical shape based on the extension portions on the left and right sides of the second trench T2. The substrate insulating layer 112 may be at least partially exposed on the bottom surface of the second trench T2. In some embodiments, the second trench T2 may extend into the substrate insulating layer 112.

[0022] refer to Figure 4A and Figure 4B This can form a first channel layer 120, a storage node 130, a second channel layer 140, and a selection line SL.

[0023] Specifically, the first channel layer 120 can be along, for example... Figure 3A and Figure 3B The sidewall of the protruding portion of the second trench T2 shown is formed in an approximately "C" shape. One sidewall of the first trench layer 120 may face as shown... Figure 3A and Figure 3B The sidewall of the second trench T2 is shown, and the other sidewall of the first trench layer 120 can face the storage node 130 and the second trench layer 140. For example... Figure 4A and Figure 4B As shown, an approximately “C”-shaped gate dielectric film 132, which at least partially surrounds the sidewall of the storage node 130 and the sidewall of the second channel layer 140, may be located between the other sidewall of the first channel layer 120 and the storage node 130 and the second channel layer 140.

[0024] One sidewall of storage node 130 may face the other sidewall of the first channel layer 120, and the other sidewall of storage node 130 may face a sidewall of the second channel layer 140.

[0025] Storage node 130 may include semiconductor materials and / or oxide semiconductor materials. For example, storage node 130 may include impurity-doped semiconductor materials and / or impurity-doped oxide semiconductor materials. In some embodiments, storage node 130 may include polycrystalline silicon material doped with n-type impurities and / or oxide semiconductor material doped with n-type impurities. For example, storage node 130 may include amorphous oxide semiconductor materials, single-crystal oxide semiconductor materials, polycrystalline oxide semiconductor materials, spinel oxide semiconductor materials, and / or C-axis oriented crystal (CAAC) oxide semiconductor materials. The oxide semiconductor material may be a binary or ternary oxide semiconductor material including a first metal element, a ternary oxide semiconductor material including a first metal element and a second metal element that are different from each other, or a quaternary oxide semiconductor material including a first metal element, a second metal element, and a third metal element that are different from each other. Binary or ternary oxide semiconductor materials may include, for example, zinc oxide (ZnO, Zn2O2). x O), gallium oxide (GaO, Ga x O), tin oxide (TiO, Ti) x O), zinc oxide (ZnON, Zn) x O y N), indium zinc oxide (IZO, In) x Zn y O), zinc gallium oxide (GZO, Ga) x Zn y O), zinc tin oxide (TZO, Sn) x Zn y O) and / or gallium tin oxide (TGO, Sn) x Ga y One or more of the following (O): , but the embodiments are not limited thereto. The quaternary oxide semiconductor material may include, for example, indium gallium zinc oxide (IGZO, In...). x Ga y Zn z O), indium gallium silicon oxide (IGSO, In) x Ga y Si z O), Indium tin zinc oxide (ITZO, In) x Sn y Zn z O), Indium tin gallium oxide (ITGO, In) x Sn y Ga z O), Zirconia zinc tin (ZZTO, Zr) x Zn y Sn z O), hafnium indium zinc oxide (HIZO, Hf) x In y Znz O), gallium zinc tin oxide (GZTO, Ga) x Zn y Sn z O), aluminum zinc tin oxide (AZTO, Al) x Zn y Sn z O) and / or ytterbium gallium zinc oxide (YGZO, Yb x Ga y Zn z One of O), but the embodiments are not limited thereto.

[0026] For example, storage node 130 may include a single layer or multiple layers of oxide semiconductor material.

[0027] One sidewall of the second channel layer 140 may face the other sidewall of the storage node 130, and the other sidewall of the second channel layer 140 may face one sidewall of the selection line SL. Figure 4B The vertical cross-section diagram taken along line A-A' and Figure 4A In the horizontal cross-sectional view taken along line B-B', the first channel layer 120 may have a shape that at least partially surrounds the second channel layer 140 in a "C" shape.

[0028] Multiple selection lines SL can extend in the vertical direction (Z direction) and are spaced apart from each other along a first horizontal direction (X direction) and a second horizontal direction (Y direction). In some embodiments, they can be located at the position of the protrusion forming the second groove T2 (see...). Figure 3A and Figure 3B A selection line SL is formed. One end of the selection line SL can be set at the same vertical height (Z direction) as the upper surface of the first molded pattern 114, and the other end can be set at the same vertical height (Z direction) as the upper surface of the substrate insulating layer 112.

[0029] One sidewall of the select line SL may contact the first channel layer 120, the gate dielectric film 132, and the second channel layer 140, and the other sidewall of the select line SL may face another adjacent select line SL in the second horizontal direction (Y direction). The first molded pattern 114 may at least partially fill the select lines SL that are spaced apart from each other along the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0030] The gate dielectric film 132 may include at least one material selected from silicon oxide, a high-k dielectric material with a dielectric constant higher than that of silicon oxide, and / or a ferroelectric material. In some embodiments, the gate dielectric film 132 may have a stacked structure of a first dielectric film of silicon oxide and a second dielectric film of at least one of a high-k dielectric material and / or a ferroelectric material. For example, high-k dielectric materials and ferroelectric materials may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxysilane (HfSiON), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxysilane (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO).

[0031] refer to Figure 4A The second width w2 can be greater than the first width w1. The second width w2 is the width of the selection line SL in the first horizontal direction (X direction), and the first width w1 is the width of the "C"-shaped first channel layer 120 in the first horizontal direction (X direction). In this case, in the first channel layer 120 including one extension along the first horizontal direction (X direction) and two extensions along the second horizontal direction (Y direction) facing each other, the first width w1 of the first channel layer 120 can represent the distance between the second surfaces of the two extensions along the second horizontal direction (Y direction), wherein the two extensions along the second horizontal direction have first surfaces facing each other and second surfaces opposite to the first surfaces. In some other embodiments, the second width w2 can be equal to the first width w1.

[0032] refer to Figure 4B The thickness of the first channel layer 120 in the second horizontal direction (Y direction) and the thickness of the first channel layer 120 in the vertical direction (Z direction) can be equal to each other, i.e., the first thickness t1. In some embodiments, the first channel layer 120 can be formed by atomic layer deposition (ALD) method, wherein, along such... Figure 3A and Figure 3B The thickness of the first channel layer deposited on the sidewall of the second trench T2 shown can be constant.

[0033] In some embodiments, the first channel layer 120 may be as follows: Figure 12The first transistor Tr1 is shown as having a channel layer, and the first transistor Tr1 can be an n-channel metal-oxide-semiconductor (NMOS) transistor. The second channel layer 140 can be as follows: Figure 12 The second transistor Tr2 is shown as having a channel layer, and Tr2 can be an NMOS transistor or a p-channel MOS (PMOS) transistor. The first transistor Tr1 may include a read transistor, and the second transistor Tr2 may include a write transistor. References will follow below. Figure 11 and Figure 12 Describe in detail the relationship between the first transistor Tr1 and the second transistor Tr2.

[0034] The first channel layer 120 and the second channel layer 140 may include semiconductor materials, such as oxide semiconductors. In some embodiments, the first channel layer 120 and the second channel layer 140 may include polycrystalline silicon or two-dimensional (2D) material semiconductors.

[0035] refer to Figure 5A and Figure 5B It can remove things like Figure 4A and Figure 4B A portion of the first molded pattern 114 shown. In some embodiments, such as... can be removed by an etching process. Figure 4A and Figure 4B The first molded pattern 114 is shown. According to the etching process, along as shown... Figure 3A and Figure 3B The molded liner 116L formed on the sidewall of the second trench T2 shown and the upper surface of the base insulation layer 112 can be at least partially exposed to the outside.

[0036] refer to Figure 6A and Figure 6B After removing the molding liner 116L and subsequently a portion of the molding insulating film 118, a cover insulating layer 122, having a conformal thickness, can be formed to cover the sidewalls of the first channel layer 120 in a "C" shape. As may be used herein, the term "cover" (or similar term) is intended to broadly refer to an element, structure, or layer that is directly on or over another element, structure, or layer, or has one or more other intermediate elements, structures, or layers between them. Next, a surrounding layer can be formed as... Figure 3A and Figure 3B The word line WL is at least a portion of the protruding part of the second groove T2 shown. The word line WL can be as follows: Figure 11 The form of the GAA shown is around, as Figure 3A and Figure 3B At least a portion of the protruding portion of the second groove T2 shown. In some embodiments, the insulating pad 124 may be located between the word line WL and the covering insulating layer 122.

[0037] and Figure 11 Let's refer to each other. Figure 6A and Figure 6B The word line WL may extend in a first horizontal direction (X direction) and may at least partially surround the second channel layer 140, while the select line SL may extend in a vertical direction (Z direction) relative to the substrate 110. In some embodiments, the word line WL may have a cross-section in a ring shape that at least partially surrounds the first channel layer 120 and the second channel layer 140 in a plane defined by the first horizontal direction (X direction) and the vertical direction (Z direction). However, although not shown in the figures, in some other embodiments, the word line WL may extend in the first horizontal direction (X direction) and at least partially surround only the upper surfaces of the first channel layer 120 and the second channel layer 140. In other embodiments, the word line WL may extend in the first horizontal direction (X direction) and, in the form of a sandwich, at least partially surround the upper and lower portions of the first channel layer 120 and the second channel layer 140.

[0038] Word lines (WL) can include doped polysilicon, metals, conductive metal nitrides, conductive metal silicides, or combinations thereof. For example, word lines (WL) can include, but are not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or combinations thereof.

[0039] refer to Figure 7A and Figure 7B The remaining space may be at least partially filled with the molded insulating layer 134, and a portion of the molded insulating layer 134 may be removed to form a bit line BL that contacts a sidewall of the first channel layer 120.

[0040] Multiple bit lines BL can extend in the vertical direction (Z direction) and are spaced apart from each other along a first horizontal direction (X direction) and a second horizontal direction (Y direction). In some embodiments, the bit lines BL can be formed such that the first channel layer 120 is located between the bit lines BL and the select line SL. That is, the extension portion of the first channel layer 120 in the first horizontal direction (X direction) can contact the bit lines BL. In some embodiments, the width of the bit lines BL in the first horizontal direction (X direction) can be greater than that of the first channel layer 120. Figure 4A The first width w1 is shown in the figure.

[0041] refer to Figure 7A The width of bit line BL in the first horizontal direction (X direction) is shown to be the same as the width of selection line SL in the first horizontal direction (X direction), but embodiments of the present invention are not limited thereto.

[0042] refer to Figure 7B The first channel layer 120 may have a first thickness t1 in the vertical direction (Z direction) and a second thickness t2 in the second horizontal direction (Y direction). Figure 4B Let's refer to each other. Figure 7B The first channel layer 120 can be like Figure 4B The layer is formed to have the same thickness in all directions, but in the process of etching a portion of the molded insulating layer 134 to form the bit line BL, a portion of the extension of the first channel layer 120 in the vertical direction (Z direction) can be etched together. Therefore, Figure 7B The second thickness t2 can be less than Figure 7B and Figure 4B The first thickness t1. However, embodiments of the present invention are not limited thereto. In some other embodiments, during the etching process of a portion of the molded insulating layer 134, the first trench layer 120 may not be etched, so that the second thickness t2 can remain the same as the first thickness t1.

[0043] refer to Figure 8A and Figure 8B , can Figure 7A and Figure 7B An upper insulating layer 136 is formed on the resulting structure, and a portion of the upper insulating layer 136 can be removed to form a plurality of word line pads PD1 and PD2. The plurality of word line pads PD1 and PD2 may include a first pad PD1 and a second pad PD2.

[0044] In some embodiments, one end of the first pad PD1 may be electrically connected to the bit line BL and the other end may be electrically connected to the first metal line ML1, and one end of the second pad PD2 may be electrically connected to the select line SL and the other end may be connected to the second metal line ML2.

[0045] exist Figure 8B In the diagram, the first metal wire ML1 is shown arranged at a higher vertical height (Z direction) than the second metal wire ML2, but this is to ensure that along the... Figure 8A The first metal line ML1 and the second metal line ML2 are shown simultaneously on the vertical cross-sectional view taken along line A-A'. The first metal line ML1 can be arranged at the same vertical height (Z direction) as the second metal line ML2. Furthermore, for the same reason as above, the vertical height (Z direction) of the first pad PD1 relative to the substrate, which serves as the base surface, can be the same as the vertical height of the second pad PD2. Additionally, in the top view, both the first metal line ML1 and the second metal line ML2 can extend in a direction perpendicular to the direction of the word line WL. For example, as... Figure 8AAs shown, the first metal line ML1 and the second metal line ML2 can be spaced apart from each other in the first horizontal direction (X direction) and can extend in the second horizontal direction (Y direction), and the word line WL can extend in the first horizontal direction (X direction).

[0046] The semiconductor memory device 100 with a three-dimensional structure can be manufactured using the above-described process. In some embodiments, the first metal line ML1 and the second metal line ML2 can constitute the back-end process (BEOL) of the semiconductor memory device 100.

[0047] A semiconductor memory device 100 according to an embodiment of the present invention may include a plurality of unit cells UC arranged in three dimensions along a first horizontal direction (X direction), a second horizontal direction (Y direction), and a vertical direction (Z direction), and therefore can have a high storage capacity. Furthermore, in the semiconductor memory device 100, Figure 12 The first channel layer 120 of the first transistor Tr1 in the middle can be at least partially surrounded in a "C" shape. Figure 12 The second channel layer 140 of the second transistor Tr2 in the memory device 100 allows information to be stored in the memory node 130 instead of in a capacitor, thus improving the device's integration density. Furthermore, the semiconductor memory device 100 may have bit lines BL and select lines SL extending in a vertical direction (Z direction) perpendicular to the substrate 110, and word lines WL of a GAA structure horizontally arranged between the bit lines BL and SL, thus enabling the semiconductor memory device 100 to have excellent gate controllability.

[0048] Figure 9A , Figure 9B , Figure 10A and Figure 10B This is a cross-sectional view showing a portion of a method for manufacturing a semiconductor memory device 100a according to an embodiment.

[0049] Specifically, Figure 9A and Figure 10A It is along Figure 9B and Figure 10B The horizontal cross-section diagram taken by line B-B', and Figure 9B and Figure 10B They are along Figure 9A and Figure 10A A vertical cross-sectional view taken along line A-A'. In the method for manufacturing semiconductor memory device 100a, reference is made to... Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B, Figure 6A and Figure 6B The described process can be compared with Figure 8A and 8B The semiconductor memory device 100 shown is implemented in the same manner, and only references Figure 7A , Figure 7B , Figure 8A and Figure 8B The processes described are different, so repeated descriptions will be omitted, and only the parts that differ in process and structure will be described.

[0050] refer to Figure 9A and Figure 9B , Figure 6A and Figure 6B The remaining space in the resulting structure can be at least partially filled with the molded insulating layer 134, and a portion of the molded insulating layer 134 can be removed to form multiple bit lines BL that extend in the vertical direction (Z direction) and are spaced apart from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0051] In some embodiments, a portion of the first channel layer 120 may be removed together with the process of removing a portion of the molding insulating layer 134 prior to forming the bit line BL. Specifically, the first horizontal (X-direction) extension of the first channel layer 120 may be removed.

[0052] Therefore, from Figure 6A and Figure 6B The diagram shows a first channel layer 120 with a "C"-shaped cross-section (this cross-section includes a first horizontal (X-direction) extension and a pair of second horizontal (Y-direction) extensions, wherein the pair of second horizontal (Y-direction) extensions extend from both ends of the first horizontal (X-direction) extension toward the selection line SL in the second horizontal (Y-direction) direction), serving as an execution reference. Figure 9A and Figure 9B The described process results in leaving only a pair of extensions spaced apart in the second horizontal direction (Y direction). Therefore, each end of the pair of extensions in the second horizontal direction (Y direction) can be electrically connected to the bit line BL perpendicularly (Z direction).

[0053] refer to Figure 9A The width of bit line BL in the first horizontal direction (X direction) is shown to be the same as the width of selection line SL in the first horizontal direction (X direction), but embodiments of the present invention are not limited thereto.

[0054] refer to Figure 10A and Figure 10B , can Figure 9A and Figure 9BAn upper insulating layer 136 is formed on the resulting structure, and a portion of the upper insulating layer 136 can be removed to form a plurality of word line pads PD1 and PD2. The plurality of word line pads PD1 and PD2 may include a first pad PD1 and a second pad PD2.

[0055] In some embodiments, one end of the first pad PD1 may be electrically connected to the bit line BL and the other end may be electrically connected to the first metal line ML1, and one end of the second pad PD2 may be electrically connected to the select line SL and the other end may be connected to the second metal line ML2.

[0056] A semiconductor memory device 100a with a three-dimensional structure can be manufactured using the above-described process. Detailed descriptions and references are provided regarding the first metal line ML1 and the second metal line ML2, the first pad PD1 and the second pad PD2, and the upper insulating layer 136. Figure 8A and Figure 8B The above is the same, therefore it can be omitted. Furthermore, similar to... Figure 8A and Figure 8B The semiconductor memory device 100 shown, in the top view, may have a first metal line ML1 and a second metal line ML2 extending in a direction perpendicular to the word line WL. For example, as Figure 10A As shown, the first metal line ML1 and the second metal line ML2 can be spaced apart from each other in the first horizontal direction (X direction) and can extend in the second horizontal direction (Y direction), and the word line WL can extend in the first horizontal direction (X direction).

[0057] Figure 11 This is a perspective view showing a semiconductor memory device 100 (and 100a) according to an embodiment. Figure 12 This is an equivalent circuit diagram showing the cell array of semiconductor memory devices 100 (and 100a) according to an embodiment.

[0058] Figure 11 The cross section of the unit cell UC shown in the 3D diagram can correspond to Figure 8B and Figure 10B The cross section of the unit element UC, and Figure 11 The circuit diagram of the unit cell UC shown in the 3D diagram can correspond to Figure 12 The circuit diagram of the unit UC.

[0059] Below, you can refer to Figure 11 and Figure 12 Describe the equivalent circuit diagram of a semiconductor memory device.

[0060] Semiconductor memory devices may include multiple unit cells (UCs). Figure 12A unit cell UC is shown as an example. The unit cell UC may include a pair of transistors, for example, a first transistor Tr1 and a second transistor Tr2. In some embodiments, each of the first transistor Tr1 and the second transistor Tr2 may include a field-effect transistor (FET).

[0061] In some embodiments, the channel layer of the first transistor Tr1 may correspond to Figure 8A , Figure 8B , Figure 10A , Figure 10B and Figure 11 The first channel layer 120, and the channel layer of the second transistor Tr2 can correspond to Figure 8A , Figure 8B , Figure 10A , Figure 10B and Figure 11 The second channel layer 140.

[0062] Each unit cell UC in a semiconductor memory device can operate as a dynamic random access memory (DRAM) cell, where write operations for storing information and read operations for retrieving information are performed. The unit cell UC can replace a capacitor in, for example... Figure 11 Information is stored in the storage node 130 shown. A semiconductor memory device comprising multiple unit cells UC can be referred to as a DRAM device on a floating gate substrate. A semiconductor memory device comprising multiple unit cells UC can also include a volatile semiconductor memory device.

[0063] In some embodiments, word lines WL may be electrically connected to the gate lines of each of the first transistor Tr1 and the second transistor Tr2 included in a plurality of unit cells UC. In some embodiments, the plurality of word lines WL may extend in a first horizontal direction and be spaced apart from each other in a second horizontal direction orthogonal to the first horizontal direction. Although in Figure 12 Not shown, but the gate line of each of the first transistor Tr1 and the second transistor Tr2 may extend in a vertical direction orthogonal to the first horizontal direction and the second horizontal direction.

[0064] One end of the channel region of the first transistor Tr1 can be electrically coupled to the bit line BL, and the other end can be electrically coupled to the select line SL. For example... Figure 11 As shown, one end of the channel region of the second transistor Tr2 can be electrically coupled to the memory node 130, and the other end can be electrically coupled to the select line SL. In some embodiments, each of the bit line BL and the select line SL can extend in the vertical direction.

[0065] The second transistor Tr2 can store charge in storage node 130. Depending on the amount of charge stored in storage node 130, the threshold voltage of the first transistor Tr1, which acts as a floating gate in storage node 130, can be changed, and the information stored in unit cell UC can be read as "0" or "1" based on the threshold voltage of the first transistor Tr1 determined by the amount of charge stored in storage node 130. For example, the second transistor Tr2 of a unit cell UC can be selected by a word line WL and a bit line BL to store charge in storage node 130. Alternatively, the first transistor Tr1 of a unit cell UC can be selected by a word line WL, a bit line BL, and a select line SL, and the information stored in unit cell UC can be read based on the threshold voltage of the first transistor Tr1 determined by the amount of charge stored in storage node 130. The first transistor Tr1 can be referred to as the read transistor, and the second transistor Tr2 can be referred to as the write transistor. The unit cell UC can be referred to as a 2T memory cell.

[0066] Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A and Figure 16B This is a cross-sectional view sequentially illustrating a method for manufacturing a semiconductor memory device 100b according to an embodiment. Specifically, Figure 13A , Figure 14A , Figure 15A and Figure 16A It is along Figure 13B , Figure 14B , Figure 15B and Figure 16B The horizontal cross-section diagram taken by line B-B', and Figure 13B , Figure 14B , Figure 15B and Figure 16B It is along Figure 13A , Figure 14A , Figure 15A and Figure 16A The vertical cross-section diagram taken by line A-A'.

[0067] Will understand, refer to Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A and Figure 16B The components described in the method for manufacturing semiconductor memory device 100b are similar to those in the reference. Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A and Figure 8B as well as Figure 9A , Figure 9B , Figure 10A and Figure 10B The components described in the methods for manufacturing semiconductor memory devices 100 and 100a are not mutually exclusive, and components having the same reference numerals are identical components. (Refer to reference...) Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A and Figure 8B The semiconductor memory device 100 described and the reference Figure 9A , Figure 9B , Figure 10A and Figure 10B Compared to the semiconductor memory device 100a described, the reference... Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A and Figure 16B The described semiconductor memory device 100b may have structural differences between components rather than functional differences. Specifically, semiconductor memory devices 100 and 100a may have 3D structures, and refer to... Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A and Figure 16B The described semiconductor memory device 100b may have a vertical channel transistor (VCT) structure. In the following text, repeated descriptions of the same components will be simplified or omitted, and the main focus will be on describing... Figure 1A , Figure 1B , Figure 2A, Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A and Figure 8B Semiconductor memory device 100 and Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A and Figure 16B Structural differences between semiconductor memory devices 100b.

[0068] refer to Figure 13A and Figure 13B Multiple bit lines BL can be formed on the substrate 110. Each bit line in the multiple bit lines BL can be spaced apart from each other in a first horizontal direction (X direction) and extend in a second horizontal direction (Y direction).

[0069] refer to Figure 14A and Figure 14B A first molded insulating layer 152 and a second molded insulating layer 154 can be formed on the bit line BL. A third trench T3 can be formed by removing portions of the first molded insulating layer 152 and the second molded insulating layer 154. A first channel layer 120 can then be formed by conformally covering at least partially the sidewalls and bottom surface of the third trench T3.

[0070] refer to Figure 14B A third trench T3 with a "U"-shaped cross-section can be formed, and by forming the third trench T3, the upper surface of the bit line BL can be exposed at least partially. A first channel layer 120 can be formed along the third trench T3, and the first channel layer 120 can be deposited with a "U"-shaped cross-section similar to the third trench T3.

[0071] After forming the first channel layer 120, a memory node 130 may be formed to fill at least a portion of the remaining space of the third trench T3, and then a second channel layer 140 may be formed on the memory node 130 to fill at least partially the entire remaining space of the third trench T3. In some embodiments, a gate dielectric film 156 may be located between the first channel layer 120 and the memory node 130, and between the first channel layer 120 and the second channel layer 140. In some embodiments, the upper surface of the second channel layer 140 may be located at the same vertical height (Z direction) as the upper surface of the second molded insulating layer 154.

[0072] Reference as along Figure 14B The horizontal cross-section diagram intercepted by line B-B' Figure 14A The second channel layer 140 may be disposed within the first channel layer 120 which is at least partially surrounded in a rectangular shape around the third trench T3, and the four side surfaces of the second channel layer 140 may be at least partially surrounded on all sides by the gate dielectric film 156.

[0073] The first channel layer 120 can be formed in a "U" shape around the second channel layer 140 based on a vertical cross section, and it can be structurally similar to Figure 8A and Figure 8B The semiconductor memory device 100 (wherein, the first channel layer 120 is formed in a “C” shape based on a vertical cross section to at least partially surround the second channel layer 140).

[0074] In some embodiments, the first channel layer 120 may be as follows: Figure 12 The first transistor Tr1 shown has a channel layer, and the second channel layer 140 can be as follows: Figure 12 The channel layer of the second transistor Tr2 is shown.

[0075] refer to Figure 15A and Figure 15B It can remove things like Figure 14A and Figure 14B The second molded insulating layer 154 shown can be formed into a cover insulating layer 158 that at least partially covers the upper surface of the first molded insulating layer 152 and the side surfaces of the first channel layer 120. Then, as shown... Figure 15A and Figure 15B The word line WL is shown to at least partially surround the third groove T3. Next, a third molded insulating layer 162 may be formed to at least partially surround the word line WL and the covering insulating layer 158. In some embodiments, an insulating pad 159 may be additionally disposed between the word line WL and the covering insulating layer 158. In some embodiments, the third molded insulating layer 162 may include, as shown... Figure 14A and Figure 14B The second molded insulating layer 154 shown is made of essentially the same material.

[0076] like Figure 15B As shown, the word line WL can be formed in the form of a GAA that at least partially surrounds the first channel layer 120 in all directions at a predetermined height. This predetermined height is a vertical height lower than the upper surface of the vertical extension of the first channel layer 120 relative to the substrate 110, and the word line WL can correspond to Figure 12 The letter line WL.

[0077] refer to Figure 16A and Figure 16B , can Figure 15A and Figure 15B Select lines SL are formed on the resulting structure. Multiple select lines SL can be formed at the locations where select lines SL and multiple bit lines BL overlap in the vertical direction (Z direction), can extend in the second horizontal direction (Y direction), and can be spaced apart from each other in the first horizontal direction (X direction). In some embodiments, the space where multiple select lines SL are not formed can be at least partially filled with a buried insulating layer 164. Through the above process, a semiconductor memory device 100b including a vertical channel structure can be formed.

[0078] Figure 16A and Figure 16B The semiconductor memory device 100b can have a 2T memory cell structure similar to the semiconductor memory devices 100 and 100A described above, and can store information in memory nodes 130 instead of capacitors, thus it is expected to achieve high device integration. Furthermore, the word line WL can be formed in the form of a GAA, and the semiconductor memory device 100b can have a structure in which the first channel layer 120 at least partially surrounds the second channel layer 140 in a "U" shape (or, depending on its orientation, in a "C" shape).

[0079] In some embodiments, one end of the first channel layer 120 may contact the bit line BL, and the other end may contact the select line SL. One end of the second channel layer 140 may contact the select line SL, and the other end may contact the memory node 130.

[0080] Figure 16A and Figure 16B The semiconductor memory device 100b may have a VCT structure. Specifically, the semiconductor memory device 100b may include: a bit line BL extending in a direction parallel to the upper surface of the substrate 110; a select line SL arranged to overlap the bit line BL perpendicularly (in the Z direction) at a vertical height higher than the bit line BL relative to a reference plane provided by the substrate 110; a first channel layer 120 disposed between the bit line BL and the select line SL; a second channel layer 140 at least partially surrounded by the first channel layer 120 on three sides; and a word line WL in the form of a GAA.

[0081] As described above, embodiments have been disclosed in the accompanying drawings and specification. Although specific terms have been used to describe embodiments in this specification, they are for illustrative purposes only and are not intended to limit the meaning or scope of the inventive concept set forth in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent embodiments are possible from the embodiments disclosed herein. Consequently, the scope of the inventive concept should be determined by the appended claims.

[0082] Although embodiments of the inventive concept have been shown and described with reference to them, it will be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A memory cell is arranged three-dimensionally on a substrate along a first direction, a second direction orthogonal to the first direction, and a third direction. The memory cell includes a first transistor having a first channel layer and a second transistor having a second channel layer. Bit lines, which are electrically connected to a first end of the first channel layer and extend upward thereon; Selection line, the selection line being electrically connected to a second end of the first channel layer and extending upward thereon; A storage node that directly contacts the first surface of the second channel layer and is adjacent to the first channel layer; and A word line, located between the bit line and the select line, at least partially surrounding the second end of the first channel layer in both the first and second directions, and extending in the first direction. Wherein, the word line has a cross-section in a ring shape surrounding the second end of the first channel layer and the second channel layer in a plane defined by the first direction and the third direction, and The first channel layer has a "C" shape in a plane defined by the second direction and the third direction, and the storage node and the second channel layer are arranged inside the "C" shape of the first channel layer.

2. The semiconductor memory device according to claim 1, wherein, The first transistor includes a read transistor, and the second transistor includes a write transistor.

3. The semiconductor memory device according to claim 1, wherein, The first transistor includes an n-channel metal-oxide-semiconductor transistor, and the second transistor includes an n-channel metal-oxide-semiconductor transistor or a p-channel metal-oxide-semiconductor transistor.

4. The semiconductor memory device according to claim 1, wherein, The second surface of the second channel layer, which is opposite to the first surface, directly contacts the selection line.

5. The semiconductor memory device according to claim 1, wherein, The first channel layer includes a vertically extending portion, a first horizontally extending portion connected to one end of the vertically extending portion, and a second horizontally extending portion connected to the other end of the vertically extending portion. The thickness of the first horizontal extension is the same as the thickness of the second horizontal extension, and the thickness of the vertical extension is less than the thickness of the first horizontal extension and the thickness of the second horizontal extension.

6. The semiconductor memory device according to claim 1, wherein, The first channel layer includes a vertically extending portion, a first horizontally extending portion connected to one end of the vertically extending portion, and a second horizontally extending portion connected to the other end of the vertically extending portion. The thicknesses of the first horizontal extension, the second horizontal extension, and the vertical extension are equal.

7. The semiconductor memory device according to claim 1, wherein, One end of the bit line directly contacts the substrate, and the other end of the bit line is electrically connected to the first metal line via the first pad. One end of the select line is in direct contact with the substrate, and the other end of the select line is electrically connected to the second metal line via the second pad, and the first metal line and the second metal line extend in the second direction.

8. The semiconductor memory device according to claim 1, further comprising: A gate dielectric film is disposed between the first channel layer and the memory node, and between the first channel layer and the second channel layer.

9. The semiconductor memory device according to claim 1, wherein, Both the first channel layer and the second channel layer comprise oxide semiconductors, polycrystalline silicon, two-dimensional material semiconductors, or combinations thereof.

10. The semiconductor memory device according to claim 1, wherein, The storage node includes the floating gate of the first transistor.

11. A semiconductor memory device, the semiconductor memory device comprising: Bit lines extend on the substrate along a second direction that intersects the first direction; A first channel layer having a "U" shape in a plane defined by the second direction and a third direction perpendicular to the upper surface of the substrate, the first channel layer including a horizontally extending portion that directly contacts the upper surface of the bit line and a vertically extending portion that extends from the end of the horizontally extending portion along the third direction. The second channel layer is located inside the "U" shape of the first channel layer, and the second channel layer includes an upper surface that is coplanar with the upper surface of the vertical extension portion and a lower surface that is opposite to the upper surface. A storage node, the storage node including a first surface and a second surface opposite to the first surface, wherein the first surface directly contacts the upper surface of the horizontal extension of the first channel layer, and the second surface directly contacts the lower surface of the second channel layer; A letter line extending in the first direction and at least partially surrounding the side surface of the vertically extending portion of the first channel layer in an annular shape in both the first and second directions; and The selection line directly contacts the upper surface of the second channel layer and overlaps with the bit line in the third direction.

12. The semiconductor memory device according to claim 11, wherein, The semiconductor memory device includes a first transistor and a second transistor, wherein the first transistor includes a first channel layer and the second transistor includes a second channel layer.

13. The semiconductor memory device according to claim 12, wherein, The first transistor includes a read transistor, and the second transistor includes a write transistor.

14. The semiconductor memory device according to claim 11, wherein, The upper surface of the word line is farther from the substrate than the lower surface of the second channel layer, and closer to the substrate than the upper surface of the second channel layer.

15. The semiconductor memory device of claim 11, further comprising: An insulating cover is provided, which is located between the vertical extension of the first channel layer and the word line, and at least partially surrounds the side surface of the vertical extension.

16. A semiconductor memory device, the semiconductor memory device comprising: A plurality of memory cells are arranged in three dimensions on a substrate along a first direction, a second direction orthogonal to the first direction, and a third direction, and each of the plurality of memory cells includes a first transistor and a second transistor; Multiple bit lines, each of which extends upward on the third party; Multiple selection lines, each of which extends upwards from the third party; A first channel layer, the first channel layer being included in the first transistor; A second channel layer is included in the second transistor; as well as Storage nodes, The first channel layer includes: a vertically extending portion extending upward from the third party and directly contacting one of the plurality of bit lines; and a horizontally extending portion extending from both ends of the vertically extending portion along a second direction toward one of the plurality of select lines, wherein the horizontally extending portion is electrically connected to the select line. The second channel layer is at least partially surrounded by the horizontal extension of the first channel layer, and includes a first surface that directly contacts the selection line and a second surface that faces the vertical extension of the first channel layer. The storage node is at least partially surrounded by the horizontal extension of the first channel layer and includes a first surface that directly contacts the second surface of the second channel layer and a second surface that faces the vertical extension of the first channel layer. The semiconductor memory device further includes a word line located between the bit line and the select line, at least partially surrounding a horizontally extending portion of the first channel layer in both the first and second directions, and extending in the first direction. The word line has a horizontally extending portion in a ring shape surrounding the first channel layer and the second channel layer in a plane defined by the first direction and the third direction.

17. The semiconductor memory device according to claim 16, wherein, The first transistor includes a read transistor, and the second transistor includes a write transistor.

18. The semiconductor memory device according to claim 16, wherein, One end of the bit line directly contacts the substrate, and the other end of the bit line is electrically connected to the first metal line via the first pad. One end of the select line is in direct contact with the substrate, and the other end of the select line is electrically connected to the second metal line via the second pad, and the first metal line and the second metal line extend in the second direction.

19. The semiconductor memory device according to claim 16, wherein, Both the first channel layer and the second channel layer comprise oxide semiconductors, polycrystalline silicon, two-dimensional material semiconductors, or combinations thereof.

20. The semiconductor memory device according to claim 16, wherein, The width of the vertical extension portion of the first channel layer is not greater than the width of the horizontal extension portion of the first channel layer.

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