Composite igbt power semiconductor chip standard sample plate, preparation method and test method
By preparing and testing standard prototypes of composite IGBT power semiconductor chips, the problems of high cost and insufficient measurement accuracy of single-type prototypes in existing technologies are solved, and multi-size calibration and efficient testing are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- THE 13TH RES INST OF CHINA ELECTRONICS TECH GRP CORP
- Filing Date
- 2026-03-24
- Publication Date
- 2026-07-10
AI Technical Summary
Existing IGBT/SiC power chip standard samples are mostly of a single size and type, which is costly, and the measurement accuracy and consistency of measuring instruments are limited by the lack of traceability chain and the accumulation of length value transmission errors.
A standard prototype of a composite IGBT power semiconductor chip is designed, comprising a substrate and a dielectric layer. A stepped structure region, a thin film structure region, and a grating structure region are sequentially arranged on the dielectric layer. Tracking markers are set in each region. A silicon carbide wafer is used as the substrate material. The prototype is prepared through steps such as cleaning, drying, growing the dielectric layer, coating photoresist, and dry etching. The prototype is tested and calibrated using a traceable atomic force microscope.
It integrates multi-size calibration requirements, significantly reduces testing costs, improves measurement accuracy and consistency, and meets the high-precision requirements of IGBT chip manufacturing.
Smart Images
Figure CN122373381A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of nanometerization technology, and in particular to a standard template for a composite IGBT power semiconductor chip, its preparation method, and its testing method. Background Technology
[0002] Power semiconductors are core components in power electronic devices, enabling power conversion and circuit control. Depending on the voltage, power, and frequency selected, they are widely used in new energy vehicles, photovoltaics, wind power, energy storage, charging piles, power grids, railways, industry, communications, and consumer electronics. In particular, the deepening of the new round of technological and industrial revolutions, driven by the transformation of new energy sources, has led to a continuous increase in demand for next-generation IGBT / SiC power semiconductors. For the manufacturing and packaging processes of next-generation trench-gate IGBT / SiC power semiconductors, metrology and testing are crucial for ensuring the yield of power semiconductor chips and modules. These processes are integral to the entire production flow, and high-quality chip manufacturing and module packaging require a large number of sophisticated testing equipment as the primary quality assurance.
[0003] Currently, the most widely used IGBT / SiC power chips utilize a trench gate as their key structure. This trench gate is a complex, multi-dimensional structure encompassing trench width, trench depth, cell spacing, and gate oxide thickness. Typically, the trench width ranges from 0.5μm to 2μm, the depth from 2μm to 10μm, the cell spacing from 3μm to 6μm, and the gate oxide thickness from 50nm to 200nm. The accuracy of these structural dimensions needs to be controlled within ±5%, otherwise, their reliability will be severely affected. With the continuous advancement of IGBT power chip manufacturing processes, the dimensions of its key structures are becoming increasingly smaller, making the demand for accuracy and consistency in micro- and nano-scale measurements increasingly urgent. Micro- and nano-scale measurements require a continuous, uninterrupted length traceability chain connected to the definition of a "meter." Therefore, the absence of this traceability chain or the accumulation of errors during length value transfer can reduce the accuracy, consistency, and comparability of measuring instruments, thus limiting chip manufacturing precision. Micro- and nano-scale geometric standard materials, as preferred physical measurement standards, are widely used in the calibration and measurement of precision instruments in the semiconductor industry.
[0004] Currently, many existing technologies have produced a number of standard templates of relevant dimensions, but these standard templates are all of a single size and type, and the cost of a single template is relatively high. Summary of the Invention
[0005] This invention provides a standard template, preparation method, and testing method for a composite IGBT power semiconductor chip, which solves the problems in the prior art where standard templates are all of a single size and type, and the cost of a single template is high.
[0006] This invention provides a method for preparing a standard sample, comprising: Substrate and dielectric layer; Within the effective area of the dielectric layer, from top to bottom, there are coaxially aligned stepped structure area, thin film structure area, and grating structure area. The thin film structure region includes at least two thin film structures with different thicknesses; the step structure region includes at least two step structures with different heights; and the grating structure region includes at least one grating structure. Tracking markers are installed in the stepped structure area, the thin film structure area, and the grating structure area.
[0007] In one possible implementation, the thin film structure region includes two thin film structures with different thicknesses; the stepped structure region includes two stepped structures with different heights; and the grating structure region includes three grating structures of the same size. Each side of the thin film structure area has a tracking marker; each side of each step structure has a tracking marker; and each side of each grating structure has a tracking marker.
[0008] In one possible implementation, the thicknesses of the two thin film structures are 48 nm and 96 nm, respectively, the grating period size of the grating structure is 800 nm, and the heights of the two step structures are 48 nm and 96 nm, respectively.
[0009] In one possible implementation, the thin film structure region includes four thin film structures of different thicknesses; the step structure region includes four step structures of different heights; the grating structure region includes two sets of grating structures with different grating period sizes; each set of grating structures includes at least one grating structure. Each side of the thin film structure area has a tracking marker; each side of each step structure has a tracking marker; and each side of each grating structure has a tracking marker.
[0010] In one possible implementation, the thicknesses of the four thin film structures are 48 nm, 96 nm, 150 nm and 200 nm, respectively; the grating period sizes of the two sets of grating structures are 800 nm and 4 μm, respectively; and the heights of the four step structures are 48 nm, 96 nm, 150 nm and 200 nm, respectively.
[0011] A second aspect of the present invention provides a method for preparing a standard template, which is used to prepare a standard template of the composite IGBT power semiconductor chip as described in the first aspect above; the standard template has a corresponding pattern design scheme with multiple preparation areas, each preparation area corresponding to a pattern structure of a certain size, and the method includes: Silicon carbide wafers are used as substrate materials, and the wafers are cleaned and dried. Growing a dielectric layer on a substrate material; Photoresist is coated onto the surface of the dielectric layer; Based on the pattern structure corresponding to a certain preparation area, the photoresist in the light-transmitting area is removed, and dry etching technology is used for etching; wherein, the mask used in the photolithography process is a genuine mask; Remove the photoresist in the non-transparent areas to complete the fabrication of the pattern structure corresponding to the current fabrication area; Photoresist is coated onto the surface of the current fabrication area, and the process proceeds to the step of growing a dielectric layer on the silicon carbide wafer to fabricate the next fabrication area, until all patterned structures are fabricated.
[0012] In one possible implementation, a silicon carbide wafer is used as the substrate material, and the wafer is cleaned and dried, including: Using silicon carbide wafers as substrate material, the substrate material is boiled in a first cleaning solution at a preset time and temperature; Rinse the substrate material with water until neutral; The substrate material was rinsed in hydrofluoric acid; Rinse the substrate material with water until neutral; The substrate material is boiled in the second cleaning solution at a preset time and temperature. Rinse the substrate material with water until neutral; The substrate material was dried using filtered nitrogen gas. The first cleaning solution consists of water, ammonia, and hydrogen peroxide in a volume ratio of 4:1:1; the second cleaning solution consists of water, hydrochloric acid, and hydrogen peroxide in a volume ratio of 4:1:1.
[0013] In one possible implementation, based on the pattern structure corresponding to a certain fabrication area, the photoresist in the light-transmitting area is removed, and etching is performed using a dry etching technique, including: The photolithographically etched substrate material is placed in a NaOH solution to remove the photoresist in the light-transmitting areas; Bake the substrate material; The substrate material is etched using dry etching technology.
[0014] In one possible implementation, the etching gas is SF6 or C4F8; the etching rate is set to 15nm / min-20nm / min; and the etching depth is the thickness of the dielectric layer.
[0015] A third aspect of the present invention provides a test and calibration method for a standard template, the method being used to test the composite IGBT power semiconductor chip standard template as described in the first aspect above; the method includes: A standard template is placed on the sample stage of a traceable atomic force microscope, and the step structure area to be measured is located according to the tracking marks set on the standard template to obtain the final value of the step height. The traceable atomic force microscope consists of X, Y, and Z direction laser interferometers and X, Y, and Z direction goniometers. The final value of the step height is used as the final value of the film thickness. The grating structure area is located according to the tracking markers set on the standard template for testing, and the final value of the grating period size is obtained.
[0016] Compared to traditional technologies, this invention provides a composite IGBT power semiconductor chip standard template, its fabrication method, and its testing method. The standard template includes a substrate and a dielectric layer. Within the effective region of the dielectric layer, coaxially aligned stepped structure region, thin film structure region, and grating structure region are sequentially arranged from top to bottom. The thin film structure region includes at least two thin film structures of different thicknesses; the stepped structure region includes at least two stepped structures of different heights; and the grating structure region includes at least one grating structure. Tracking markers are provided in the stepped structure region, thin film structure region, and grating structure region. The standard template provided by this invention is a composite structure, integrating the stepped structure region, thin film structure region, and grating structure region within the effective region of the dielectric layer on the same substrate. It can meet multi-size calibration requirements, significantly reducing the number of standard templates used and substantially lowering testing costs. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the structure of the composite IGBT power semiconductor chip standard template provided in the embodiments of the present invention; Figure 2 This is a flowchart illustrating the implementation of the standard sample preparation method provided in this embodiment of the invention. Figure 3 This is a flowchart illustrating the implementation of a standard sample preparation method provided in another embodiment of the present invention. Detailed Implementation
[0018] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0019] Figure 1 This is a schematic diagram of the structure of a standard template for a composite IGBT power semiconductor chip provided in an embodiment of the present invention. Figure 1 As shown, a standard template for a composite IGBT power semiconductor chip includes: a substrate and a dielectric layer; Within the effective area of the dielectric layer, from top to bottom, there are coaxially aligned stepped structure region 1, thin film structure region 2, and grating structure region 3. The thin film structure region 2 includes at least two thin film structures 4 with different thicknesses; the step structure region 1 includes at least two step structures 5 with different heights; and the grating structure region 3 includes at least one grating structure 6. Tracking markers 7 are provided in the stepped structure area 1, the thin film structure area 2, and the grating structure area 3.
[0020] In this embodiment of the invention, silicon carbide is used as the substrate material, and the dielectric layer is made of silicon dioxide or silicon nitride. The overall size is 10mm × 10mm. The effective measurement area of the dielectric layer is arranged in a coaxial layout, with a stepped structure area, a thin film structure area, and a grating structure area arranged sequentially. Each of the three functional areas is equipped with a dedicated tracking marker, which facilitates rapid positioning and accurate measurement by micro-nano testing instruments. The tracking markers of each structural area cooperate with the indicator marks of the thin film structure area, allowing the measurement equipment to quickly identify the position of each functional area and the measurement target point, ensuring the accuracy and efficiency of micro-nano scale measurements. The overall prototype realizes the composite integration of multiple structures, types, and sizes of film thickness, steps, and gratings, adapting to the comprehensive calibration requirements of IGBT power semiconductor chip geometric feature measurement systems.
[0021] The structure within the effective area of the present invention will be described below through two embodiments, but these are not intended to be limiting.
[0022] Example 1: In some embodiments, the thin film structure region includes two thin film structures with different thicknesses; the step structure region includes two step structures with different heights; the grating structure region includes three grating structures of the same size; a tracking marker is provided on each side of the thin film structure region; a tracking marker is provided on each side of each step structure; and a tracking marker is provided on each side of each grating structure.
[0023] In this embodiment of the invention, the stepped structure area, the thin film structure area, and the grating structure area are coaxially aligned along the effective area of the dielectric layer. The thin film structure area is centrally located and additionally equipped with a dedicated indicator mark. This mark can assist the measuring device in quickly identifying the core film thickness measurement area. The stepped structure area is located directly above the thin film structure area, and the grating structure area is located directly below the thin film structure area. Each tracking mark is precisely aligned with its corresponding structural unit. Its function is to provide a clear positioning reference for micro-nano measuring instruments, guide the probe to quickly find the structure to be measured, avoid measurement errors caused by positioning deviations, and greatly improve measurement efficiency and positioning accuracy.
[0024] In some embodiments, the thicknesses of the two thin film structures are 48 nm and 96 nm, respectively, the grating period size of the grating structure is 800 nm, and the heights of the two step structures are 48 nm and 96 nm, respectively.
[0025] In this embodiment of the invention, two thin film structures of different thicknesses, 48nm and 96nm, are respectively located on the left and right sides of the thin film structure region. They are independently formed and have clear boundaries. This layout can realize rapid switching measurement of two film thickness parameters in the same region, which is suitable for the calibration requirements of thin-size segments of the gate oxide layer of IGBT chips. The two step structures of different heights, 48nm and 96nm, in the step structure region are arranged in a stepped continuous manner. The step surface is flat and the height difference is accurate, which can simulate the step characteristics of the trench structure of IGBT chips and is used to calibrate the step height detection accuracy of the measuring instrument. The three 800nm periodic grating structures in the grating structure region are distributed in an equally spaced array. This design can effectively reduce the random error of grating period measurement and improve the reliability of grating parameter calibration by taking the average value through repeated measurement of multiple sets of gratings of the same specification. The dimensional accuracy of each structure is controlled within ±5%, which fully matches the accuracy requirements of geometric feature measurement of IGBT power semiconductor chips.
[0026] Example 2: In some embodiments, the thin film structure region includes four thin film structures of different thicknesses; the step structure region includes four step structures of different heights; the grating structure region includes two sets of grating structures with different grating period sizes; each set of grating structures includes at least one grating structure; a tracking marker is provided on each side of the thin film structure region; a tracking marker is provided on each side of each step structure; and a tracking marker is provided on each side of each grating structure.
[0027] In this embodiment of the invention, the stepped structure area, the thin film structure area, and the grating structure area are coaxially aligned along the effective area of the dielectric layer. In addition to the tracking markers on both sides, the central thin film structure area is additionally equipped with dedicated indicator marks, which can quickly calibrate the core area for film thickness measurement. The stepped structure area and the grating structure area are respectively located directly above and below the thin film structure area. Various tracking markers are precisely matched with each structural unit, and the geometric features of the markers are clear and highly recognizable. Their core function is to guide the optical system and probe of traceable atomic force microscopes and other micro-nano measurement equipment to accurately identify the measurement areas of different sizes and types of structures, realize the rapid positioning and scanning of each structure, and at the same time avoid the probe from accidentally touching non-measurement areas during the scanning process, causing damage to the sample or probe, thus ensuring the accuracy and safety of micro-nano scale measurements.
[0028] In some embodiments, the thicknesses of the four thin film structures are 48nm, 96nm, 150nm and 200nm, respectively; the grating period sizes of the two grating structures are 800nm and 4μm, respectively; and the heights of the four step structures are 48nm, 96nm, 150nm and 200nm, respectively.
[0029] In this embodiment of the invention, four thin film structures of different thicknesses (48nm, 96nm, 150nm, and 200nm) in the thin film structure region are arranged on the left and right sides of the region according to a size gradient, with two structures of different thicknesses on each side. This gradient arrangement design can achieve full coverage calibration of the entire gate oxide layer of the IGBT chip (50nm~200nm), meeting the calibration requirements of measurement equipment for film thickness parameters of IGBT chips with different processes. The four step structures of different heights in the step structure region are arranged in a multi-level stepped continuous layout. The vertical plane of the step has high verticality and good flatness. Its height dimension is precisely matched with the key dimension range of trench depth and step characteristics of the IGBT chip, which can comprehensively calibrate the detection capability of measurement instruments for steps of different heights and adapt to the step characteristic measurement calibration of trench gate structure IGBT chips. The 800nm and 4nm thin film structures in the grating structure region... Two sets of grating structures with different grating periods are set up independently in μm. Each set of grating structures consists of at least one arrayed grating unit. The 800nm small-period grating is adapted to the grating parameter calibration of the micro-nano scale fine structure of IGBT chip, while the 4μm grating matches the measurement requirements of the relatively large-size grating features of the chip, realizing the integrated calibration of grating parameters with different periods. The size design of each structure is highly adapted to the micro-nano scale of the key structure of the trench gate of IGBT power semiconductor chip (trench width 0.5μm~2μm, depth 2μm~10μm, cell spacing 3μm~6μm, gate oxide layer thickness 50nm~200nm). It can realize the integrated calibration of multi-dimensional and multi-specification geometric feature measurement system of film thickness, step height, and grating period, which greatly improves the calibration efficiency and reduces the time spent on replacing and positioning multiple single-specification samples.
[0030] It should be noted that in the two embodiments above, the dimensions of the thin film structure and the dimensions of the step structure are one-to-one and the same. That is, the thickness of the thin film structure is 48nm and 96nm from left to right, and the height of the step structure is also 48nm and 96nm from left to right.
[0031] Figure 2 This is a flowchart illustrating the implementation of the standard sample preparation method provided in this embodiment of the invention. Figure 2 As shown, in some embodiments, the standard template preparation method is used to prepare a composite IGBT power semiconductor chip standard template as shown in any of the above embodiments; the corresponding graphic design scheme of the standard template has multiple preparation areas, each preparation area corresponding to a graphic structure of a certain size, and the method includes: S210 uses silicon carbide wafers as substrate material, and cleans and dries the wafers; S220, growing a dielectric layer on a substrate material; S230, photoresist is coated on the surface of the dielectric layer; S240, based on the pattern structure corresponding to a certain preparation area, remove the photoresist in the light-transmitting area and etch it using dry etching technology; wherein, the mask used in the photolithography process is a genuine mask; S250, remove the photoresist in the non-transparent areas to complete the fabrication of the pattern structure corresponding to the current fabrication area; S260, apply photoresist to the surface of the current fabrication area, and proceed to the step of growing a dielectric layer on the silicon carbide wafer to fabricate the next fabrication area, until the fabrication of all patterned structures is completed.
[0032] In this embodiment of the invention, the fabrication method is based on a multi-area step-by-step processing flow designed with overlay technology. Each fabrication area corresponds to a single-size pattern structure of one type among film thickness, step, and grating. Through a cyclic processing method of "growth-photolithography-etching-protection-regrowth", the integrated fabrication of multi-size, multi-structure composite standard templates is achieved. This ensures the dimensional accuracy of the pattern structure in each fabrication area and allows different structures to be coaxially aligned on the dielectric layer, meeting the overall pattern design requirements of the template. At the same time, the dielectric layer material can be flexibly selected according to the template design requirements, and the process parameters of each step can be precisely controlled, effectively controlling the processing error of micro- and nano-scale structures and meeting the stringent requirements of the standard template for uniformity and stability.
[0033] In some embodiments, a silicon carbide wafer is used as the substrate material. The cleaning and drying of the wafer includes: using a silicon carbide wafer as the substrate material, boiling the substrate material in a first cleaning solution for a preset time and at a preset temperature; rinsing the substrate material with water until neutral; rinsing the substrate material in hydrofluoric acid; rinsing the substrate material with water until neutral; boiling the substrate material in a second cleaning solution for a preset time and at a preset temperature; rinsing the substrate material with water until neutral; and drying the substrate material using dried and filtered nitrogen gas. The first cleaning solution consists of water, ammonia, and hydrogen peroxide in a volume ratio of 4:1:1; the second cleaning solution consists of water, hydrochloric acid, and hydrogen peroxide in a volume ratio of 4:1:1.
[0034] In this embodiment of the invention, a combination of stepwise chemical cleaning and physical drying is used to thoroughly remove impurities such as oil, particles, and metal ions from the surface of silicon carbide wafers. The alkaline system of the first cleaning solution effectively decomposes organic contaminants, while the acidic system of the second cleaning solution efficiently removes surface metal impurities. Hydrofluoric acid rinsing removes the natural oxide layer on the substrate surface, preventing impurities and the oxide layer from affecting the adhesion and uniformity of the subsequent dielectric layer growth. The preset temperature and time parameters are 80℃~90℃ and 10min~15min. These parameters ensure the reactivity of the cleaning solution while avoiding structural damage to the silicon carbide wafers caused by prolonged high-temperature treatment. Finally, nitrogen gas filtered for drying is used to prevent watermarks and ensure the cleanliness and flatness of the substrate surface.
[0035] In some embodiments, based on the pattern structure corresponding to a certain fabrication area, the photoresist in the light-transmitting area is removed and etched using a dry etching technique, including: placing the photolithographically etched substrate material in a NaOH solution to remove the photoresist in the light-transmitting area; baking the substrate material; and etching the substrate material using a dry etching technique.
[0036] In this embodiment of the invention, the photoresist in the transparent area is first removed by NaOH alkaline developer to achieve precise exposure of the area to be etched, while the photoresist in the non-transparent area is completely retained as an etching mask layer to ensure the contour accuracy of the etched area. After development, the substrate material is baked at 130°C for 15 minutes. This baking operation can thoroughly dry the residual developer and improve the bonding strength between the photoresist mask layer and the dielectric layer, preventing photoresist peeling and edge lifting during subsequent dry etching, and avoiding defects such as over-etching and side etching during the etching process. The application of subsequent dry etching technology has higher etching anisotropy and dimensional control accuracy compared to wet etching, and can accurately etch micro- and nano-scale film thickness, steps, and grating structures, ensuring the verticality of the vertical plane and the clarity of the contour of the structure.
[0037] In some embodiments, the etching gas is SF6 or C4F8; the etching rate is set to 15nm / min-20nm / min; and the etching depth is the thickness of the dielectric layer.
[0038] In this embodiment of the invention, SF6 and C4F8 are used together as etching gases. SF6, as the main etching gas, has strong corrosiveness and high etching efficiency, enabling rapid etching of the dielectric layer. C4F8, as a passivation gas, can form a polymer protective film on the sidewalls of the etched structure, effectively suppressing lateral etching during the etching process, ensuring the sidewall perpendicularity and dimensional accuracy of the etched structure, and preventing contour distortion of the micro / nano structure. The etching rate is precisely set in the range of 15nm / min-20nm / min, which ensures both processing efficiency and... It ensures that the etching process is precisely controllable, preventing excessively fast etching rates from causing etching depth deviations and excessively slow rates from affecting processing efficiency. The etching depth is strictly matched with the preset thickness of the dielectric layer, enabling precise etching through the dielectric layer and ensuring that the dimensions of the prepared film thickness, steps, and other structures are highly consistent with the design values. At the same time, the etching parameters are adaptable to the etching requirements of dielectric layers with different thicknesses such as 48nm, 96nm, 150nm, and 200nm. By adjusting the etching time, precise etching of structures of different sizes can be achieved, providing process assurance for the preparation of multi-size composite standard templates.
[0039] For example, Figure 3 This is a flowchart illustrating the implementation of a standard sample preparation method provided in another embodiment of the present invention. (See attached flowchart.) Figure 3As shown, the processing dimensions of the sample are designed as follows: film thickness of 48nm, 96nm, 150nm and 200nm, precision grating period of 800nm and 4μm, and step height of 48nm, 96nm, 150nm and 200nm.
[0040] The graphic design includes thin film structure, grating structure, step structure, and various positioning structures, with an overall size of 10mm×10mm.
[0041] There are three different structures in the effective area: film thickness, grating, and step. The film thickness is located in the middle and is marked with an indicator. The step structure is above and the grating structure is below, and corresponding tracking marks are designed for each.
[0042] S30, graphic design, prepares photomasks based on graphics, and uses projection lithography technology to create various template graphics.
[0043] S31, Cleaning: Using silicon carbide wafers as substrate material, the wafers are cleaned and dried.
[0044] Using silicon carbide wafers as the substrate material, boil in cleaning solution #1 for 10-15 minutes at a temperature controlled at 80-90℃, then rinse with water until neutral. Rinse in hydrofluoric acid for 2 minutes, then rinse with water until neutral. Boil in sufficient cleaning solution #2 at 80-90℃ for 10-15 minutes, then rinse with water until neutral. After cleaning, the wafers are dried using filtered and dried nitrogen gas. The cleaning solution preparation is as follows: Cleaning solution #1: Water: Ammonia: Hydrogen peroxide = 4:1:1 (volume ratio) #2 Cleaning solution: Water: Hydrochloric acid: Hydrogen peroxide = 4:1:1 (volume ratio) S32, Oxidation / Deposition: A dielectric layer (silicon dioxide or silicon nitride) with a thickness of approximately 48 nm is grown on a silicon carbide wafer. A 90 nm thick photoresist layer is then coated onto its surface and baked at 110°C for 90 seconds. Projection lithography is used to fabricate the corresponding dimensional structure, with the mask being the positive image and the patterned area being the non-transparent region. Development in NaOH solution removes the photoresist in the transparent areas, followed by baking at 130°C for 15 minutes. Dry etching is used to etch the dielectric layer in the unmasked patterned areas. The etching gas is SF6 or C4F8; SF6 primarily serves the etching function, while C4F8 provides polymer protection. The etching rate is set to 15 nm / min-20 nm / min, and the etching depth is equal to the thickness of the dielectric layer. Acetone solution is used to remove the photoresist, followed by appropriate cleaning.
[0045] S33, Projection Lithography: Because the prototype contains two thin-film structures and stepped structures of different thicknesses, only one dimension is processed after the initial etching and cleaning. To process the other dimension, the processed structure area needs to be protected with photoresist, and then a dielectric layer (silicon dioxide or silicon nitride) of 48nm is grown, bringing its thickness to 96nm. Then, photoresist of 100nm thickness is coated on its surface and baked at 110°C for 90s. Projection lithography is then used to process the corresponding dimension structure, followed by etching using the method described in step six. Finally, a chemical solution is used to remove all photoresist, completing the prototype processing.
[0046] S34, Etching: A dielectric layer (silicon dioxide or silicon nitride) with a thickness of approximately 150 nm is grown on a silicon carbide wafer. A photoresist layer with a thickness of 120 nm is then coated onto its surface and baked at 110°C for 90 seconds. Projection lithography is used to fabricate the corresponding dimensional structure, with the mask being the positive image and the patterned area being the non-transparent region. Development is performed in NaOH solution to remove the photoresist in the transparent areas, followed by baking at 130°C for 15 minutes. Dry etching is then used to etch the dielectric layer in the unmasked patterned areas. The etching gas is either SF6 or C4F8; SF6 primarily serves the etching function, while C4F8 provides polymer protection. The etching rate is set to 15 nm / min–20 nm / min, and the etching depth is equal to the thickness of the dielectric layer. S35, Cleaning: Use acetone solution to remove photoresist and perform appropriate cleaning.
[0047] S36, Adhesive Protection: Because the sample contains two thin-film structures and stepped structures of different thicknesses, only one dimension is processed after the initial etching and cleaning. To complete the processing of the other dimension, the processed structural areas need to be protected with adhesive. S37, oxidation / deposition, followed by the growth of a 50nm dielectric layer (silicon dioxide or silicon nitride) to achieve a thickness of 200nm. Then, photoresist is coated on its surface to a thickness of 150nm, and it is baked at 110°C for 90s; S38, projection lithography, uses projection lithography technology to process structures of corresponding dimensions.
[0048] S39, Etching: Etching the area of the projection lithography using the etching method in S34. S40, finally, uses a chemical solution to remove all photoresist. S41, Clean the template to complete the template processing.
[0049] The completed samples were calibrated and tested using a traceable atomic force microscope, the structure of which is shown in the diagram below. Figure 3As shown, the main component of the device is the laser interferometry and attitude monitoring system, which is the core for achieving traceable measurement of nanoscale geometric dimensions. It mainly consists of nanoscale laser interferometers in the X, Y, and Z directions and goniometers in the X, Y, and Z directions. Based on the "zero" Abbe error design principle, a roof-angle reflection structure is adopted in the design of the interferometry system. During measurement, the measurement beams in the X, Y, and Z directions coincide with the aiming point of the atomic force probe.
[0050] The sample is placed on the stage of a traceable atomic force microscope. Using its optical system, the measurement area is located based on the sample's tracking marks, and scanning begins. When measuring the step structure, the probe is brought close to the sample surface. A feedback system controls the interaction force between the probe and the sample, causing it to vibrate with a specific amplitude above the sample surface. The morphology image of the sample is acquired through scanning. The step area is selected, and the step height is measured using software analysis tools. Multiple measurements are taken, and the average value is used as the final step height measurement for the sample.
[0051] S38, with adhesive protection. Since the step height dimensions in the processed sample are 48nm, 96nm, 150nm and 200nm, which are the same as the dimensions of the thin film structure, the corresponding film thickness can also be determined after measuring the step structure with a traceable atomic force microscope.
[0052] S39, Oxidation / Deposition: The sample is placed on the stage of a traceable atomic force microscope. Using its optical system, the measurement area is located based on the sample's tracking markers, and scanning begins. When measuring the grating structure, an appropriate scanning range is set according to the characteristics of the grating sample, typically selecting a range that measures more than 10 cycles. A suitable scanning rate is chosen to avoid image distortion or damage to the sample due to excessively fast scanning. Scanning is initiated to acquire surface morphology data of the grating sample. To improve scanning accuracy, multiple scans of the same area can be performed, and the average value can be calculated or data fusion can be applied. The acquired image data is processed and analyzed to measure parameters such as the grating period, height, and duty cycle. The grating period measurement result is determined by averaging the data from 10 cycles, thus establishing a fixed value for the grating sample.
[0053] This invention also proposes a test and calibration method for a standard template, used to test the composite IGBT power semiconductor chip standard template as described in any of the above embodiments; the method includes: A standard template is placed on the sample stage of a traceable atomic force microscope, and the step structure area to be measured is located according to the tracking marks set on the standard template to obtain the final value of the step height. The traceable atomic force microscope consists of X, Y, and Z direction laser interferometers and X, Y, and Z direction goniometers. The final value of the step height is used as the final value of the film thickness. The grating structure area is located according to the tracking markers set on the standard template for testing, and the final value of the grating period size is obtained.
[0054] In this embodiment of the invention, the test calibration method is based on a traceable atomic force microscope to build a traceability system for micro- and nano-scale geometric values. It relies on the tracking marks of each structural area of the template to achieve precise positioning of the measurement area. Combined with the matching design of the step and the film size, it achieves multi-parameter determination in one measurement, which greatly improves the calibration efficiency. At the same time, the synergistic effect of the laser interferometry and the angle measurement system ensures the accuracy, traceability and comparability of the measurement results. It fully meets the determination requirements of the geometric feature standard template of the composite IGBT power semiconductor chip. The obtained determination results can be used as the calibration benchmark of the geometric feature measurement system of IGBT power semiconductor chip. It builds a continuous and uninterrupted length traceability chain for the measurement instruments and equipment at the chip manufacturing process end, and solves the problems of missing measurement traceability chains and accumulation of value transmission errors in the existing system. The traceable atomic force microscope is designed based on the principle of "zero" Abbe error. It adopts a roof-shaped reflective structure to make the measurement light in the X, Y, and Z directions coincide with the aiming point of the atomic force probe. Combined with a multi-directional laser interferometer and goniometer, it can achieve nanometer-level position measurement and attitude monitoring, effectively eliminating systematic errors in the measurement process and ensuring the accuracy of micro- and nano-sized measurements such as step height, film thickness, and grating period. The positioning function of the tracking marker can avoid positioning deviation of the probe scan, prevent mis-scanning of non-measurement areas from damaging the sample and probe, and make the measurement switching of each structural area more efficient. The step height test result is directly used as the film thickness determination result, relying on the design logic of the step height and film thickness dimensions being perfectly matched in the sample design. This eliminates the need for repeated scanning measurements of the film structure area, reducing measurement operation steps and scanning time while ensuring consistency of the determination results. It also avoids morphological damage to the film structure that may be caused by multiple scans, ensuring the structural integrity and measurement stability of the sample. The independent testing process for the grating structure area is designed with specific operating procedures for the measurement characteristics of the grating period, enabling accurate measurement and determination of multiple parameters such as grating period, height, and duty cycle. This complements the determination processes for the step and film thickness, ultimately achieving comprehensive calibration and determination of the multi-dimensional geometric features of the sample film thickness, step height, and grating period. The accuracy of the obtained results can be controlled within ±5%.
[0055] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not detailed or described in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Unless otherwise specified or in conflict with logic, the terminology and / or descriptions between different embodiments are consistent and can be referenced interchangeably. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.
[0056] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.
Claims
1. A standard template for a composite IGBT power semiconductor chip, characterized in that, include: Substrate and dielectric layer; The effective area of the dielectric layer is provided with a coaxially aligned stepped structure area, a thin film structure area and a grating structure area from top to bottom. Wherein, the thin film structure region includes at least two thin film structures with different thicknesses; the stepped structure region includes at least two stepped structures with different heights; and the grating structure region includes at least one grating structure. Tracking markers are provided in the stepped structure area, the thin film structure area, and the grating structure area.
2. The composite IGBT power semiconductor chip standard template according to claim 1, characterized in that, The thin film structure region includes two thin film structures with different thicknesses; the stepped structure region includes two stepped structures with different heights; the grating structure region includes three grating structures of the same size. Each side of the thin film structure region is provided with a tracking marker; each side of each step structure is provided with a tracking marker; each side of each grating structure is provided with a tracking marker.
3. The composite IGBT power semiconductor chip standard template according to claim 2, characterized in that, The thicknesses of the two thin film structures are 48 nm and 96 nm, respectively. The grating period size of the grating structure is 800 nm, and the heights of the two stepped structures are 48 nm and 96 nm, respectively.
4. The composite IGBT power semiconductor chip standard template according to claim 1, characterized in that, The thin film structure region includes four thin film structures with different thicknesses; the stepped structure region includes four stepped structures with different heights; the grating structure region includes two sets of grating structures with different grating period sizes; each set of grating structures includes at least one grating structure. Each side of the thin film structure region is provided with a tracking marker; each side of each step structure is provided with a tracking marker; each side of each grating structure is provided with a tracking marker.
5. The composite IGBT power semiconductor chip standard template according to claim 4, characterized in that, The thicknesses of the four thin film structures are 48 nm, 96 nm, 150 nm and 200 nm, respectively. The grating period sizes of the two grating structures are 800 nm and 4 μm, respectively. The heights of the four step structures are 48 nm, 96 nm, 150 nm and 200 nm, respectively.
6. A method for preparing a standard template, characterized in that, The method is used to prepare a standard sample of the composite IGBT power semiconductor chip as described in any one of claims 1-5 above; The standard template has multiple preparation areas for its corresponding graphic design scheme, each preparation area corresponding to a graphic structure of a certain size. The method includes: Silicon carbide wafers are used as substrate materials, and the wafers are cleaned and dried. A dielectric layer is grown on the substrate material; Photoresist is coated onto the surface of the dielectric layer; Based on the pattern structure corresponding to a certain preparation area, the photoresist in the light-transmitting area is removed, and dry etching technology is used for etching; wherein, the mask used in the photolithography process is a genuine mask; Remove the photoresist in the non-transparent areas to complete the fabrication of the pattern structure corresponding to the current fabrication area; Photoresist is coated onto the surface of the current fabrication area, and the process proceeds to the step of growing a dielectric layer on the silicon carbide wafer to fabricate the next fabrication area, until all patterned structures are fabricated.
7. The standard sample preparation method according to claim 6, characterized in that, Using silicon carbide wafers as the substrate material, the wafers are cleaned and dried, including: Using silicon carbide wafers as substrate materials, the substrate materials are boiled in a first cleaning solution for a preset time and at a preset temperature; Rinse the substrate material with water until it is neutral; The substrate material is rinsed in hydrofluoric acid; Rinse the substrate material with water until it is neutral; The substrate material is boiled in a second cleaning solution at a preset time and temperature. Rinse the substrate material with water until it is neutral; The substrate material was dried using filtered nitrogen gas. The first cleaning solution is composed of water, ammonia, and hydrogen peroxide in a volume ratio of 4:1:1; the second cleaning solution is composed of water, hydrochloric acid, and hydrogen peroxide in a volume ratio of 4:1:
1.
8. The standard sample preparation method according to claim 6, characterized in that, Based on the pattern structure corresponding to a certain fabrication area, the photoresist in the light-transmitting area is removed, and dry etching is performed, including: The photolithographically etched substrate material is placed in a NaOH solution to remove the photoresist in the light-transmitting areas; The substrate material is baked; The substrate material is etched using a dry etching technique.
9. The standard sample preparation method according to claim 8, characterized in that, The etching gas is SF6 or C4F8; the etching rate is set to 15nm / min-20nm / min, and the etching depth is the thickness of the dielectric layer.
10. A test and calibration method for a standard template, characterized in that, The method is used to test the composite IGBT power semiconductor chip standard sample as described in any one of claims 1-5; the method includes: The standard template is placed on the sample stage of the traceable atomic force microscope, and the step structure area to be measured is located according to the tracking mark set on the standard template to obtain the final value of the step height; wherein, the traceable atomic force microscope is composed of X, Y, Z direction laser interferometer and X, Y, Z direction goniometer; The final value of the step height is used as the final value of the film thickness. The grating structure area is located according to the tracking markers set on the standard template for testing, and the final value of the grating period size is obtained.