Semiconductor structure and method of forming the same

Abstract

This disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate; a drift region located within the substrate; a body region located within the drift region; a source region located within the body region; at least two gate structures symmetrically located on either side of the source region; and a drain region located within the drift region. The source region includes: at least one set of first source regions, where the ratio of the total area of ​​the first source regions to the total area of ​​the source regions on a plane parallel to the substrate surface is less than 1 / 2; at least one second source region; the second source region has a connecting portion and multiple extension portions, the extension portions extending from both sides of the connecting portion along the carrier movement direction, and the first source regions being located between adjacent extension portions on one side of the gate structure; or, the second source region is a plurality of second sub-source regions extending along the carrier movement direction and spaced apart from each other, the first source regions and second sub-source regions being staggered in a direction perpendicular to the carrier movement direction. Using the above technical solution can improve the thermal failure resistance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing processes, laterally diffused metal-oxide-semiconductor (LDMOS) devices are widely used in power integrated circuits due to their advantages of high voltage withstand capability, low on-resistance, and ease of integration. To meet the high power density requirements of modern electronic products, LDMOS devices are continuously evolving towards lower on-resistance and higher operating current density.

[0003] However, within an LDMOS device, a parasitic NPN bipolar transistor is formed by the N-drift region, the P-type body region, and the N+ source region. Under high-current operating conditions, electrons flowing through the P-type body region generate a voltage drop across its parasitic resistance. When this voltage drop exceeds the built-in potential, the parasitic NPN is triggered to conduct, and the device enters a latch-up state. Traditional all-N+ source structures lack effective body region outtake, resulting in a large parasitic resistance in the body region. Under high current, this easily leads to the formation of localized current filaments, causing a rapid rise in junction temperature and thermal failure, severely limiting the device's safe operating area.

[0004] Therefore, how to provide technical solutions to improve the thermal failure resistance of semiconductor structures has become an urgent technical problem to be solved. Summary of the Invention

[0005] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, which can improve the resistance of the semiconductor structure to thermal failure.

[0006] To address the aforementioned technical problems, this disclosure provides a semiconductor structure comprising: a substrate; a drift region located within the substrate and having a first conductivity type; a body region located within the drift region and having a second conductivity type opposite to the first conductivity type; a source region located within the body region; at least two gate structures symmetrically located on both sides of the source region and respectively covering the edge regions on both sides of the body region; and drain regions corresponding one-to-one with the gate structures, respectively located within the drift region on one side of the gate structure and far from the source region; wherein the source region comprises: at least one set of first source regions having the first conductivity type and a doping concentration greater than that of the drift region, the projection of which on the substrate overlaps with the projection of the gate structure, and lies on a plane parallel to the surface of the substrate. The ratio of the total area of ​​the first source region to the total area of ​​the source regions is less than 1 / 2; at least one second source region having the second conductivity type and a doping concentration greater than that of the body region; wherein the second source region has a connecting portion and a plurality of extension portions, the extension portions extending from both sides of the connecting portion along the carrier movement direction, the projection of the extension portions on the substrate abutting the projection of the gate structure, the number of the first source regions is two sets, respectively located between adjacent extension portions on one side of the gate structure and adjacent to the connecting portion; or, the second source region is a plurality of second sub-source regions extending along the carrier movement direction and spaced apart from each other, the projection of the second source regions on the substrate abutting the projection of the gate structure, the first source regions and the second sub-source regions are staggered in a direction perpendicular to the carrier movement direction.

[0007] Optionally, the semiconductor structure further includes: a plurality of first source region contact plugs electrically connected to the first source region; and a source metal layer located above the first source region contact plugs and electrically connected to the plurality of first source region contact plugs.

[0008] Optionally, the number of the first source region contact plugs corresponds one-to-one with the number of the first source regions.

[0009] Optionally, the second source region forms an electrical connection with the body region in the body region, and both the first source region and the second source region are in electrical contact with the source metal layer.

[0010] Optionally, two adjacent sets of the first source regions are symmetrical about the second source region.

[0011] Optionally, it also includes a field plate structure located above the drift region; a portion of the gate structure is located above the field plate structure; wherein the field plate structure is located away from the first source region.

[0012] This disclosure also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a drift region having a first conductivity type in the substrate; forming at least two gate structures, the at least two gate structures being symmetrically located on both sides of a predetermined source region location; forming a body region having a second conductivity type opposite to the first conductivity type in the drift region, the edges of the body region being located below adjacent gate structures respectively; forming drain regions corresponding one-to-one with the gate structures, the drain regions being located within the drift region on one side of the gate structure and away from the predetermined source region location; forming a source region at the predetermined source region location in the body region, the step of forming the source region comprising: forming at least one set of first source regions having the first conductivity type in the body region, the doping concentration of the first source regions being greater than the doping concentration of the drift regions, and their projection on the substrate being the same as the projection of the gate structures. The projections of the first source regions onto the substrate surface are parallel to each other. On a plane parallel to the substrate surface, the ratio of the total area of ​​the first source region to the total area of ​​the other source regions is less than 1 / 2. At least one second source region having the second conductivity type is formed in the body region, and the doping concentration of the second source region is greater than that of the body region. The second source region has a connecting portion and multiple extensions. The extensions extend from both sides of the connecting portion along the carrier movement direction, and their projections on the substrate abut against the projection of the gate structure. The number of first source regions is two sets, located between adjacent extensions on one side of the gate structure and adjacent to the connecting portion. Alternatively, the second source region may be multiple second sub-source regions extending along the carrier movement direction and spaced apart from each other, whose projections on the substrate abut against the projection of the gate structure. The first source regions and the second sub-source regions are arranged alternately perpendicular to the carrier movement direction.

[0013] Optionally, the method further includes: forming a plurality of first source region contact plugs, the first source region contact plugs being electrically connected to the first source region; forming a source metal layer, the source metal layer being located above the first source region contact plugs and electrically connected to the plurality of first source region contact plugs, and electrically connected to the second source region.

[0014] Optionally, the step of forming the second source region includes: defining a window of the second source region by photolithography and performing ion implantation; wherein the dopant type of the second source region ion implantation is opposite to that of the first source region, and the implantation dose of the second source region is greater than the implantation dose of the first source region within the window of the second source region, and the area of ​​the window of the second source region is greater than 50% of the window area of ​​the source region.

[0015] Optionally, the method further includes: forming a field plate structure above the drift region; wherein the field plate structure and the gate structure are patterned from the same material layer, the field plate structure and the gate structure are formed in the same step, and the field plate structure is located above the field oxide layer, and the gate structure is located above the gate oxide layer.

[0016] Compared with the prior art, the technical solution of the present disclosure has the following advantages: The semiconductor structure and its formation method provided in this disclosure include: a substrate; a drift region located above the substrate and having a first conductivity type; a body region located above the substrate and adjacent to the drift region, having a second conductivity type opposite to the first conductivity type; a gate structure located above the body region; and a source region located in the body region, the source region including: at least one first source region having the first conductivity type and adjacent to the gate structure; and at least one second source region having the second conductivity type, wherein a portion or all of the second source region is alternately arranged with a portion or all of the first source region along a first direction; wherein, on a plane parallel to the surface of the substrate, the ratio of the total area of ​​the first source region to the total area of ​​the source region is less than 50%. By setting alternating first source regions (having the first conductivity type) and second source regions (having the second conductivity type) in the source region, and by controlling the total area ratio of the first source region to less than 50%, the electron injection area is effectively reduced, the local current density is reduced, the electron-hole pairs generated by collisional ionization are reduced, the current filament effect and hot spot formation are avoided, thereby reducing the trigger source of parasitic NPN and reducing the trigger sensitivity. Therefore, the semiconductor structure can improve the resistance to thermal failure of the semiconductor structure and enhance the reliability and robustness of high-voltage LDMOS under high current and high junction temperature operating conditions. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments disclosed in this specification, the drawings used in the description of the embodiments disclosed in this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figures 1 to 7 This is a cross-sectional structural schematic diagram of some steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure; Figure 8 This is a schematic diagram of the cross-sectional structure and the top view of the corresponding part of a semiconductor structure according to an embodiment of this disclosure; Figure 9 and Figure 10This is a schematic diagram of a partial top view of the semiconductor structure in an embodiment of this disclosure; Figure 11 This is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0019] The technical solutions described herein will be described in detail below with reference to specific embodiments and accompanying drawings. The embodiments described herein are specific implementations of this disclosure and are used to illustrate the concept of this disclosure. These descriptions are illustrative and exemplary and should not be construed as limiting the implementation methods or the scope of protection of this disclosure. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein.

[0020] It should be noted that the accompanying drawings in this embodiment are schematic diagrams used to illustrate the concept of this disclosure, and to schematically show the shape and interrelationship of each part. It should be understood that, in order to clearly show the structure of each component of this disclosure, the drawings are not drawn to the same scale, and the same reference numerals are used to indicate the same parts in the drawings.

[0021] As described in the background section, in semiconductor manufacturing processes, laterally diffused metal-oxide-semiconductor (LDMOS) devices are widely used in the field of power integrated circuits due to their advantages of high voltage withstand capability, low on-resistance, and ease of integration. To meet the high power density requirements of modern electronic products, LDMOS devices are continuously evolving towards lower on-resistance and higher operating current density.

[0022] However, within an LDMOS device, a parasitic NPN bipolar transistor is formed by the N-drift region, the P-type body region, and the N+ source region. Under high-current operating conditions, electrons flowing through the P-type body region generate a voltage drop across its parasitic resistance. When this voltage drop exceeds the built-in potential, the parasitic NPN is triggered to conduct, and the device enters a latch-up state. Traditional all-N+ source structures lack effective body region outtake, resulting in a large parasitic resistance in the body region. Under high current, this easily leads to the formation of localized current filaments, causing a rapid rise in junction temperature and thermal failure, severely limiting the device's safe operating area.

[0023] Therefore, how to provide technical solutions to improve the thermal failure resistance of semiconductor structures has become an urgent technical problem to be solved.

[0024] To address the aforementioned technical problems, the semiconductor structure and its formation method provided in this disclosure include: a substrate; a drift region located above the substrate and having a first conductivity type; a body region located above the substrate and adjacent to the drift region, having a second conductivity type opposite to the first conductivity type; a gate structure located above the body region; and a source region located within the body region. The source region includes: at least one first source region having the first conductivity type and adjacent to the gate structure; and at least one second source region having the second conductivity type, wherein a portion or all of the second source region alternates with a portion or all of the first source region along a first direction; wherein, on a plane parallel to the substrate surface, the ratio of the total area of ​​the first source region to the total area of ​​the source regions is less than 50%. This is achieved by providing alternately arranged first source regions (having the first conductivity type) and second source regions (having the second conductivity type) within the source region. By controlling the total area ratio of the first source region to less than 50%, the electron injection area is effectively reduced, the local current density is lowered, and the number of electron-hole pairs generated by collisional ionization is reduced, avoiding current filamentation and hot spot formation. This reduces the trigger sources of parasitic NPN and lowers the trigger sensitivity. Therefore, the semiconductor structure can improve the thermal failure resistance of the semiconductor structure and enhance the reliability and robustness of high-voltage LDMOS under high current and high junction temperature operating conditions.

[0025] To make the above-described objects, features and advantages of this disclosure more apparent and understandable, the disclosure is illustrated below with reference to the accompanying drawings.

[0026] See Figure 11 , Figure 11 This is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure. The method may perform the following steps S201 to S207.

[0027] In step S201, a substrate is provided.

[0028] In step S202, a drift region having a first conductivity type is formed in the substrate.

[0029] In step S203, at least two gate structures are formed, which are symmetrically located on both sides of a preset source region.

[0030] In step S204, a body region having a second conductivity type opposite to the first conductivity type is formed in the drift region, and the edges on both sides of the body region are located below the adjacent gate structure.

[0031] In step S205, drain regions corresponding to the gate structures are formed. The drain regions are located in the drift region on one side of the gate structure and are far away from the preset source region.

[0032] In step S206, a source region is formed at the preset source region location in the body region. The step of forming the source region includes: forming at least one set of first source regions having the first conductivity type in the body region, wherein the doping concentration of the first source region is greater than the doping concentration of the drift region, its projection on the substrate is opposite to the projection of the gate structure, and on a plane parallel to the surface of the substrate, the ratio of the total area of ​​the first source region to the total area of ​​the source region is less than 1 / 2.

[0033] In step S207, at least one second source region having the second conductivity type is formed in the body region, and the doping concentration of the second source region is greater than the doping concentration of the body region.

[0034] The following combination Figures 1 to 10 The above methods will be explained.

[0035] See Figure 1 Substrate 100 is provided.

[0036] The substrate 100 is used to provide a process platform for the formation of semiconductor structures.

[0037] The substrate 100 is made of single-crystal silicon. In other embodiments, the substrate 100 may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium dihydrogen nitride. The substrate 100 may also be other types of substrates, such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. In other embodiments, an epitaxial layer with the same crystal structure as the substrate 100 may also be formed on the surface of the substrate 100.

[0038] A shallow trench isolation structure 101 is formed in the substrate 100.

[0039] Specifically, a hard mask layer (not shown) is deposited on the surface of the substrate 100. The hard mask layer, made of silicon nitride, is formed using chemical vapor deposition and serves as a barrier layer for subsequent trench etching. A photoresist pattern is formed on the hard mask layer using photolithography to define the shallow trench isolation region, exposing the area where the isolation structure will be formed. The photolithography process includes standard steps such as spin-coating photoresist, exposure, and development to ensure the accuracy of the pattern size and position. Using the photoresist pattern as a mask, a dry etching process is used to sequentially etch the hard mask layer and further etch the substrate 100 to form shallow trenches (not shown). The etching gas can be a mixture of carbon tetrafluoride, trifluoromethane, argon, etc. By controlling the etching time and gas flow rate, the depth and sidewall angle of the shallow trenches are controlled to facilitate step coverage by the subsequent filling material. After etching, the photoresist pattern is removed. An isolation material layer is deposited in the shallow trenches and on the surface of the hard mask layer using high-density plasma chemical vapor deposition. The isolation material layer is typically silicon oxide, and its deposition thickness must be sufficient to completely fill the shallow trench. High-density plasma chemical vapor deposition (PDCVD) has excellent filling capability, preventing voids or gaps within the shallow trench. After deposition, the wafer surface is planarized using chemical mechanical polishing (CMP), with a hard mask layer serving as a polishing stop layer. Excess isolation material in the shallow trench is removed, leaving only the isolation material layer within the trench. Finally, the remaining silicon nitride hard mask layer is removed using a hot phosphoric acid wet etching process, exposing the surface of the substrate 100. Thus, the shallow trench isolation structure 101 is formed in the substrate 100, defining the location of the active region and providing electrical isolation for subsequent formation of device structures such as drift regions and body regions.

[0040] See Figure 2 This creates a drift zone.

[0041] A drift region (initial drift region 110a) having a first conductivity type is formed in the substrate 100.

[0042] The initial drift region 110a is located between adjacent shallow trench isolation structures 101, that is, within the active region defined by the shallow trench isolation structures 101.

[0043] Specifically, photolithography processes such as resist coating, exposure, and development are used to define the implantation window of the initial drift region 110a. An ion implantation process is then performed to form the initial drift region 110a. An ashing process combined with wet cleaning is used to thoroughly remove any photoresist residue from the substrate surface. Finally, an annealing process is performed to activate the implanted dopant ions and repair implantation damage.

[0044] Based on the required drift region conductivity type, select the appropriate doping ions to determine the first conductivity type.

[0045] In this embodiment, taking the first conductivity type as N-type as an example, the implanted ions can be phosphorus (P) or arsenic (As).

[0046] The implantation energy and dosage need to be optimized based on the voltage rating and on-resistance requirements of the target device. For example, for LDMOS devices with an operating voltage of around 100V, the implantation energy can be set to 80keV to 200keV. For devices with higher voltage ratings, multiple implantations or multi-energy implantations can be used to create a gradually varying doping distribution. During implantation, the photoresist pattern acts as an implantation mask, preventing ions from entering the non-implanted regions.

[0047] It should be noted that the initial drift region 110a may undergo further thermal processes in subsequent processes (such as body region formation), resulting in a fine-tuning of the doping distribution. The initial drift region 110a is located within the active region between adjacent shallow trench isolation structures 101, and its upper surface is flush with the surface of the substrate 100 (or slightly recessed, depending on the implantation and annealing conditions). The initial drift region 110a will cooperate with the body region, drain region, and other structures in subsequent steps to form the drift region of the LDMOS device, serving to withstand reverse bias voltage and provide transport channels for majority carriers.

[0048] See also Figure 3 , Figure 4 and Figure 5 This forms a gate oxide layer 102, a field plate structure 103, and a gate structure 120.

[0049] The specific steps are as follows: An initial gate oxide layer 102a is formed.

[0050] Specifically, the surface of substrate 100 undergoes standard cleaning to remove the native oxide layer and contaminants. Then, a thin silicon oxide layer is grown on the surface of substrate 100 using a thermal oxidation method, such as dry oxidation or wet oxidation, as the initial gate oxide layer 102a. The initial gate oxide layer 102a covers the entire active region, including above the subsequently formed body region and above the initial drift region 110a. The thickness of the initial gate oxide layer 102a is determined according to the operating voltage of the device. In subsequent processes, part of the initial gate oxide layer 102a is retained as the gate oxide layer 102, and part is replaced by a field oxide layer.

[0051] In some embodiments, a field oxide layer (not shown) is formed first, prior to the initial gate oxide layer 102a. The thickness of the field oxide layer is greater than the thickness of the initial gate oxide layer 102a. The initial gate oxide layer 102a covers the field oxide layer.

[0052] Specifically, a silicon nitride hard mask is deposited on the surface of substrate 100, and the area where the field oxide layer needs to be formed (i.e., above the drift region) is opened by photolithography. Then, thermal oxidation is performed to grow a thick field oxide layer. The thickness of the field oxide layer is greater than the thickness of the initial gate oxide layer 102a formed later.

[0053] The initial field plate structure 103a is formed.

[0054] The initial field plate structure 103a is formed using polycrystalline silicon material.

[0055] Specifically, a polysilicon layer is deposited above the initial gate oxide layer 102a using a low-pressure chemical vapor deposition (LPCVD) process. After deposition, the polysilicon is doped, either through in-situ doping or ion implantation (such as phosphorus or boron implantation). The polysilicon layer is then patterned using photolithography and dry etching processes to form the initial field plate structure 103a. This initial field plate structure 103a is located above the initial drift region 110a and extends along the carrier movement direction. It should be noted that the initial field plate structure 103a formed at this stage is still integral with the subsequently formed gate structure and will be separated in subsequent etching steps.

[0056] In some embodiments, a thermal oxidation method is used to consume or thicken the initial gate oxide layer 102a below the initial field plate structure 103a, ultimately forming a thicker field oxide layer, while the initial field plate structure 103a itself serves as a mask or is subsequently retained as a field plate. After oxidation, the initial gate oxide layer 102a in the preset gate region remains essentially unchanged, becoming the final gate oxide layer 102; while the initial gate oxide layer 102a located above the drift region is transformed into a field oxide layer, and the initial field plate structure 103a covering it becomes the final field plate structure 103. The field plate structure 103 is located above the field oxide layer and is used to modulate the electric field distribution on the surface of the drift region.

[0057] In some embodiments, the initial gate oxide layer 102a and the initial field plate structure 103a and / or the gate structure material layer are first formed, and then photolithography and etching steps are performed layer by layer to form the gate oxide layer 102, the field plate structure 103, and the gate structure 120.

[0058] In some embodiments, the material layer of the initial field plate structure 103a and the gate structure 120 is the same material layer, and the material layer is patterned in the same conductive layer.

[0059] At least two gate structures 120 are formed.

[0060] The at least two gate structures 120 are symmetrically located on both sides of the preset source region position.

[0061] Specifically, the material layer forming the gate structure 120 (which may be a polysilicon layer, the polysilicon layer may include the initial field plate structure 103a) is photolithographically and etched to pattern the material layer of the gate structure 120 into the gate structure 120.

[0062] Two gate structures 120 are located on the left and right sides (or the top and bottom sides) of the source region to be formed. The gate structures 120 are located on the gate oxide layer 102, while the field plate structure 103 is located on the field oxide layer.

[0063] In some embodiments, a portion of the gate oxide layer 102 is located above the field oxide layer, and this portion of the gate oxide layer 102 is located below the field plate structure 103.

[0064] In some embodiments, the gate oxide layer 102 is located below the gate structure 120, and the field oxide layer is located below the field plate structure 103.

[0065] The gate structure 120 and the field plate structure 103 can be formed by patterning the same polysilicon layer and defined in the same step.

[0066] In this embodiment, the gate structure 120 and the field plate structure 103 can be physically continuous (i.e., the polysilicon layer is not completely etched off) or disconnected (i.e., a gap is formed by etching).

[0067] In some embodiments, in order to independently control the gate and field plate potentials, a gap is defined between them by photolithography to electrically isolate the gate structure 120 from the field plate structure 103, and the gate structure 120 is located on the thin gate oxide layer 102, while the field plate structure 103 is located on the thick field oxide layer.

[0068] In some embodiments, the field plate structure 103 and the gate structure 120 are patterned from the same material layer, formed in the same step, with the field plate structure 103 located above the field oxide layer and the gate structure 120 located above the gate oxide layer 102. Furthermore, a portion of the gate structure 120 may extend above the field plate structure 103, but the field plate structure 103 should be kept away from the region of the predetermined source region to reduce parasitic capacitance between the gate and drain. The field plate can modulate the surface electric field of the drift region.

[0069] See Figure 6 , forming sidewall 121.

[0070] The sidewall 121 is located on the sidewall of the gate structure 120.

[0071] The sidewall 121 is located on the top and sidewall of the gate structure 120.

[0072] The sidewall 121 is located on the sidewall of the gate structure 120 and the field plate structure 103.

[0073] The sidewall 121 is located on the top and sidewall of the gate structure 120, and on the top and sidewall of the field plate structure 103.

[0074] The sidewall 121 is used to protect the gate edge, define the self-alignment boundary for subsequent source / drain injection, and adjust the parasitic capacitance between the gate and the source / drain region.

[0075] Specifically, an insulating dielectric material is conformally deposited on the substrate 100 using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) processes. The insulating dielectric material may be silicon nitride (SiN), silicon oxide (SiO2), or a composite stack of the two (e.g., an ONO structure: silicon oxide-silicon nitride-silicon oxide).

[0076] In this embodiment, silicon nitride is preferably used as the sidewall material 121, as silicon nitride has a high etching selectivity and good step coverage.

[0077] The sidewall 121 is formed by anisotropic dry etching (e.g., reactive ion etching (RIE) process).

[0078] In some embodiments, the sidewall 121 is retained on the sidewalls of the gate structure 120 and the field plate structure 103, forming a self-aligned sidewall 121. The sidewall 121 covers the sidewalls of the gate structure 120 and the field plate structure 103.

[0079] The sidewall 121 can act as an implantation mask in subsequent source / drain implantation steps to ensure that high-dose source / drain implantation is kept at a certain distance from the gate edge, thereby forming a lightly doped drain region (LDD) structure or avoiding channel punch-through.

[0080] For the symmetrical gate LDMOS structure of this disclosure, since there are two gate structures 120, the sidewalls 121 are formed on the inner side (towards the source region) and the outer side (towards the drain region) of each gate structure 120, respectively.

[0081] In some embodiments, the sidewall 121 also extends to the sidewall of the field plate structure 103. Since the field plate structure 103 is located above the drift region, the sidewall 121 of the sidewall of the field plate structure 103 helps to reduce electric field concentration at the edge of the field plate and improve the reliability of the device.

[0082] See Figure 7 A cross-sectional view of a semiconductor structure in an embodiment of this disclosure.

[0083] The body region 130 has a second conductivity type (e.g., P-type) opposite to the first conductivity type (e.g., N-type), the body region 130 is located in the drift region 110 between two adjacent gate structures 120, and the edges on both sides of the body region 130 extend to the bottom of the adjacent gate structure 120, respectively.

[0084] Specifically, an implantation window for the body region 130 is defined on the substrate 100 using photolithography. The implantation window is located between adjacent gate structures 120, and its edge is substantially aligned with the inner edge of the gate structure 120 to ensure that the body region edge can self-align and extend below the gate. An ion implantation process is used to implant a dopant of a second conductivity type (such as boron) into the implantation window, forming the initial doping distribution of the body region 130. During implantation, the gate structure 120 and sidewalls 121 serve as masks. High-temperature annealing is performed to activate the dopant and allow it to diffuse, resulting in a predetermined junction depth for the body region 130, with the edges of the body region 130 laterally diffusing below the gate structure 120. Furthermore, the gate structure 120 covers the edge region of the body region 130, laying the foundation for the subsequent formation of a conductive channel.

[0085] In this embodiment, the body region 130 is located in the drift region 110 between two adjacent gate structures 120, and the two side edges of the body region 130 are respectively located below the two gate structures 120, so that one body region 130 can serve two symmetrical LDMOS cells on the left and right at the same time, which is beneficial to improving the integration density.

[0086] Leakage zone 133 is formed.

[0087] The drain region 133 corresponds one-to-one with the gate structure 120, and is located in the drift region 110 on the side of each gate structure 120 away from the preset source region.

[0088] Specifically, a drain implantation window located outside the gate structure 120 (i.e., away from the preset source region) is defined on the substrate 100 using photolithography. Ion implantation is then used to implant heavily doped ions of the first conductivity type (such as arsenic or phosphorus) into the drain implantation window, forming a highly doped region of the drain region 133. During implantation, the gate structure 120, sidewalls 121, and photoresist pattern together act as a mask to protect other areas. After implantation, the photoresist pattern is removed and annealing is performed to activate the doped ions and repair implantation damage, resulting in a high doping concentration and low resistivity in the drain region 133, thus enabling a good ohmic connection with the subsequently formed drain contact.

[0089] In some embodiments, the edge of the drain injection window is substantially aligned with the edge of the sidewall 121 outside the gate structure 120 to maintain appropriate lateral spacing.

[0090] In this embodiment, at least two symmetrically distributed gate structures 120 correspondingly form at least two drain regions 133, which are located in the drift region 110 on the side of the gate structure 120 away from the preset source region. Each drain region 133 and the corresponding gate structure 120 constitute an LDMOS cell, sharing the subsequently formed source region.

[0091] The preset source region is located in the drift region between adjacent gate structures 120.

[0092] The first source region 131 and the second source region 132 are formed.

[0093] A source region is formed at a preset source region location in body region 130.

[0094] The source region includes a first source region 131 having a first conductivity type and a second source region 132 having a second conductivity type.

[0095] The first source region 131 and the second source region 132 are arranged alternately within the body region 130.

[0096] At least one set of first source regions 131 with a first conductivity type are formed.

[0097] The doping concentration of the first source region 131 is greater than that of the drift region 110, and the projection of the first source region 131 onto the substrate 100 coincides with the projection of the gate structure 120 (i.e., the edge of the first source region 131 extends below or is aligned with the gate structure 120). On a plane parallel to the surface of the substrate 100, the ratio of the total area of ​​the first source region 131 to the total area of ​​the source regions is less than 1 / 2.

[0098] Specifically, an implantation window for the first source region 131 is defined at a predetermined source region location in the bulk region 130 using photolithography. This window is located inside the gate structure 120, with its edge substantially aligned with the edge of the sidewall 121 inside the gate structure 120, ensuring that the first source region 131 can extend self-aligned below the gate structure 120. Ion implantation is then performed to implant heavily doped ions of a first conductivity type, such as arsenic (As) or phosphorus (P) for N-type devices, forming a high-concentration N+ source region. After implantation, the photoresist pattern can be retained as a partial mask for subsequent second source region implantation, or it can be removed before re-lithography.

[0099] At least one second source region 132 having a second conductivity type is formed in the body region 130.

[0100] The doping concentration of the second source region 132 is greater than that of the body region 130, and the projection of the second source region 132 onto the substrate 100 cancels out the projection of the gate structure 120.

[0101] The dopant type implanted in the second source region 132 is opposite to that of the first source region 131.

[0102] Referring to Figures 8 to 10 , Figure 8 FIG. is a schematic cross-sectional structure and a corresponding partial top view structure of a semiconductor structure in an embodiment of the present disclosure. Among them, the cross-sectional structure of the semiconductor structure corresponds to the top view part through dashed lines A1, A2, and A3, and the top view part is a top view of a partial structure. Figure 9 and Figure 10 FIG. is a schematic diagram of a partial top view structure of a semiconductor structure in an embodiment of the present disclosure.

[0103] The second source region 132 has a connecting portion 1321 and a plurality of extending portions 1322. The extending portions 1322 extend from both sides of the connecting portion 1321 along the carrier movement direction, and the projection of the extending portions 1322 on the substrate 100 abuts against the projection of the gate structure 120. The number of the first source regions 131 is two groups, which are respectively located between adjacent extending portions 1322 on one side of the gate structure 120 and are adjacent to the connecting portion 1321. Adjacent devices can share the second source region 132, and the second source region 132 is overall in a "rich" - shaped layout.

[0104] A window of the second source region 132 is defined by a lithography process, and the window pattern includes a connecting portion 1321 and a plurality of extending portions 1322. This window covers the region where part of the original first source region 131 is located. Subsequently, ion implantation is performed to implant heavily doped ions of the second conductive type. For example, boron or boron fluoride is implanted for a P - type device. The implantation dose of the second source region 132 is greater than the implantation dose of the first source region 131 within this window to ensure that it can compensate and invert the original N+ doping to form a P+ region.

[0105] The second source region 132 divides the first source region 131 into multiple independent regions.

[0106] The number of the first source regions 131 can be the same as the number of subsequent first source plugs and correspond one by one.

[0107] The junction depth of the second source region 132 is greater than that of the first source region 131, so as to form a good electrical connection with the underlying body region 130.

[0108] The window area of the second source region 132 is greater than 50% of the total source region window area to ensure sufficient body region lead - out area.

[0109] It should be noted that the overall layout of the second source region 132 is in the shape of the Chinese character "丰", which does not mean that there are three extension parts 1322 on each side of the connecting part 1321. The number of extension parts 1322 on one side of the connecting part 1321 can be one, two, three, four, etc. The present disclosure does not limit the number of extension parts 1322 in this regard.

[0110] See Figure 9 , in some embodiments, the first source region 131 may be in a comb shape. In the direction perpendicular to the carrier flow direction, the protruding parts of the first source region 131 and the extension parts 1322 of the second source region 132 are arranged alternately.

[0111] See Figure 10 , the second source region 132 is a plurality of second sub-source regions 1323 extending along the carrier movement direction and spaced from each other, and their projections on the substrate 100 coincide with the projection of the gate structure 120. The first source region 131 and the second sub-source regions 1323 are arranged staggeredly in the direction perpendicular to the carrier movement direction.

[0112] Specifically, windows of a plurality of mutually spaced second sub-source regions 1323 are defined by a lithography process. These windows extend along the carrier movement direction and are arranged alternately in the direction perpendicular to the carrier movement direction. By ion implantation, heavily doped ions of the second conductive type are implanted. The implantation dose of the second source region 132 is also greater than the implantation dose of the first source region 131 in the corresponding region to achieve doping compensation and inversion. The total window area of the second sub-source regions 1323 is also greater than 50% of the total window area of the source region.

[0113] The shape of the Chinese character "丰" formed by the connecting part 1321 and the extension part 1322 provides a continuous body region lead-out path for the second source region 132, significantly reducing the parasitic resistance of the body region 130; two groups of the first source regions 131 are located between the extension parts 1322, effectively reducing the electron injection area, and the total area ratio of the first source region is less than 1 / 2, achieving the dual effects of low-resistance lead-out of the body region and reduction of the electron injection area, and improving the anti-thermal failure ability of the semiconductor structure.

[0114] The staggered arrangement of a plurality of second sub-source regions 1323 and the first source region 131 achieves the dual effects of low-resistance lead-out of the body region and reduction of the electron injection area, which can effectively suppress the parasitic NPN trigger and improve the anti-thermal failure ability of the semiconductor structure.

[0115] It should be noted that the overall layout of the plurality of second sub-source regions 1323 is in the shape of the Chinese character "三", which does not mean that the number of the second sub-source regions 1323 is three. The number of the second sub-source regions 1323 can be one, two, three, four, etc. The present disclosure does not limit the number of the second sub-source regions 1323 in this regard.

[0116] Forming a source region contact plug.

[0117] The first source region contact plug is electrically connected to the first source region 131 and is used to lead out the potential of the source region through the subsequent metal layer.

[0118] Specifically, an interlayer dielectric layer (not shown) is deposited above the substrate 100, covering the entire device surface, including the gate structure 120, field plate structure 103, sidewall 121, source region, and drain region 133. The interlayer dielectric layer is then planarized. Using photolithography and etching processes, contact holes are opened at positions corresponding to the first source region 131, exposing a portion of the silicon surface of the first source region 131. Conductive material is filled into the contact holes to form a first source region contact plug. The upper surface of the first source region contact plug is substantially flush with the upper surface of the interlayer dielectric layer. For the second source region 132, a second source region contact plug can be formed in the same manner, or it can be made to directly contact the source metal layer in subsequent steps.

[0119] A source metal layer (not shown) is formed.

[0120] The source metal layer is located above the first source region contact plug and is electrically connected to a plurality of the first source region contact plugs and to the second source region 132.

[0121] Specifically, a metal layer is deposited above the interlayer dielectric layer and the contact plugs. The metal layer is patterned by photolithography and etching to form a source metal layer that covers the entire area above the source region, ensuring electrical connection with all first source region contact plugs and the second source region 132 (directly or through contact plugs).

[0122] In some embodiments, metal grooves can be formed in the interlayer medium, the metal grooves can be filled, and the medium can be planarized to obtain the source metal layer.

[0123] In some embodiments, the source metal layer shorts the first source region 131 and the second source region 132 to the same potential (source potential), so that the second source region 132 can effectively reduce the parasitic resistance of the body region 130.

[0124] Accordingly, this disclosure also provides a semiconductor structure.

[0125] See also Figures 8 to 10 The semiconductor structure includes a substrate 100.

[0126] The substrate 100 is used to provide a process platform for semiconductor structures. The material of the substrate 100 is single-crystal silicon. In other embodiments, the material of the substrate 100 may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium dihydrogen nitride. The substrate 100 may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. In other embodiments, the surface of the substrate 100 may also have an epitaxial layer with the same crystal structure as the substrate 100.

[0127] The substrate 100 includes a shallow trench isolation structure 101. The shallow trench isolation structure 101 defines the location of the active region and provides electrical isolation for device structures such as the drift region 110 and the body region 130. The shallow trench isolation structure 101 is made of silicon oxide, which is filled into the shallow trenches using a high-density plasma chemical vapor deposition process and planarized by chemical mechanical polishing, with its surface flush with the surface of the substrate 100.

[0128] The semiconductor structure also includes a drift region 110.

[0129] The drift region 110 is located within the substrate 100 and has a first conductivity type.

[0130] The drift region 110 is located between adjacent shallow trench isolation structures 101, that is, within the active region defined by the shallow trench isolation structure 101.

[0131] In this embodiment, the first conductivity type is N-type, and the doping ions of the drift region 110 are phosphorus or arsenic.

[0132] The drift region 110 is used to withstand the reverse bias voltage and provide a transport path for majority carriers.

[0133] The semiconductor structure further includes: a gate oxide layer 102, a field plate structure 103, and at least two gate structures 120.

[0134] The gate oxide layer 102 is located below the gate structure 120.

[0135] The gate oxide layer 102 is a thin silicon oxide layer, the thickness of which is determined by the operating voltage of the device.

[0136] Part of the gate oxide layer 102 is located above the field oxide layer (not shown) and below the field plate structure 103. The field oxide layer is located above the drift region 110, and the thickness of the field oxide layer is greater than the thickness of the gate oxide layer 102.

[0137] The field plate structure 103 is located above the drift region 110 and above the field oxide layer. The field plate structure 103 is used to modulate the electric field distribution on the surface of the drift region 110. The field plate structure 103 is located away from the first source region (i.e., near the drain region).

[0138] The field plate structure 103 and the gate structure 120 are formed by patterning the same polysilicon layer, and a portion of the gate structure 120 extends above the field plate structure 103.

[0139] The field plate structure 103 and the gate structure 120 can be physically continuous or disconnected.

[0140] In some embodiments, the field plate structure 103 is located on the field oxide layer, and the gate structure 120 is located on the gate oxide layer.

[0141] The at least two gate structures 120 are symmetrically located on both sides of the source region. The gate structures 120 respectively cover the edge regions on both sides of the body region 130. The gate structures 120 are made of polycrystalline silicon and have sidewalls 121 on their top and sidewalls.

[0142] The semiconductor structure also includes: sidewall 121.

[0143] The sidewall 121 is located on the sidewall of the gate structure 120.

[0144] In some embodiments, the sidewall 121 also extends to the sidewall of the field plate structure 103.

[0145] The sidewall 121 is used to protect the gate edge, define the self-alignment boundary of the source / drain injection, and adjust the parasitic capacitance between the gate and the source / drain region.

[0146] The sidewall 121 is made of silicon nitride, silicon oxide, or a composite of both.

[0147] The semiconductor structure also includes a body region 130.

[0148] The body region 130 is located within the drift region 110 and has a second conductivity type opposite to the first conductivity type. The second conductivity type is P-type. The body region 130 is located within the drift region 110 between two adjacent gate structures 120, and the edges on both sides of the body region 130 extend below the adjacent gate structures 120, respectively.

[0149] In this embodiment, the dopant of the body region 130 is boron, its junction depth reaches a predetermined value, and the edges on both sides of the body region 130 laterally diffuse to the bottom of the gate structure 120.

[0150] The gate structure 120 covers the edge region of the body region 130.

[0151] One of the body regions 130 simultaneously serves two symmetrical LDMOS cells on the left and right.

[0152] The semiconductor structure also includes a drain region 133.

[0153] The drain region 133 corresponds one-to-one with the gate structure 120, and is located within the drift region 110 on one side of each gate structure 120, away from the source region. The drain region 133 is located in the drift region 110 outside the gate structure 120 (i.e., away from the source region). The drain region 133 is a heavily doped region (N+) of the first conductivity type, with a doping concentration higher than that of the drift region 110, and maintains an appropriate lateral spacing with the edge of the sidewall 121 outside the gate structure 120. The dopant ions of the drain region 133 are arsenic or phosphorus, which have a high doping concentration and low resistivity, enabling them to form a good ohmic connection with the drain electrode.

[0154] The semiconductor structure also includes a source region.

[0155] The source region is located within the body region 130.

[0156] The source region includes at least one set of first source regions 131 and at least one second source region 132.

[0157] The first source region 131 has the first conductivity type (such as N+) and the doping concentration is greater than that of the drift region 110.

[0158] The projection of the first source region 131 onto the substrate 100 is opposite to the projection of the gate structure 120 onto the substrate 100 (i.e., the edge of the first source region 131 extends below or is aligned with the gate structure 120).

[0159] On a plane parallel to the surface of the substrate 100, the ratio of the total area of ​​the first source region 131 to the total area of ​​the source region is less than 1 / 2.

[0160] The first source region 131 is a high-concentration N+ source region.

[0161] The second source region 132 has the second conductivity type (e.g., P+) and the doping concentration is greater than that of the body region 130.

[0162] The projection of the second source region 132 onto the substrate 100 cancels out the projection of the gate structure 120 onto the substrate 100.

[0163] The dopant type of the second source region 132 is opposite to that of the first source region 131.

[0164] The junction depth of the second source region 132 is greater than that of the first source region 131, so as to form a good electrical connection with the underlying body region 130.

[0165] The second source region 132 is electrically connected to the body region 130 in the body region 130, and both the first source region 131 and the second source region 132 are in electrical contact with the source metal layer.

[0166] In some embodiments, the second source region 132 has a connecting portion 1321 and a plurality of extending portions 1322.

[0167] The extending portions 1322 extend from both sides of the connecting portion 1321 along the carrier movement direction, and the projection of the extending portions 1322 on the substrate 100 abuts against the projection of the gate structure 120.

[0168] The number of the first source regions 131 is two groups, which are respectively located between adjacent extending portions 1322 on one side of the gate structure 120 and are adjacent to the connecting portion 1321. The second source region 132 is shared by adjacent devices, and the second source region 132 is overall in a "rich" - shaped layout. The second source region 132 divides the first source region 131 into multiple independent regions.

[0169] In some embodiments, the number of the first source regions 131 is the same as the number of subsequent first source contact plugs and they correspond one by one.

[0170] The window area of the second source region 132 is greater than 50% of the total window area of the source regions to ensure sufficient body region lead - out area.

[0171] The "rich" - shaped second source region 132 formed by the connecting portion 1321 and the extending portions 1322 provides a continuous body region lead - out path, significantly reducing the parasitic resistance of the body region 130; the two groups of the first source regions 131 are located between the extending portions 1322, effectively reducing the electron injection area, improving the thermal failure resistance of the semiconductor structure, and enhancing the reliability and robustness of the high - voltage LDMOS under the working conditions of high current and high junction temperature.

[0172] Two adjacent groups of the first source regions 131 are symmetric about the second source region 132.

[0173] In some embodiments, the second source region 132 comprises a plurality of second sub-source regions 1323 extending along the carrier movement direction and spaced apart from each other, the projection of which onto the substrate 100 coincides with the projection of the gate structure 120 onto the substrate 100. The first source region 131 and the second sub-source regions 1323 are arranged alternately perpendicular to the carrier movement direction. The alternating arrangement of the plurality of second sub-source regions 1323 and the first source region 131 achieves the dual effects of low bulk resistance extraction and reduced electron injection area, improving the thermal failure resistance of the semiconductor structure and enhancing the reliability and robustness of high-voltage LDMOS under high current and high junction temperature operating conditions.

[0174] The semiconductor structure further includes a plurality of first source region contact plugs electrically connected to the first source region 131. The number of first source region contact plugs corresponds one-to-one with the number of first source regions 131. The first source region contact plugs are used to lead out the potential of the source region through a subsequent metal layer. The first source region contact plugs fill the contact holes in the interlayer dielectric layer, and their upper surfaces are substantially flush with the upper surface of the interlayer dielectric layer.

[0175] The semiconductor structure further includes a source metal layer located above the first source region contact plugs and electrically connected to a plurality of the first source region contact plugs, and electrically connected to the second source region 132. The source metal layer covers the entire area above the source region and is electrically connected to all the first source region contact plugs and the second source region 132 (directly or through the second source region contact plugs). The source metal layer short-circuits the first source region 131 and the second source region 132 to the same source potential, so that the second source region 132 can effectively reduce the parasitic resistance of the body region 130.

[0176] The foregoing describes several embodiments of semiconductor structures and their formation methods. The various optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed in this disclosure.

[0177] This disclosure also provides a semiconductor device comprising the semiconductor structure described in any of the preceding embodiments.

[0178] The semiconductor devices include logic chips and memory chips.

[0179] It should be understood that in the embodiments of this application, the logic chip may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSPs), etc.

[0180] It should also be understood that the memory chip in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.

[0181] This disclosure also provides an electronic device, including any of the semiconductor devices described above.

[0182] The semiconductor device can be built into or externally connected to the electronic device, which includes, but is not limited to, mobile phones, computers, tablets, servers, cloud platforms, etc.

[0183] It should be noted that the illustrated embodiments only show a portion of the semiconductor structure. Those skilled in the art should understand that other embodiments obtained by mirroring, flipping, rotating, or adapting the position, relative connection, or orientation of the various structures in the semiconductor structure based on the structure shown in the figures, or by making adaptive adjustments to its shape and size, should all be considered within the scope of this disclosure.

[0184] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0185] In the embodiments of this application, "multiple" refers to two or more.

[0186] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of objects in the embodiments of this application. They cannot constitute any limitation on the embodiments of this application.

[0187] While the embodiments disclosed herein are as described above, this disclosure is not limited thereto. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A drift region, located within the substrate, and having a first conductivity type; The body region, located within the drift region, has a second conductivity type opposite to the first conductivity type; The source region is located within the body region; At least two gate structures are symmetrically located on both sides of the source region and respectively cover the edge regions on both sides of the body region; The drain regions, which correspond one-to-one with the gate structures, are located in the drift regions on one side of the gate structure and are far away from the source regions. The source region includes: At least one set of first source regions, having the first conductivity type and a doping concentration greater than that of the drift region, whose projection on the substrate coincides with the projection of the gate structure, and on a plane parallel to the surface of the substrate, the ratio of the total area of ​​the first source regions to the total area of ​​the source regions is less than 1 / 2. At least one second source region having the second conductivity type and having a doping concentration greater than that of the bulk region; The second source region has a connecting portion and multiple extensions. The extensions extend from both sides of the connecting portion along the carrier movement direction, and their projections on the substrate abut against the projection of the gate structure. The first source region is in two groups, located between adjacent extensions on one side of the gate structure and adjacent to the connecting portion; or... The second source region consists of a plurality of second sub-source regions that extend along the carrier movement direction and are spaced apart from each other. Their projections on the substrate overlap with the projections of the gate structure. The first source region and the second sub-source region are arranged alternately in a direction perpendicular to the carrier movement direction.

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: a plurality of first source region contact plugs electrically connected to the first source region; The source metal layer is located above the first source region contact plug and is electrically connected to multiple first source region contact plugs.

3. The semiconductor structure according to claim 2, characterized in that, The number of contact plugs in the first source region corresponds one-to-one with the number of the first source regions.

4. The semiconductor structure according to claim 2, characterized in that, The second source region is electrically connected to the body region in the body region, and both the first source region and the second source region are electrically in contact with the source metal layer.

5. The semiconductor structure according to claim 1, characterized in that, The two adjacent sets of the first source regions are symmetrical about the second source region.

6. The semiconductor structure according to claim 1, characterized in that, It also includes a field plate structure, which is located above the drift region; A portion of the gate structure is located above the field plate structure; The field plate structure is located away from the first source region.

7. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A drift region having a first conductivity type is formed in the substrate; At least two gate structures are formed, and the at least two gate structures are symmetrically located on both sides of a predetermined source region location; A body region having a second conductivity type opposite to the first conductivity type is formed in the drift region, and the edges on both sides of the body region are respectively located below the adjacent gate structure; Drain regions are formed that correspond one-to-one with the gate structure. The drain regions are located in the drift region on one side of the gate structure and are far away from the preset source region. A source region is formed at the predetermined source region location within the body region. The step of forming the source region includes: At least one set of first source regions having the first conductivity type are formed in the body region, the doping concentration of the first source regions is greater than the doping concentration of the drift region, the projection of the first source regions on the substrate is opposite to the projection of the gate structure, and the ratio of the total area of ​​the first source regions to the total area of ​​the source regions on a plane parallel to the surface of the substrate is less than 1 / 2. At least one second source region having the second conductivity type is formed in the body region, and the doping concentration of the second source region is greater than the doping concentration of the body region; The second source region has a connecting portion and multiple extension portions. The extension portions extend from both sides of the connecting portion along the carrier movement direction, and their projections on the substrate abut against the projection of the gate structure. The number of the first source regions is two sets, located between adjacent extension portions on one side of the gate structure and adjacent to the connecting portion. Alternatively, the second source region is a plurality of second sub-source regions that extend along the carrier movement direction and are spaced apart from each other. Their projections on the substrate abut against the projection of the gate structure. The first source regions and the second sub-source regions are arranged alternately in a direction perpendicular to the carrier movement direction.

8. The method according to claim 7, characterized in that, The method further includes: Multiple first source region contact plugs are formed, and the first source region contact plugs are electrically connected to the first source region. A source metal layer is formed, which is located above the first source region contact plug and is electrically connected to a plurality of first source region contact plugs and to the second source region.

9. The method according to claim 7, characterized in that, The steps for forming the second source region include: The window of the second source region is defined using photolithography, and ion implantation is then performed. Wherein, the dopant type of the second source region ion implantation is opposite to that of the first source region, and the implantation dose of the second source region is greater than the implantation dose of the first source region within the window of the second source region, and the area of ​​the window of the second source region is greater than 50% of the window area of ​​the source region.

10. The method according to claim 7, characterized in that, Also includes: A field plate structure is formed above the drift region; The field plate structure and the gate structure are patterned from the same material layer, and the field plate structure and the gate structure are formed in the same step. The field plate structure is located on the field oxide layer, and the gate structure is located on the gate oxide layer.

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