Voltage data capture circuit and technique

Abstract

Voltage data acquisition circuitry and techniques are disclosed. In one example, a circuit includes a differential transconductance stage (306), a differential transimpedance stage (308), and an analog-to-digital converter (ADC) (304). The differential transconductance stage (306) is configured to convert a differential input voltage (318) into a differential current, and the differential transimpedance stage (308) is configured to convert the differential current into a differential output voltage. The ADC (304) is configured to sample the differential output voltage to generate a digital output signal (210). The circuit may further include a common-mode voltage regulator (310) configured to regulate the common-mode input voltage of the differential transimpedance stage (308). The circuit can be used, for example, in battery monitoring systems or other voltage monitoring applications.

Description

[0001] This specification relates to data acquisition devices, and more specifically, to voltage data acquisition circuitry and techniques. Background Technology

[0002] Many circuit applications require ensuring that a given supply voltage is within an acceptable range for the application. For example, automotive applications use batteries (or a battery bank) to supply various voltages to the vehicle's electrical system, and these supply voltages must be within target ranges for the circuitry to function properly. Therefore, voltage monitoring circuits can be used to provide samples of the monitored voltage. The sampled voltage is input to an analog-to-digital converter (ADC), which in turn provides digital output data representing the monitored voltage. If the monitored voltage is found to be outside tolerances, remedial measures can be taken. However, several significant issues remain regarding accurate voltage measurement / monitoring, particularly in high-voltage applications. Summary of the Invention

[0003] According to one example, a circuit includes a differential transconductance stage configured to convert a differential input voltage into a differential current, a differential transimpedance stage configured to convert the differential current into a differential output voltage, a common-mode voltage regulator configured to regulate the common-mode input voltage of the differential transimpedance stage, and an analog-to-digital converter configured to sample the differential output voltage to generate a digital output signal.

[0004] According to another example, a circuit includes: a differential transimpedance amplifier having a first input terminal, a second input terminal, a first output terminal, and a second output terminal; and a differential transconductance stage comprising a first transistor series coupled between a voltage supply terminal and the first input terminal of the differential transimpedance amplifier, and a second transistor series coupled between the voltage supply terminal and the second input terminal of the differential transimpedance amplifier. The differential transconductance stage further includes: a first unity-gain buffer having a first input terminal coupled to a first input voltage terminal, a second input terminal coupled to a voltage supply terminal, and an output coupled to a control terminal of the first transistor; a second unity-gain buffer having a first input terminal coupled to a second input voltage terminal, a second input terminal coupled to a voltage supply terminal, and an output coupled to a control terminal of the second transistor; and a resistor coupled between the second input terminals of the first unity-gain buffer and the second input terminal of the second unity-gain buffer. The circuit further includes an analog-to-digital converter having a first input terminal and a second input terminal respectively coupled to the first output terminal and the second output terminal of the differential transimpedance amplifier.

[0005] According to another example, a circuit includes a differential transconductance stage configured to generate a differential current based on a first input voltage and a second input voltage received at a first input voltage terminal and a second input voltage terminal, respectively. The differential transconductance stage includes: a first unity-gain buffer having a first input terminal and a second input terminal switchably coupled to a first input voltage terminal and a voltage supply terminal; a second unity-gain buffer having a first input terminal and a second input terminal switchably coupled to a second input voltage terminal and a voltage supply terminal; and a resistor coupled between the first unity-gain buffer and the second unity-gain buffer. The circuit further includes: a differential transimpedance stage coupled to the differential transconductance stage and configured to convert the differential current into a differential output voltage; and a chopper circuit system having a clock terminal and configured to switch the first input terminal and the second input terminal of each of the first unity-gain buffer and the second unity-gain buffer according to the frequency of a chopper clock signal received via the clock terminal. Attached Figure Description

[0006] Figure 1 This is a block diagram of the battery monitoring system in the example.

[0007] Figure 2 This is a block diagram of the battery monitoring signal chain in the example.

[0008] Figure 3 This is a block diagram illustrating the differential voltage measurement circuit system in the example.

[0009] Figure 4 This is an example illustrating a system containing a chopper circuit. Figure 3 Block diagram of the differential voltage measurement circuit system.

[0010] Figure 5 In another instance Figure 3 A schematic diagram of a differential voltage measurement circuit system.

[0011] Figure 6A This shows instances that can be included. Figure 3-5 The circuit diagram of the operational amplifier in the differential voltage measurement circuit system.

[0012] Figure 6B This shows the formation in the example. Figure 6A A circuit diagram of a part of the operational amplifier circuit system.

[0013] Figure 6C This is an example shown for... Figure 6A A circuit diagram of an example of an operational amplifier chopper circuit system.

[0014] Figure 7This is a schematic diagram illustrating an analog-to-digital converter (ADC) including a chopper circuit system in an example. The chopper circuit system may be included in... Figure 3-5 In the differential voltage measurement circuit system. Detailed Implementation

[0015] Techniques for acquiring voltage measurements are described. These techniques can be used in a variety of circuits and systems, including, for example, battery monitoring systems. As described in more detail below, these techniques can be used to provide a fully differential signal chain to achieve high measurement accuracy (e.g., better than 2 mV DC accuracy) and relatively low noise floor over a measurement voltage range that can be from negative to positive voltages (e.g., -2 V to 5.5 V). In an example, the circuit includes a differential transconductance stage, a differential transimpedance stage, and an analog-to-digital converter (ADC). The differential transconductance stage is configured to convert a differential input voltage to a differential current, and the differential transimpedance stage is configured to convert the differential current to a differential output voltage. The ADC is configured to sample the differential output voltage to generate a digital output signal. The circuit may further include a common-mode voltage regulator configured to regulate the common-mode input voltage for the differential transimpedance stage. As described further below, in some such examples, the differential transconductance stage includes a pair of unity-gain buffers. Furthermore, in some instances, the circuit includes an offset stage configured to adjust the differential current converted by the differential transimpedance stage based on the ADC's input range, thereby reducing the ADC's input-referred error. This circuit can be used, for example, in battery monitoring applications. These and other aspects are described in more detail below.

[0016] General Overview

[0017] As mentioned above, many significant challenges are associated with performing accurate voltage measurements in voltage monitoring applications. For example, in some measurement systems, raw DC error can limit the accuracy of achievable measurements. Raw DC error (or simply raw error) refers to the error in the DC (direct current) voltage measurement channel. One possible solution to this problem is to perform digital calibration during the manufacture of the voltage measurement system to compensate for this channel error as much as possible. However, in some cases, the expected tolerance of the monitored voltage may exceed the test measurement accuracy, thus accuracy limitations still exist after calibration. For example, in some cases with a tolerance of + / -2 millivolts for voltages in the range of 0.5 volts to 5.5 volts, digital calibration may overcompensate for channel error, while in other cases it may undercompensate. Furthermore, it is expected that future generations of voltage monitoring circuitry systems will support lower noise densities (noise floor) and wider input voltage ranges (e.g., -2 volts to 5.5 volts) while meeting even more stringent tolerance requirements.

[0018] Therefore, the voltage measurement circuit described herein supports lower noise density and provides improved test measurement accuracy compared to other voltage measurement techniques. Furthermore, as described below, in some instances, the voltage measurement device can support a relatively wide range of input voltages, including negative input voltages. According to some instances, the voltage data acquisition device for voltage measurement implements a fully differential signal chain to achieve these and other benefits. In some instances, the fully differential signal chain includes an analog front-end with a differential transconductance (GM) stage and a differential transimpedance (TIA) stage, followed by a unity-gain Δ-Σ analog-to-digital converter (ADC). In some examples, the differential transconductance stage can support relatively high input voltages (e.g., a common-mode voltage of 150 V) and includes a pair of low-voltage unity-gain buffers and resistors that together generate a differential current proportional to the differential input voltage. The low-voltage differential transimpedance stage converts the differential current into a differential voltage with a selected gain. In some instances, the analog front-end includes an offset stage to center the unipolar input at zero in order to maximize the gain of the analog front-end, as further described below. An ADC digitizes the differential voltage supplied across an impedance level to produce a digital measurement of the input voltage. By using a fully differential signal chain, common-mode noise can be eliminated or reduced to a negligible level, significantly reducing noise density and improving measurement accuracy by minimizing channel native error. As described in more detail below, integrated solutions incorporating an analog front-end and a delta-Σ ADC can produce signal measurements with sufficiently low native error to potentially avoid the need for digital calibration, and thus further avoid limitations regarding the accuracy of the test equipment that might be used for calibration.

[0019] System Architecture

[0020] Battery monitoring is one example of an application where providing accurate voltage measurements may be desirable. For instance, many systems and devices, including electric vehicles and computing devices, require monitoring of the state of charge of their batteries to provide an estimate of the remaining charge and, consequently, the amount of time the system or device can use before the battery needs to be recharged. In some systems or devices (e.g., electric vehicles), accurate battery voltage measurement may be important for informing the user how much remaining usage time (e.g., the vehicle's range) is available. Similarly, monitoring the various supply voltages derived from these batteries may be desirable to ensure the proper operation of the various systems powered by them.

[0021] Figure 1This is a block diagram of a battery monitoring system based on an example, including the circuitry. A battery pack 102 contains multiple battery groups 104 (individually identified as battery groups 104a, 104b, ..., 104n), each containing one or more battery cells 106. Battery monitoring devices 108 (individually identified as battery monitoring devices 108a, 108b, ..., 108n) are coupled to the battery groups 104. In some applications, such as battery monitoring in electric vehicles, the total voltage across the battery pack 102 may be relatively high, for example, up to approximately 800 V or higher. Since a single battery monitoring device 108 may not be able to accurately measure the full voltage of the battery pack 102, the battery cells 106 of the battery pack 102 can be grouped into multiple battery groups 104, such that each battery monitoring device 108a-n measures the voltage across the corresponding battery group 104a-n. Therefore, Figure 1 The battery monitoring system can be called a "stackable battery monitor" because the battery monitoring device 108a-n can be like... Figure 1 The cells are "stacked" and connected together. For example, battery monitoring device 108a can read the voltage from battery pack 104a and provide an output measurement signal to battery monitoring device 108b. Battery monitoring device 108b then reads the voltage from battery pack 104b and provides an output measurement signal (which includes its own measurement value and the measurement value received from battery monitoring device 108a) to the next battery monitoring device in the stack. This arrangement continues to the last battery monitoring device 108n in the battery stack, which provides the final grouped measurement values ​​from the complete stack to the base device 114.

[0022] The base unit 114 includes a base component 116 that collects voltage measurements from the stack of battery monitoring devices 108a-n as described above. The battery monitoring devices 108a-n and the base component 116 can be connected together via a high-voltage isolation element 112, as shown. Each of the battery monitoring devices 108a-n includes a voltage measuring device 110, which may include a voltage data acquisition circuitry system, as referenced below. Figure 2-7Further described. In the base unit 114, a base component 116 is coupled to a microcontroller unit (MCU) 118. The base component 116 communicates with the MCU 118 via a serial communication interface as indicated by 120. For example, the base component 116 may provide information representing voltage measurements of the battery pack 102 to the MCU 118. The MCU 118 may include, for example, input and output ports and a processor, or may otherwise be configured to process this information, use the information in various ways depending on the application using the battery monitoring system, and / or transmit the information to one or more external systems or devices. For example, the base component 116 and the MCU 118 may be coupled to a ground reference 122, such as the chassis of an electric vehicle.

[0023] Figure 2 For example, it can be shown that... Figure 1 Examples of battery monitoring signal chains or circuits used in the system. Such battery monitoring signal circuits can be implemented, for example, within each voltage measurement device 110. As shown, an analog front end 202 couples across the battery pack 104 and measures the differential voltage (VC). n+1 With VC n The difference between them). Although Figure 2 Only one signal chain is shown, but the corresponding analog front-end 202 can be coupled across each battery pack 104 in the battery pack 102 to allow simultaneous measurement of the voltage at each battery pack 104. (See above reference.) Figure 1 Each battery pack 104 may contain one or more battery cells 106.

[0024] The analog front end 202 provides an output measurement signal to the analog-to-digital converter (ADC) 204 corresponding to the measured voltage at the corresponding battery pack 104. In some instances, a buffer 206 is coupled between the analog front end 202 and the ADC 204, such as... Figure 2 As shown. See below for reference. Figure 3-7 A further description of an example simulating a 202 front-end error.

[0025] The ADC 204 digitizes the output measurement signal received from the analog front-end 202 and provides a digital sample 210 of the voltage at the battery pack 104 to the digital circuit system 220. The reference circuit system 208 provides the operating voltage range for the ADC 204. In the illustrated example, the digital circuit system 220 includes a digital low-pass filter 212 and a temperature correction circuit system 214. In some examples, the temperature correction circuit system 214 is configured to provide digital compensation or correction for temperature variations in the battery pack 102 that may affect the voltage measurements. The temperature correction circuit system 214 may be coupled to a temperature sensor 216 that provides temperature measurements. In some examples, the temperature correction circuit system 214 is configured to provide second-order temperature correction (based on three temperature measurements from the temperature sensor 216). In other examples, the temperature correction circuit system 214 may be configured to provide third-order temperature correction (based on four temperature measurements from the temperature sensor 216). In some instances, the digital circuit system 220 is further coupled to a strain gauge 218, which can provide additional measurements that can be used to provide digital correction for voltage measurements obtained from the analog front end 202.

[0026] like Figure 2 As shown, the analog front-end 202 provides the initial voltage measurement from the battery pack 102 to the ADC for digitization and further processing. In some instances, the analog front-end 202 provides a single-ended output signal to one terminal of a relatively large (e.g., 600 kΩ) resistor, with the other terminal of the resistor coupled to a voltage reference. The input of the ADC 204 is coupled across the resistor to produce the input signal for the ADC 204. This large output impedance from the analog front-end 202 makes it sensitive to input reference noise or kickback from the ADC 204 and can result in poor linearity. Furthermore, in the single-ended configuration, only half of the positive range of the input voltage of the ADC 204 is used. In some instances, the analog front-end 202 can be configured to use an auto-zeroing technique to remove voltage offset; however, in this case, the noise floor may be high due to aliasing. For example, in applications involving a main amplifier and a zero-adjustment amplifier, an example of auto-zeroing could involve measuring the offset voltage of the zero-adjustment amplifier during a first clock phase and storing the measurement on a first sample-and-hold capacitor, and measuring and (on a second sample-and-hold capacitor) storing the offset voltage of the main amplifier during a second clock phase. The total offset can then be applied to the main amplifier when processing the input signal. Because this auto-zeroing technique uses sampling to correct the offset, sampling can cause noise aliasing back into the baseband, and therefore, this auto-zeroing amplifier configuration can suffer from relatively high in-band noise. To suppress noise, a larger current can be used; however, this operation results in higher power dissipation, which may be undesirable in some applications.

[0027] To address these drawbacks associated with the single-ended front-end 202, the analog front-end 202 may include a fully differential measurement signal channel to provide differential output measurement signals to the ADC 204. Compared to the single-ended configuration, the fully differential configuration of the analog front-end 202 (see reference below) Figure 3-7 The described ADC 204 can provide significantly improved common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR). For example, some examples of fully differential analog front-ends as described herein can achieve a CMRR greater than 100 dB over an input voltage range of 0–100 V. Therefore, such implementations can achieve significantly lower noise floor. Furthermore, by providing a differential output measurement signal and, where possible, using an offset stage to center the voltage at zero, the need for auto-zeroing techniques can be avoided, and the full input voltage range of the ADC 204 can be utilized, as further described below.

[0028] Example circuit implementation plan

[0029] refer to Figure 3 The diagram shows a block diagram of a voltage measurement circuit system including an analog front-end 302 coupled to an ADC 304, according to one example. In some examples, the analog front-end 302 can be used to implement... Figure 2 A fully differential version of the analog front-end 202 in the signal chain. Additionally, in some instances, the ADC 304 corresponds to or can be used to implement... Figure 2 The ADC 204 is part of the signal chain. In some instances, the ADC 304 is a unity-gain Δ-Σ ADC 304, which receives differential measurement signals from the analog front-end 302 and provides digitized samples 210. As described above, configuring the analog front-end 302 to provide a fully differential signal chain can achieve significant advantages over single-ended configurations in similar applications.

[0030] In some instances, the analog front end 302 includes a differential transconductance stage 306, a differential transimpedance stage 308, and a differential common-mode regulator 310. The analog front end 302 may further include a voltage offset circuit 312. Each of these components is further described below.

[0031] The differential transconductance stage 306 can be coupled to voltage supply terminal 316 and receive input voltage 318. The supply voltage provided at voltage supply terminal 316 can be a relatively high voltage, for example, approximately 100 V. Figure 3 In the example shown, the input voltage 318 includes a first voltage V_pos and a second voltage V_neg. In some instances, these voltages V_pos and V_neg correspond to those mentioned in the reference above. Figure 1 and 2The voltage VC across the battery pack 104 described n+1 and VC n In some instances, the differential transconductance stage 306 operates at least partially in the high-voltage domain, for example, receiving input voltages V_pos and V_neg in the range of 80 V–150 V in some applications. However, the differential input voltage, i.e., the difference between V_pos and V_neg, can be relatively low, for example, in the range of approximately -0.05 V to 6 V. Therefore, the remaining circuitry of the analog front-end 302 (e.g., the differential transimpedance stage 308, the differential common-mode regulator 310, and the voltage offset circuit 312) can operate in the low-voltage domain. Figure 3 In the diagram, the separation between the high-voltage and low-voltage domains is indicated by line 314. The differential transconductance stage 306 generates a differential current supplied to the differential transimpedance stage 308 based on the differential input voltage 318. In some instances, the differential current is proportional to the differential input voltage 318.

[0032] The differential transimpedance stage 308 converts the differential current received from the differential transconductance stage 306 into a differential voltage output to the ADC 304. In some instances, the differential common-mode regulator 310 operates to stabilize the common-mode voltage at the input of the differential transimpedance stage 308, as further described below.

[0033] In certain instances, some or all of the differential transconductance stage 306, differential transimpedance stage 308, differential common-mode regulator 310, voltage offset circuit 312, and / or ADC 304 may be implemented using one or more amplifiers, as referenced below. Figure 5-7 Further described. In some instances, some or all of the inputs to these various amplifiers are “chopped” (e.g., their inputs are rapidly switched), and the outputs are “de-chopped” (e.g., rapidly switched in the same manner as the inputs). Thus, the voltage output from the amplifier has the desired voltage level, but the offset is modulated according to the chopping frequency (e.g., the frequency at which chopping occurs, such as the frequency at which the amplifier inputs are switched). The use of chopping can reduce offset and “flicker” noise (e.g., 1 / f noise) without the disadvantages associated with using auto-zeroing techniques. As mentioned above, using auto-zeroing to remove offset can result in a higher noise floor due to aliasing. Conversely, using chopping can remove offset and flicker noise to produce a relatively clean noise floor where little noise is aliased back into the signal.

[0034] Therefore, refer to Figure 4In some instances, the analog front end 302 includes a chopper circuitry system for implementing chopping (and de-chopping) functions at various amplifier and / or other circuitry inputs / outputs. As described in more detail below, in some instances, the differential transconductance stage 306 includes a pair of unity-gain buffers, which can be implemented using operational amplifiers. In some instances, the chopper circuitry system 402 is used to implement chopping at these unity-gain buffers. As mentioned above, the input voltages V_pos and V_neg can contain relatively high voltages, causing the differential transconductance stage 306 to operate at least partially in the high-voltage domain, such as... Figure 3 As shown. Therefore, and as described in more detail below, techniques can be implemented in the differential transconductance stage 306 and the chopper circuit system 402 to generate a virtual low-voltage environment in the high-voltage domain, such that chopping performed by the chopper circuit system 402 can be performed at low voltage. In some instances, the chopper circuit system 402 is coupled to the differential transconductance stage 306. In other instances, some or all of the chopper circuit system 402 may be part of the differential transconductance stage 306.

[0035] The chopper circuit system 402 operates to perform chopping at a chopping frequency set by a chopping clock signal. Therefore, in some instances, the analog front-end 302 includes a chopping clock source 404. In other instances, for example, the chopping clock source may be external to the analog front-end 302, and the chopping clock signal may be received via input / output terminals.

[0036] In the low voltage domain (in Figure 3Below line 314 in the diagram, chopper circuitry system 406 can be used to implement chopping at some or all of the amplifiers included in the components of analog front-end 302 and / or ADC 304. In some instances, analog front-end 302 includes chopper circuitry system 406a that performs chopping in differential transimpedance stage 308 and / or common-mode regulator 310. Chopper circuitry system 406a can be part of differential transimpedance stage 308 and / or common-mode regulator 310, or can be coupled to components of differential transimpedance stage 308 and / or common-mode regulator 310. In instances where analog front-end 302 includes voltage offset circuitry 312, analog front-end 302 can also include chopper circuitry system 406b. Chopper circuitry system 406b can be coupled to voltage offset circuitry 312 and / or is part of said voltage offset circuitry. In some instances, analog front-end 302 further includes chopper circuitry system 406c that can be coupled to ADC 304. In other instances, chopper circuitry 406c can be external to analog front-end 302. Chopper circuitry 406a, 406b, and 406c, as well as chopper circuitry 402, can be coupled to chopper clock source 404 to receive the same chopper clock signal. This ensures that all chopping operations in analog front-end 302 and ADC 304 can be performed synchronously, without considering timing variations between different chopper clocks.

[0037] refer to Figure 5 , shows Figure 3 A schematic diagram of an example of a differential voltage measurement circuit system is provided. As described above, in this example, the differential transconductance stage 306 includes a pair of unity-gain buffers 504a and 504b, with an input voltage 318 across the buffer resistor 506. As shown, the input voltage V_pos is supplied to the first input terminal of the first unity-gain buffer 504a, and the input voltage V_neg is supplied to the first input terminal of the second unity-gain buffer 504b. The second input terminals of the first unity-gain buffer 504a and the second unity-gain buffer 504b are coupled to the voltage supply terminal 316 via current sources 508a and 508b, respectively. The outputs of the first unity-gain buffer 504a and the second unity-gain buffer 504b are coupled to the control terminals of the corresponding transistors 502. When the input voltages V_pos and V_neg are supplied to the input terminals of the first unity-gain buffer 504a and the second unity-gain buffer 504b respectively, current flows through the resistor 506 coupled between the two unity-gain buffers 504a and 504b, and differential output current is generated at the output terminals 510a and 501b of the differential transconductance stage 306.

[0038] The output terminals 510a and 510b of the differential transconductance stage 306 are coupled to the input terminals 512a and 512b of the differential transimpedance stage 308, respectively. Therefore, the differential current generated by the differential transconductance stage 306 flows to the input terminals 512a and 512b of the differential transimpedance stage 308. The differential transimpedance stage 308 includes a transimpedance amplifier 514, which has input terminals coupled to or corresponding to the input terminals 512a and 512b of the differential transimpedance stage 308. Feedback paths from the output terminals of the transimpedance amplifier 514 to its input terminals are provided via resistors 516a and 516b, respectively. The output terminals of the transimpedance amplifier 514 are coupled to the input terminals 522a and 522b of the ADC 304, respectively. The transimpedance amplifier 514 converts the differential current received at input terminals 512a and 512b into differential output voltages provided to input terminals 522a and 522b of the ADC 304.

[0039] As described above, in some single-ended implementations of the analog front-end 202, a large resistor is placed at the output to provide a single-ended input voltage to the ADC 204. Due to this high output impedance, the analog front-end 202 may be susceptible to sampling kickback from the ADC 204. Conversely, the fully differential transimpedance stage 308 can present a low output impedance to the ADC 304, which may result in improved linearity and reduced input reference noise from the ADC 304. According to some examples, the differential transimpedance stage 308 includes a filter coupled between the output terminals of the transimpedance amplifier 514 and the input terminals 522a, 522b of the ADC 304. In some examples, the filter is a resistor-capacitor (RC) filter, which includes a pair of series resistors 518a, 518b and a parallel capacitor 520. Therefore, in this example, a first resistor 518a is coupled between the output terminal of the transimpedance amplifier 514 and the first input terminal 522a of the ADC 304, and a second resistor 518b is coupled between the output terminal of the transimpedance amplifier 514 and the second input terminal 522b of the ADC 304. A capacitor 520 is connected between the two input terminals 522a and 522b of the ADC 304. This RC filter can act as an anti-aliasing filter for the ADC 304.

[0040] As described above, the differential common-mode regulator 310 can be operated to stabilize the common-mode voltage at the input of the differential transimpedance stage 308. Figure 5As shown, in some examples, the differential common-mode regulator includes an operational amplifier 524 and a pair of transistors 526a and 526b. In some examples, the operational amplifier 524 has first and second (+) input terminals coupled to a first output terminal 510a and a second output terminal 510b of a differential transconductance stage 306, respectively, and a third (-) input terminal coupled to a reference voltage terminal to receive a first reference voltage (REF1). Transistors 526a and 526b are coupled between the output terminals 510a and 510b of the differential transconductance stage 306 and a ground terminal. The output terminals of the operational amplifier 524 are coupled to the control terminals of transistors 526a and 526b, which are coupled together, as shown in the diagram. Figure 5 As shown. In some instances, the differential common-mode regulator 310 provides a dummy connection and stabilizes the common-mode voltage at the input of the differential transimpedance stage 308 based on a first reference voltage REF1. This allows for optimization of the voltage margin of the transimpedance amplifier 514 in the transimpedance stage 308. For example, because variations in the common-mode voltage at the input of the differential transimpedance stage 308 can be reduced by the differential common-mode regulator 310, it may not be necessary to maintain a wide range of voltage margins to account for variations in the input common-mode voltage.

[0041] As described above, in some instances, the analog front end 302 includes a voltage offset circuit 312 configured to center the range of the differential input voltage 318 around a reference point 534 (e.g., zero volts). Therefore, in some instances, by using the voltage offset circuit 312, the center voltage at the differential inputs 512a, 512b of the transimpedance stage 308 can be made close to zero (e.g., within an acceptable tolerance for a given application, such as + / - 10 mV or other suitable tolerance). This allows the use of the full operating voltage range of the ADC 304. (Refer to the above...) Figure 2As described, the reference circuit system 208 can supply and set the reference voltage range of the ADC 304. For example, this range can be ±4 V. Therefore, by controlling the maximum absolute value of the voltage at the input terminals 522a, 522b of the ADC 304 to be no greater than the maximum reference voltage (e.g., ≤4 V) and centered at zero, the full or near-full operating range of the ADC 304 (e.g., within one or two least significant bits) can be used. For example, if the differential voltage at the input terminals 522a, 522b of the ADC 304 has a range of -1.6 V to +1.6 V, then because the signal is fully differential, a maximum input voltage of +3.2 V is generated at the ADC 304. Reversing the polarity will produce a minimum input voltage of -3.2 V. Therefore, the differential input voltage range can be -3.2 V to 3.2 V, which is relatively close to the full operating range of -4 V to +4 V for the ADC 304 in this example. In contrast, as described above, when the analog front-end 202 is configured to provide a single-ended output voltage rather than a differential output, only half of the positive range of the ADC operating voltage range (e.g., 0 V to +4 V) can be used. Furthermore, in practical applications with this single-ended configuration, the buffer 206 may limit the lower limit of the available voltage range because it may not be able to support input voltages close to 0 V (e.g., <0.5 V or other suitable tolerances). Therefore, the fully differential configuration of the example of the analog front-end 302 described herein can significantly extend the available voltage range of the ADC 304. The voltage range described above is only for illustrative purposes, and many other voltage ranges can be used, including both the reference voltage and the differential input voltage for the ADC 304.

[0042] Still referencing Figure 5 In some instances, the voltage offset circuit 312 includes a first amplifier 528a and a second amplifier 528b. The first amplifier 528a has a first input terminal coupled to a second reference voltage terminal to receive a second reference voltage REF2, and the second amplifier 528b has a first input terminal coupled to a third reference voltage terminal to receive a third reference voltage REF3. The second input terminals of the two amplifiers 528a and 528b are connected via… Figure 5 Resistor 532a is shown coupled together. Voltage offset circuit 312 may further include first transistor 530a and second transistor 530b. In the illustrated example, first transistor 530a is coupled between output terminal 510b of differential transconductance stage 306 and resistor 532, and second transistor 530b is coupled between resistor 532 and ground terminal. In some examples, output terminal of first amplifier 528a is coupled to control terminal (e.g., gate) of first transistor 530a, and output terminal of second amplifier 528b is coupled to control terminal of second transistor 530b.

[0043] In some instances, the voltage offset circuit 312 can be enabled or disabled depending on whether the differential input voltage 318 is centered at zero (or some other selected reference point). For example, in some cases, the differential input voltage may be in the range of approximately -0.05 V to +5.77 V, and therefore not centered at zero. Thus, the voltage offset circuit 312 can be enabled to center the differential voltage at the input of the transimpedance stage 308 at zero, for example, in the range of -3.2 V to +3.2 V as described above. In other instances, the differential input voltage 318 may already be centered at zero, for example, in the range of -2.91 V to +2.91 V, and therefore may not require recentering of the differential voltage at the input of the transimpedance stage 308. Therefore, in this case, the voltage offset circuit 312 can be disabled.

[0044] In some instances, the voltage offset circuit 312 is configured to generate an offset voltage by subtracting a certain offset voltage from the differential input voltage 318, so that the differential voltage at the input of the transimpedance stage 308 is centered at zero. This offset voltage can be set by the ratio of the values ​​of resistors 532 and 506. For example, if the value of resistor 506 is 20R (R is a constant value that can be chosen according to a specific application and / or circuit design) and the value of resistor 532 is 7R, the voltage subtracted by the voltage offset circuit is given by 20R / 7R = 2.86 V. For the above instances where the differential input voltage 318 is in the range of -0.05 V to +5.77 V, subtracting 2.86 V (or adding -2.86 V) using the voltage offset circuit 312 repositions the center of the voltage range of -2.91 V to +2.91 V.

[0045] Therefore, to achieve center repositioning of the input voltage of ADC 304, voltage offset circuit 312 adds an offset voltage amount to the ADC input when enabled. However, to maintain the accuracy of the measurement results, it may also be necessary to remove something from the ADC output when it is added to the ADC input. However, accurately removing it can be difficult unless the addition can be accurately measured and / or tracked. Therefore, to address this issue, voltage offset circuit 312 can be configured to operate based on the ADC reference voltage Vref. In some instances, a voltage divider is used to derive reference voltages REF2 and REF3, respectively, from the ADC reference voltage and input to the first amplifier 528a and the second amplifier 528b. In one instance, reference voltages REF2 and REF3 are selected such that REF3 - REF2 = 0.5Vref. Therefore, the offset voltage added by voltage offset circuit 312 tracks the ADC reference voltage, and the accuracy of the offset voltage is insensitive to drift in the reference voltage. Therefore, the offset voltage can be removed using fixed gain correction via digital logic within ADC 304. In some instances, a fixed digital gain can be implemented as a shift adder, which can use, for example, far fewer digital logic gates than a multiplier.

[0046] As mentioned above, in some instances, chopping is used to reduce noise in the signal chain. (Reference) Figure 3-5 In the low voltage domain (in Figure 3 Below line 314 in the diagram, chopper circuit system 406a can be used to interchange the input terminals of transimpedance amplifier 514 and amplifier 524. Similarly, chopper circuit system 406b can be used to interchange the inputs of first amplifier 528a and second amplifier 528b, as shown below. Figure 5 As shown. Additionally, the chopper circuit system 406c can be used to switch the inputs 522a and 522b of the ADC 304. However, as mentioned above, the voltages V_pos and V_neg input to the amplifiers 504a and 504b of the differential transconductance stage 306, respectively, can be relatively high voltages, such as 90 V, 95 V, 100 V, or higher, and therefore, the chopper circuit system 402 may need to perform high-voltage chopping. Therefore, in some instances, techniques are employed to implement high-voltage domain (…). Figure 3 A virtual low-voltage environment (above line 314) is provided to allow low-voltage chopping to be implemented in the high-voltage domain portion of the differential transconductance stage 306.

[0047] refer to Figure 6A -C illustrates an example of a chopper circuit system 402 applied to a first unity-gain buffer 504a. Although the following description refers to the first unity-gain buffer 504a, the same circuit system and techniques can be applied to a second unity-gain buffer 504b.

[0048] like Figure 6A As shown, the first unity-gain buffer includes a first input terminal 622a and a second input terminal 622b. As indicated by 602, these input terminals 622a and 622b are chopped using a chopper circuit system 402. The first input terminal 622a is coupled to a current source 508a, and the second input terminal 622b receives an input voltage V_pos (V+). The current source 508a is coupled to a voltage supply terminal 316. As described above, in some instances, the supply voltage provided at the voltage supply terminal 316 is a relatively high voltage, such as 100 V. Additionally, the input voltage V+ can be a relatively high voltage, such as 90 V. Therefore, the chopper circuit system 402 can operate within this high voltage domain. According to some instances, a local supply voltage for the first unity-gain buffer 504a, a local ground voltage, and a chopping signal for operating the chopper circuit system 402 are locally generated at the first unity-gain buffer 504a based on the input voltage V+. Therefore, a floating local supply voltage Vmax, a floating local ground voltage Vmin, and a chopping signal can be generated locally to track the voltage V+ (“pin voltage”) at the second input terminal 522b of the first unity-gain buffer 504a.

[0049] Figure 6B A circuit system is shown that can be used to generate a floating ground voltage Vmin and a floating local supply voltage Vmax. As shown, in this example, the circuit system includes a first transistor 604a coupled to a second input terminal 622b and a terminal 614, and a second transistor 604b and a third transistor 604c coupled between a current source 508a and terminal 614. A capacitor 606 is coupled in parallel with the second transistor 604b and the third transistor 604c. In some examples, the first transistor 604a generates a voltage at terminal 614 that is one gate-source voltage drop (Vgs) lower than the input voltage V+. This voltage can be used as the floating ground voltage Vmin. The floating local supply voltage Vmax is generated by the input voltage V+ through the second transistor 604b and the third transistor 604c in two gate-source increments. Therefore, in this example, the local supply voltage Vmax is equal to the input voltage (V+) + 2Vgs, and Vmin is equal to the input voltage (V+) - 1Vgs. Once the floating local power supply Vmax and the floating local ground voltage Vmin have been generated, they can be used as the power supply for the first unity-gain buffer 504a, as well as the chopper circuit system and signals, such as... Figure 6C As shown.

[0050] Although the floating local power supply Vmax and the floating local ground voltage Vmin are derived from the input voltage V+ and are therefore in the high voltage domain, the difference between them can be small (e.g., 3Vgs). Therefore, refer to Figure 6C A virtual low-voltage environment 608 can be created in the high-voltage domain relative to the floating ground voltage Vmin. Therefore, a chopper circuit system that can be used to chop the input terminals 622a, 622b of the first unity-gain buffer 504a can operate within this virtual low-voltage environment 608. In some instances, this circuit system includes a digital logic circuit system 610 and a switching network 612, both of which can be... Figure 4 This is part of a chopper circuit system 402. A chopper clock signal 616 is generated from a chopper clock source 404, which may be part of or external to the analog front-end 302. The chopper clock signal 616 is in a low-voltage domain (e.g., 0 V–5 V). Therefore, capacitor 620 is used to isolate and decouple the low-voltage domain from the high-voltage domain.

[0051] In some instances, the digital logic circuit system 610 generates two switching signals CHA and CHB based on the chopper clock signal 616. These switching signals CHA and CHB are used to control the switching network 612 to switch (chopper) the input terminals 622a and 622b of the first unity-gain buffer 504a and to perform internal de-chopping on the output, such as... Figure 6C As shown.

[0052] Chopping the two input terminals 622a, 622b of the first unity-gain buffer 504a (and the second unity-gain buffer 504b) can offer several advantages. See again... Figure 6AWith the first input terminal 622a of the first unity-gain buffer 504a connected as shown (connected to the output of the first unity-gain buffer 504a via transistor 502), the voltages (V+ and V-) at each of the two input terminals 622a and 622b can be nearly identical. The voltage V- at the first input terminal 622a tracks the input voltage V+ at the second input terminal 622b. Therefore, when the input terminals 622a and 622b are chopped, chopping does not involve switching a relatively high voltage difference, and thus the switching current flowing into the input terminals 622a and 622b may be relatively low. Conversely, if instead chopping is performed on the input terminals of both unity-gain buffers 504a and 504b (e.g., alternately connecting the input terminal 622b to the two voltages V_pos and V_neg constituting the differential input voltage 318 and performing the same switching at the second unity-gain buffer 504b), this may involve potentially switching a high voltage difference, and therefore involves a high switching current. For example, in some cases, the input voltage V_pos can be 100 V, and the input voltage V_neg can be 95 V. Therefore, chopping by reversing the polarity of the two unity-gain buffers 504a, 504b may cause the input terminals at each unity-gain buffer 504a, 504b to switch at a voltage difference of 5 V. This can result in high switching current. Therefore, as described above, implementing chopping locally and individually at each unity-gain buffer 504a, 504b can achieve the noise reduction benefits of chopping without requiring high switching current and / or causing large input leakage current.

[0053] Now for reference Figure 7 An example of ADC 304 is shown. As described above, in some instances, ADC 304 is a unity-gain Δ-Σ ADC. ADC 304 may include a first amplifier 702 configured as a switched-capacitor integrator. As shown, the input of the first amplifier 702 can be chopped using switch 710. ADC 704 may include one or more additional integrators 704 depending on the order of the ADC, and includes an output stage 706. A pair of input buffers 712a, 712b are coupled to the output of differential transimpedance stage 308 to receive the voltage V from the output of differential transimpedance stage 308, respectively. INP and V INM In some instances, as shown in the figure, it is possible to use... Figure 4 A chopper circuit system 406c is used to chop the inputs of these buffers 712a and 712b. Additionally, a set of switches 718 can be used to chop the connection between the outputs of the buffers 712a and 712b and the sampling capacitors 716a and 716b. For example, switches 710 and 718 can form part of the chopper circuit system 406c.

[0054] Δ-Σ ADC uses the input voltage V INP and V INM The ADC operates by comparing samples to reference voltages REFP and REFM, respectively. In this example, REFP is equal to Vref (e.g., +4 V) as described above, and REFM is grounded (e.g., 0 V). In the illustrated example, the ADC 304 includes a pair of sampling capacitors 716a and 716b, with one sampling capacitor corresponding to each of the two differential inputs. A set of switches 714 is used to alternately connect capacitors 716a and 716b to either the reference voltage REFP or REFM, or to the outputs of buffers 712a and 712b. Therefore, at each capacitor 716a and 716b, the ADC 304 can alternately sample the input voltage (Vref)... INP or V INM The reference voltage (REFP or REFM) is sampled.

[0055] Another configuration can use a separate reference sampling capacitor for sampling the reference voltage and an input sampling capacitor for sampling the input voltage. However, in this arrangement, capacitor mismatch can be a major source of the ADC's original error and may cause the ADC gain to deviate from unity gain. Using the same capacitors to sample both the input and reference voltages, as... Figure 7 The configuration shown eliminates the capacitor mismatch issue, and the ADC 304 has unity gain. Although some mismatch may exist between capacitors 716a and 716b, this mismatch may only affect common-mode rejection and not gain. For unity-gain operation, the common-mode voltage level at inputs 522a, 522b is the same as the reference voltage common-mode level (e.g., 2 V in the example above), or within an acceptable tolerance (e.g., + / - 5% or better, but other examples may have different tolerances). This is achieved by the output from transimpedance stage 308 being fully differential, as described above, where the common-mode level is set via a feedback path from the ADC reference voltage. For example, a common-mode feedback loop can be implemented to feed the ADC reference voltage common-mode to transimpedance amplifier 514 to adjust the output from transimpedance amplifier 514 to match the reference common-mode voltage level.

[0056] Therefore, various aspects and examples provide a voltage measurement circuit that implements a fully differential signal chain to provide improved performance superior to some other voltage measurement devices. As mentioned above, examples of the circuit can accept a differential input voltage range including negative voltages (e.g., approximately -3 V to +6 V), while some single-ended designs can only accept positive input voltages. Furthermore, examples of the circuit can provide improved linearity and reduced gain error, while maintaining a relatively clean noise floor. In some examples, the original error in the signal chain of the analog front-end 302 and ADC 304 is sufficiently small (e.g., < 800 μV), making the need for digital calibration unnecessary. Moreover, instead of using auto-zeroing, noise and offset are reduced by using chopping, as mentioned above, allowing the ADC 304 to perform true continuous sampling without the interference and distortion that could potentially result from auto-zeroing.

[0057] Other examples

[0058] Example 1 is a circuit comprising: a differential transconductance stage configured to convert a differential input voltage into a differential current; a differential transimpedance stage configured to convert the differential current into a differential output voltage; a common-mode voltage regulator configured to regulate the common-mode input voltage of the differential transimpedance stage; and an analog-to-digital converter configured to sample the differential output voltage to generate a digital output signal.

[0059] Example 2 includes the circuit described in Example 1, further including an offset stage configured to adjust the differential current converted by the differential transimpedance stage based on the input range of the analog-to-digital converter, in order to reduce the input reference error of the analog-to-digital converter.

[0060] Example 3 includes a circuit according to one of Examples 1 or 2, wherein the analog-to-digital converter is a unity-gain Δ-Σ analog-to-digital converter.

[0061] Example 4 includes a circuit according to any one of Examples 1 to 3, wherein the differential transimpedance stage includes a differential transimpedance amplifier and a resistor-capacitor filter coupled between the differential output terminal of the differential transimpedance amplifier and the differential input terminal of the analog-to-digital converter.

[0062] Example 5 includes a circuit according to any one of Examples 1 to 4, wherein the differential transconductance stage includes a first unity-gain buffer and a second unity-gain buffer, and a resistor coupled between the first unity-gain buffer and the second unity-gain buffer.

[0063] Example 6 includes the circuit according to Example 5, wherein the differential transconductance stage includes a first transistor coupled between a voltage supply terminal and a first differential input terminal of the differential transimpedance stage, and a second transistor coupled between the voltage supply terminal and a second differential input terminal of the differential transimpedance stage, wherein the first unity-gain buffer has a first input terminal coupled to a first input voltage terminal, a second input terminal coupled to the voltage supply terminal, and an output terminal coupled to a control terminal of the first transistor, wherein the second unity-gain buffer has a first input terminal coupled to a second input voltage terminal, a second input terminal coupled to the voltage supply terminal, and an output terminal coupled to a control terminal of the second transistor, and wherein the resistor is coupled between the second input terminal of the first unity-gain buffer and the second input terminal of the second unity-gain buffer.

[0064] Example 7 includes the circuit according to Example 6, comprising: a first chopper circuit coupled to a chopper clock terminal and configured to switch the first input terminal and the second input terminal of the first unity-gain buffer based on the frequency of a chopper clock signal received via the chopper clock terminal; and a second chopper circuit coupled to the chopper clock terminal and configured to switch the first input terminal and the second input terminal of the second unity-gain buffer based on the frequency of the chopper clock signal.

[0065] Example 8 includes the circuit described in Example 7, wherein each of the first chopper circuit and the second chopper circuit comprises: a transistor circuit system configured to generate a floating supply voltage and a floating reference voltage based on the pin voltage of a respective of the first unity-gain buffer or the second unity-gain buffer; a plurality of switches; a digital logic circuit system configured to generate switching signals based on the chopper clock signal to control the operation of the plurality of switches, the switching signals transitioning between the floating supply voltage and the floating reference voltage to open and close the plurality of switches; and one or more capacitors coupled between the chopper clock terminal and the digital logic circuit system.

[0066] Example 9 includes a circuit according to any one of Examples 1 to 8, wherein the differential transconductance stage is configured to operate in a first voltage domain, and the differential transimpedance stage is configured to operate in a second voltage domain, and the voltage of the first voltage domain is higher than the voltage of the second voltage domain.

[0067] Example 10 includes a circuit according to any one of Examples 1 to 9, wherein the differential transconductance stage is a high-voltage differential transconductance stage and the differential transimpedance stage is a low-voltage differential transimpedance stage because the first voltage and the second voltage of the differential input voltage are higher than the first voltage and the second voltage of the differential output voltage.

[0068] Example 11 is a battery monitoring system that includes the circuitry according to any one of Examples 1 to 10.

[0069] Example 12 is a stackable battery monitoring device that includes the battery monitoring system according to Example 11.

[0070] Example 13 provides a system comprising: a battery pack including a plurality of battery cells; and a plurality of battery monitoring circuits, each battery monitoring circuit being coupled to one or more of the plurality of battery cells, wherein each battery monitoring circuit includes circuitry according to any one of Examples 1 to 10.

[0071] Example 14 provides a circuit including a differential transimpedance amplifier having a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The circuit further includes a differential transconductance stage comprising: a first transistor coupled in series between a voltage supply terminal and the first input terminal of the differential transimpedance amplifier; a second transistor coupled in series between the voltage supply terminal and the second input terminal of the differential transimpedance amplifier; a first unity-gain buffer having a first input terminal coupled to a first input voltage terminal, a second input terminal coupled to the voltage supply terminal, and an output coupled to a control terminal of the first transistor; a second unity-gain buffer having a first input terminal coupled to a second input voltage terminal, a second input terminal coupled to the voltage supply terminal, and an output coupled to a control terminal of the second transistor; and a resistor coupled between the second input terminals of the first unity-gain buffer and the second input terminal of the second unity-gain buffer. The circuit further includes an analog-to-digital converter having a first input terminal and a second input terminal coupled to the first output terminal and the second output terminal of the differential transimpedance amplifier, respectively.

[0072] Example 15 includes the circuit described in Example 14, which includes a common-mode voltage regulator coupled to the first and second input terminals of the differential transimpedance amplifier.

[0073] Example 16 includes the circuit described in one of Examples 14 or 15, further including a voltage offset circuit coupled to the second input terminal of the differential transimpedance amplifier.

[0074] Example 17 includes the circuit according to Example 16, wherein the resistor is a first resistor, and the voltage offset circuit includes: a second resistor; a third transistor coupled in series between the second input terminal of the differential transimpedance amplifier and the first resistor terminal of the second resistor; a fourth transistor coupled in series between the second resistor terminal of the second resistor and a ground terminal; a first amplifier having a first input terminal coupled to a first reference voltage terminal, a second input terminal coupled to the first resistor terminal, and an output terminal coupled to a control terminal of the third resistor; and a second amplifier having a first input terminal coupled to a second reference voltage terminal, a second input terminal coupled to the second resistor terminal, and an output terminal coupled to the control terminal of the fourth transistor.

[0075] Example 18 includes a circuit according to any one of Examples 14 to 17, comprising a resistor-capacitor filter coupled between the first and second output terminals of the differential transimpedance amplifier and the first and second input terminals of the analog-to-digital converter.

[0076] Example 19 includes the circuit described in Example 18, wherein the resistor-capacitor filter comprises: a first resistor coupled between the first output terminal of the differential transimpedance amplifier and the first input terminal of the analog-to-digital converter; a second resistor coupled between the second output terminal of the differential transimpedance amplifier and the second input terminal of the analog-to-digital converter; and a capacitor coupled between the first input terminal and the second input terminal of the analog-to-digital converter.

[0077] Example 20 includes a circuit according to any one of Examples 14 to 19, wherein the analog-to-digital converter is a unity-gain Δ-Σ analog-to-digital converter.

[0078] Example 21 includes a circuit according to any one of Examples 14 to 20, comprising a chopper circuit configured to switch the first input terminal and the second input terminal of the first unity-gain buffer according to a chopper frequency. The chopper circuit includes: a transistor circuit system configured to generate a floating supply voltage and a floating reference voltage based on a pin voltage received at the first input terminal of the first unity-gain buffer; a plurality of switches coupled to the first input terminal and the second input terminal of the first unity-gain buffer; a digital logic circuit system coupled to the plurality of switches and a chopper clock terminal, the digital logic circuit system being configured to control the operation of the plurality of switches to switch the first input terminal and the second input terminal of the first unity-gain buffer based on a chopper clock signal received via the chopper clock terminal, wherein the chopper clock signal has the chopper frequency; and one or more capacitors coupled between the chopper clock terminal and the digital logic circuit system.

[0079] Example 22 includes the circuit according to Example 21, wherein, in order to control the operation of the plurality of switches, the digital logic circuit system is configured to generate one or more switching signals that transition between the floating supply voltage and the floating reference voltage to open and close the plurality of switches based on the chopping frequency.

[0080] Example 23 provides a circuit comprising: a differential transconductance stage configured to generate a differential current based on a first input voltage and a second input voltage received at a first input voltage terminal and a second input voltage terminal, respectively; and a differential transimpedance stage coupled to the differential transconductance stage and configured to convert the differential current into a differential output voltage. The differential transconductance stage includes: a first unity-gain buffer having a first input terminal and a second input terminal switchably coupled to the first input voltage terminal and a voltage supply terminal; a second unity-gain buffer having a first input terminal and a second input terminal switchably coupled to the second input voltage terminal and a voltage supply terminal; and a resistor coupled between the first unity-gain buffer and the second unity-gain buffer. The circuit further includes a chopper circuit system having a clock terminal and configured to switch the first input terminal and the second input terminal of each of the first unity-gain buffer and the second unity-gain buffer according to the frequency of a chopper clock signal received via the clock terminal.

[0081] Example 24 includes the circuit described in Example 23, wherein the chopper circuit system includes a first chopper circuit and a second chopper circuit. The first chopper circuit includes: a first transistor circuit system configured to generate a first floating supply voltage and a first floating reference voltage based on the first input voltage; a first plurality of switches configured to switch between a connection to the first input voltage terminal and a connection to the voltage supply terminal of the first unity-gain buffer; a first digital logic circuit system configured to use the first floating supply voltage and the first floating reference voltage to generate one or more first switching signals to control the operation of the first plurality of switches based on the chopper clock signal; and one or more first capacitors coupled between the clock terminal and the first digital logic circuit system. The second chopper circuit includes: a second transistor circuit system configured to generate a second floating supply voltage and a second floating reference voltage based on the second input voltage; a second plurality of switches configured to switch between a connection to the second input voltage terminal and a connection to the voltage supply terminal of the second unity-gain buffer; a second digital logic circuit system configured to use the second floating supply voltage and the second floating reference voltage to generate one or more second switching signals to control the operation of the second plurality of switches based on the chopper clock signal; and one or more second capacitors coupled between the clock terminal and the second digital logic circuit system.

[0082] Example 25 is a circuit comprising a resistor having a first resistor terminal and a second resistor terminal, a first current source coupled between a high-voltage power supply and the first resistor terminal, a second current source coupled between the high-voltage power supply and the second resistor terminal, and a first chopper amplifier and a second chopper amplifier buffering a differential input voltage across the resistor. The voltage output terminal of the first chopper amplifier is coupled to the first resistor terminal, and the voltage output of the second chopper amplifier is coupled to the second resistor terminal. Each of the first and second chopper amplifiers includes a positive input terminal and a negative input terminal, wherein each amplifier input is chopped at the positive and negative input terminals, and the polarity of the output voltage from the amplifier, offset across the resistor, is reversed with each chop.

[0083] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0084] A device “configured to” perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or a combination thereof.

[0085] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnects or the ends of devices, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0086] The circuits or devices described herein as containing certain components may be practically adaptable to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may practically contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the said passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0087] While specific transistors are described herein, other transistors (or equivalent devices) may actually be used. For example, a p-channel field-effect transistor (PFET) may be used instead of an n-channel field-effect transistor (NFET) with little or no change to the circuitry. Furthermore, other types of transistors (e.g., bipolar junction transistors (BJTs)) may be used. Additionally, the device may be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate. Furthermore, references to transistor features such as gate, source, or drain do not exclude any suitable transistor technology. For example, features such as source, drain, and gate are used to refer to an FET, while emitter, collector, and base are used to refer to a BJT. These features are used interchangeably herein. For example, a reference to the gate of a transistor may refer to the gate of an FET or the base of a BJT, and vice versa. In some instances, a control terminal may refer to the gate of an FET or the base of a BJT. Any other suitable transistor technology may be used. Any such transistor can be used as a switch, where the gate or base or other equivalent feature acts as a switch selection input, which can be driven to connect the source and drain (or, depending on the case, the emitter and collector).

[0088] In this article, "FET" being "on" (or "switched off") means that a conductive channel exists within the FET and drain current can flow through it. "FET" being "off" (or "switched on") means that no conductive channel exists and drain current does not flow through it. However, a switched-off FET may still have current flowing through its body diode.

[0089] The circuits described herein can be reconfigured to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0090] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, general grounding, and / or any other form of grounding connection applicable to or suited to the teachings herein. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of the parameter.

[0091] Within the scope of the claims, modifications to the described examples are possible, and other examples are also possible.

Claims

1. A circuit comprising: A differential transconductance stage, configured to convert differential input voltage into differential current; A differential transimpedance stage configured to convert the differential current into a differential output voltage; A common-mode voltage regulator configured to regulate the common-mode input voltage of the differential transimpedance stage; as well as An analog-to-digital converter configured to sample the differential output voltage to generate a digital output signal.

2. The circuit according to claim 1, comprising: An offset stage is configured to adjust the differential current converted by the differential transimpedance stage based on the input range of the analog-to-digital converter, thereby reducing the input reference error of the analog-to-digital converter.

3. The circuit according to claim 1, wherein the analog-to-digital converter is a unity-gain Δ-Σ analog-to-digital converter.

4. The circuit of claim 1, wherein the differential transimpedance stage comprises: Differential transimpedance amplifier; as well as A resistor-capacitor filter is coupled between the differential output terminal of the differential transimpedance amplifier and the differential input terminal of the analog-to-digital converter.

5. The circuit according to claim 1, wherein the differential transconductance stage comprises: A first transistor is coupled between a voltage supply terminal and a first differential input terminal of the differential transimpedance stage; A second transistor is coupled between the voltage supply terminal and the second differential input terminal of the differential transimpedance stage; A first unity-gain buffer has a first input terminal coupled to a first input voltage terminal, a second input terminal coupled to the voltage supply terminal, and an output terminal coupled to a control terminal of the first transistor. The second unity-gain buffer has a first input terminal coupled to a second input voltage terminal, a second input terminal coupled to the voltage supply terminal, and an output terminal coupled to a control terminal of the second transistor. as well as A resistor coupled between the second input terminal of the first unity-gain buffer and the second input terminal of the second unity-gain buffer.

6. The circuit according to claim 5, comprising: A first chopper circuit is coupled to a chopper clock terminal and configured to switch the first input terminal and the second input terminal of the first unity-gain buffer based on the frequency of the chopper clock signal received via the chopper clock terminal. as well as A second chopper circuit is coupled to the chopper clock terminal and configured to switch the first and second input terminals of the second unity-gain buffer based on the frequency of the chopper clock signal.

7. The circuit of claim 6, wherein each of the first chopper circuit and the second chopper circuit comprises: A transistor circuit system configured to generate a floating supply voltage and a floating reference voltage based on the pin voltage of a corresponding one of the first unity-gain buffer or the second unity-gain buffer; Multiple switches; A digital logic circuit system configured to generate switching signals based on the chopper clock signal to control the operation of the plurality of switches, the switching signals switching between the floating supply voltage and the floating reference voltage to open and close the plurality of switches; as well as One or more capacitors are coupled between the chopper clock terminal and the digital logic circuit system.

8. The circuit of claim 1, wherein the differential transconductance stage is configured to operate in a first voltage domain, and the differential transimpedance stage is configured to operate in a second voltage domain, and the voltage in the first voltage domain is higher than the voltage in the second voltage domain.

9. The circuit of claim 1, wherein the differential transconductance stage is a high-voltage differential transconductance stage and the differential transimpedance stage is a low-voltage differential transimpedance stage, because the first voltage and the second voltage of the differential input voltage are higher than the first voltage and the second voltage of the differential output voltage.

10. A system comprising: A battery pack, which includes multiple battery cells; as well as Multiple battery monitoring circuits, each battery monitoring circuit being coupled to one or more of the multiple battery cells; Each battery monitoring circuit includes the circuit according to claim 1.

11. A circuit comprising: A differential transimpedance amplifier having a first input terminal, a second input terminal, a first output terminal, and a second output terminal; Differential transconductance stage, which includes A first transistor, which is series-coupled between the voltage supply terminal and the first input terminal of the differential transimpedance amplifier, A second transistor is coupled in series between the voltage supply terminal and the second input terminal of the differential transimpedance amplifier. A first unity-gain buffer has a first input terminal coupled to a first input voltage terminal, a second input terminal coupled to the voltage supply terminal, and an output coupled to a control terminal of the first transistor. The second unity-gain buffer has a first input terminal coupled to the second input voltage terminal, a second input terminal coupled to the voltage supply terminal, and an output coupled to the control terminal of the second transistor. A resistor coupled between the second input terminal of the first unity-gain buffer and the second input terminal of the second unity-gain buffer; as well as An analog-to-digital converter having a first input terminal and a second input terminal respectively coupled to the first output terminal and the second output terminal of the differential transimpedance amplifier.

12. The circuit of claim 11, comprising: A common-mode voltage regulator coupled to the first and second input terminals of the differential transimpedance amplifier.

13. The circuit of claim 11, further comprising: A voltage offset circuit is coupled to the second input terminal of the differential transimpedance amplifier.

14. The circuit of claim 13, wherein the resistor is a first resistor, and the voltage offset circuit comprises: Second resistor; A third transistor is coupled in series between the second input terminal of the differential transimpedance amplifier and the first resistor terminal of the second resistor; The fourth transistor is coupled in series between the second resistor terminal and the ground terminal of the second resistor; The first amplifier has a first input terminal coupled to a first reference voltage terminal, a second input terminal coupled to a first resistor terminal, and an output terminal coupled to a control terminal of the third transistor; as well as The second amplifier has a first input terminal coupled to a second reference voltage terminal, a second input terminal coupled to a second resistor terminal, and an output terminal coupled to a control terminal of the fourth transistor.

15. The circuit of claim 11, wherein the analog-to-digital converter is a unity-gain Δ-Σ analog-to-digital converter.

16. The circuit of claim 11, comprising: A resistor-capacitor filter is coupled between the first and second output terminals of the differential transimpedance amplifier and the first and second input terminals of the analog-to-digital converter. The resistor-capacitor filter includes A first resistor is coupled between the first output terminal of the differential transimpedance amplifier and the first input terminal of the analog-to-digital converter. A second resistor is coupled between the second output terminal of the differential transimpedance amplifier and the second input terminal of the analog-to-digital converter. A capacitor coupled between the first input terminal and the second input terminal of the analog-to-digital converter.

17. The circuit of claim 11, comprising: A chopper circuit configured to switch the first and second input terminals of the first unity-gain buffer according to a chopping frequency, the chopper circuit comprising... A transistor circuit system configured to generate a floating supply voltage and a floating reference voltage based on the pin voltage received at the first input terminal of the first unity-gain buffer. Multiple switches coupled to the first input terminal and the second input terminal of the first unity-gain buffer; A digital logic circuit system coupled to the plurality of switches and a chopper clock terminal, the digital logic circuit system being configured to control the operation of the plurality of switches to switch the first input terminal and the second input terminal of the first unity-gain buffer based on a chopper clock signal received via the chopper clock terminal, wherein the chopper clock signal has the chopper frequency; and One or more capacitors are coupled between the chopper clock terminal and the digital logic circuit system.

18. The circuit of claim 17, wherein, in order to control the operation of the plurality of switches, the digital logic circuit system is configured to generate one or more switching signals, the one or more switching signals switching between the floating supply voltage and the floating reference voltage to open and close the plurality of switches based on the chopping frequency.

19. A circuit comprising: A differential transconductance stage configured to generate a differential current based on a first input voltage and a second input voltage received at a first input voltage terminal and a second input voltage terminal, respectively, the differential transconductance stage comprising... A first unity-gain buffer has a first input terminal and a second input terminal that are switchably coupled to the first input voltage terminal and the voltage supply terminal. A second unity-gain buffer has a first input terminal and a second input terminal that are switchably coupled to the second input voltage terminal and the voltage supply terminal, and A resistor coupled between the first unity-gain buffer and the second unity-gain buffer; A differential transimpedance stage coupled to the differential transconductance stage and configured to convert the differential current into a differential output voltage; as well as A chopper circuit system having a clock terminal and configured to switch the first and second input terminals of each of the first unity-gain buffer and the second unity-gain buffer according to the frequency of a chopper clock signal received via the clock terminal.

20. The circuit of claim 19, wherein the chopper circuit system comprises: The first chopper circuit includes A first transistor circuit system is configured to generate a first floating supply voltage and a first floating reference voltage based on the first input voltage. A first plurality of switches are configured to switch between the first input terminal and the second input terminal of the first unity-gain buffer between a connection to the first input voltage terminal and a connection to the voltage supply terminal. A first digital logic circuit system configured to use the first floating supply voltage and the first floating reference voltage to generate one or more first switching signals to control the operation of the first plurality of switches based on the chopper clock signal, and One or more first capacitors are coupled between the clock terminal and the first digital logic circuit system; as well as The second chopper circuit includes The second transistor circuit system is configured to generate a second floating supply voltage and a second floating reference voltage based on the second input voltage. A second plurality of switches are configured to switch between the first and second input terminals of the second unity-gain buffer between a connection to the second input voltage terminal and a connection to the voltage supply terminal. A second digital logic circuit system configured to use the second floating supply voltage and the second floating reference voltage to generate one or more second switching signals to control the operation of the plurality of switches based on the chopper clock signal, and One or more second capacitors are coupled between the clock terminal and the second digital logic circuit system.

Images