Image classification method based on nonlinear pulse p system memristor neural network

Abstract

The application discloses an image classification method based on a nonlinear pulse P system memristor neural network, and belongs to the technical field of image classification.The method comprises the following steps: step 1, constructing an image classification system based on a nonlinear pulse P system memristor neural network, wherein the image classification system is provided with an image acquisition module, a preprocessing module and an image classification module which are sequentially connected, and the image classification module is internally provided with a nonlinear pulse P system memristor neural network; step 2, collecting original image data a by the image acquisition module; step 3, performing standardization processing on the original image data a by the preprocessing module to obtain standard image data b; and step 4, inputting the standard image data b into the nonlinear pulse P system memristor neural network by the image classification module, performing image classification and recognition, and outputting an image classification result Y.The method can guarantee the image classification accuracy of the system and reduce the time cost.

Description

Technical Field

[0001] This invention relates to the field of image classification technology, and in particular to an image classification method based on a nonlinear pulse P-system memristor neural network. Background Technology

[0002] In memristor-based in-memory computing, there are two main training methods: online training and offline training. Online training directly updates parameters and performs inference on the chip, more realistically reflecting the non-ideal characteristics of the device, but its implementation often comes with significant time and energy costs. In contrast, offline training performs weight optimization on an external platform, and then maps the trained parameters to the memristor crossbar array through conductance modulation, thereby significantly reducing on-chip circuit complexity and implementation costs. This has become one of the mainstream methods for accelerating memristor neural network inference.

[0003] However, existing offline training schemes still face two key bottlenecks in practical deployment: On the one hand, many methods rely on idealized memristor models, making it difficult to characterize the non-ideal switching dynamics introduced by factors such as series resistance, variable conduction channels, and leakage branches; on the other hand, there is a mismatch between the high-precision floating-point weights of deep networks and the finite discrete conductance states of memristors. If simple strategies such as uniform quantization are used, severe accuracy degradation is likely to occur in low-bit cases. While K-means-based quantization methods improve quantization accuracy to some extent, their random initialization and iterative convergence processes bring high computational overhead, making it difficult to balance accuracy improvement with time consumption.

[0004] The drawback of existing technologies is that existing memristor image classification models are difficult to reduce time overhead while ensuring image classification accuracy. Summary of the Invention

[0005] The present invention provides an image classification method based on a nonlinear pulse P-system memristor neural network, which can reduce time overhead while ensuring the accuracy of image classification.

[0006] To achieve the above objectives, this invention provides an image classification method based on a nonlinear pulse P-system memristor neural network, which, crucially, includes the following steps:

[0007] Step 1: Construct an image classification system based on a nonlinear pulse P-system memristor neural network. The image classification system is equipped with an image acquisition module, a preprocessing module, and an image classification module connected in sequence. The image classification module has a built-in nonlinear pulse P-system memristor neural network.

[0008] Step 2: The image acquisition module acquires raw image data a and transmits it to the preprocessing module;

[0009] Step 3: The preprocessing module standardizes the original image data a to obtain standard image data b, and then passes it to the image classification module;

[0010] The standardization process includes image cropping, filtering, normalization, and other processing.

[0011] Step 4: The image classification module inputs the standard image data b into the nonlinear pulse P system memristor neural network to perform image classification and recognition, and outputs the image classification result Y.

[0012] Through the above design, this invention performs image classification tasks by designing a nonlinear pulse P-system memristor neural network. This nonlinear pulse P-system memristor neural network can significantly reduce time overhead while ensuring inference accuracy, and has the advantages of high accuracy and high efficiency.

[0013] Preferably, the nonlinear pulse P system memristor neural network is provided with M NSNP type convolutional layers connected end to end. The input of the first NSNP type convolutional layer is used to acquire the standard image data b, and the output of the last NSNP type convolutional layer is connected to an NSNP type fully connected output layer through a flattening layer. The NSNP type fully connected output layer is used to output the image classification result Y.

[0014] The NSNP type convolutional layer is provided with NSNP type convolutional units and max pooling layers connected in sequence.

[0015] Preferably, hafnium dioxide is used in the nonlinear pulse P system memristor neural network. The memristor model serves as a neuron synapse to store the weights of the neuron network; the weight values ​​of each weight matrix in the nonlinear pulse P system memristor neural network are mapped to the conductance values ​​of each memristor in the memristor cross array.

[0016] As a preferred option: the The expression for the memristor model is:

[0017] ;

[0018] The voltage threshold function expression for the memristor model is as follows:

[0019] ;

[0020] ;

[0021] in, This is the positive threshold voltage of the memristor. This is the negative threshold voltage of the memristor. It is a positive threshold voltage function. It is a function of negative threshold voltage. The positive threshold voltage rate coefficient, The negative threshold voltage rate coefficient. It is a non-linear window function. It is a threshold voltage function. It is a function with maximum value. For memristor state variables, For time, Apply an external voltage to the memristor. The positive threshold voltage exponential parameter, The negative threshold voltage exponential parameter;

[0022] The nonlinear window function expression for the memristor model is as follows:

[0023] ;

[0024] ;

[0025] in, For control parameters, , used to indicate the degree of nonlinearity;

[0026] Therefore, the above The state equation of the memristor model is:

[0027] .

[0028] Preferably, the nonlinear pulse P-system memristor neural network is trained through the following steps:

[0029] Step A1: The image acquisition module obtains an image sample set, which is then standardized by the preprocessing module and divided into a training set, a test set, and a validation set.

[0030] Step A2: Construct a nonlinear pulse P-system memristor neural network. Iteratively train the nonlinear pulse P-system memristor neural network using an offline training method with a training set. Then, test and verify the nonlinear pulse P-system memristor neural network using a test set and a validation set to obtain the optimal weight matrix of the nonlinear pulse P-system memristor neural network.

[0031] Step A3: Employ the greedy multi-threshold OTSU quantization algorithm, iterating on the weight histogram. -1 times and select the optimal segmentation point to obtain Cluster That is, image categories, and calculate each cluster. Corresponding weight centroid value ;

[0032] Step A4: Employ a weight mapping strategy to assign weights to each cluster. Corresponding weight centroid value The values ​​are mapped to the conductance values ​​in the memristor cross array, ultimately resulting in the trained nonlinear pulse P system memristor neural network.

[0033] This invention performs image classification tasks by constructing a simple nonlinear pulse P-system memristor neural network. In the weight mapping and inference stages of network construction, a greedy multi-threshold Otsu algorithm (GMT-OTSU) is used to quantize the network weights, and then based on... The memristor model maps weights to memristor conductance values, and finally deploys the mapped weights in the designed nonlinear pulse P-system memristor neural network, which effectively improves the classification accuracy and computational efficiency of the network and reduces the time cost of image classification tasks.

[0034] Preferably, the offline training of the nonlinear pulse P system memristor neural network is performed by an NSNP memristor neural network accelerator, which is equipped with a control unit connected to an instruction cache, a global cache and an in-memory macro computing unit.

[0035] The control unit is used to read instructions from the instruction cache and schedule the global cache and in-memory computation macrounits to perform corresponding operations according to a predetermined data flow; the instruction cache is used to prefetch and store the running instruction flow required by the NSNP memristor neural network accelerator, and the global cache is used to handle the temporary access of intermediate feature maps, weights and activation values.

[0036] The in-memory computing macrounit is integrated into a chip mesh network (NoC). This chip mesh network (NoC) has L computing unit tiles, each of which is composed of… It consists of in-memory computation macro units, local caches, and special function units such as batch normalization and activation functions; each central macro is connected to a hierarchical router shared by four surrounding macros.

[0037] Each in-memory computation macrocell is equipped with a first register, a second register, a first multiplexer, a second multiplexer, a memristor crossbar array, a digital-to-analog converter (DAC), and an analog-to-digital converter (ADC). The first register sends input data to the input group of the memristor crossbar array via the DAC and the first multiplexer. The output group of the memristor crossbar array outputs the calculation result to the second register via the second multiplexer, the ADC, and an adder.

[0038] In the in-memory computing macrocell, weight information is converted into memristor conductance values ​​and pre-stored in a memristor crossover array. The image input information is converted into voltage by a DAC and then applied to the memristor crossover array. The output current of the memristor crossover array is the result of vector-matrix multiplication and then converted into a digital signal by an ADC. Although the weights are stored in the memristor crossover array, the input, output, and intermediate results can be accessed from a hierarchical buffer. In the offline training in-memory computing architecture based on a nonlinear spiking neural P-system, the training process is performed off-chip, directly mapping software weights to the in-memory computing chip. After training is completed on the software side, the weights are pre-programmed into the array, realizing static task partitioning and data flow optimization, providing a new paradigm of high performance and low power consumption for large-scale DNN training.

[0039] Preferably, in step A3, a greedy multi-threshold OTSU quantization algorithm is used to iterate on the weight histogram. -1 times and select the optimal segmentation point to obtain Cluster That is, image categories, and calculate each cluster. Corresponding weight centroid value The specific steps are as follows:

[0040] Step S1: Constructing the histogram: First, flatten the optimal weight matrix to be quantized into a one-dimensional vector. The interval is divided into Ξ equal intervals, where the number of samples and the weights in the i-th interval Ξ(i) are:

[0041] ;

[0042] ;

[0043] in, Let n be the number of samples in the i-th interval Ξ(i), n be the weight index, and N be the total number of weights. ; Indicates if If it is established, then ,otherwise ; For the nth weight, Let be the set of weights for the i-th interval;

[0044] The center value of each interval Ξ(i) for:

[0045] ;

[0046] in, For weight The maximum value, For weight The minimum value, For the number of intervals, For range index, ;

[0047] Therefore, the normalized probability of the i-th interval Ξ(i) is:

[0048] ;

[0049] And have Then the global first moment for:

[0050] ;

[0051] Step S2: Greedy multi-threshold selection:

[0052] In each In this iteration, the interval [0, Ξ) is divided into part , , ..., ,in , , Indicates a segmented index. This indicates the number of segments corresponding to the last iteration;

[0053] For any segment The normalized probability within the segment is:

[0054] ;

[0055] have ;

[0056] in, For section The intra-segment normalized probability;

[0057] For Duan If at t∈[s,e) segment The split results in two subclasses. Then the cumulative probability and cumulative first moment of segment [s,t) are:

[0058] ;

[0059] ;

[0060] in, Let be the cumulative probability of segment [s,t). Let be the cumulative first moment of the segment [s,t);

[0061] And the global first moment within the segment is: That is, take hour;

[0062] Then the inter-class variance of the tangent point t on segment [s,t) for:

[0063] ;

[0064] in, It is an infinitesimal positive number;

[0065] Calculate the inter-class variance of all tangent points on the entire segment. Then, the position corresponding to the maximum inter-class variance is obtained by searching. and the location The corresponding weight value is recorded as the new threshold. ;

[0066] Follow the steps above to execute. The next iteration operation yields a multi-threshold set. ,Right now Each threshold divides the weight interval [0, Ξ) into... There are 3 non-overlapping intervals, each interval corresponding to a cluster. ;

[0067] Step S3: Assign labels and calculate cluster centroids: for each weight Its tags are:

[0068] ;

[0069] in, For the label of the nth weight, For the threshold; Indicates if If it is established, then ,otherwise ;

[0070] Then calculate each cluster The centroid of the weights is the mean of all weights in that class:

[0071] ;

[0072] in, For clusters That is, the weight centroid of image category a. .

[0073] Preferably, in step A4, a weight mapping strategy is used to assign each weight centroid value... Linear mapping to the conductance range supported by memristors :

[0074] ;

[0075] in, This is the maximum conductance of the memristor. This is the minimum conductance of the memristor;

[0076] To address the issue of quantized weights having both positive and negative values, the signs of the weights are distinguished and processed separately before being mapped to the memristor conductance. First, the centroids of the weights for each quantization level are... Break it down into positive and negative parts:

[0077] ;

[0078] ;

[0079] The memristor cross array adopts a differential cross array structure, including a positive array. and negative array Among them, positive array Used to store positive weights negative array Used to store negative weights The mapping scheme is as follows:

[0080] ;

[0081] ;

[0082] ;

[0083] ;

[0084] in, Clusters in a positive array The conductivity value, Clusters in a negative array The conductivity value, For clusters Positive weights, For clusters Negative weights, The maximum positive weight among all clusters. It represents the smallest negative weight among all clusters.

[0085] To accommodate both positive and negative weights, the memristor cross array adopts a differential cross array structure, with the positive weights corresponding to the array. The absolute value of the negative weight corresponds to the array The input voltage V is applied simultaneously to the positive and negative weight arrays. , The output current is taken as its difference. This enables an equivalent simulation of continuous weights.

[0086] As a preferred option: the Memristor model based on The memristor is constructed as follows: The memristor is attached to an FTO glass substrate from bottom to top. Functional layer and Ag top electrode.

[0087] Preferably, the NSNP-type fully connected output layer calculates the probability distribution values ​​of various image categories through fully connected computation, and then outputs the image category corresponding to the maximum probability distribution value as the image classification result Y.

[0088] The image classification method based on nonlinear pulse P-system memristor neural network provided by this invention can be applied to various image classification and recognition scenarios such as handwritten digit recognition, gesture recognition, and test paper score recognition. The system can be trained using image sets of the corresponding categories according to specific image recognition needs, thereby achieving fast and accurate classification of the corresponding image categories.

[0089] The beneficial effects of this invention are:

[0090] (1) FTO / / Ag memristors were used, and a mathematical model of the memristor including series resistance, variable channels, and leakage branches was constructed to accurately capture nonlinear switching dynamics, thus getting closer to the measured IV characteristics.

[0091] (2) To address the mismatch between high-precision weights and the discrete conductance state of memristors, a greedy multi-threshold Otsu algorithm, GMT-OTSU, is proposed. It can adaptively determine the quantization threshold, significantly reducing time overhead while ensuring inference accuracy.

[0092] (3) An offline training in-memory computing architecture based on NSNP was constructed. The obtained quantized weights were deployed to the in-memory computing architecture of the NSNP memristor neural network accelerator through the proposed mapping strategy, so as to achieve efficient end-to-end inference. Attached Figure Description

[0093] Figure 1 This is a flowchart of the method of the present invention;

[0094] Figure 2 This is a schematic diagram of a collaborative design framework based on offline training in the embodiment;

[0095] Figure 3 For the example FTO / / Ag memristor structure diagram;

[0096] Figure 4 For the example FTO / A physical schematic diagram of an Ag memristor;

[0097] Figure 5 The figures show the test results under different scanning voltages and scanning rates in the examples;

[0098] Figure 6 For the example FTO / / Ag device cycle endurance and device consistency IV scan results;

[0099] Figure 7 For the example FTO / Figure 1 shows the IV fitting results for the / Ag device.

[0100] Figure 8 For the same device under different scan numbers in the examples, FTO / Figure 1 shows the IV fitting results for the / Ag device.

[0101] Figure 9 This is a schematic diagram of the offline training in-memory computing architecture based on the nonlinear memristor pulse P system in the embodiment.

[0102] Figure 10 This is a schematic diagram of the weight mapping of the memristor cross-array in the embodiment;

[0103] Figure 11 This is a schematic diagram of the NSNP-MNN structure in the embodiment;

[0104] Figure 12 This is a schematic diagram showing the inference accuracy and average quantization time of the greedy multi-threshold OTSU strategy proposed in the embodiment on NSNP-MNN;

[0105] Figure 13 This is a schematic diagram of the NSNP-VGG11 structure in the embodiment;

[0106] Figure 14 The graphs show the robustness analysis of input noise under different quantization bit widths in the examples. Detailed Implementation

[0107] The present invention will be further described in detail below with reference to the accompanying drawings and specific examples. The following embodiments or drawings are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0108] like Figure 1 As shown, an image classification method based on a nonlinear pulse P-system memristor neural network includes the following steps:

[0109] Step 1: Construct an image classification system based on a nonlinear pulse P-system memristor neural network. This image classification system is configured with an image acquisition module, a preprocessing module, and an image classification module connected in sequence. The image classification module has a built-in nonlinear pulse P-system memristor neural network. In this embodiment, the image classification system based on the nonlinear pulse P-system memristor neural network is used to recognize and classify handwritten digit images 0-9.

[0110] Step 2: The image acquisition module acquires the raw handwritten digit image data 'a' and transmits it to the preprocessing module;

[0111] Step 3: The preprocessing module standardizes the original handwritten digit image data a to obtain standard image data b, and then passes it to the image classification module;

[0112] Step 4: The image classification module inputs the standard image data b into the nonlinear pulse P system memristor neural network to perform image classification and recognition, and outputs the handwritten digit image classification result Y.

[0113] like Figure 2 As shown, the nonlinear pulse P system memristor neural network NSNP-MNN is configured with M NSNP-type convolutional layers connected end to end. The input of the first NSNP-type convolutional layer is used to acquire the standard image data b, and the output of the last NSNP-type convolutional layer is connected to an NSNP-type fully connected output layer via a flattening layer. The NSNP-type fully connected output layer is used to output the image classification result Y.

[0114] The NSNP type convolutional layer is provided with NSNP type convolutional units and max pooling layers connected in sequence.

[0115] The NSNP-type fully connected output layer calculates the probability distribution values ​​of ten handwritten digits from 0 to 9 through fully connected computation, and then outputs the handwritten digit corresponding to the maximum probability distribution value as the image classification result Y.

[0116] Hafnium dioxide is used in the nonlinear pulse P system memristor neural network. The memristor model realizes the non-volatile synaptic function in the neural network and is used to store the weights of the neuron network; the weight values ​​of each weight matrix in the nonlinear pulse P system memristor neural network are mapped to the conductance values ​​of each memristor in the memristor cross array.

[0117] The Memristor model based on The memristor is constructed as follows: The memristor is attached to an FTO glass substrate from bottom to top. Functional layer and Ag top electrode.

[0118] This invention achieves precise control of the functional layer The deposition parameters were: chamber vacuum, argon flow rate, sputtering power, and deposition time, to prepare a FTO-based material. A stable non-volatile memristor with an / Ag structure, structured as follows: Figure 3 As shown, the specific preparation process is as follows:

[0119] First, the FTO glass substrate was sequentially treated with Dicon 90, acetone, ethanol, and deionized water, each for 10 minutes, repeated three times. Then, it was ultrasonically cleaned and dried with nitrogen. Finally, in a magnetron sputtering system, the cavity was first evacuated to a background vacuum of 5.0 × 10⁻⁶. Pa, then by controlling the molecular pump and argon flow rate, the chamber pressure was adjusted to a working vacuum of 1.0 Pa, and the sample was prepared by radio frequency sputtering at an Ar flow rate of 35 Sccm and a power of 60 W for 40 minutes. After the functional layer is formed, the top electrode is fabricated. In the magnetron sputtering system, the cavity is first evacuated to a background vacuum of 5.0 × 10⁻⁶. Pa, then by controlling the molecular pump and argon flow rate, the chamber pressure is adjusted to a working vacuum of 0.8 Pa, and the Ag top electrode is deposited by DC sputtering with Ar flow rate of 35 Sccm and power of 20 W for 90 seconds. The Ag target material was 2 inches in diameter, 3 mm thick, and >99.99% pure. The gas was 99.99% high-purity argon, resulting in a thin-film device with uniform thickness and chemical stability. The microstructure of the obtained device is shown below. Figure 4 As shown.

[0120] In order to evaluate FTO / The electrical characteristics of the / Ag device were determined by IV scanning on a comprehensive testing platform consisting of a Lakeshore TTPX probe station and a CHI660D electrochemical workstation. Before testing, the device was placed on the probe station platform, and the two probes were precisely aligned using a microscope to contact the bottom electrode FTO and the top electrode Ag, respectively. During the test, the bottom electrode FTO was always grounded, and a DC scanning voltage was applied to the top electrode.

[0121] Figure 5 FTO / is given Test results of the / Ag device at different scan voltages and scan rates. Figure 5 In (a), the IV characteristic curves of the same device at different scan voltages, from 1.4V to 2.2V, are shown. The results show that the device exhibits a clear resistance switching characteristic under all voltage conditions. Figure 5(b) shows the IV characteristic curves of the device at three different scan rates of 0.3V / s, 0.5V / s and 0.8V / s. It can be seen that the device exhibits stable and repeatable memristor switching characteristics at different scan rates.

[0122] Figure 6 The prepared FTO / The electrical performance of / Ag in terms of cycle durability (C2C) and device consistency (D2D) is shown in the figure. The I-V curves all exhibit stable resistive switching characteristics, indicating that the fabricated device can maintain reliable HRS and LRS switching behavior in multiple cycles and between different devices. Figure 6 (a) shows the I-V scan curves of 500 consecutive scans at the same location, demonstrating the excellent C2C stability of the device during repeated programming and erasing. Figure 6 (b) shows the I-V characteristic curves of different devices, which show similar memristor characteristics, verifying that the fabricated devices have good D2D stability, which helps to achieve uniform storage performance in large-scale arrays.

[0123] For FTO / The IV characteristic curve of the / Ag device was modeled by considering the equivalent circuit structure of series resistance, variable channel, and leakage branch under the applied voltage. and port current Under the action of internal voltage satisfy:

[0124] ;

[0125] in, This indicates the external voltage connected to the memristor. For series resistance, This refers to the memristor port current.

[0126] Channel resistance of memristor model With state variables , Related, the expression is:

[0127] ;

[0128] in, For memristor state variables, The minimum resistance of the memristor. This is the maximum resistance of the memristor. State variables The channel resistance below;

[0129] Leakage branches formed by the combined effects of interface defects, edge leakage paths, and tunneling effects, through... The linear leakage current and nonlinear tunneling leakage current of the memristor model are described as follows:

[0130] ;

[0131] in, The linear leakage coefficient is... The nonlinear leakage coefficient; It is a nonlinear leakage current index used to control the response rate of nonlinear leakage to voltage and to control the curvature of the leakage current curve. It is a symbolic function;

[0132] The equation for the memristor port current is as follows:

[0133] ;

[0134] In order to obtain experimental data Extract state variables ,definition:

[0135] ;

[0136] ;

[0137] ;

[0138] ;

[0139] Based on the definition of channel resistance, the state variable can be rewritten as:

[0140] ;

[0141] Due to state variables It is difficult to find an explicit analytical solution, so its derivative is approximated by the central difference quotient formula, which is expressed as:

[0142] ;

[0143] in, This represents the sampling time interval.

[0144] The dynamic characteristics of a memristor are jointly determined by the function g describing the model threshold phenomenon and the nonlinear window function f, and can be described as follows:

[0145] ;

[0146] The voltage threshold function expression for the memristor model is as follows:

[0147] ;

[0148] ;

[0149] in, This is the positive threshold voltage of the memristor. This is the negative threshold voltage of the memristor. It is a positive threshold voltage function. It is a function of negative threshold voltage. The positive threshold voltage rate coefficient, The negative threshold voltage rate coefficient. It is a non-linear window function. It is a threshold voltage function. It is a function with maximum value. For memristor state variables, For time, Apply an external voltage to the memristor. The positive threshold voltage exponential parameter, The negative threshold voltage exponential parameter;

[0150] and The positive and negative thresholds of the memristor are described. Changes in the state variable only occur when the threshold voltage is exceeded. Different memristor devices exhibit different mobilities at positive or negative voltages, therefore, two different adjustable parameters are used to determine the mobility. and To describe this phenomenon, the rate coefficient and It needs to be obtained through fitting experimental data.

[0151] The nonlinear window function expression for the memristor model is as follows:

[0152] ;

[0153] ;

[0154] in, For control parameters, , used to indicate the degree of nonlinearity;

[0155] Therefore, the above The state equation of the memristor model is:

[0156] .

[0157] based on State equations for memristor model, constructing residual functions:

[0158] ;

[0159] in, For the residual function, The derivative of the k-th state variable;

[0160] To improve numerical stability, weights are introduced. ∈[0.2,1], thus minimizing the weighted 2-norm:

[0161] ;

[0162] This problem is solved numerically using the Trust Region Reflection (TRF) algorithm to obtain the optimal parameters. .

[0163] After obtaining the optimal parameters Then, the current is reconstructed using the equivalent equation. It satisfies the following nonlinear equation:

[0164] ;

[0165] The theoretical current can be obtained by solving the equation using the fzero function. Then compared with experimental data The effectiveness of the model was verified by comparing the results and using the root mean square error (RMSE).

[0166] ;

[0167] Where N is the total number of sampling points, Let be the current at the k-th sampling point.

[0168] Based on the previous memristor experimental data, the relevant parameters of the memristor can be obtained as follows: ≈39.4Ω, ≈590Ω ≈-0.85V, ≈0.6V. Furthermore, the effects of series resistance and leakage current branches were considered during the modeling process, making... = 7.5Ω, =2× , =4× , as well as =1.8. Based on the VTEAM model, fixed parameters are selected. =1, =1, p=1. The optimal parameters are finally calculated. , The fitting results are as follows: Figure 7As shown in (a), the blue scatter plots represent the experimental data, and the red curve represents the fitting result calculated based on the optimized parameters. The calculated root mean square error (RMSE) is 0.000103, indicating that the established model can accurately characterize the IV characteristics of the memristor, verifying the effectiveness of the constructed model. Figure 7 (b) Only the variable channel model, i.e., the traditional VTEAM model, was considered, without taking into account the effects of series resistance and leakage current branches, and no parameter optimization was performed; all other parameters remained unchanged. As can be seen from the figure, the fitting effect is very poor. Therefore, the parameter extraction modeling method that introduces series resistance and leakage current branches significantly improves the model's fitting accuracy and robustness, and can more realistically reflect the physical characteristics of the device.

[0169] Figure 8 FTO / for the same device at different scan numbers is given. The root mean square errors of the IV fitting results for the / Ag device are: 9.27 × 6.96 × The values ​​are 0.000107 and 0.00012. The results show that the proposed model accurately describes the IV characteristics of the device under different scan numbers, demonstrating high fitting accuracy and good robustness.

[0170] The embodiment proposed The memristor model maintains excellent fitting accuracy and can effectively simulate the dynamic behavior of actual memristors. It can serve as a theoretical basis at the device level for circuit simulation and performance prediction of cross-arrays. This provides a reliable modeling tool and theoretical support for subsequent research on weight mapping based on memristor arrays and neuromorphic computing systems.

[0171] The nonlinear pulse P-system memristor neural network is trained through the following steps:

[0172] Step A1: The image acquisition module obtains an image sample set, which is then standardized by the preprocessing module and divided into a training set, a test set, and a validation set.

[0173] Step A2: Construct a nonlinear pulse P-system memristor neural network. Iteratively train the nonlinear pulse P-system memristor neural network using an offline training method with a training set. Then, test and verify the nonlinear pulse P-system memristor neural network using a test set and a validation set to obtain the optimal weight matrix of the nonlinear pulse P-system memristor neural network.

[0174] Step A3: Employ the greedy multi-threshold OTSU quantization algorithm, iterating on the weight histogram. -1 times and select the optimal segmentation point to obtain Cluster That is, image categories, and calculate each cluster. Corresponding weight centroid value ;

[0175] Step A4: Employ a weight mapping strategy to assign weights to each cluster. Corresponding weight centroid value The values ​​are mapped to the conductance values ​​in the memristor cross array, ultimately resulting in the trained nonlinear pulse P system memristor neural network.

[0176] This invention proposes an offline training in-memory computing architecture based on a nonlinear spiking neural network (P-system), leveraging the parallel computing capabilities of the P-system to achieve high-throughput vector-matrix operations. Subsequently, to address the mismatch between high-precision weights and the finite discrete conductance states of memristors, a greedy multi-threshold OTSU algorithm is proposed. This algorithm adaptively determines the quantization threshold, significantly reducing hardware storage and programming overhead while maintaining inference accuracy. Finally, based on the proposed memristor model, an efficient weight mapping strategy is presented, accurately mapping the quantized weights to conductance values ​​in the memristor cross array, thereby achieving efficient end-to-end deployment and inference.

[0177] Specifically, such as Figure 9 As shown, the offline training of the nonlinear pulse P system memristor neural network is completed through an NSNP memristor neural network accelerator. The NSNP memristor neural network accelerator is equipped with a control unit, which is connected to an instruction cache, a global cache, and an in-memory macro computing unit.

[0178] The control unit is used to read instructions from the instruction cache and schedule the global cache and in-memory computation macrounits to perform corresponding operations according to a predetermined data flow. The instruction cache is used to prefetch and store the instruction flow required for the operation of the NSNP memristor neural network accelerator, and the global cache is used to handle the temporary access of intermediate feature maps, weights, and activation values.

[0179] The in-memory computing macrounit is integrated into a chip mesh network (NoC). This chip mesh network (NoC) has L computing unit tiles, each of which is composed of… It consists of in-memory computation macro units, local caches, and special function units such as batch normalization and activation functions; each central macro is connected to a hierarchical router shared by four surrounding macros.

[0180] Each in-memory computation macrocell is equipped with a first register, a second register, a first multiplexer, a second multiplexer, a memristor crossbar array, a digital-to-analog converter (DAC), and an analog-to-digital converter (ADC). The first register sends input data to the input group of the memristor crossbar array via the DAC and the first multiplexer. The output group of the memristor crossbar array outputs the calculation result to the second register via the second multiplexer, the ADC, and an adder.

[0181] In the in-memory computing macrocell, weight information is converted into memristor conductance values ​​and pre-stored in a memristor crossover array. The image input information is converted into voltage by a DAC and then applied to the memristor crossover array. The output current of the memristor crossover array is the result of vector-matrix multiplication and then converted into a digital signal by an ADC. Although the weights are stored in the memristor crossover array, the input, output, and intermediate results can be accessed from a hierarchical buffer. In the offline training in-memory computing architecture based on a nonlinear spiking neural P-system, the training process is performed off-chip, directly mapping software weights to the in-memory computing chip. After training is completed on the software side, the weights are pre-programmed into the array, realizing static task partitioning and data flow optimization, providing a new paradigm of high performance and low power consumption for large-scale DNN training.

[0182] In step A3, a greedy multi-threshold OTSU quantization algorithm is used to iterate on the weight histogram. -1 times and select the optimal segmentation point to obtain Cluster That is, image categories, and calculate each cluster. Corresponding weight centroid value The specific steps are as follows:

[0183] Step S1: Constructing the histogram: First, flatten the optimal weight matrix to be quantized into a one-dimensional vector. The interval is divided into Ξ equal intervals, where the number of samples and the weights in the i-th interval Ξ(i) are:

[0184] ;

[0185] ;

[0186] in, Let n be the number of samples in the i-th interval Ξ(i), n be the weight index, and N be the total number of weights. ; Indicates if If it is established, then ,otherwise ; For the nth weight, Let be the set of weights for the i-th interval;

[0187] The center value of each interval Ξ(i) for:

[0188] ;

[0189] in, For weight The maximum value, For weight The minimum value, For the number of intervals, For range index, ;

[0190] Therefore, the normalized probability of the i-th interval Ξ(i) is:

[0191] ;

[0192] And have Then the global first moment for:

[0193] ;

[0194] Step S2: Greedy multi-threshold selection:

[0195] In each In this iteration, the interval [0, Ξ) is divided into part , , ..., ,in , , Indicates a segmented index. This indicates the number of segments corresponding to the last iteration;

[0196] For any segment The normalized probability within the segment is:

[0197] ;

[0198] have ;

[0199] in, For section The intra-segment normalized probability;

[0200] For Duan If at t∈[s,e) segment The split results in two subclasses. Then the cumulative probability and cumulative first moment of segment [s,t) are:

[0201] ;

[0202] ;

[0203] in, Let be the cumulative probability of segment [s,t). Let be the cumulative first moment of the segment [s,t);

[0204] And the global first moment within the segment is: That is, take hour;

[0205] Then the inter-class variance of the tangent point t on segment [s,t) for:

[0206] ;

[0207] in, It is an infinitesimal positive number;

[0208] Calculate the inter-class variance of all tangent points on the entire segment. Then, the position corresponding to the maximum inter-class variance is obtained by searching. and the location The corresponding weight value is recorded as the new threshold. ;

[0209] Follow the steps above to execute. The next iteration operation yields a multi-threshold set. ,Right now Each threshold divides the weight interval [0, Ξ) into... There are 3 non-overlapping intervals, each interval corresponding to a cluster. ;

[0210] For ease of understanding, Table 1 provides a... =4 A simple example: At the start of the first iteration, the segment before partitioning is S = {[0, Ξ)}, then there must exist a... ∈[0, Ξ) makes the local inter-class variance within the segment Maximum, that is:

[0211] ;

[0212] Table 1 Examples of Greedy Multi-Threshold Selection

[0213]

[0214] As shown in Table 1, the threshold value is taken. , for The weight value corresponding to the position, and the segment [0,Ξ) from Divide into two: and The segmented parts are obtained. In the second iteration, the segment before splitting is updated as follows: Iterate through all segments. Find the segment whose local inter-class variance is equal to the inter-class variance calculated using the formula for inter-class variance. The largest segment and its dividing point position Obtain a new threshold. Assuming the split point ∈ Then this segment will be in The location is divided into two: and The resulting segment is: In the third iteration, the segments before splitting are updated again: Similarly, iterate through all current segments. Find the segment that results in a local inter-class variance equal to the inter-class variance calculated using the inter-class variance formula. The largest segment and its dividing point position Obtain a new threshold. Assuming the split point ∈[ If ,Ξ), then this segment will be in The location is divided into two: as well as The resulting segment is: The iteration is now complete, resulting in a multi-threshold set { , , }

[0215] Step S3: Assign labels and calculate cluster centroids: for each weight Its tags are:

[0216] ;

[0217] in, For the label of the nth weight, For the threshold; Indicates if If it is established, then ,otherwise ;

[0218] Then calculate each cluster The centroid of the weights is the mean of all weights in that class:

[0219] ;

[0220] in, For clusters That is, the weight centroid of image category a. .

[0221] Before weight mapping, offline training is first performed on an external general-purpose computing platform (CPU or GPU) to obtain 32-bit floating-point weights. Then, to accommodate the limited discrete conductance states of the memristor, a greedy multi-threshold OTSU quantization algorithm is used to perform low-bit quantization on these high-precision weights, generating... The system quantizes the values ​​and calculates the corresponding centroids, then converts these centroids into a programmable conductance range for the memristor via a linear mapping. Based on the previously proposed memristor model, a weight mapping scheme for a memristor cross array is constructed. By applying different voltages, the device conductance is precisely adjusted, thereby achieving accurate mapping and accumulation of neural network weights. This provides theoretical support for the design of memristor-based neuromorphic computing hardware.

[0222] In step A4, a weight mapping strategy is used to assign each weight centroid value... Linear mapping to the conductance range supported by memristors :

[0223] ;

[0224] in, This is the maximum conductance of the memristor. This is the minimum conductance of the memristor.

[0225] To accommodate both positive and negative weights, the memristor cross array adopts a differential cross array structure, with the positive weights corresponding to the array. The absolute value of the negative weight corresponds to the array The input voltage V is applied simultaneously to the positive and negative weight arrays. , The output current is taken as its difference. This enables an equivalent simulation of continuous weights.

[0226] The specific implementation process is as follows: Figure 10 As shown, the input vector x = [ , ,…, The signal is converted into a voltage signal via a DAC, and the weights are then... Stored in a cross array, since the weights can be both positive and negative, we consider using the blue positive array. and the orange negative array , , where positive array When storing weights, positive weights are used where the weight value is positive, and 0 is used where the weight value is negative. negative array When storing weights, positive weights are represented by 0, and negative weights are represented by their absolute values. For example, if the weight vector is When the sum is [-0.4; 0.3; -0.2; 0.1], the weight information stored in the memristors of the positive array corresponds to... = [0;0.3;0;0.1], the weight information stored in the memristors in the negative array corresponds to =[0.4;0;0.2;0]. Based on Kirchhoff's laws and Ohm's law, by performing multiplication and accumulation, the output currents of the positive and negative arrays can be obtained respectively. as well as The current is then converted to voltage by a transimpedance amplifier (TIA). A standard subtractor is then used to subtract the output voltages of the positive and negative arrays to obtain the final output voltage. Finally, an ADC converts the output voltage value into a digital value, yielding the final output. Where m represents the number of input rows of the memristor cross-connect array, n represents the number of positive and negative weight columns of the memristor cross-connect array, i represents the row index, and j represents the column index.

[0227] The above solution effectively addresses the limitation that memristors can only represent non-negative conductance, reducing the special requirements for memristor materials and processes, and improving compatibility and manufacturability. Although this differential cross array structure requires twice the number of cross arrays, resulting in double the resource overhead, the difference between the positive and negative currents creates a larger output dynamic range. Furthermore, the positive and negative weights can be independently programmed and calibrated, allowing for differentiated compensation algorithms to be applied to the two different error characteristics, thereby improving overall mapping accuracy.

[0228] Therefore, when considering mapping the weights obtained by the greedy multi-threshold OTSU algorithm to the conductance of a memristor, for cases where the quantized weights have both positive and negative values, the signs of the weights are distinguished and processed separately before mapping to the memristor conductance. First, the centroid of the weights at each quantization level is determined. Break it down into positive and negative parts:

[0229] ;

[0230] ;

[0231] Positive array Used to store positive weights negative array Used to store negative weights The mapping scheme is as follows:

[0232] ;

[0233] ;

[0234] ;

[0235] ;

[0236] in, Clusters in a positive array The conductivity value, Clusters in a negative array The conductivity value, For clusters Positive weights, For clusters Negative weights, The maximum positive weight among all clusters. It represents the smallest negative weight among all clusters.

[0237] For mapping of positive arrays, when the weights When > 0, programming operations are applied only to the corresponding cells of the positive array, and the target conductance is determined by... The mapping formula is given for the weights. The part with = 0 applies no voltage to either the positive or negative array, keeping both array cells in the lowest conductance state to save programming energy and avoid unnecessary writes. At this time, the negative array maintains its original low conductance to avoid introducing a negative weight response.

[0238] For the mapping of negative arrays, when weight When the value is > 0, programming operations are applied only to the corresponding cells of the negative array, and the target conductance is determined by... The mapping formula is given, for weights The part with = 0 applies pulses to neither the positive nor the negative array, keeping both array cells in the lowest conductance state to save programming energy and avoid unnecessary writing. At this time, the positive array remains unchanged with its original low conductance to avoid introducing a positive weight response.

[0239] After obtaining the target conductances of the positive and negative arrays, the required programming voltage is solved offline based on the memristor model proposed above, and applied in one go during the online programming stage, eliminating the need for a write-read-verify cycle, thereby significantly reducing latency and extending device life.

[0240] Through the above-mentioned architecture design, quantization method and weight mapping strategy, efficient weight deployment for memristor cross arrays is achieved, providing a new energy-efficient in-memory computing paradigm for subsequent large-scale neural network inference.

[0241] Next, experiments were conducted using Ubuntu 20.04, an NVIDIA GeForce GTX 1080 Ti graphics card, and the PyTorch platform. The MNIST dataset was used to evaluate the effectiveness of the proposed nonlinear pulsating P-system memristor neural network. This dataset consists of 70,000 images of handwritten digits from 250 different people, with 60,000 images used for training and 10,000 images used for testing. Each image consists of 28*28 images of handwritten digits from 0 to 9.

[0242] The experiments used quantization bit depths of 2-bit, 3-bit, and 4-bit to evaluate the performance changes of the neural network in inference tasks at different levels of precision. The bit depth was not increased further because performance comparable to full-precision training is achieved with approximately 4 bits, and higher bit depths have little impact on network performance. Increasing the bit depth further would significantly increase the complexity of memristor pulse modulation and the required precision of conductance series, potentially introducing nonlinear errors and device mismatches.

[0243] (I) Image classification experiment on NSNP memristor neural network:

[0244] This embodiment constructs a memristor neural network based on the nonlinear pulse P system NSNP, and its network structure is as follows: Figure 11 As shown, the constructed NSNP memristor neural network (NSNP-MNN) consists of three NSNP-type convolutional layers and one NSNP-type fully connected layer. In the first NSNP-type convolutional layer, a 1×3×3×32 convolutional kernel is used for feature extraction, followed by downsampling through a 2×2 kernel max-pooling layer with a stride of 2. In the second NSNP-type convolutional layer, a 32×3×3×64 convolutional kernel is used for feature extraction, followed by downsampling through a 2×2 kernel max-pooling layer with a stride of 2. The third NSNP-type convolutional layer uses a 64×3×3×64 convolutional kernel for feature extraction, followed by flattening, and finally outputs 10 neurons through an NSNP-type fully connected layer.

[0245] exist Figure 11 In this example, the input image is the MNIST dataset, NSNPConv represents an NSNP type convolutional layer, Pooling represents a pooling layer, and NSNPFC represents an NSNP type fully connected layer.

[0246] NSNP-MNN was trained for 100 rounds on the MNIST dataset using a batch size of 32, the Adadelta optimizer, and an initial learning rate of 0.3. A StepLR piecewise constant decay strategy was employed, with a step size of 30 and a decay coefficient of 0.6 for updating the learning rate. The cross-entropy loss function was used as the target loss function during training. Its inference accuracy and average execution time are as follows: Figure 12 As shown.

[0247] like Figure 12 As shown, the horizontal axis represents the number of bits used for weight quantization: 2-bit, 3-bit, and 4-bit. The left vertical axis uses a bar chart to represent the inference accuracy of the full-precision model and the proposed greedy multi-threshold OTSU strategy at different quantization bit widths. The right vertical axis uses a line graph to show the average quantization time of the strategy. In the full-precision test, the model's baseline classification accuracy was 99.53%. The proposed strategy achieved inference accuracies of 98.84%, 99.43%, and 99.52% with 2-bit, 3-bit, and 4-bit weights, respectively, with corresponding average quantization times of 5.48ms, 8.14ms, and 15.49ms. It can be seen that the inference accuracy gradually increases with the increase in the number of quantization bits, and the 4-bit quantization time is almost comparable to that of the full-precision model. Although the quantization time increases slightly with the increase in the number of bits, it remains in the millisecond range. Therefore, the proposed greedy multi-threshold OTSU strategy can achieve high-precision inference on NSNP-MNN with extremely low time overhead.

[0248] To more fully verify the effectiveness of the proposed greedy multi-threshold OTSU approximation scheme, it was compared with various quantization methods, and the comparison results are shown in Table 2. Taking the NSNP-MNN network structure 32C3-64C3-64C3-4096-10 as an example, 32C3 represents 32 3×3 convolutional kernels, 4096 represents the number of neurons after flattening, and 10 represents the number of output neurons. The representation of other network structures in the comparison is consistent with this.

[0249] Table 2 Comparison of Greedy Multi-Threshold OTSU Approximation with Other Quantization Schemes

[0250]

[0251] In Table 2, QAT represents quantization-aware training, LKQ represents uniform-Kmeans hybrid quantization, and PTQ represents post-training quantization.

[0252] As shown in Table 2, the greedy multi-threshold OTSU scheme proposed in this invention significantly outperforms existing quantization methods on NSNP-MNN. Compared to the QAT, LKQ, and PTQ methods in the literature, this invention achieves 99.43% inference accuracy with 3-bit quantization, surpassing the 4-bit performance of most methods. Compared to quantization methods such as QAT, PTQ, and LKQ, this scheme surpasses their quantization accuracy with lower bit widths, such as 3-bit, while maintaining quantization time in the millisecond range. Experimental results demonstrate that this method can achieve near-full-precision performance with limited hardware resources, while alleviating the requirements for memristor multi-conductance state stability, laying the foundation for its application in resource-constrained edge AI scenarios.

[0253] (II) Image classification experiments on NSNP-VGG11:

[0254] The experiments in this section are mainly conducted on the VGG11 network based on NSNP, and its network structure is as follows: Figure 13As shown, the constructed NSNP-VGG11 consists of 8 NSNP-type convolutional layers and 3 NSNP-type fully connected layers. In the first NSNP-type convolutional layer, the input data is first normalized using a batch normalization (BN) layer, then feature extraction is performed using 64 3×3 NSNP-type convolutional kernels, followed by downsampling using a 2×2 kernel and a stride of 2 max pooling layer. In the second NSNP-type convolutional layer, the output data from the previous layer is first normalized using a BN layer, then feature extraction is performed using 128 3×3 NSNP-type convolutional kernels, followed by downsampling using a 2×2 kernel and a stride of 2 max pooling layer. In the third NSNP-type convolutional layer, the output data from the previous layer is first normalized using a BN layer, then feature extraction is performed using 256 3×3 NSNP-type convolutional kernels. In the fourth NSNP-type convolutional layer, the output data from the previous layer is first normalized using a Batch Normalization (BN) layer, then feature extraction is performed using 256 3×3 NSNP-type convolutional kernels, followed by downsampling using a 2×2 kernel and a stride of 2 max pooling layer. In the fifth NSNP-type convolutional layer, the output data from the previous layer is first normalized using a BN layer, then feature extraction is performed using 512 3×3 NSNP-type convolutional kernels. In the sixth NSNP-type convolutional layer, the output data from the previous layer is first normalized using a BN layer, then feature extraction is performed using 512 3×3 NSNP-type convolutional kernels, followed by downsampling using a 2×2 kernel and a stride of 2 max pooling layer. In the seventh NSNP-type convolutional layer, the output data from the previous layer is first normalized using a BN layer, then feature extraction is performed using 512 3×3 NSNP-type convolutional kernels. In the eighth NSNP-type convolutional layer, the output data from the previous layer is first normalized using a batch normalization (BN) layer. Then, 512 3×3 NSNP-type convolutional kernels are used for feature extraction, followed by downsampling using a 2×2 kernel max pooling layer with a stride of 2. A flattening operation is then performed. In the first NSNP-type fully connected layer, the obtained data is fed into 512 NSNP-type neurons. In the second NSNP-type fully connected layer, the obtained data is fed into 512 NSNP-type neurons. Finally, in the third NSNP-type fully connected layer, 10 NSNP-type neurons are used for classification.

[0255] exist Figure 13 In this context, NSNPConv represents an NSNP type convolutional layer, Pooling represents a pooling layer, and NSNPFC represents an NSNP type fully connected layer.

[0256] The NSNP-VGG11 network was trained on the MNIST dataset for 280 rounds using a batch size of 1000, the SGD optimizer, an initial learning rate of 0.01, a momentum of 0.9, and a weight decay of 5e-4. The learning rate was dynamically decayed to 0 using cosine annealing. Cross-entropy loss was used as the target loss function during training. In full-precision testing, the network achieved a baseline classification accuracy of 99.66%.

[0257] Since the DPC algorithm and the classic multi-threshold OTSU algorithm are computationally time-consuming and resource-intensive when the network structure is complex and the number of parameters is large, this invention compares the proposed greedy multi-threshold OTSU algorithm with uniform quantization and K-Means quantization under the NSNP-VGG11 architecture. Quantization is performed at 2-bit, 3-bit and 4-bit precision, and the classification accuracy and average quantization time are statistically analyzed. The comparison results are shown in Table 3.

[0258] Table 3 Weight Quantization Strategy of Memristor Neural Network Based on Nonlinear Impulse P System

[0259]

[0260] As shown in Table 3, the proposed greedy multi-threshold OTSU approximation algorithm significantly outperforms uniform quantization in classification accuracy at 2-bit, 3-bit, and 4-bit precision levels. Compared to K-Means quantization, it also shows a slight improvement in accuracy and performs better in terms of quantization time, although it is still significantly higher than uniform quantization. Overall, this algorithm significantly reduces computational overhead while maintaining high accuracy, demonstrating a good trade-off between accuracy and efficiency.

[0261] (III) Robustness analysis on NSNP-MLP

[0262] In this section, the robustness of the proposed algorithm is verified based on the constructed 4-layer multilayer perceptron network. The network structure adopts a 4-layer fully connected structure: 784×512×256×128×10. NSNP-MLP was trained on the MNIST dataset for 100 rounds with a batch size of 32, an Adadelta optimizer, and an initial learning rate of 0.3. The learning rate was updated using a StepLR piecewise constant decay strategy with a step size of 30 and a decay coefficient of 0.6. During training, the cross-entropy loss function was used as the objective function. Similar to the previous sections, the inference accuracy and quantization time of the algorithm at 2-bit, 3-bit, and 4-bit precision were analyzed. The results are detailed in Table 4.

[0263] Table 4 Performance of several quantization strategies on NSNP-MLP

[0264]

[0265] As shown in Table 4, at 2-bit, 3-bit, and 4-bit precision, the proposed algorithm consistently outperforms uniform quantization and K-Means quantization in classification accuracy, and consistently outperforms K-Means in inference time. Furthermore, compared to uniform quantization, its quantization time difference is only around 1ms, and at 2-bit precision, it is even lower than uniform quantization. Overall, this method achieves higher accuracy while further reducing quantization time.

[0266] To further verify the robustness of the algorithm, a standard dataset was used during the training phase, and Gaussian noise was added during the testing phase to simulate the deformation and noise interference that the input might encounter in a real-world environment. This was used to test the model's robustness to input perturbations. In the robustness analysis of noise, 10%, 20%, and 30% noise were added to the test set, and the inference accuracy at 2-bit, 3-bit, and 4-bit precision was as follows: Figure 14 As shown.

[0267] from Figure 14 As can be seen, the inference accuracy of all methods decreases with increasing noise factor, but the magnitude of the decrease varies: at 2-bit accuracy, uniform quantization shows the most significant performance drop, while the proposed GMT-OTSU maintains high accuracy throughout, demonstrating stronger noise resistance than other methods; at 3-bit accuracy, the accuracy gap between methods narrows, but GMT-OTSU still maintains its advantage under different noise levels; at 4-bit accuracy, the overall gap further decreases, but GMT-OTSU still maintains slightly higher performance under different noise conditions. Overall, GMT-OTSU exhibits superior robustness across different quantization bit widths, especially in low-bit quantization scenarios.

[0268] (iv) Analysis of the computational complexity of the algorithm

[0269] The greedy multi-threshold OTSU strategy proposed in this invention maintains the deterministic and low parameter dependency advantages of OTSU while achieving efficient multi-level segmentation with a time complexity of only O(n). N). Table 5 provides a detailed complexity analysis for each step, due to the fact that... In the case of >0, log This holds true throughout, therefore the overall computational complexity is O(max{ N, However, in general, the number of samples N is greater than the number of bins Π in the histogram, so the computational complexity should be O(N). N).

[0270] Table 5. Derivation of computational complexity for each step

[0271]

[0272] Table 6 compares the computational complexity of several common clustering algorithms. The traditional OTSU algorithm determines the optimal split threshold by maximizing the inter-class variance of the data histogram in binary classification, ensuring determinism and global optimality. Its computational complexity is O(max{N, Π}). Since the number of bins Π in the histogram is generally less than the number of samples N, the computational complexity of the traditional single-threshold OTSU algorithm is O(N). However, extending the OTSU algorithm to... When there is a threshold, it is necessary to consider all combinations (Π) -1) Exhaustive search was performed, resulting in O(Π) The computational complexity increases exponentially with the threshold. The K-Means algorithm relies heavily on multiple iterations and random initialization, therefore its computational complexity is O(IN). The more iterations (I), the longer the computation time. Density peak clustering mainly requires calculating the pairwise distances of all samples, resulting in a computational complexity of O(N²). The proposed greedy multi-threshold OTSU approximation algorithm, through a greedy strategy of segmented splitting on the histogram, significantly reduces complexity. It retains the stability, determinism, and low parameter characteristics of OTSU while efficiently generating multi-level thresholds for subsequent weight parameter quantization.

[0273] Figure 6 Computational complexity analysis of several clustering algorithms

[0274]

[0275] This invention constructs a memristor in-memory computing acceleration scheme based on a nonlinear spiking neural P system. First, an FTO / This paper proposes a mathematical model for memristors ( / Ag) with series resistance, variable conductivity channels, and leakage branches, based on their I-V characteristics. Secondly, addressing the mismatch between high-precision weights and the finite discrete conductance states of the memristor, a greedy multi-threshold OTSU quantization method is proposed, significantly reducing time overhead while maintaining inference accuracy. Then, based on the proposed memristor model, an efficient weight mapping strategy is presented, accurately mapping the quantized weights to the conductance values ​​in the memristor cross array. An offline training memristor in-memory computing architecture based on a nonlinear pulse P system is also proposed, supporting efficient end-to-end deployment and inference. Finally, the effectiveness of the proposed greedy multi-threshold OTSU algorithm is verified on the MNIST dataset, demonstrating that the proposed method combines accuracy and efficiency at low bit depths. In summary, this invention provides an effective design paradigm for the offline deployment of memristor in-memory computing.

[0276] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An image classification method based on a nonlinear pulse P-system memristor neural network, characterized in that, Includes the following steps: Step 1: Construct an image classification system based on a nonlinear pulse P-system memristor neural network. The image classification system is equipped with an image acquisition module, a preprocessing module, and an image classification module connected in sequence. The image classification module has a built-in nonlinear pulse P-system memristor neural network. Step 2: The image acquisition module acquires raw image data a and transmits it to the preprocessing module; Step 3: The preprocessing module standardizes the original image data a to obtain standard image data b, and then passes it to the image classification module; Step 4: The image classification module inputs the standard image data b into the nonlinear pulse P system memristor neural network to perform image classification and recognition, and outputs the image classification result Y.

2. The image classification method based on a nonlinear pulse P-system memristor neural network according to claim 1, characterized in that: The nonlinear pulse P system memristor neural network is configured with M NSNP type convolutional layers connected end to end. The input of the first NSNP type convolutional layer is used to acquire the standard image data b, and the output of the last NSNP type convolutional layer is connected to an NSNP type fully connected output layer via a flattening layer. The NSNP type fully connected output layer is used to output the image classification result Y. The NSNP type convolutional layer is provided with NSNP type convolutional units and max pooling layers connected in sequence.

3. The image classification method based on a nonlinear pulse P-system memristor neural network according to claim 1, characterized in that: In the nonlinear pulse P system memristor neural network, the following is adopted: The memristor model serves as a neuron synapse to store the weights of the neuron network; the weight values ​​of each weight matrix in the nonlinear pulse P system memristor neural network are mapped to the conductance values ​​of each memristor in the memristor cross array.

4. The image classification method based on a nonlinear pulse P-system memristor neural network according to claim 3, characterized in that: The The expression for the memristor model is: ； The voltage threshold function expression for the memristor model is as follows: ； ； in, This is the positive threshold voltage of the memristor. This is the negative threshold voltage of the memristor. It is a function of positive threshold voltage. It is a function of negative threshold voltage. The positive threshold voltage rate coefficient, The negative threshold voltage rate coefficient. It is a non-linear window function. It is a threshold voltage function. It is a function with maximum value. For memristor state variables, For time, Apply an external voltage to the memristor. The positive threshold voltage exponential parameter, The negative threshold voltage exponential parameter; The nonlinear window function expression for the memristor model is as follows: ； ； in, For control parameters, ; Therefore, the above The state equation of the memristor model is: 。 5. The image classification method based on a nonlinear pulse P-system memristor neural network according to claim 3, characterized in that: The nonlinear pulse P-system memristor neural network is trained through the following steps: Step A1: The image acquisition module obtains an image sample set, which is then standardized by the preprocessing module and divided into a training set, a test set, and a validation set. Step A2: Construct a nonlinear pulse P-system memristor neural network. Iteratively train the nonlinear pulse P-system memristor neural network using an offline training method with a training set. Then, test and verify the nonlinear pulse P-system memristor neural network using a test set and a validation set to obtain the optimal weight matrix of the nonlinear pulse P-system memristor neural network. Step A3: Employ the greedy multi-threshold OTSU quantization algorithm, iterating on the weight histogram. -1 times and select the optimal segmentation point to obtain Cluster That is, image categories, and calculate each cluster. Corresponding weight centroid value ; Step A4: Employ a weight mapping strategy to assign weights to each cluster. Corresponding weight centroid value The values ​​are mapped to the conductance values ​​in the memristor cross array, ultimately resulting in the trained nonlinear pulse P system memristor neural network.

6. The image classification method based on a nonlinear pulse P-system memristor neural network according to claim 5, characterized in that: The offline training of the nonlinear pulse P system memristor neural network is completed through an NSNP memristor neural network accelerator. The NSNP memristor neural network accelerator is equipped with a control unit, which is connected to an instruction cache, a global cache, and an in-memory macro computing unit. The control unit is used to read instructions from the instruction cache and schedule the global cache and in-memory computation macrounits to perform corresponding operations according to a predetermined data flow; the instruction cache is used to prefetch and store the running instruction flow of the NSNP memristor neural network accelerator, and the global cache is used to handle the temporary access of intermediate feature maps, weights and activation values. The in-memory computing macrounit is integrated into a chip mesh network (NoC). This chip mesh network (NoC) has L computing unit tiles, each of which is composed of… It consists of in-memory computing macro units, local caches, and special function units; Each in-memory computation macrocell is equipped with a first register, a second register, a first multiplexer, a second multiplexer, a memristor crossbar array, a digital-to-analog converter (DAC), and an analog-to-digital converter (ADC). The first register sends input data to the input group of the memristor crossbar array via the DAC and the first multiplexer. The output group of the memristor crossbar array outputs the calculation result to the second register via the second multiplexer, the ADC, and an adder.

7. The image classification method based on a nonlinear pulse P-system memristor neural network according to claim 5, characterized in that: In step A3, a greedy multi-threshold OTSU quantization algorithm is used to iterate on the weight histogram. -1 times and select the optimal segmentation point to obtain Cluster That is, image categories, and calculate each cluster. Corresponding weight centroid value The specific steps are as follows: Step S1: Constructing the histogram: First, flatten the optimal weight matrix to be quantized into a one-dimensional vector. The interval is divided into Ξ equal intervals, where the number of samples and the weights in the i-th interval Ξ(i) are: ； ； in, Let n be the number of samples in the i-th interval Ξ(i), n be the weight index, and N be the total number of weights. ; Indicates if If it is established, then ,otherwise ; For the nth weight, Let be the set of weights for the i-th interval; The center value of each interval Ξ(i) for: ； in, For weight The maximum value, For weight The minimum value, For the number of intervals, For range index, ; Therefore, the normalized probability of the i-th interval Ξ(i) is: ； And have Then the global first moment for: ； Step S2: Greedy multi-threshold selection: In each In this iteration, the interval [0, Ξ) is divided into part , , ..., ,in , , Indicates a segmented index. This indicates the number of segments corresponding to the last iteration; For any segment The normalized probability within the segment is: ； have ; in, For section The intra-segment normalized probability; For Duan If at t∈[s,e) segment The split results in two subclasses. Then the cumulative probability and cumulative first moment of segment [s,t) are: ； ； in, Let be the cumulative probability of segment [s,t). Let be the cumulative first moment of the segment [s,t); And the global first moment within the segment is: That is, take hour; Then the inter-class variance of the tangent point t on segment [s,t) for: ； in, It is a positive number; Calculate the inter-class variance of all tangent points on the entire segment. Then, the position corresponding to the maximum inter-class variance is obtained by searching. and the location The corresponding weight value is recorded as the new threshold. ; Follow the above steps to execute. The next iteration operation yields a multi-threshold set. ,Right now Each threshold divides the weight interval [0, Ξ) into... There are intervals, each interval corresponds to a cluster. ; Step S3: Assign labels and calculate cluster centroids: for each weight Its tags are: ； in, For the label of the nth weight, For threshold; Indicates if If it is established, then ,otherwise ; Then calculate each cluster The centroid of the weights is the mean of all weights in that class: ； in, For clusters That is, the weight centroid of image category a. .

8. The image classification method based on a nonlinear pulse P-system memristor neural network according to claim 5, characterized in that: In step A4, a weight mapping strategy is used to assign each weight centroid value... Linear mapping to the conductance range of memristors : ； in, This is the maximum conductance of the memristor. This is the minimum conductance of the memristor; To address the issue of quantized weights having both positive and negative values, the signs of the weights are distinguished and processed separately before being mapped to the memristor conductance. First, the centroids of the weights for each quantization level are... Break it down into positive and negative parts: ； ； The memristor cross array adopts a differential cross array structure, including a positive array. and negative array Among them, positive array Used to store positive weights negative array Used to store negative weights The mapping scheme is as follows: ； ； ； ； in, Clusters in a positive array The conductivity value, Clusters in a negative array The conductivity value, For clusters Positive weights, For clusters Negative weights, The maximum positive weight among all clusters. It represents the smallest negative weight among all clusters.

9. The image classification method based on a nonlinear pulse P-system memristor neural network according to claim 5, characterized in that: The Memristor model based on The memristor is constructed as follows: The memristor is attached to an FTO glass substrate from bottom to top. Functional layer and Ag top electrode.

10. The image classification method based on a nonlinear pulse P-system memristor neural network according to claim 2, characterized in that: The NSNP-type fully connected output layer calculates the probability distribution values ​​of various image categories through full connection, and then outputs the image category corresponding to the maximum probability distribution value as the image classification result Y.

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