Multichannel transceiver chip

Abstract

The application relates to the field of wireless communication technology and provides a multi-channel transceiving multifunctional chip, which comprises a chip, a first single-pole four-throw switch, a first transmitting channel, a second transmitting channel, a first receiving channel, a second receiving channel and a second single-pole four-throw switch which are integrated in the chip respectively; the input end of the first single-pole four-throw switch is used for accessing a transceiving port; the first output end of the first single-pole four-throw switch is connected with the input end of the first transmitting channel; the second output end of the first single-pole four-throw switch is connected with the input end of the second transmitting channel; the first logic control signal to the fourth logic control signal of a control unit are used for controlling the first transmitting channel and the second transmitting channel to be conductive respectively; and the fifth logic control signal to the eighth logic control signal are used for controlling the first receiving channel and the second receiving channel to be conductive respectively. The application can realize the application of multi-frequency-band multi-channels.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a multi-channel transceiver chip. Background Technology

[0002] Due to the rapid development of the electronics industry, radio frequency (RF) circuits are receiving increasing attention. The core component of RF circuits is the RF transceiver chip, used to transmit and receive data, and widely used in various mobile communications, satellite communications, broadcasting, wireless broadband, and the Internet of Things (IoT). Currently, the requirements for transceiver chips are becoming increasingly stringent, evolving from single-input single-output single-channel to multiple-input multiple-output multi-channel, while also needing to be smaller, perform better, and be more price-competitive. Therefore, improving the integration of multi-functional chips, increasing chip functionality, reducing chip size and weight, and achieving high reliability, small size, and lightweight multi-functional chips, while simultaneously developing towards multi-band and multi-channel designs, is urgently needed.

[0003] Currently, multi-functional transceiver systems are typically built using components such as control switches, low-noise amplifiers, power amplifiers, and filters. This results in low overall integration and large size for multi-channel transceiver systems. Furthermore, the transmit and receive channels operate on a single frequency band with narrow bandwidth. While thin-film multilayer circuit technology can address this, its main process uses a serial configuration, leading to lower yield and higher manufacturing costs. Additionally, using LTCC (Low Temperature Co-fired Ceramic) technology instead of traditional thin-film ceramic planar circuits, and employing a mixed-signal design including microwave transmission lines, logic control lines, and power supply lines, integrates numerous functional chips, filters, and amplifiers into a single LTCC three-dimensional microwave transmission structure. Passive resistors and capacitors, and filters are embedded within the substrate structure, achieving high-density integration. Signal transmission between layers uses vertical interconnection, with chips, control signal lines, and power lines arranged on the top and middle layers respectively. Power chips are directly grounded or grounded via heat dissipation vias, resulting in complex processes and high costs. Using silicon-based technology to integrate switches, low-noise amplifiers, power amplifiers, filters, etc. onto the same chip results in poor noise figure, linearity, and limited output power. Summary of the Invention

[0004] To address the shortcomings of the existing technologies, this invention proposes a multi-channel transceiver multifunction chip to solve the problems of low integration, high cost, and limited frequency band and channel in existing multi-channel transceiver multifunction systems.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0006] This invention provides a multi-channel transceiver chip, which includes a chip, a first single-pole four-throw switch, a first transmitting channel, a second transmitting channel, a first receiving channel, a second receiving channel, and a second single-pole four-throw switch, all integrated into the chip. The input terminal of the first single-pole four-throw switch is used to connect to the transceiver port. The first output terminal of the first single-pole four-throw switch is connected to the input terminal of the first transmitting channel. The second output terminal of the first single-pole four-throw switch is connected to the input terminal of the second transmitting channel. The output terminal of the first transmitting channel is connected to the first output terminal of the second single-pole four-throw switch. The output terminal of the second transmitting channel is connected to the second output terminal of the second single-pole four-throw switch. The first transmitting channel and the second transmitting channel are used to amplify the power of the signals passing through their paths. The third output terminal of the first single-pole four-throw switch is connected to the output terminal of the first receiving channel, the fourth output terminal of the first single-pole four-throw switch is connected to the output terminal of the second receiving channel, the input terminal of the first receiving channel and the input terminal of the second receiving channel are respectively connected to the third output terminal and the fourth output terminal of the second single-pole four-throw switch, and the input terminal of the second single-pole four-throw switch is used to connect to the antenna port. The first transmitting channel, the second transmitting channel, the first receiving channel, and the second receiving channel are all controlled by an external control unit; The control unit is configured to output a first logic control signal, a second logic control signal, a third logic control signal, a fourth logic control signal, a fifth logic control signal, a sixth logic control signal, a seventh logic control signal, and an eighth logic control signal; wherein the second logic control signal is the inverse logic of the first logic control signal, the fourth logic control signal is the inverse logic of the third logic control signal, the sixth logic control signal is the inverse logic of the fifth logic control signal, and the eighth logic control signal is the inverse logic of the seventh logic control signal; The first logic control signal and the second logic control signal are used to jointly control the conduction of the first transmission channel, and the third logic control signal and the fourth logic control signal are used to jointly control the conduction of the second transmission channel; The fifth logic control signal and the sixth logic control signal are used to jointly control the conduction of the first receiving channel; the seventh logic control signal and the eighth logic control signal are used to jointly control the conduction of the second receiving channel; When one of the first transmitting channel, the second transmitting channel, the first receiving channel, and the second receiving channel is in the on state, the other three channels are in the off state.

[0007] Preferably, the first receiving channel includes a first single-pole double-throw switch, a first low-noise amplifier, a first bypass circuit, a second single-pole double-throw switch, and a first filter; The control unit is also used to output a ninth logic control signal, a tenth logic control signal, an eleventh logic control signal, and a twelfth logic control signal; wherein the tenth logic control signal is the inverse logic of the ninth logic control signal, and the twelfth logic control signal is the inverse logic of the eleventh logic control signal; The first terminal of the first filter serves as the input terminal of the first receiving channel. The second terminal of the first filter is connected to the input terminal of the second single-pole double-throw switch. The first output terminal of the second single-pole double-throw switch is connected to the input terminal of the first low-noise amplifier. The second output terminal of the second single-pole double-throw switch is connected to the input terminal of the first bypass circuit. The output terminal of the first low-noise amplifier is connected to the first output terminal of the first single-pole double-throw switch. The output terminal of the first bypass circuit is connected to the second output terminal of the first single-pole double-throw switch. The input terminal of the first single-pole double-throw switch serves as the output terminal of the first receiving channel. When the ninth logic control signal outputs a high level and the tenth logic control signal outputs a low level, the first low-noise amplifier is turned on, and the first bypass circuit is turned off. When the ninth logic control signal outputs a low level and the tenth logic control signal outputs a high level, the first low-noise amplifier is turned off, and the first bypass circuit is turned on. The second receiving channel includes a third single-pole double-throw switch, a second low-noise amplifier, a second bypass circuit, a fourth single-pole double-throw switch, and a second filter; The first terminal of the second filter serves as the input terminal of the second receiving channel. The second terminal of the second filter is connected to the input terminal of the fourth single-pole double-throw switch. The first output terminal of the fourth single-pole double-throw switch is connected to the input terminal of the second low-noise amplifier. The second output terminal of the fourth single-pole double-throw switch is connected to the input terminal of the second bypass circuit. The output terminal of the second low-noise amplifier is connected to the first output terminal of the third single-pole double-throw switch. The output terminal of the second bypass circuit is connected to the second output terminal of the third single-pole double-throw switch. The input terminal of the third single-pole double-throw switch serves as the output terminal of the second receiving channel. When the eleventh logic control signal outputs a high level and the twelfth logic control signal outputs a low level, the second low-noise amplifier is turned on, and the second bypass circuit is turned off. When the eleventh logic control signal outputs a low level and the twelfth logic control signal outputs a low level, the second low-noise amplifier is turned off, and the second bypass circuit is turned on.

[0008] Preferably, the circuit structures of the first transmission channel and the second transmission channel are the same; The first transmission channel includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a sixth inductor, a seventh inductor, an eighth inductor, a first MOSFET, a second MOSFET, and a third MOSFET; The first terminal of the first capacitor serves as the input terminal of the first transmission channel. The second terminal of the first capacitor is connected to the first terminal of the first inductor, the gate of the first MOS transistor, and the first terminal of the second capacitor. The second terminal of the first inductor is connected to the first terminal of the first resistor, the second terminal of the first resistor is connected to the first terminal of the ninth capacitor, and the second terminal of the ninth capacitor is grounded. The second terminal of the second capacitor is connected to the first terminal of the second resistor, the second terminal of the second resistor is connected to the first terminal of the second inductor, the second terminal of the second inductor is connected to the first terminal of the third inductor, the first terminal of the third capacitor and the drain of the first MOS transistor, and the source of the first MOS transistor is grounded. The second terminal of the third inductor is connected to the first terminal of the tenth capacitor, the first terminal of the eleventh capacitor, the first terminal of the twelfth capacitor, the first terminal of the sixth inductor, and the first terminal of the eighth inductor, and is connected to the power supply; the second terminals of the tenth capacitor, the eleventh capacitor, and the twelfth capacitor are all grounded. The second terminal of the third capacitor is connected to the first terminal of the fourth inductor, the first terminal of the fourth capacitor, and the gate of the second MOS transistor. The second terminal of the fourth inductor is connected to the first terminal of the third resistor. The second terminal of the third resistor is connected to the first terminal of the eighth capacitor and the second terminal of the first resistor. The second terminal of the eighth capacitor is grounded. The second terminal of the fourth capacitor is connected to the first terminal of the fourth resistor, the second terminal of the fourth resistor is connected to the first terminal of the fifth inductor, the second terminal of the fifth inductor is connected to the second terminal of the sixth inductor, the drain of the second MOS transistor, and the first terminal of the fifth capacitor, respectively, and the source of the second MOS transistor is grounded. The second terminal of the fifth capacitor is connected to the first terminal of the seventh inductor and the gate of the third MOS transistor, and the source of the third MOS transistor is grounded; the second terminal of the seventh inductor is connected to the first terminal of the fifth resistor, the second terminal of the fifth resistor is connected to the first terminal of the seventh capacitor and the second terminal of the first resistor, and the second terminal of the seventh capacitor is grounded; The drain of the third MOS transistor is connected to the second terminal of the eighth inductor and the first terminal of the sixth capacitor, respectively. The second terminal of the sixth capacitor serves as the output terminal of the first emitter channel.

[0009] Preferably, the first low-noise amplifier and the second low-noise amplifier have the same circuit structure; The first low-noise amplifier includes an input control module, an input matching circuit, an active bias circuit, a fourth MOSFET, an interstage matching circuit, a fifth MOSFET, a power supply bias circuit, a stabilization circuit, and an output matching circuit. The input terminal of the input control module serves as the input terminal of the first low-noise amplifier. The output terminal of the input control module is connected to the input terminal of the input matching circuit. The control unit is used to control the input control module to be turned on or off. The output terminal of the input matching circuit is connected to the first terminal of the active bias circuit and the gate of the fourth MOS transistor. The source of the fourth MOS transistor is grounded. The second terminal of the active bias circuit is connected to the first terminal of the power bias circuit and connected to the power supply. The drain of the fourth MOS transistor is connected to the input terminal of the interstage matching circuit, the output terminal of the interstage matching circuit is connected to the gate of the fifth MOS transistor and the second terminal of the power supply bias circuit, and the source of the fifth MOS transistor is grounded. The drain of the fifth MOS transistor and the third terminal of the power supply bias circuit are respectively connected to the input terminal of the stabilization circuit. The output terminal of the stabilization circuit is connected to the input terminal of the output matching circuit. The output terminal of the output matching circuit serves as the output terminal of the first low-noise amplifier. The input matching circuit is used to achieve impedance matching; The active bias circuit is used to provide a bias voltage for the gate of the fourth MOS transistor; The interstage matching circuit is used to connect the matching between the fourth MOS transistor and the fifth MOS transistor; The power bias circuit is used to provide bias power to the fifth MOS transistor; The stabilization circuit is used to improve the stability of the first low-noise amplifier; The output matching circuit is used to achieve output impedance matching.

[0010] Preferably, the input matching circuit includes a ninth inductor, a thirteenth capacitor, and a tenth inductor; the first end of the ninth inductor is connected to the first end of the thirteenth capacitor and connected to the output terminal of the input control module, the second end of the ninth inductor is grounded, the second end of the thirteenth capacitor serves as the output terminal of the input matching circuit, the first end of the tenth inductor is connected to the source of the fourth MOS transistor, and the second end of the tenth inductor is grounded.

[0011] Preferably, the active bias circuit includes a sixth resistor, a seventh resistor, an eighth resistor, a sixth MOSFET, a ninth resistor, a tenth resistor, a first diode, and a second diode; The first end of the sixth resistor serves as the first end of the active bias circuit. The second end of the sixth resistor is connected to the first end of the seventh resistor and the first end of the eighth resistor. The second end of the seventh resistor is connected to the negative terminal of the second diode and grounded. The positive terminal of the second diode is connected to the negative terminal of the first diode. The positive terminal of the first diode is connected to the first end of the tenth resistor and the gate of the sixth MOS transistor. The source of the sixth MOS transistor is connected to the second end of the eighth resistor. The second end of the ninth resistor is connected to the second end of the tenth resistor and serves as the second end of the active bias circuit.

[0012] Preferably, the interstage matching circuit includes an eleventh inductor, a fourteenth capacitor, and a fifteenth capacitor, and the source of the fifth MOS transistor is grounded through the fifteenth capacitor; The first end of the eleventh inductor is connected to the fourteenth capacitor and serves as the input terminal of the interstage matching circuit. The second end of the eleventh inductor is connected to the source of the fifth MOS transistor. The second end of the fourteenth capacitor serves as the output terminal of the interstage matching circuit.

[0013] Preferably, the power supply bias circuit includes an eleventh resistor, a twelfth resistor, and a thirteenth resistor; The first end of the thirteenth resistor serves as the first end of the power supply bias circuit. The second end of the thirteenth resistor is connected to the first end of the eleventh resistor and the first end of the twelfth resistor. The second end of the eleventh resistor serves as the second end of the power supply bias circuit, and the second end of the twelfth resistor serves as the third end of the power supply bias circuit.

[0014] Preferably, the stabilizing circuit includes a fourteenth resistor and a sixteenth capacitor; the first end of the fourteenth resistor serves as both the input and output of the stabilizing circuit, and the second end of the fourteenth resistor is grounded after being connected in series with the sixteenth capacitor.

[0015] Preferably, the output matching circuit includes a twelfth inductor, a seventeenth capacitor, and an eighteenth capacitor; The first terminal of the twelfth inductor serves as the input terminal of the output matching circuit. The second terminal of the twelfth inductor is connected to the first terminal of the seventeenth capacitor and the first terminal of the eighteenth capacitor. The second terminal of the seventeenth capacitor is grounded, and the second terminal of the eighteenth capacitor serves as the output terminal of the output matching circuit. The multi-channel transceiver chip also includes a nineteenth capacitor, the first end of which is connected to the power supply, and the second end of which is grounded.

[0016] Preferably, the first bypass circuit and the second bypass circuit have the same circuit structure; The first bypass circuit includes a twentieth capacitor, a fifteenth resistor, a sixteenth resistor, a seventh MOSFET, a seventeenth resistor, an eighteenth resistor, an eighth MOSFET, a nineteenth resistor, a twentieth resistor, a ninth MOSFET, a twenty-first capacitor, a twenty-second capacitor, a twenty-third resistor, a twenty-fourth resistor, and a twenty-fifth resistor; The first terminal of the twentieth capacitor serves as the input terminal of the first bypass circuit. The second terminal of the twentieth capacitor is connected to the first terminal of the fifteenth resistor, the first terminal of the sixteenth resistor, and the source of the seventh MOS transistor. The second terminal of the fifteenth resistor is connected to the first terminal of the seventeenth resistor and the first terminal of the nineteenth resistor, and is connected to the power supply. The gate of the seventh MOS transistor is connected to the first terminal of the twenty-third resistor, the gate of the eighth MOS transistor is connected to the first terminal of the twenty-fourth resistor, the gate of the ninth MOS transistor is connected to the first terminal of the twenty-fifth resistor, and the second terminals of the twenty-third, twenty-fourth, and twenty-fifth resistors are respectively connected to the control unit. The drain of the seventh MOS transistor is connected to the second terminal of the sixteenth resistor, the second terminal of the seventeenth resistor, the first terminal of the eighteenth resistor, the source of the eighth MOS transistor, the first terminal of the twentieth resistor, and the drain of the ninth MOS transistor. The source of the ninth MOS transistor is connected to the second terminal of the twentieth resistor and the first terminal of the twentieth capacitor. The second terminal of the twentieth capacitor is grounded. The second terminal of the eighteenth resistor is connected to the drain of the eighth MOS transistor, the second terminal of the nineteenth resistor, and the first terminal of the twentieth capacitor. The second terminal of the twentieth capacitor serves as the output terminal of the first bypass circuit.

[0017] Preferably, the first filter and the second filter have the same circuit structure; The first filter includes a low-pass filter circuit and a high-pass filter circuit that are electrically connected in sequence; The low-pass filter circuit includes capacitors numbered twenty-third, twenty-fourth, twenty-fifth, twenty-sixth, twenty-seventh, twenty-eighth, and twenty-ninth, as well as inductors numbered thirteenth, fourteenth, and fifteenth. The first terminal of the 23rd capacitor is connected to the first terminal of the 24th capacitor and the first terminal of the 13th inductor, respectively, and serves as the first terminal of the first filter. The second terminal of the 24th capacitor is connected to the first terminal of the 25th capacitor, the second terminal of the 13th inductor, the first terminal of the 26th capacitor, and the first terminal of the 14th inductor, respectively. The second terminal of the 26th capacitor is connected to the first terminal of the 27th capacitor, the second terminal of the 14th inductor, the first terminal of the 15th inductor, and the first terminal of the 28th capacitor, respectively. The second terminal of the 28th capacitor is connected to the second terminal of the 15th inductor and the first terminal of the 29th capacitor, respectively. The second terminals of the 23rd capacitor, the 25th capacitor, the 27th capacitor, and the 29th capacitor are grounded, respectively. The high-pass filter circuit includes a 30th capacitor, a 31st capacitor, a 32nd capacitor, a 33rd capacitor, a 34th capacitor, a 35th capacitor, a 36th capacitor, a 16th inductor, a 17th inductor, and an 18th inductor. The first terminal of the thirtieth capacitor is connected to the second terminal of the twenty-eighth capacitor. The second terminal of the thirtieth capacitor is connected to the first terminals of the sixteenth inductor and the thirty-second capacitor. The second terminal of the sixteenth inductor is grounded after being connected in series with the thirty-first capacitor. The second terminal of the thirty-second capacitor is connected to the first terminals of the seventeenth inductor and the thirty-fourth capacitor. The second terminal of the seventeenth inductor is grounded after being connected in series with the thirty-third capacitor. The second terminal of the thirty-fourth capacitor is connected to the first terminals of the eighteenth inductor and the thirty-sixth capacitor. The second terminal of the thirty-sixth capacitor serves as the second terminal of the first filter. The second terminal of the eighteenth inductor is grounded after being connected in series with the thirty-fifth capacitor.

[0018] Preferably, the first single-pole four-throw switch and the second single-pole four-throw switch have the same circuit structure; The first single-pole four-throw switch includes a first switching unit, a second switching unit, a third switching unit, and a fourth switching unit; The input terminals of the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit are connected and serve as the input terminals of the first single-pole four-throw switch. The output terminals of the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit serve as the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal of the first single-pole four-throw switch, respectively. The control unit controls the on or off states of the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit, respectively.

[0019] Preferably, the first switching unit, the second switching unit, the third switching unit, and the fourth switching unit have the same circuit structure; The first switching unit includes a twenty-sixth resistor, a twenty-seventh resistor, a tenth MOSFET, and an eleventh MOSFET; The first end of the 27th resistor is connected to the control unit, the second end of the 27th resistor is connected to the gate of the 10th MOS transistor, the drain of the 10th MOS transistor serves as the input terminal of the first switching unit, the source of the 10th MOS transistor is connected to the drain of the 11th MOS transistor and serves as the output terminal of the first switching unit, the source of the 11th MOS transistor is grounded, the gate of the 11th MOS transistor is connected to the first end of the 26th resistor, and the second end of the 26th resistor is connected to the control unit.

[0020] Preferably, the first single-pole double-throw switch, the second single-pole double-throw switch, the third single-pole double-throw switch and the fourth single-pole double-throw switch have the same circuit structure; The first single-pole double-throw switch includes a fifth switching unit and a sixth switching unit; The input terminal of the fifth switch unit is connected to the input terminal of the sixth switch unit and serves as the input terminal of the first single-pole double-throw switch. The output terminals of the fifth switch unit and the sixth switch unit serve as the first output terminal and the second output terminal of the first single-pole double-throw switch, respectively.

[0021] Preferably, the fifth switching unit has the same circuit structure as the sixth switching unit; The fifth switching unit includes a thirty-seventh capacitor, a thirty-eighth capacitor, a thirty-ninth capacitor, a twelfth MOSFET, a thirteenth MOSFET, a fourteenth MOSFET, a twenty-eighth resistor, a twenty-ninth resistor, a thirtieth resistor, and a thirty-first resistor; The first terminal of the thirty-seventh capacitor serves as the input terminal of the fifth switching unit. The second terminal of the thirty-seventh capacitor is connected to the drain of the twelfth MOS transistor. The source of the twelfth MOS transistor is connected to the first terminal of the twenty-ninth resistor, the first terminal of the thirty-ninth capacitor, and the drain of the thirteenth MOS transistor, respectively. The gate of the twelfth MOS transistor is connected to the first terminal of the thirty-first resistor. The source of the thirteenth MOS transistor is connected to the first terminal of the thirty-eighth capacitor. The second terminal of the thirty-eighth capacitor serves as the output terminal of the fifth switching unit. The gate of the thirteenth MOS transistor is connected to the first terminal of the twenty-eighth resistor. The second terminal of the twenty-ninth resistor is connected to the second terminal of the thirty-ninth capacitor and the drain of the fourteenth MOS transistor, respectively. The source of the fourteenth MOS transistor is grounded. The gate of the fourteenth MOS transistor is connected to the first terminal of the thirtieth resistor. The second terminals of the thirty-first resistor, the twenty-eighth resistor, and the thirtieth resistor are respectively used to connect to the control unit.

[0022] Compared with related technologies, in the embodiments of the present invention, by integrating the first single-pole four-throw switch, the first transmitting channel, the second transmitting channel, the first receiving channel, the second receiving channel, and the second single-pole four-throw switch onto the same chip, the integration level is improved, the cost is reduced, and the output power, linearity, and noise are improved. The first single-pole four-throw switch's input terminal is used to connect to the transceiver port; its first output terminal is connected to the input terminal of the first transmitting channel; its second output terminal is connected to the input terminal of the second transmitting channel; and the output terminal of the first transmitting channel is connected to the first output terminal of the second single-pole four-throw switch. The output of the transmitting channel is connected to the second output of the second single-pole four-throw switch; the first and second transmitting channels are used to amplify the power of the signals passing through their paths; the third output of the first single-pole four-throw switch is connected to the output of the first receiving channel, the fourth output of the first single-pole four-throw switch is connected to the output of the second receiving channel, the input of the first receiving channel is connected to the third output of the second single-pole four-throw switch, the input of the second receiving channel is connected to the fourth output of the second single-pole four-throw switch, and the input of the second single-pole four-throw switch is used to connect to the antenna port, enabling the chip to integrate multiple frequency bands and multiple channels, thus making the chip more widely applicable. Attached Figure Description

[0023] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1 A block diagram of a multi-channel transceiver chip provided in an embodiment of the present invention; Figure 2A circuit diagram of the first single-pole four-throw switch of the multi-channel transceiver multi-function chip provided in an embodiment of the present invention; Figure 3 A circuit diagram of the first transmit channel of a multi-channel transceiver chip provided in an embodiment of the present invention; Figure 4 A circuit diagram of the first single-pole double-throw switch of the multi-channel transceiver multi-function chip provided in an embodiment of the present invention; Figure 5 A circuit diagram of the first low-noise amplifier of the multi-channel transceiver multifunction chip provided in an embodiment of the present invention; Figure 6 A circuit diagram of the first bypass circuit of the multi-channel transceiver multifunction chip provided in an embodiment of the present invention; Figure 7 The circuit diagram shows the first filter of the multi-channel transceiver multi-function chip provided in the embodiment of the present invention.

[0024] Among them, 100 is a multi-channel transceiver multifunction chip; 1. a first single-pole four-throw switch; 11. a first switching unit; 12. a second switching unit; 13. a third switching unit; 14. a fourth switching unit; 2. a first transmitting channel; 3. a second transmitting channel; 4. a first receiving channel; 41. a first single-pole double-throw switch; 411. a fifth switching unit; 412. a sixth switching unit; 42. a first low-noise amplifier; 421. an input control module; 422. an input matching circuit; 423. an active bias circuit; 424. Interstage matching circuit, 425; power supply bias circuit, 426; stabilization circuit, 427; output matching circuit, 43; first bypass circuit, 44; second single-pole double-throw switch, 45; first filter, 451; low-pass filter circuit, 452; high-pass filter circuit, 5; second receiving channel, 51; third single-pole double-throw switch, 52; second low-noise amplifier, 53; second bypass circuit, 54; fourth single-pole double-throw switch, 55; second filter, 6; second single-pole quadruple-throw switch, 7; control unit, 8; chip. Detailed Implementation

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0026] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] Please see Figures 1-7 As shown, this embodiment of the invention provides a multi-channel transceiver multifunction chip 100. The multi-channel transceiver multifunction chip 100 includes a chip 8, a first single-pole four-throw switch 1, a first transmitting channel 2, a second transmitting channel 3, a first receiving channel 4, a second receiving channel 5, and a second single-pole four-throw switch 6, all integrated into the chip 8. The first single-pole four-throw switch 1 divides the signal into four channels: two transmitting channels (first transmitting channel 2 and second transmitting channel 3), and two receiving channels (first receiving channel 4 and second receiving channel 5). These channels can receive or transmit signals in two frequency bands. The switching between channels is controlled by the first single-pole four-throw switch 1 and the second single-pole four-throw switch 6.

[0029] The input terminal of the first single-pole four-throw switch 1 is used to connect to the transceiver port. The first output terminal of the first single-pole four-throw switch 1 is connected to the input terminal of the first transmitting channel 2. The second output terminal of the first single-pole four-throw switch 1 is connected to the input terminal of the second transmitting channel 3. The output terminal of the first transmitting channel 2 is connected to the first output terminal of the second single-pole four-throw switch 6. The output terminal of the second transmitting channel 3 is connected to the second output terminal of the second single-pole four-throw switch 6. The first transmitting channel 2 and the second transmitting channel 3 are used to amplify the power of the signal passing through their paths.

[0030] The third output terminal of the first single-pole four-throw switch 1 is connected to the output terminal of the first receiving channel 4, the fourth output terminal of the first single-pole four-throw switch 1 is connected to the output terminal of the second receiving channel 5, the input terminal of the first receiving channel 4 and the input terminal of the second receiving channel 5 are respectively connected to the third output terminal and the fourth output terminal of the second single-pole four-throw switch 6, the input terminal of the second single-pole four-throw switch 6 is used to connect to the antenna port, and the first filter 45 and the second filter 55 are used to filter two different frequency bands of signals and send them to the first receiving channel 4 or the second receiving channel 5.

[0031] The first transmitting channel 2, the second transmitting channel 3, the first receiving channel 4, and the second receiving channel 5 are all controlled by an external control unit 7; The control unit 7 is used to output a first logic control signal V1, a second logic control signal V2, a third logic control signal V3, a fourth logic control signal V4, a fifth logic control signal V5, a sixth logic control signal V6, a seventh logic control signal V7, and an eighth logic control signal V8; wherein the second logic control signal V2 is the inverse logic of the first logic control signal V1, the fourth logic control signal V4 is the inverse logic of the third logic control signal V3, the sixth logic control signal V6 is the inverse logic of the fifth logic control signal V5, and the eighth logic control signal V8 is the inverse logic of the seventh logic control signal V7.

[0032] It should be noted that the circuit structure of the second single-pole four-throw switch 6 is the same as that of the first single-pole four-throw switch 1, and the connection method and working principle of its control signal are the same as those of the first single-pole double-throw switch 41.

[0033] The first logic control signal V1 and the second logic control signal V2 are used to jointly control the conduction of the first transmission channel 2, and the third logic control signal V3 and the fourth logic control signal V4 are used to jointly control the conduction of the second transmission channel 3. The fifth logic control signal V5 and the sixth logic control signal V6 are used to jointly control the conduction of the first receiving channel 4; the seventh logic control signal V7 and the eighth logic control signal V8 are used to jointly control the conduction of the second receiving channel 5. When one of the first transmitting channel 2, the second transmitting channel 3, the first receiving channel 4, and the second receiving channel 5 is in the conducting state, the other three channels are in the off state.

[0034] Specifically, by integrating the first single-pole quad-throw switch 1, the first transmitting channel 2, the second transmitting channel 3, the first receiving channel 4, the second receiving channel 5, and the second single-pole quad-throw switch 6 onto the same chip 8, the integration level is improved, the cost is reduced, and the output power, linearity, and noise are better. The input terminal of the first single-pole quad-throw switch 1 is used to connect to the transceiver port; the first output terminal of the first single-pole quad-throw switch 1 is connected to the input terminal of the first transmitting channel 2; the second output terminal of the first single-pole quad-throw switch 1 is connected to the input terminal of the second transmitting channel 3; the output terminal of the first transmitting channel 2 is connected to the first output terminal of the second single-pole quad-throw switch 6; and the output terminal of the second transmitting channel 3 is connected to the second output terminal of the second single-pole quad-throw switch 6. Transmit channel 2 and second transmit channel 3 are used to amplify signals passing through their paths; the third output terminal of the first single-pole four-throw switch 1 is connected to the output terminal of the first receiving channel 4, the fourth output terminal of the first single-pole four-throw switch 1 is connected to the output terminal of the second receiving channel 5, the input terminal of the first receiving channel 4 is connected to the third output terminal of the second single-pole four-throw switch 6, the input terminal of the second receiving channel 5 is connected to the fourth output terminal of the second single-pole four-throw switch 6, and the input terminal of the second single-pole four-throw switch 6 is used to connect to the antenna port; the first filter 45 and the second filter 55 are used to filter two different frequency band signals through the first receiving channel 4 or the second receiving channel 5, so that the chip integrates multiple frequency bands and multiple channels, making the chip more widely applicable.

[0035] In this embodiment, the first receiving channel 4 includes a first single-pole double-throw switch 41, a first low-noise amplifier 42, a first bypass circuit 43, a second single-pole double-throw switch 44, and a first filter 45.

[0036] The control unit 7 is also used to output a ninth logic control signal V9, a tenth logic control signal V10, an eleventh logic control signal, and a twelfth logic control signal; wherein, the tenth logic control signal V10 is the inverse logic of the ninth logic control signal V9, and the twelfth logic control signal is the inverse logic of the eleventh logic control signal. It should be noted that since the circuit structures of the first single-pole double-throw switch 41, the second single-pole double-throw switch 44, the third single-pole double-throw switch 51, and the fourth single-pole double-throw switch 54 are the same, and the connection method and working principle of their control signals are the same as those of the first single-pole double-throw switch 41, although the eleventh and twelfth logic control signals are not separately marked in the figures, it does not affect the understanding and implementation of the technical solution by those skilled in the art. The first end of the first filter 45 serves as the input end of the first receiving channel 4, the second end of the first filter 45 is connected to the input end of the second single-pole double-throw switch 44, the first output end of the second single-pole double-throw switch 44 is connected to the input end of the first low-noise amplifier 42, the second output end of the second single-pole double-throw switch 44 is connected to the input end of the first bypass circuit 43, the output end of the first low-noise amplifier 42 is connected to the first output end of the first single-pole double-throw switch 41, the output end of the first bypass circuit 43 is connected to the second output end of the first single-pole double-throw switch 41, and the input end of the first single-pole double-throw switch 41 serves as the output end of the first receiving channel 4. The first receiving channel 4 is switched by the first single-pole double-throw switch 41 and the second single-pole double-throw switch 44, and complementary level control is adopted. When the ninth logic control signal V9 outputs a high level and the tenth logic control signal V10 outputs a low level, the first low-noise amplifier 42 is turned on and the first bypass circuit 43 is turned off; when the ninth logic control signal V9 outputs a low level and the tenth logic control signal V10 outputs a high level, the first low-noise amplifier 42 is turned off and the first bypass circuit 43 is turned on.

[0037] The second receiving channel 5 includes a third single-pole double-throw switch 51, a second low-noise amplifier 52, a second bypass circuit 53, a fourth single-pole double-throw switch 54, and a second filter 55.

[0038] The first end of the second filter 55 serves as the input end of the second receiving channel 5. The second end of the second filter 55 is connected to the input end of the fourth single-pole double-throw switch 54. The first output end of the fourth single-pole double-throw switch 54 is connected to the input end of the second low-noise amplifier 52. The second output end of the fourth single-pole double-throw switch 54 is connected to the input end of the second bypass circuit 53. The output end of the second low-noise amplifier 52 is connected to the first output end of the third single-pole double-throw switch 51. The output end of the second bypass circuit 53 is connected to the second output end of the third single-pole double-throw switch 51. The input end of the third single-pole double-throw switch 51 serves as the output end of the second receiving channel 5. The second receiving channel 5 is switched by the third single-pole double-throw switch 51 and the fourth single-pole double-throw switch 54, using complementary level control. When the eleventh logic control signal outputs a high level and the twelfth logic control signal outputs a low level, the second low-noise amplifier 52 is turned on and the second bypass circuit 53 is turned off; when the eleventh logic control signal outputs a low level and the twelfth logic control signal outputs a high level, the second low-noise amplifier 52 is turned off and the second bypass circuit 53 is turned on.

[0039] Specifically, the first filter 45 and the second filter 55 are used to filter signals of two different frequency bands passing through the first receiving channel 4 or the second receiving channel 5. When the signal passes through the first receiving channel 4, the first low-noise amplifier 42 and the first bypass circuit 43 are switched on or off by the first single-pole double-throw switch 41 and the second single-pole double-throw switch 44. When the signal passes through the second receiving channel 5, the second low-noise amplifier 52 and the second bypass circuit 53 are switched on or off by the third single-pole double-throw switch 51 and the fourth single-pole double-throw switch 54. Each of the first single-pole double-throw switch 41, the second single-pole double-throw switch 44, the third single-pole double-throw switch 51, and the fourth single-pole double-throw switch 54 adopts a series-parallel structure with a series-parallel RC matching network introduced at the output port. This has the effects of low insertion loss, high isolation, and small mismatch at the shut-off branch port.

[0040] In this embodiment, the circuit structures of the first transmission channel 2 and the second transmission channel 3 are the same; The first transmitting channel 2 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, a seventh inductor L7, an eighth inductor L8, a first MOSFET M1, a second MOSFET M2, and a third MOSFET M3.

[0041] The first terminal of the first capacitor C1 serves as the input terminal of the first transmitting channel 2. The second terminal of the first capacitor C1 is connected to the first terminal of the first inductor L1, the gate of the first MOS transistor M1, and the first terminal of the second capacitor C2. The second terminal of the first inductor L1 is connected to the first terminal of the first resistor R1. The second terminal of the first resistor R1 is connected to the first terminal of the ninth capacitor C9. The second terminal of the ninth capacitor C9 is grounded.

[0042] The second terminal of the second capacitor C2 is connected to the first terminal of the second resistor R2, the second terminal of the second resistor R2 is connected to the first terminal of the second inductor L2, the second terminal of the second inductor L2 is connected to the first terminal of the third inductor L3, the first terminal of the third capacitor C3 and the drain of the first MOS transistor M1, and the source of the first MOS transistor M1 is grounded.

[0043] The second terminal of the third inductor L3 is connected to the first terminal of the tenth capacitor C10, the first terminal of the eleventh capacitor C11, the first terminal of the twelfth capacitor C12, the first terminal of the sixth inductor L6, and the first terminal of the eighth inductor L8, and is connected to the power supply; the second terminals of the tenth capacitor C10, the eleventh capacitor C11, and the twelfth capacitor C12 are all grounded.

[0044] The second terminal of the third capacitor C3 is connected to the first terminal of the fourth inductor L4, the first terminal of the fourth capacitor C4, and the gate of the second MOS transistor M2. The second terminal of the fourth inductor L4 is connected to the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to the first terminal of the eighth capacitor C8 and the second terminal of the first resistor R1. The second terminal of the eighth capacitor C8 is grounded.

[0045] The second terminal of the fourth capacitor C4 is connected to the first terminal of the fourth resistor R4, the second terminal of the fourth resistor R4 is connected to the first terminal of the fifth inductor L5, the second terminal of the fifth inductor L5 is connected to the second terminal of the sixth inductor L6, the drain of the second MOS transistor M2 and the first terminal of the fifth capacitor C5, respectively, and the source of the second MOS transistor M2 is grounded.

[0046] The second terminal of the fifth capacitor C5 is connected to the first terminal of the seventh inductor L7 and the gate of the third MOS transistor M3, and the source of the third MOS transistor M3 is grounded; the second terminal of the seventh inductor L7 is connected to the first terminal of the fifth resistor R5, and the second terminal of the fifth resistor R5 is connected to the first terminal of the seventh capacitor C7 and the second terminal of the first resistor R1, and the second terminal of the seventh capacitor C7 is grounded.

[0047] The drain of the third MOS transistor M3 is connected to the second terminal of the eighth inductor L8 and the first terminal of the sixth capacitor C6, respectively. The second terminal of the sixth capacitor C6 serves as the output terminal of the first emitter channel 2.

[0048] In this embodiment, the circuit structures of the first low-noise amplifier 42 and the second low-noise amplifier 52 are identical. The first low-noise amplifier 42 and the second low-noise amplifier 52 adopt a two-stage common-source structure with source negative feedback current multiplexing, which has the effects of high gain, low power consumption and low noise.

[0049] The first low-noise amplifier 42 includes an input control module 421, an input matching circuit 422, an active bias circuit 423, a fourth MOSFET M4, an interstage matching circuit 424, a fifth MOSFET M5, a power supply bias circuit 425, a stabilization circuit 426, and an output matching circuit 427.

[0050] The input terminal of the input control module 421 serves as the input terminal of the first low-noise amplifier 42. The output terminal of the input control module 421 is connected to the input terminal of the input matching circuit 422. The control unit 7 is used to control the input control module 421 to be turned on or off. The output terminal of the input matching circuit 422 is connected to the first terminal of the active bias circuit 423 and the gate of the fourth MOS transistor M4. The source of the fourth MOS transistor M4 is grounded. The second terminal of the active bias circuit 423 is connected to the first terminal of the power bias circuit 425 and connected to the power supply.

[0051] The drain of the fourth MOS transistor M4 is connected to the input terminal of the interstage matching circuit 424, the output terminal of the interstage matching circuit 424 is connected to the gate of the fifth MOS transistor M5 and the second terminal of the power supply bias circuit 425, and the source of the fifth MOS transistor M5 is grounded.

[0052] The drain of the fifth MOS transistor M5 and the third terminal of the power supply bias circuit 425 are respectively connected to the input terminal of the stabilization circuit 426. The output terminal of the stabilization circuit 426 is connected to the input terminal of the output matching circuit 427. The output terminal of the output matching circuit 427 serves as the output terminal of the first low-noise amplifier.

[0053] The input matching circuit 422 is used to achieve impedance matching; the active bias circuit 423 is used to provide a bias voltage to the gate of the fourth MOSFET M4; the inter-stage matching circuit 424 is used to connect the matching between the fourth MOSFET M4 and the fifth MOSFET M5; the power supply bias circuit 425 is used to provide a bias power supply to the fifth MOSFET M5; the stabilization circuit 426 is used to improve the stability of the first low-noise amplifier. The output matching circuit 427 is used to achieve output impedance matching.

[0054] In this embodiment, the input matching circuit 422 includes a ninth inductor L9, a thirteenth capacitor C13, and a tenth inductor L10. The first terminal of the ninth inductor L9 is connected to the first terminal of the thirteenth capacitor C13 and is connected to the output terminal of the input control module 421. The second terminal of the ninth inductor L9 is grounded, and the second terminal of the thirteenth capacitor C13 serves as the output terminal of the input matching circuit 422. The first terminal of the tenth inductor L10 is connected to the source of the fourth MOS transistor M4, and the second terminal of the tenth inductor L10 is grounded. The input matching circuit 422 primarily affects the noise of the first low-noise amplifier 42. The ninth inductor L9 and the tenth inductor L10 improve impedance matching, and the thirteenth capacitor C13, while participating in matching, also acts as a DC blocking capacitor.

[0055] In this embodiment, the active bias circuit 423 includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a sixth MOSFET M6, a ninth resistor R9, a tenth resistor R10, a first diode, and a second diode.

[0056] The first end of the sixth resistor R6 serves as the first end of the active bias circuit 423. The second end of the sixth resistor R6 is connected to the first ends of the seventh resistor R7 and the eighth resistor R8, respectively. The second end of the seventh resistor R7 is connected to the negative terminal of the second diode and grounded. The positive terminal of the second diode is connected to the negative terminal of the first diode. The positive terminal of the first diode is connected to the first end of the tenth resistor R10 and the gate of the sixth MOS transistor M6, respectively. The source of the sixth MOS transistor M6 is connected to the second end of the eighth resistor R8. The second end of the ninth resistor R9 is connected to the second end of the tenth resistor R10 and serves as the second end of the active bias circuit 423.

[0057] Specifically, the active bias circuit 423 mainly provides gate bias for the fourth MOSFET M4, the seventh resistor R7 and the eighth resistor R8 are mainly used to limit current and make the sixth MOSFET M6 work in the saturation region, the first diode and the second diode are used for voltage regulation, and the ninth resistor R9 and the tenth resistor R10 are used to divide the gate voltage of the sixth MOSFET M6 to make the gate bias at a suitable point.

[0058] In this embodiment, the interstage matching circuit 424 includes an eleventh inductor L11, a fourteenth capacitor C14, and a fifteenth capacitor C15; the source of the fifth MOS transistor M5 is grounded through the fifteenth capacitor C15.

[0059] The first end of the eleventh inductor L11 is connected to the fourteenth capacitor C14 and serves as the input terminal of the interstage matching circuit 424. The second end of the eleventh inductor L11 is connected to the source of the fifth MOS transistor M5. The second end of the fourteenth capacitor C14 serves as the output terminal of the interstage matching circuit 424.

[0060] Specifically, while the eleventh inductor L11 participates in matching, it also supplies the source voltage of the fifth MOSFET M5 to the drain of the fourth MOSFET M4, thereby achieving current reuse and reducing power consumption. While participating in matching, the fourteenth capacitor C14 also separates the drain voltage of the fourth MOSFET M4 and the gate voltage of the fifth MOSFET M5, thus playing a role in DC blocking. While participating in matching, the fifteenth capacitor C15 ensures that the source voltage of the fifth MOSFET M5 is not grounded.

[0061] In this embodiment, the power supply bias circuit 425 includes an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13. The first terminal of the thirteenth resistor R13 serves as the first terminal of the power supply bias circuit 425. The second terminal of the thirteenth resistor R13 is connected to the first terminals of the eleventh resistor R11 and the twelfth resistor R12. The second terminal of the eleventh resistor R11 serves as the second terminal of the power supply bias circuit 425, and the second terminal of the twelfth resistor R12 serves as the third terminal of the power supply bias circuit 425. A simple voltage divider is performed using the eleventh resistor R11, the twelfth resistor R12, and the thirteenth resistor R13 to supply power to the gate and drain of the fifth MOSFET M5, respectively.

[0062] In this embodiment, the stabilizing circuit 426 includes a fourteenth resistor R14 and a sixteenth capacitor C16. The first end of the fourteenth resistor R14 serves as both the input and output of the stabilizing circuit 426, and the second end of the fourteenth resistor R14 is grounded after being connected in series with the sixteenth capacitor C16. The connection between the fourteenth resistor R14 and the sixteenth capacitor C16 and grounding them improves the overall stability of the circuit.

[0063] In this embodiment, the output matching circuit 427 includes a twelfth inductor L12, a seventeenth capacitor C17, and an eighteenth capacitor C18. The first terminal of the twelfth inductor L12 serves as the input terminal of the output matching circuit 427, and the second terminal of the twelfth inductor L12 is connected to the first terminals of the seventeenth capacitor C17 and the eighteenth capacitor C18, respectively. The second terminal of the seventeenth capacitor C17 is grounded, and the second terminal of the eighteenth capacitor C18 serves as the output terminal of the output matching circuit 427. The multi-channel transceiver multifunction chip 100 also includes a nineteenth capacitor C19, the first terminal of which is connected to the power supply, and the second terminal of which is grounded.

[0064] Optionally, the output matching circuit 427 is configured with a T-type structure, and output matching is performed through the output matching circuit 427.

[0065] In this embodiment, the fourth MOSFET M4, the fifth MOSFET M5, and the sixth MOSFET M6 are enhancement-mode pseudo-high electron mobility transistors (E-mode transistors). The nineteenth capacitor C19 is a decoupling capacitor, which is used to filter out power supply noise and stabilize the power supply voltage to ensure that the load receives clean and continuous power.

[0066] In this embodiment, the first bypass circuit 43 and the second bypass circuit 53 have the same circuit structure. The first bypass circuit 43 includes a twentieth capacitor C20, a fifteenth resistor R15, a sixteenth resistor R16, a seventh MOSFET M7, a seventeenth resistor R17, an eighteenth resistor R18, an eighth MOSFET M8, a nineteenth resistor R19, a twentieth resistor R20, a ninth MOSFET M9, a twenty-first capacitor C21, a twenty-second capacitor C22, a twenty-third resistor R23, a twenty-fourth resistor R24, and a twenty-fifth resistor R25. Among them, the seventh MOSFET M7, the eighth MOSFET M8, and the ninth MOSFET M9 are depletion-mode pseudo-high electron mobility transistors (D-mode transistors).

[0067] The first terminal of the twentieth capacitor C20 serves as the input terminal of the first bypass circuit 43. The second terminal of the twentieth capacitor C20 is connected to the first terminal of the fifteenth resistor R15, the first terminal of the sixteenth resistor R16, and the source of the seventh MOS transistor M7. The second terminal of the fifteenth resistor R15 is connected to the first terminal of the seventeenth resistor R17 and the first terminal of the nineteenth resistor R19, and is connected to the power supply.

[0068] The gate of the seventh MOS transistor M7 is connected to the first terminal of the twenty-third resistor R23, the gate of the eighth MOS transistor M8 is connected to the first terminal of the twenty-fourth resistor R24, the gate of the ninth MOS transistor M9 is connected to the first terminal of the twenty-fifth resistor R25, and the second terminals of the twenty-third resistor R23, the twenty-fourth resistor R24, and the twenty-fifth resistor R25 are respectively connected to the control unit 7.

[0069] The drain of the seventh MOSFET M7 is connected to the second terminal of the sixteenth resistor R16, the second terminal of the seventeenth resistor R17, the first terminal of the eighteenth resistor R18, the source of the eighth MOSFET M8, the first terminal of the twentieth resistor R20, and the drain of the ninth MOSFET M9. The source of the ninth MOSFET M9 is connected to the second terminal of the twentieth resistor R20 and the first terminal of the twentieth capacitor C22. The second terminal of the twentieth capacitor C22 is grounded. The second terminal of the eighteenth resistor R18 is connected to the drain of the eighth MOSFET M8, the second terminal of the nineteenth resistor R19, and the first terminal of the twentieth capacitor C21. The second terminal of the twentieth capacitor C21 serves as the output terminal of the first bypass circuit 43.

[0070] Specifically, the first bypass circuit 43 and the second bypass circuit 53, in their respective bypass modes, can ensure that when the input signal is too large, the signal does not pass through the first low-noise amplifier 42 or the second low-noise amplifier 52, thereby protecting the low-noise amplifier from damage and ensuring high safety.

[0071] In this embodiment, the circuit structures of the first filter 45 and the second filter 55 are the same.

[0072] The first filter 45 includes a low-pass filter circuit 451 and a high-pass filter circuit 452 connected in sequence. The low-pass filter circuit 451 includes a 23rd capacitor C23, a 24th capacitor C24, a 25th capacitor C25, a 26th capacitor C26, a 27th capacitor C27, a 28th capacitor C28, a 29th capacitor C29, a 13th inductor L13, a 14th inductor L14, and a 15th inductor L15. The low-pass filter circuit 451 is a seventh-order low-pass filter, and the high-pass filter circuit 452 is a seventh-order high-pass filter. Both filters employ an elliptic function structure to generate multiple transmission zeros in the stopband, enhancing out-of-band rejection and frequency selectivity.

[0073] The first terminal of the 23rd capacitor C23 is connected to the first terminal of the 24th capacitor C24 and the first terminal of the 13th inductor L13, respectively, and serves as the first terminal of the first filter 45. The second terminal of the 24th capacitor is connected to the first terminal of the 25th capacitor C25, the second terminal of the 13th inductor L13, the first terminal of the 26th capacitor C26, and the first terminal of the 14th inductor L14, respectively. The second terminal of the 26th capacitor C26 is connected to the first terminal of the 27th capacitor C27, the second terminal of the 14th inductor L14, the first terminal of the 15th inductor L15, and the first terminal of the 28th capacitor C28, respectively. The second terminal of the 28th capacitor C28 is connected to the second terminal of the 15th inductor L15 and the first terminal of the 29th capacitor C29, respectively. The second terminals of the 23rd capacitor C23, the 25th capacitor C25, the 27th capacitor C27, and the 29th capacitor C29 are grounded, respectively.

[0074] The high-pass filter circuit 452 includes a 30th capacitor C30, a 31st capacitor C31, a 32nd capacitor C32, a 33rd capacitor C33, a 34th capacitor C34, a 35th capacitor C35, a 36th capacitor C36, a 16th inductor L16, a 17th inductor L17, and an 18th inductor L18. The first terminal of the 30th capacitor C30 is connected to the second terminal of the 28th capacitor C28. The second terminal of the 30th capacitor C30 is connected to the first terminals of both the 16th inductor L16 and the 32nd capacitor C32. The second terminal of the 16th inductor L16 is connected in series with... The 31st capacitor C31 is grounded; the second terminal of the 32nd capacitor C32 is connected to the first terminal of the 17th inductor L17 and the first terminal of the 34th capacitor C34, and the second terminal of the 17th inductor L17 is grounded after being connected in series with the 33rd capacitor C33; the second terminal of the 34th capacitor C34 is connected to the first terminal of the 18th inductor L18 and the first terminal of the 36th capacitor C36, and the second terminal of the 36th capacitor C36 serves as the second terminal of the first filter 45; the second terminal of the 18th inductor L18 is grounded after being connected in series with the 35th capacitor C35.

[0075] In this embodiment, the circuit structures of the first single-pole four-throw switch 1 and the second single-pole four-throw switch 6 are the same; the first single-pole four-throw switch 1 includes a first switch unit 11, a second switch unit 12, a third switch unit 13 and a fourth switch unit 14.

[0076] The input terminals of the first switch unit 11, the second switch unit 12, the third switch unit 13, and the fourth switch unit 14 are connected and serve as the input terminals of the first single-pole four-throw switch 1. The output terminals of the first switch unit 11, the second switch unit 12, the third switch unit 13, and the fourth switch unit 14 serve as the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal of the first single-pole four-throw switch 1, respectively. The control unit 7 controls the on or off states of the first switch unit 11, the second switch unit 12, the third switch unit 13, and the fourth switch unit 14, respectively.

[0077] In this embodiment, the circuit structures of the first switching unit 11, the second switching unit 12, the third switching unit 13, and the fourth switching unit 14 are the same. The first switching unit 11 includes a twenty-sixth resistor R26, a twenty-seventh resistor R27, a tenth MOSFET M10, and an eleventh MOSFET M11. The first end of the twenty-seventh resistor R27 is connected to the control unit 7, and the second end of the twenty-seventh resistor R27 is connected to the gate of the tenth MOSFET M10. The drain of the tenth MOSFET M10 serves as the input terminal of the first switching unit 11. The source of the tenth MOSFET M10 is connected to the drain of the eleventh MOSFET M11 and serves as the output terminal of the first switching unit 11. The source of the eleventh MOSFET M11 is grounded, and the gate of the eleventh MOSFET M11 is connected to the first end of the twenty-sixth resistor R26. The second end of the twenty-sixth resistor R26 is connected to the control unit 7.

[0078] In this embodiment, the circuit structures of the first single-pole double-throw switch 41, the second single-pole double-throw switch 44, the third single-pole double-throw switch 51, and the fourth single-pole double-throw switch 54 are the same. The first single-pole double-throw switch 41 includes a fifth switch unit 411 and a sixth switch unit 412; the input terminal of the fifth switch unit 411 is connected to the input terminal of the sixth switch unit 412 and serves as the input terminal of the first single-pole double-throw switch 41; the output terminals of the fifth switch unit 411 and the sixth switch unit 412 serve as the first output terminal and the second output terminal of the first single-pole double-throw switch 41, respectively.

[0079] In this embodiment, the circuit structure of the fifth switch unit 411 and the sixth switch unit 412 is the same; The fifth switching unit 411 includes a 37th capacitor C37, a 38th capacitor C38, a 39th capacitor C39, a 12th MOSFET M12, a 13th MOSFET M13, a 14th MOSFET M14, a 27th resistor R27, a 28th resistor R28, a 29th resistor R29, and a 30th resistor R30.

[0080] The first terminal of the thirty-seventh capacitor C37 serves as the input terminal of the fifth switching unit 411. The second terminal of the thirty-seventh capacitor C37 is connected to the drain of the twelfth MOSFET M12. The source of the twelfth MOSFET M12 is connected to the first terminal of the twenty-ninth resistor R29, the first terminal of the thirty-ninth capacitor C39, and the drain of the thirteenth MOSFET M13, respectively. The gate of the twelfth MOSFET M12 is connected to the first terminal of the thirty-first resistor R31. The source of the thirteenth MOSFET M13 is connected to the first terminal of the thirty-eighth capacitor C38. The second terminal of the thirty-eighth capacitor C38... As the output terminal of the fifth switching unit 411, the gate of the thirteenth MOSFET M13 is connected to the first terminal of the twenty-eighth resistor R28; the second terminal of the twenty-ninth resistor R29 is connected to the second terminal of the thirty-ninth capacitor C39 and the drain of the fourteenth MOSFET M14, respectively; the source of the fourteenth MOSFET M14 is grounded; and the gate of the fourteenth MOSFET M14 is connected to the first terminal of the thirtieth resistor R30; the second terminals of the thirty-first resistor R31, the twenty-eighth resistor R28, and the thirtieth resistor R30 are respectively used to connect to the control unit 7.

[0081] The specific working principle of this embodiment is as follows: When the chip is in transmit mode, the signal comes in from the transmit / receive port, passes through the first single-pole quad-throw switch 1, and has two transmit paths to choose from: the first transmit channel 2 and the second transmit channel 3. After the signal passes through the first transmit channel 2 or the second transmit channel 3, it is transmitted to the antenna port through the second single-pole quad-throw switch 6.

[0082] like Figure 4 As shown, the transmit / receive port is the input terminal of the first single-pole quad-throw switch 1. Each channel first connects a pseudo-high electron mobility transistor (PHMT) in series, and then connects another pseudo-high electron mobility transistor (PHMT) in parallel. A resistor is connected in series with the gate of each transistor, and the voltage controls the gate of each transistor. The first output terminal RFOUT1 of the first single-pole quad-throw switch 1 is connected to the input terminal (RFIN) of the first transmit channel 2. The second output terminal RFOUT2 of the first single-pole quad-throw switch 1 is connected to the input terminal (RFIN) of the second transmit channel 3. The third output terminal RFOUT3 of the first single-pole quad-throw switch 1 is connected to the input terminal (RFIN) of the first single-pole double-throw switch 41. The fourth output terminal RFOUT4 of the first single-pole quad-throw switch 1 is connected to the input terminal (RFIN) of the third single-pole double-throw switch 51. The output terminal (RFOUT) of the first transmit channel 2 is connected to the first output terminal RFOUT1 of the second single-pole quad-throw switch 6, and the output terminal (RFOUT) of the second transmit channel 3 is connected to the second output terminal RFOUT2 of the second single-pole quad-throw switch 6.

[0083] When the chip is in receive mode, the signal enters from the antenna port, passes through the second single-pole quad-throw switch 6, and has two receive paths to choose from. After selecting one of them, the useful signal is filtered out by the first filter 45 or the second filter 55 and then passes through the second single-pole double-throw switch 44 or the fourth single-pole double-throw switch 54. There are two modes to choose from: amplification mode and bypass mode. After selecting one of the paths, the signal passes through the first single-pole double-throw switch 41 or the third single-pole double-throw switch 51 to the first single-pole quad-throw switch 1 and then to the transceiver port.

[0084] The input terminal RFIN of the second single-pole four-throw switch 6 is the antenna port. The third output terminal RFOUT3 of the second single-pole four-throw switch 6 is connected to the RFIN of the low-pass filter circuit 451, and the fourth output terminal RFOUT4 of the second single-pole four-throw switch 6 is connected to the RFIN of the high-pass filter circuit 452. The RFOUT of the low-pass filter circuit 451 is connected to the RFIN of the second single-pole double-throw switch 44. The RFOUT of the high-pass filter circuit 452 is connected to the RFIN of the fourth single-pole double-throw switch 54. The RFOUT1 of the second single-pole double-throw switch 44 is connected to the RFIN of the first low-noise amplifier 42 (LNA1). The RFOUT2 of the second single-pole double-throw switch 44 is connected to the RFIN of the first bypass circuit 43. The RFOUT1 of the fourth single-pole double-throw switch 54 is connected to the RFIN of the second low-noise amplifier 52 (LNA2). The RFOUT2 of the fourth single-pole double-throw switch 54 is connected to the RFIN of the second bypass circuit 53. The RFOUT of the first low-noise amplifier 42 is connected to the RFOUT1 of the first single-pole double-throw switch 41. The RFOUT of the first bypass circuit 43 is connected to the RFOUT2 of the first single-pole double-throw switch 41. The RFOUT of the second low-noise amplifier 52 is connected to the RFOUT1 of the third single-pole double-throw switch 51. The RFOUT of the second bypass circuit 53 is connected to the RFOUT2 of the third single-pole double-throw switch 51. By using the gallium arsenide phemet 0.25um process to integrate the above components onto the same chip, the integration density is improved, the cost is reduced, the output power is higher, the linearity is better and the noise is better. At the same time, the integration of multiple frequency bands and multiple channels within the chip makes the chip more widely applicable.

[0085] It should be noted that the various embodiments described above with reference to the accompanying drawings are merely illustrative of the present invention and not intended to limit its scope. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from its spirit and scope should be included within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include those in the plural, and vice versa. Additionally, unless specifically stated otherwise, all or part of any embodiment may be used in conjunction with all or part of any other embodiment.

Claims

1. A multi-channel transceiver chip, characterized in that, The multi-channel transceiver chip includes a chip, a first single-pole four-throw switch, a first transmitting channel, a second transmitting channel, a first receiving channel, a second receiving channel, and a second single-pole four-throw switch, all integrated into the chip. The input terminal of the first single-pole four-throw switch is used to connect to the transceiver port. The first output terminal of the first single-pole four-throw switch is connected to the input terminal of the first transmitting channel. The second output terminal of the first single-pole four-throw switch is connected to the input terminal of the second transmitting channel. The output terminal of the first transmitting channel is connected to the first output terminal of the second single-pole four-throw switch. The output terminal of the second transmitting channel is connected to the second output terminal of the second single-pole four-throw switch. The first transmitting channel and the second transmitting channel are used to amplify the power of the signals passing through their paths. The third output terminal of the first single-pole four-throw switch is connected to the output terminal of the first receiving channel, the fourth output terminal of the first single-pole four-throw switch is connected to the output terminal of the second receiving channel, the input terminal of the first receiving channel and the input terminal of the second receiving channel are respectively connected to the third output terminal and the fourth output terminal of the second single-pole four-throw switch, and the input terminal of the second single-pole four-throw switch is used to connect to the antenna port. The first transmitting channel, the second transmitting channel, the first receiving channel, and the second receiving channel are all controlled by an external control unit; The control unit is configured to output a first logic control signal, a second logic control signal, a third logic control signal, a fourth logic control signal, a fifth logic control signal, a sixth logic control signal, a seventh logic control signal, and an eighth logic control signal; wherein the second logic control signal is the inverse logic of the first logic control signal, the fourth logic control signal is the inverse logic of the third logic control signal, the sixth logic control signal is the inverse logic of the fifth logic control signal, and the eighth logic control signal is the inverse logic of the seventh logic control signal; The first logic control signal and the second logic control signal are used to jointly control the conduction of the first transmission channel, and the third logic control signal and the fourth logic control signal are used to jointly control the conduction of the second transmission channel; The fifth and sixth logic control signals are used to jointly control the conduction of the first receiving channel; the seventh and eighth logic control signals are used to jointly control the conduction of the second receiving channel. When one of the first transmitting channel, the second transmitting channel, the first receiving channel, and the second receiving channel is in the on state, the other three channels are in the off state.

2. The multi-channel transceiver chip according to claim 1, characterized in that, The first receiving channel includes a first single-pole double-throw switch, a first low-noise amplifier, a first bypass circuit, a second single-pole double-throw switch, and a first filter; The control unit is also used to output a ninth logic control signal, a tenth logic control signal, an eleventh logic control signal, and a twelfth logic control signal; wherein the tenth logic control signal is the inverse logic of the ninth logic control signal, and the twelfth logic control signal is the inverse logic of the eleventh logic control signal; The first terminal of the first filter serves as the input terminal of the first receiving channel. The second terminal of the first filter is connected to the input terminal of the second single-pole double-throw switch. The first output terminal of the second single-pole double-throw switch is connected to the input terminal of the first low-noise amplifier. The second output terminal of the second single-pole double-throw switch is connected to the input terminal of the first bypass circuit. The output terminal of the first low-noise amplifier is connected to the first output terminal of the first single-pole double-throw switch. The output terminal of the first bypass circuit is connected to the second output terminal of the first single-pole double-throw switch. The input terminal of the first single-pole double-throw switch serves as the output terminal of the first receiving channel. When the ninth logic control signal outputs a high level and the tenth logic control signal outputs a low level, the first low-noise amplifier is turned on, and the first bypass circuit is turned off. When the ninth logic control signal outputs a low level and the tenth logic control signal outputs a high level, the first low-noise amplifier is turned off, and the first bypass circuit is turned on. The second receiving channel includes a third single-pole double-throw switch, a second low-noise amplifier, a second bypass circuit, a fourth single-pole double-throw switch, and a second filter; The first terminal of the second filter serves as the input terminal of the second receiving channel. The second terminal of the second filter is connected to the input terminal of the fourth single-pole double-throw switch. The first output terminal of the fourth single-pole double-throw switch is connected to the input terminal of the second low-noise amplifier. The second output terminal of the fourth single-pole double-throw switch is connected to the input terminal of the second bypass circuit. The output terminal of the second low-noise amplifier is connected to the first output terminal of the third single-pole double-throw switch. The output terminal of the second bypass circuit is connected to the second output terminal of the third single-pole double-throw switch. The input terminal of the third single-pole double-throw switch serves as the output terminal of the second receiving channel. When the eleventh logic control signal outputs a high level and the twelfth logic control signal outputs a low level, the second low-noise amplifier is turned on, and the second bypass circuit is turned off. When the eleventh logic control signal outputs a low level and the twelfth logic control signal outputs a high level, the second low-noise amplifier is turned off, and the second bypass circuit is turned on.

3. The multi-channel transceiver multifunction chip according to claim 1, characterized in that, The first transmission channel and the second transmission channel have the same circuit structure; The first transmission channel includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a sixth inductor, a seventh inductor, an eighth inductor, a first MOSFET, a second MOSFET, and a third MOSFET; The first terminal of the first capacitor serves as the input terminal of the first transmission channel. The second terminal of the first capacitor is connected to the first terminal of the first inductor, the gate of the first MOS transistor, and the first terminal of the second capacitor. The second terminal of the first inductor is connected to the first terminal of the first resistor, the second terminal of the first resistor is connected to the first terminal of the ninth capacitor, and the second terminal of the ninth capacitor is grounded. The second terminal of the second capacitor is connected to the first terminal of the second resistor, the second terminal of the second resistor is connected to the first terminal of the second inductor, the second terminal of the second inductor is connected to the first terminal of the third inductor, the first terminal of the third capacitor and the drain of the first MOS transistor, and the source of the first MOS transistor is grounded. The second terminal of the third inductor is connected to the first terminal of the tenth capacitor, the first terminal of the eleventh capacitor, the first terminal of the twelfth capacitor, the first terminal of the sixth inductor, and the first terminal of the eighth inductor, and is connected to the power supply; the second terminals of the tenth capacitor, the eleventh capacitor, and the twelfth capacitor are all grounded. The second terminal of the third capacitor is connected to the first terminal of the fourth inductor, the first terminal of the fourth capacitor, and the gate of the second MOS transistor. The second terminal of the fourth inductor is connected to the first terminal of the third resistor. The second terminal of the third resistor is connected to the first terminal of the eighth capacitor and the second terminal of the first resistor. The second terminal of the eighth capacitor is grounded. The second terminal of the fourth capacitor is connected to the first terminal of the fourth resistor, the second terminal of the fourth resistor is connected to the first terminal of the fifth inductor, the second terminal of the fifth inductor is connected to the second terminal of the sixth inductor, the drain of the second MOS transistor, and the first terminal of the fifth capacitor, respectively, and the source of the second MOS transistor is grounded. The second terminal of the fifth capacitor is connected to the first terminal of the seventh inductor and the gate of the third MOS transistor, and the source of the third MOS transistor is grounded; the second terminal of the seventh inductor is connected to the first terminal of the fifth resistor, the second terminal of the fifth resistor is connected to the first terminal of the seventh capacitor and the second terminal of the first resistor, and the second terminal of the seventh capacitor is grounded; The drain of the third MOS transistor is connected to the second terminal of the eighth inductor and the first terminal of the sixth capacitor, respectively. The second terminal of the sixth capacitor serves as the output terminal of the first emitter channel.

4. The multi-channel transceiver multifunction chip according to claim 2, characterized in that, The first low-noise amplifier and the second low-noise amplifier have the same circuit structure; The first low-noise amplifier includes an input control module, an input matching circuit, an active bias circuit, a fourth MOSFET, an interstage matching circuit, a fifth MOSFET, a power supply bias circuit, a stabilization circuit, and an output matching circuit. The input terminal of the input control module serves as the input terminal of the first low-noise amplifier. The output terminal of the input control module is connected to the input terminal of the input matching circuit. The control unit is used to control the input control module to be turned on or off. The output terminal of the input matching circuit is connected to the first terminal of the active bias circuit and the gate of the fourth MOS transistor. The source of the fourth MOS transistor is grounded. The second terminal of the active bias circuit is connected to the first terminal of the power bias circuit and connected to the power supply. The drain of the fourth MOS transistor is connected to the input terminal of the interstage matching circuit, the output terminal of the interstage matching circuit is connected to the gate of the fifth MOS transistor and the second terminal of the power supply bias circuit, and the source of the fifth MOS transistor is grounded. The drain of the fifth MOS transistor and the third terminal of the power supply bias circuit are respectively connected to the input terminal of the stabilization circuit, the output terminal of the stabilization circuit is connected to the input terminal of the output matching circuit, and the output terminal of the output matching circuit serves as the output terminal of the first low-noise amplifier. The input matching circuit is used to achieve impedance matching; The active bias circuit is used to provide a bias voltage for the gate of the fourth MOS transistor; The interstage matching circuit is used to connect the matching between the fourth MOS transistor and the fifth MOS transistor; The power bias circuit is used to provide bias power to the fifth MOS transistor; The stabilization circuit is used to improve the stability of the first low-noise amplifier; The output matching circuit is used to achieve output impedance matching.

5. The multi-channel transceiver multifunction chip according to claim 4, characterized in that, The input matching circuit includes a ninth inductor, a thirteenth capacitor, and a tenth inductor; the first end of the ninth inductor is connected to the first end of the thirteenth capacitor and connected to the output terminal of the input control module, the second end of the ninth inductor is grounded, the second end of the thirteenth capacitor serves as the output terminal of the input matching circuit, the first end of the tenth inductor is connected to the source of the fourth MOS transistor, and the second end of the tenth inductor is grounded.

6. The multi-channel transceiver multifunction chip according to claim 4, characterized in that, The active bias circuit includes a sixth resistor, a seventh resistor, an eighth resistor, a sixth MOSFET, a ninth resistor, a tenth resistor, a first diode, and a second diode; The first end of the sixth resistor serves as the first end of the active bias circuit. The second end of the sixth resistor is connected to the first end of the seventh resistor and the first end of the eighth resistor. The second end of the seventh resistor is connected to the negative terminal of the second diode and grounded. The positive terminal of the second diode is connected to the negative terminal of the first diode. The positive terminal of the first diode is connected to the first end of the tenth resistor and the gate of the sixth MOS transistor. The source of the sixth MOS transistor is connected to the second end of the eighth resistor. The second end of the ninth resistor is connected to the second end of the tenth resistor and serves as the second end of the active bias circuit.

7. The multi-channel transceiver multifunction chip according to claim 4, characterized in that, The interstage matching circuit includes an eleventh inductor, a fourteenth capacitor, and a fifteenth capacitor, and the source of the fifth MOS transistor is grounded through the fifteenth capacitor; The first end of the eleventh inductor is connected to the fourteenth capacitor and serves as the input terminal of the interstage matching circuit. The second end of the eleventh inductor is connected to the source of the fifth MOS transistor. The second end of the fourteenth capacitor serves as the output terminal of the interstage matching circuit.

8. The multi-channel transceiver multifunction chip according to claim 4, characterized in that, The power supply bias circuit includes an eleventh resistor, a twelfth resistor, and a thirteenth resistor; The first end of the thirteenth resistor serves as the first end of the power supply bias circuit. The second end of the thirteenth resistor is connected to the first end of the eleventh resistor and the first end of the twelfth resistor. The second end of the eleventh resistor serves as the second end of the power supply bias circuit, and the second end of the twelfth resistor serves as the third end of the power supply bias circuit.

9. The multi-channel transceiver multifunction chip according to claim 4, characterized in that, The stabilizing circuit includes a fourteenth resistor and a sixteenth capacitor; the first end of the fourteenth resistor serves as both the input and output of the stabilizing circuit, and the second end of the fourteenth resistor is grounded after being connected in series with the sixteenth capacitor.

10. The multi-channel transceiver multifunction chip according to claim 4, characterized in that, The output matching circuit includes a twelfth inductor, a seventeenth capacitor, and an eighteenth capacitor; The first terminal of the twelfth inductor serves as the input terminal of the output matching circuit. The second terminal of the twelfth inductor is connected to the first terminal of the seventeenth capacitor and the first terminal of the eighteenth capacitor. The second terminal of the seventeenth capacitor is grounded, and the second terminal of the eighteenth capacitor serves as the output terminal of the output matching circuit. The multi-channel transceiver chip also includes a nineteenth capacitor, the first end of which is connected to the power supply, and the second end of which is grounded.

11. The multi-channel transceiver multifunction chip according to claim 2, characterized in that, The first bypass circuit and the second bypass circuit have the same circuit structure; The first bypass circuit includes a twentieth capacitor, a fifteenth resistor, a sixteenth resistor, a seventh MOSFET, a seventeenth resistor, an eighteenth resistor, an eighth MOSFET, a nineteenth resistor, a twentieth resistor, a ninth MOSFET, a twenty-first capacitor, a twenty-second capacitor, a twenty-third resistor, a twenty-fourth resistor, and a twenty-fifth resistor; The first terminal of the twentieth capacitor serves as the input terminal of the first bypass circuit. The second terminal of the twentieth capacitor is connected to the first terminal of the fifteenth resistor, the first terminal of the sixteenth resistor, and the source of the seventh MOS transistor. The second terminal of the fifteenth resistor is connected to the first terminal of the seventeenth resistor and the first terminal of the nineteenth resistor, and is connected to the power supply. The gate of the seventh MOS transistor is connected to the first terminal of the twenty-third resistor, the gate of the eighth MOS transistor is connected to the first terminal of the twenty-fourth resistor, the gate of the ninth MOS transistor is connected to the first terminal of the twenty-fifth resistor, and the second terminals of the twenty-third, twenty-fourth, and twenty-fifth resistors are respectively connected to the control unit. The drain of the seventh MOS transistor is connected to the second terminal of the sixteenth resistor, the second terminal of the seventeenth resistor, the first terminal of the eighteenth resistor, the source of the eighth MOS transistor, the first terminal of the twentieth resistor, and the drain of the ninth MOS transistor. The source of the ninth MOS transistor is connected to the second terminal of the twentieth resistor and the first terminal of the twentieth capacitor. The second terminal of the twentieth capacitor is grounded. The second terminal of the eighteenth resistor is connected to the drain of the eighth MOS transistor, the second terminal of the nineteenth resistor, and the first terminal of the twentieth capacitor. The second terminal of the twentieth capacitor serves as the output terminal of the first bypass circuit.

12. The multi-channel transceiver multifunction chip according to claim 2, characterized in that, The first filter and the second filter have the same circuit structure; The first filter includes a low-pass filter circuit and a high-pass filter circuit that are electrically connected in sequence; The low-pass filter circuit includes capacitors numbered twenty-third, twenty-fourth, twenty-fifth, twenty-sixth, twenty-seventh, twenty-eighth, and twenty-ninth, as well as inductors numbered thirteenth, fourteenth, and fifteenth. The first terminal of the 23rd capacitor is connected to the first terminal of the 24th capacitor and the first terminal of the 13th inductor, respectively, and serves as the first terminal of the first filter. The second terminal of the 24th capacitor is connected to the first terminal of the 25th capacitor, the second terminal of the 13th inductor, the first terminal of the 26th capacitor, and the first terminal of the 14th inductor, respectively. The second terminal of the 26th capacitor is connected to the first terminal of the 27th capacitor, the second terminal of the 14th inductor, the first terminal of the 15th inductor, and the first terminal of the 28th capacitor, respectively. The second terminal of the 28th capacitor is connected to the second terminal of the 15th inductor and the first terminal of the 29th capacitor, respectively. The second terminals of the 23rd capacitor, the 25th capacitor, the 27th capacitor, and the 29th capacitor are grounded, respectively. The high-pass filter circuit includes a 30th capacitor, a 31st capacitor, a 32nd capacitor, a 33rd capacitor, a 34th capacitor, a 35th capacitor, a 36th capacitor, a 16th inductor, a 17th inductor, and an 18th inductor. The first terminal of the thirtieth capacitor is connected to the second terminal of the twenty-eighth capacitor. The second terminal of the thirtieth capacitor is connected to the first terminals of the sixteenth inductor and the thirty-second capacitor. The second terminal of the sixteenth inductor is grounded after being connected in series with the thirty-first capacitor. The second terminal of the thirty-second capacitor is connected to the first terminals of the seventeenth inductor and the thirty-fourth capacitor. The second terminal of the seventeenth inductor is grounded after being connected in series with the thirty-third capacitor. The second terminal of the thirty-fourth capacitor is connected to the first terminals of the eighteenth inductor and the thirty-sixth capacitor. The second terminal of the thirty-sixth capacitor serves as the second terminal of the first filter. The second terminal of the eighteenth inductor is grounded after being connected in series with the thirty-fifth capacitor.

13. The multi-channel transceiver multifunction chip according to claim 1, characterized in that, The first single-pole four-throw switch and the second single-pole four-throw switch have the same circuit structure; The first single-pole four-throw switch includes a first switching unit, a second switching unit, a third switching unit, and a fourth switching unit; The input terminals of the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit are connected and serve as the input terminals of the first single-pole four-throw switch. The output terminals of the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit serve as the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal of the first single-pole four-throw switch, respectively. The control unit controls the on or off states of the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit, respectively.

14. The multi-channel transceiver multifunction chip according to claim 13, characterized in that, The circuit structures of the first switching unit, the second switching unit, the third switching unit, and the fourth switching unit are the same; The first switching unit includes a twenty-sixth resistor, a twenty-seventh resistor, a tenth MOSFET, and an eleventh MOSFET; The first end of the 27th resistor is connected to the control unit, the second end of the 27th resistor is connected to the gate of the 10th MOS transistor, the drain of the 10th MOS transistor serves as the input terminal of the first switching unit, the source of the 10th MOS transistor is connected to the drain of the 11th MOS transistor and serves as the output terminal of the first switching unit, the source of the 11th MOS transistor is grounded, the gate of the 11th MOS transistor is connected to the first end of the 26th resistor, and the second end of the 26th resistor is connected to the control unit.

15. The multi-channel transceiver multifunction chip according to claim 2, characterized in that, The first single-pole double-throw switch, the second single-pole double-throw switch, the third single-pole double-throw switch and the fourth single-pole double-throw switch have the same circuit structure; The first single-pole double-throw switch includes a fifth switching unit and a sixth switching unit; The input terminal of the fifth switch unit is connected to the input terminal of the sixth switch unit and serves as the input terminal of the first single-pole double-throw switch. The output terminals of the fifth switch unit and the sixth switch unit serve as the first output terminal and the second output terminal of the first single-pole double-throw switch, respectively.

16. The multi-channel transceiver multifunction chip according to claim 15, characterized in that, The fifth switching unit has the same circuit structure as the sixth switching unit; The fifth switching unit includes a thirty-seventh capacitor, a thirty-eighth capacitor, a thirty-ninth capacitor, a twelfth MOSFET, a thirteenth MOSFET, a fourteenth MOSFET, a twenty-eighth resistor, a twenty-ninth resistor, a thirtieth resistor, and a thirty-first resistor; The first terminal of the thirty-seventh capacitor serves as the input terminal of the fifth switching unit. The second terminal of the thirty-seventh capacitor is connected to the drain of the twelfth MOS transistor. The source of the twelfth MOS transistor is connected to the first terminal of the twenty-ninth resistor, the first terminal of the thirty-ninth capacitor, and the drain of the thirteenth MOS transistor, respectively. The gate of the twelfth MOS transistor is connected to the first terminal of the thirty-first resistor. The source of the thirteenth MOS transistor is connected to the first terminal of the thirty-eighth capacitor. The second terminal of the thirty-eighth capacitor serves as the output terminal of the fifth switching unit. The gate of the thirteenth MOS transistor is connected to the first terminal of the twenty-eighth resistor. The second terminal of the twenty-ninth resistor is connected to the second terminal of the thirty-ninth capacitor and the drain of the fourteenth MOS transistor, respectively. The source of the fourteenth MOS transistor is grounded. The gate of the fourteenth MOS transistor is connected to the first terminal of the thirtieth resistor. The second terminals of the thirty-first resistor, the twenty-eighth resistor, and the thirtieth resistor are respectively used to connect to the control unit.

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