Voltage-time conversion circuit, analog-to-digital converter, chip and electronic device

Abstract

The application belongs to the field of electronic circuits, and provides a voltage-time conversion circuit, an analog-to-digital converter, a chip and an electronic device. The circuit comprises a sampling module, a linear voltage reduction module, a charging module, an acceleration module and a comparison module, the linear voltage reduction module is connected with the sampling module, the charging module, the acceleration module and the comparison module respectively, and the acceleration module is connected with the charging module and the comparison module respectively. The application introduces a linear voltage reduction stage between a sampling stage and a conversion stage: linear voltage reduction is performed on a sampling signal, so that the charging module, the acceleration module and the comparison module all work in a saturation region under full-swing input from rail to rail, the circuit has high linearity; meanwhile, the acceleration module is introduced in the conversion stage, so that "useless time" in the charging process of the input signal is greatly shortened, and the circuit enters a target conversion interval more quickly. Therefore, the voltage-time conversion circuit provided by the application can realize high voltage-time conversion speed and linearity when realizing high input swing.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a voltage-time conversion circuit, an analog-to-digital converter, a chip, and an electronic device. Background Technology

[0002] With advancements in semiconductor technology and the continuous reduction of power supply voltage, the design difficulty of traditional voltage-domain analog-to-digital converters (ADCs) is increasing, and the challenges they face are becoming more significant. In recent years, the approach of signal processing based on the time domain has gradually developed. Time-domain ADCs are mainly digital circuits, which have the advantages of simple circuit structure and small chip area, and can achieve ultra-high-speed and high-efficiency transmission in medium-resolution applications.

[0003] A time-domain analog-to-digital converter (ADC) consists of two main circuit parts: a voltage-to-time converter and a time-to-digital converter. First, the voltage-to-time converter converts the sampled voltage signal into a differential time signal; then, the time-to-digital converter quantizes the time difference between the two time signals to obtain the final digital output code value.

[0004] As the pre-amplifier input module of a time-domain analog-to-digital converter (ADC), the performance of the voltage-to-time converter (VTO) significantly impacts the overall performance of the ADC. The input swing, linearity, and conversion speed of a VTO are interdependent. Generally, a smaller input swing results in higher linearity for the voltage-to-time conversion. However, with a fixed ADC range, an excessively small input swing reduces the voltage-to-time conversion speed and the signal-to-noise ratio (SNR) of the ADC, making it difficult to meet the high-speed, medium-to-high-precision quantization requirements of ADCs. Increasing the input swing while achieving higher voltage-to-time conversion speed and linearity remains a design challenge for VTOs. Summary of the Invention

[0005] This application provides a voltage-time conversion circuit, an analog-to-digital converter, a chip, and an electronic device, which can solve the problem that existing voltage-time converters cannot simultaneously achieve high input swing, high linearity, and high voltage-time conversion speed.

[0006] In a first aspect, embodiments of this application provide a voltage-time conversion circuit, including a sampling module, a linear buck module, a charging module, an acceleration module, and a comparison module. The linear buck module is connected to the sampling module, the charging module, the acceleration module, and the comparison module, respectively. The acceleration module is connected to the charging module and the comparison module, respectively. The sampling module is used to receive a first clock signal, the linear buck module is used to receive a second clock signal, and both the charging module and the acceleration module are used to receive a third clock signal. When the first clock signal is high, the second clock signal is low, and the third clock signal is high, the sampling module is used to sample the input signal to obtain the sampled signal. When the first clock signal is low, the second clock signal is high, and the third clock signal is high, the sampling module stops sampling; the linear buck module is used to linearly buck the sampled signal to obtain the first signal. When the first clock signal is low, the second clock signal is high, and the third clock signal is low, the sampling module stops sampling; the linear buck module continues to output the first signal; the charging module outputs a first charging current and mirrors the first charging current to the acceleration module; the acceleration module outputs a second charging current based on the first time signal, the second time signal, and the mirrored first charging current; the first charging current and the second charging current jointly charge the first signal; the comparison module outputs a first time signal and a second time signal based on the threshold voltage and the first signal; when the first time signal or the second time signal flips to a high level, the acceleration module stops working, and the charging module continues working until both the first time signal and the second time signal flip to a high level.

[0007] In one possible implementation of the first aspect, the sampling module includes a first sampling unit and a second sampling unit; the linear buck module includes a first linear buck unit and a second linear buck unit; the charging module includes a first charging unit and a second charging unit; the acceleration module includes a first acceleration unit and a second acceleration unit; and the comparison module includes a first comparison unit and a second comparison unit. The first linear buck unit is connected to the first sampling unit, the first charging unit, the first acceleration unit, and the first comparison unit, respectively. The second linear buck unit is connected to the second sampling unit, the second charging unit, the second acceleration unit, and the second comparison unit, respectively. The first comparison unit is connected to the first acceleration unit and the second acceleration unit, respectively. The second comparison unit is connected to the first acceleration unit and the second acceleration unit, respectively. The unit and the second acceleration unit are connected; the first acceleration unit is connected to the first charging unit; the second acceleration unit is connected to the second charging unit; both the first sampling unit and the second sampling unit are used to receive a first clock signal; both the first linear buck unit and the second linear buck unit are used to receive a second clock signal; and the first charging unit, the second charging unit, the first acceleration unit, and the second acceleration unit are all used to receive a third clock signal; the input signal includes a first input sub-signal and a second input sub-signal; the first signal includes a first sub-signal and a second sub-signal; the sampling signal includes a first sampling sub-signal and a second sampling sub-signal; the first charging current includes a first charging sub-current and a second charging sub-current; and the second charging current includes a third charging sub-current and a fourth charging sub-current. When the first clock signal is high, the second clock signal is low, and the third clock signal is high, the first sampling unit is used to sample the first input sub-signal to obtain the first sampled sub-signal; the second sampling unit is used to sample the second input sub-signal to obtain the second sampled sub-signal. When the first clock signal is low, the second clock signal is high, and the third clock signal is high, the first sampling unit and the second sampling unit stop sampling; the first linear buck unit is used to linearly buck the first sampled sub-signal to obtain the first sub-signal; the second linear buck unit is used to linearly buck the second sampled sub-signal to obtain the second sub-signal; When the first clock signal is low, the second clock signal is high, and the third clock signal is low, the first sampling unit and the second sampling unit stop sampling; the first linear buck unit continues to output the first sub-signal; the second linear buck unit continues to output the second sub-signal; the first charging unit outputs the first charging sub-current and mirrors the first charging sub-current to the first accelerating unit; the second charging unit outputs the second charging sub-current and mirrors the second charging sub-current to the second accelerating unit; the first accelerating unit outputs the third charging sub-current based on the first time signal, the second time signal, and the mirrored first charging sub-current; the second accelerating unit outputs the third charging sub-current based on the first time signal, the second time signal, and the mirrored first charging sub-current; the second accelerating unit outputs the third charging sub-current based on the first time signal, the second time signal, and the mirrored first charging sub-current. The first charging current is output from the second charging current, the second time signal, and the mirrored second charging current; the first charging current and the third charging current jointly charge the first sub-signal; the second charging current and the fourth charging current jointly charge the second sub-signal; the first comparison unit is used to output a first time signal based on the threshold voltage and the first sub-signal; the second comparison unit is used to output a second time signal based on the threshold voltage and the second sub-signal; when the first time signal or the second time signal flips to a high level, the first acceleration unit and the second acceleration unit stop working, and the first charging unit and the second charging unit continue working until both the first time signal and the second time signal flip to a high level.

[0008] In one possible implementation of the first aspect, the first acceleration unit includes a first transistor, a second transistor, a third transistor, and a first OR gate. The gate of the first transistor is connected to the first charging unit, the source of the first transistor receives a power supply voltage, the drain of the first transistor is connected to the source of the second transistor, the gate of the second transistor receives a first bias voltage, the drain of the second transistor is connected to the source of the third transistor, the gate of the third transistor is connected to the output of the first OR gate, the drain of the third transistor is connected to the first linear buck unit, the first charging unit, and the first comparator unit, respectively. The first input of the first OR gate is used to receive a third clock signal, the second input of the first OR gate is connected to the first comparator unit and the second acceleration unit, respectively, and the third input of the first OR gate is connected to the second comparator unit and the second acceleration unit, respectively.

[0009] In one possible implementation of the first aspect, the first sampling unit includes a first switch and a first capacitor. A first terminal of the first switch is used to receive a first input sub-signal. A second terminal of the first switch is connected to the upper plate of the first capacitor and the first linear buck unit, respectively. A control terminal of the first switch is used to receive a first clock signal. The lower plate of the first capacitor is grounded.

[0010] In one possible implementation of the first aspect, the first linear buck unit includes a second switch and a second capacitor. The first terminal of the second switch is connected to the first sampling unit, and the second terminal of the second switch is connected to the upper plate of the second capacitor, the first charging unit, the first acceleration unit, and the first comparison unit, respectively. The control terminal of the second switch is used to receive a second clock signal, and the lower plate of the second capacitor is grounded.

[0011] In one possible implementation of the first aspect, the first charging unit includes a fourth transistor, a fifth transistor, and a sixth transistor. The gate of the fourth transistor is connected to the drain of the fifth transistor, the source of the sixth transistor, and the first acceleration unit, respectively. The source of the fourth transistor receives a power supply voltage, the drain of the fourth transistor is connected to the source of the fifth transistor, the gate of the fifth transistor receives a first bias voltage, the gate of the sixth transistor is used to receive a third clock signal, and the drain of the sixth transistor is connected to the first linear buck unit, the first acceleration unit, and the first comparator unit, respectively.

[0012] In one possible implementation of the first aspect, the first comparison unit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor. The sources of the seventh transistor, the fifteenth transistor, the sixteenth transistor, and the seventeenth transistor all receive a power supply voltage. The gate of the seventh transistor receives a second bias voltage. The drain of the seventh transistor is connected to the source of the eighth transistor. The drain of the eighth transistor is connected to the sources of the ninth transistor and the eleventh transistor, respectively. The gate of the ninth transistor is connected to the first linear buck unit, the first charging unit, and the first acceleration unit, respectively. The gate of the eleventh transistor receives a threshold voltage. The drain of the transistor is connected to the drain of the tenth transistor, the gate of the tenth transistor, and the gate of the thirteenth transistor, respectively. The drain of the eleventh transistor is connected to the drain of the twelfth transistor, the gate of the twelfth transistor, and the gate of the fourteenth transistor, respectively. The drain of the thirteenth transistor is connected to the drain of the fifteenth transistor, the gate of the fifteenth transistor, and the gate of the sixteenth transistor, respectively. The drain of the sixteenth transistor is connected to the drain of the fourteenth transistor, the gate of the seventeenth transistor, and the gate of the eighteenth transistor, respectively. The drain of the seventeenth transistor is connected to the drain of the eighteenth transistor, the first acceleration unit, and the second acceleration unit, respectively. The sources of the tenth transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, and the eighteenth transistor are all grounded.

[0013] Secondly, embodiments of this application provide an analog-to-digital converter, including the voltage-time conversion circuit described in any one of the first aspects.

[0014] Thirdly, embodiments of this application provide a chip including the analog-to-digital converter described in any one of the second aspects.

[0015] Fourthly, embodiments of this application provide an electronic device including the chip described in any one of the third aspects.

[0016] The beneficial effects of the embodiments in this application compared with the prior art are: This application provides a voltage-to-time conversion circuit, including a sampling module, a linear buck module, a charging module, an acceleration module, and a comparison module. The linear buck module is connected to the sampling module, the charging module, the acceleration module, and the comparison module, respectively. The acceleration module is connected to the charging module and the comparison module, respectively. The sampling module is used to receive a first clock signal, the linear buck module is used to receive a second clock signal, and both the charging module and the acceleration module are used to receive a third clock signal.

[0017] When the first clock signal is high, the second clock signal is low, and the third clock signal is high, this stage is the sampling stage. The sampling module is used to sample the input signal to obtain the sampled signal. At this time, the linear buck module, charging module, acceleration module, and comparison module are not working.

[0018] When the first clock signal is low, the second clock signal is high, and the third clock signal is high, this stage is the linear buck stage, and the sampling module stops sampling. The linear buck module is used to linearly buck the sampled signal to obtain the first signal. At this time, the charging module, acceleration module, and comparison module are not working. When the first clock signal is low, the second clock signal is high, and the third clock signal is low, this stage is the conversion stage, and the sampling module stops sampling; the linear buck module continues to output the first signal; the charging module outputs the first charging current and mirrors the first charging current to the acceleration module; the acceleration module outputs the second charging current based on the first time signal, the second time signal, and the mirrored first charging current; the first charging current and the second charging current together charge the first signal, enabling the first signal to charge at a faster rate; the comparison module outputs the first time signal and the second time signal based on the threshold voltage and the first signal. When either the first time signal or the second time signal flips to a high level, the acceleration module stops working, and the charging module continues working until both the first time signal and the second time signal flip to a high level.

[0019] As can be seen from the above, this application introduces a linear buck phase between the sampling and conversion phases. In this phase, the sampled signal output from the sampling phase is linearly bucked. This ensures that even with a full-swing input from rail to rail, the charging module, acceleration module, and comparator module all operate in the saturation region, resulting in high linearity. Simultaneously, the introduction of the acceleration module in the conversion phase significantly reduces the "useless time" during the input signal charging process, allowing the circuit to enter the target conversion range more quickly. Therefore, the voltage-time conversion circuit provided by this application can achieve high voltage-time conversion speed and linearity even with a high input swing.

[0020] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is the schematic diagram of a time-domain analog-to-digital converter; Figure 2 This is a schematic diagram of the circuit structure of an existing voltage-time converter; Figure 3 This is a schematic diagram of the operation of an existing voltage-time converter; Figure 4 This is a schematic diagram of a voltage-time conversion circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram of a voltage-time conversion circuit provided in another embodiment of this application; Figure 6 This is a circuit connection diagram of a voltage-time conversion circuit provided in an embodiment of this application; Figure 7 This is a control timing diagram of a voltage-time conversion circuit provided in an embodiment of this application; Figure 8 This is a schematic diagram of the operation of a voltage-time conversion circuit provided in an embodiment of this application.

[0023] In the diagram: 10, Sampling module; 101, First sampling unit; 102, Second sampling unit; 20, Linear buck module; 201, First linear buck unit; 202, Second linear buck unit; 30, Charging module; 301, First charging unit; 302, Second charging unit; 40, Acceleration module; 401, First acceleration unit; 402, Second acceleration unit; 50, Comparison module; 501, First comparison unit; 502, Second comparison unit. Detailed Implementation

[0024] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0025] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0026] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0027] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0028] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0029] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0030] Figure 1 The schematic diagram of a time-domain analog-to-digital converter is shown. (For example...) Figure 1 As shown, the time-domain analog-to-digital converter (ADC) comprises two main circuit parts: a voltage-to-time converter and a time-to-digital converter. First, the voltage-to-time converter converts the sampled voltage signal into a differential time signal; then, the time-to-digital converter quantizes the time difference between the two time signals to finally obtain the digital output code value.

[0031] Figure 2 The circuit structure of an existing voltage-time converter is shown. For example... Figure 2As shown, existing voltage-time converters typically employ a pseudo-differential structure, meaning that the P-terminal and N-terminal circuits have identical operating modes and connections; the input signal VI includes a first input sub-signal VIP and a second input sub-signal VIN. For example... Figure 3 As shown, the specific working principle is as follows: when CK is high, the first input sub-signal VIP and the second input sub-signal VIN are sampled onto the top plate of the capacitor, and the first sub-signal VIN... P Second sub-signal V N This refers to the first input sub-signal VIP and the second input sub-signal VIN. At this time, neither the current mirror nor the threshold voltage detection module is operational. When CK is low, the current mirror linearly charges the sampling capacitor, i.e., the first sub-signal VIN... P Second sub-signal V N The voltage rises at a constant slope, while the threshold voltage detection module detects the first sub-signal V. P Second sub-signal V N The potential state when V P or V N Above the threshold voltage V TH At that time, a corresponding first time signal T with a rising edge is generated. P Or the second time signal T N The voltage-to-time converter transmits the output signal, which is then quantized by the subsequent stage, to the first time signal T. P The rising edge and the second time signal T N The time difference T of the rising edge OUT That is, T OUT =T N -T P Ideally, the charging current remains constant, and the time difference T at the output of the voltage-time converter... OUT The voltage difference VIP-VIN is linearly related to the input signal difference. For practical circuits, the voltage range of the input signal needs to satisfy the first sub-signal V. P Second sub-signal V N During linear charging, both the threshold voltage detection module and the current mirror operate in the saturation region. However, the maximum voltage of the input signal needs to be less than the threshold voltage V. TH Furthermore, a certain margin needs to be allowed in the voltage difference between the two to ensure that the voltage-time converter maintains high linearity under PVT (Process Voltage Temperature). The threshold voltage detection module is usually composed of a continuous-time comparator. For a comparator with PMOS input, the comparator input voltage needs to be less than VDD - (V GS +V DS ), where VDD is the power supply voltage, V GS V is the voltage between the gate and source of the PMOS transistor. DSThis is the voltage between the drain and source of the PMOS transistor, which means that the input swing of the voltage-time converter needs to be further reduced. Therefore, existing voltage-time converters can only maintain high linearity within an extremely limited input swing range.

[0032] Meanwhile, the voltage-time converter completes the conversion as indicated by its output first time signal T. P Second time signal T N All are toggled to high level. Figure 2 Taking the voltage-time converter based on constant slope charging as an example, the minimum value V of the sampled input signal is... N Charge at a constant slope until the threshold voltage V is reached. TH The time can be considered as the maximum conversion time of the voltage-time converter, and its magnitude limits the maximum conversion speed that the voltage-time converter can achieve. It is important to note that the maximum value V of the sampled input signal... P Charge to threshold voltage V TH The time is included within the conversion time of the voltage-time converter, which can be considered "useless time," such as... Figure 3 As shown, because the voltage-time converter only focuses on the first time signal T P Second time signal T N The time difference between the rising edges, and the "useless time" is not related to the accuracy of voltage-time conversion, but only reduces the speed of voltage-time conversion.

[0033] As can be seen from the above, the existing voltage-time converter has the following disadvantages: (1) it can only maintain a high linearity within an extremely limited input swing; (2) the voltage-time conversion speed is limited.

[0034] To address the aforementioned issues, this application provides a voltage-to-time conversion circuit. This application introduces a linear buck stage between the sampling and conversion stages. In this stage, the sampled signal output from the sampling stage is linearly bucked. This ensures that even with a full-swing input from rail to rail, the charging module, acceleration module, and comparator module all operate in the saturation region, resulting in high linearity. Simultaneously, an acceleration module is introduced in the conversion stage, significantly reducing the "useless time" during the input signal charging process, allowing the circuit to enter the target conversion range more quickly. Therefore, the voltage-to-time conversion circuit provided by this application achieves high voltage-to-time conversion speed and linearity even with a high input swing.

[0035] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0036] Figure 4 A schematic diagram of a voltage-time conversion circuit according to an embodiment of this application is shown. Figure 4As shown, the voltage-to-time conversion circuit includes a sampling module 10, a linear buck module 20, a charging module 30, an acceleration module 40, and a comparison module 50. The linear buck module 20 is connected to the sampling module 10, the charging module 30, the acceleration module 40, and the comparison module 50, respectively. The acceleration module 40 is connected to the charging module 30 and the comparison module 50, respectively. The sampling module 10 is used to receive the first clock signal CK1, the linear buck module 20 is used to receive the second clock signal CK2, and both the charging module 30 and the acceleration module 40 are used to receive the third clock signal CK3.

[0037] Specifically, the timing sequence of the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 is as follows: Figure 7 As shown, the rising edge of the second clock signal CK2 is slightly later than the falling edge of the first clock signal CK1, and the falling edge of the third clock signal CK3 is delayed by a certain period of time compared to the rising edge of the second clock signal CK2. The falling edge of the second clock signal CK2, the rising edge of the third clock signal CK3, and the rising edge of the first clock signal CK1 occur at the same time.

[0038] When the first clock signal CK1 is high, the second clock signal CK2 is low, and the third clock signal CK3 is high, this stage is the sampling stage. The sampling module 10 is used to sample the input signal VI to obtain the sampled signal Vs. At this time, the linear buck module 20, the charging module 30, the acceleration module 40, and the comparison module 50 are all not working.

[0039] When the first clock signal CK1 is low, the second clock signal CK2 is high, and the third clock signal CK3 is high, this stage is the linear buck stage, and the sampling module 10 stops sampling; the linear buck module 20 is used to linearly buck the sampled signal Vs to obtain the first signal V1; at this time, the charging module 30, the acceleration module 40, and the comparison module 50 are all not working. When the first clock signal CK1 is low, the second clock signal CK2 is high, and the third clock signal CK3 is low, this stage is the conversion stage, and the sampling module 10 stops sampling; the linear buck module 20 continues to output the first signal V1; the charging module 30 outputs the first charging current and simultaneously mirrors the first charging current to the acceleration module 40; the acceleration module 40 is used to adjust the first time signal T... P Second time signal T N The first charging current after mirroring outputs the second charging current; at the very beginning of the conversion phase, the first time signal T... P Second time signal T N Both are at low level; the first charging current and the second charging current together charge the first signal V1, causing the first signal V1 to charge at a faster rate; the comparison module 50 is used to compare the threshold voltage V...TH The first signal V1 outputs the first time signal T. P Second time signal T N When the first time signal T P Or the second time signal T N When the signal flips to a high level, the acceleration module 40 stops working, while the charging module 30 continues working until the first time signal T. P Second time signal T N All are flipped to high level.

[0040] As can be seen from the above, this application introduces a linear buck phase between the sampling phase and the conversion phase. In this phase, the sampled signal Vs output from the sampling phase is linearly bucked. This ensures that even with a full-swing input from rail to rail, the charging module 30, acceleration module 40, and comparator module 50 all operate in the saturation region, resulting in high linearity. Simultaneously, the introduction of acceleration module 40 in the conversion phase significantly reduces the "useless time" during the charging process of the input signal VI, allowing the circuit to enter the target conversion range more quickly. Therefore, the voltage-time conversion circuit provided by this application can achieve high voltage-time conversion speed and linearity even with a high input swing.

[0041] In one embodiment of this application, such as Figure 5 As shown, the sampling module 10 includes a first sampling unit 101 and a second sampling unit 102; the linear buck module 20 includes a first linear buck unit 201 and a second linear buck unit 202; the charging module 30 includes a first charging unit 301 and a second charging unit 302; the acceleration module 40 includes a first acceleration unit 401 and a second acceleration unit 402; and the comparison module 50 includes a first comparison unit 501 and a second comparison unit 502. The first linear buck unit 201 is connected to the first sampling unit 101, the first charging unit 301, and the first acceleration unit 402, respectively. The acceleration unit 401 is connected to the first comparison unit 501. The second linear buck unit 202 is connected to the second sampling unit 102, the second charging unit 302, the second acceleration unit 402, and the second comparison unit 502. The first comparison unit 501 is connected to the first acceleration unit 401 and the second acceleration unit 402. The second comparison unit 502 is connected to the first acceleration unit 401 and the second acceleration unit 402. The first acceleration unit 401 is connected to the first charging unit 301. The second acceleration unit 402 is connected to the second charging unit 302.

[0042] The first sampling unit 101 and the second sampling unit 102 are both used to receive the first clock signal CK1, the first linear buck unit 201 and the second linear buck unit 202 are both used to receive the second clock signal CK2, and the first charging unit 301, the second charging unit 302, the first acceleration unit 401 and the second acceleration unit 402 are both used to receive the third clock signal CK3.

[0043] Input signal VI includes a first input sub-signal VIP and a second input sub-signal VIN; first signal V1 includes a first sub-signal V P Second sub-signal V N The sampling signal Vs includes a first sampling sub-signal Vx and a second sampling sub-signal Vy; the first charging current includes a first charging sub-current and a second charging sub-current; the second charging current includes a third charging sub-current and a fourth charging sub-current. Specifically, when the first clock signal CK1 is high, the second clock signal CK2 is low, and the third clock signal CK3 is high, this stage is the sampling stage. The first sampling unit 101 is used to sample the first input sub-signal VIP to obtain the first sampled sub-signal Vx; the second sampling unit 102 is used to sample the second input sub-signal VIN to obtain the second sampled sub-signal Vy. At this time, the first linear buck unit 201, the second linear buck unit 202, the first charging unit 301, the second charging unit 302, the first acceleration unit 401, the second acceleration unit 402, the first comparison unit 501, and the second comparison unit 502 are all not working.

[0044] When the first clock signal CK1 is low, the second clock signal CK2 is high, and the third clock signal CK3 is high, this stage is the linear buck stage, and the first sampling unit 101 and the second sampling unit 102 stop sampling; the first linear buck unit 201 is used to linearly buck the first sampled sub-signal Vx to obtain the first sub-signal V P The second linear buck unit 202 is used to linearly buck the second sampled sub-signal Vy to obtain the second sub-signal V. N At this time, the first charging unit 301, the second charging unit 302, the first acceleration unit 401, the second acceleration unit 402, the first comparison unit 501, and the second comparison unit 502 are all not working.

[0045] When the first clock signal CK1 is low, the second clock signal CK2 is high, and the third clock signal CK3 is low, this stage is the conversion stage, and the first sampling unit 101 and the second sampling unit 102 stop sampling; the first linear buck unit 201 continues to output the first sub-signal V. P The second linear buck unit 202 continues to output the second sub-signal V. NThe first charging unit 301 is used to output a first charging current and simultaneously mirror the first charging current to the first acceleration unit 401; the second charging unit 302 is used to output a second charging current and simultaneously mirror the second charging current to the second acceleration unit 402; the first acceleration unit 401 is used to output a first charging current according to the first time signal T. P Second time signal T N The third charge current is output based on the mirrored first charge current; the second acceleration unit 402 is used to output the third charge current based on the first time signal T. P Second time signal T N The second charged current, after mirroring, outputs the fourth charged current; it should be noted that at the very beginning of the conversion phase, the first time signal T... P Second time signal T N All are low level.

[0046] The first charging current and the third charging current together affect the first sub-signal V. P Charge the signal so that the first sub-signal V P Charging at a faster rate; the second charging current and the fourth charging current together influence the second sub-signal V. N Charge the signal so that the second sub-signal V N Charging at a faster rate; the first comparison unit 501 is used to compare the threshold voltage V. TH and the first sub-signal V P Output first time signal T P The second comparison unit 502 is used to compare the threshold voltage V. TH Second sub-signal V N Output the second time signal T N When the first time signal T P Or the second time signal T N When the signal flips to a high level, the first acceleration unit 401 and the second acceleration unit 402 stop working, while the first charging unit 301 and the second charging unit 302 continue working until the first time signal T. P Second time signal T N All are flipped to high level.

[0047] As can be seen from the above, this application consists of a pseudo-differential structure. The processing circuit for the first input sub-signal VIP is composed of a first sampling unit 101, a first linear buck unit 201, a first charging unit 301, a first acceleration unit 401, and a first comparison unit 501. The processing circuit for the second input sub-signal VIN is composed of a second sampling unit 102, a second linear buck unit 202, a second charging unit 302, a second acceleration unit 402, and a second comparison unit 502. The working principle and circuit connection of the processing circuits for the first input sub-signal VIP and the second input sub-signal VIN are exactly the same. Both the processing circuits for the first input sub-signal VIP and the processing circuits for the second input sub-signal VIN are equipped with linear buck units and acceleration units, thereby ensuring that the voltage-time conversion circuit proposed in this application can achieve high voltage-time conversion speed and linearity even when achieving a high input swing.

[0048] In one embodiment of this application, such as Figure 6 As shown, the first sampling unit 101 includes a first switch S1 and a first capacitor C1. The first end of the first switch S1 is used to receive the first input sub-signal VIP. The second end of the first switch S1 is connected to the upper plate of the first capacitor C1 and the first linear step-down unit 201, respectively. The control end of the first switch S1 is used to receive the first clock signal CK1. The lower plate of the first capacitor C1 is grounded.

[0049] Specifically, the first switch S1 is controlled by the first clock signal CK1. When the first clock signal CK1 is high, the first switch S1 is turned on, and the first capacitor C1 samples the first input sub-signal VIP to obtain the first sampled sub-signal Vx. When the first clock signal CK1 is low, the first switch S1 is turned off.

[0050] The first switch S1 is typically a gate voltage bootstrap switch to meet the high linearity sampling of the first input sub-signal VIP.

[0051] In one embodiment of this application, such as Figure 6 As shown, the second sampling unit 102 includes a third switch S3 and a third capacitor C3. The first end of the third switch S3 is used to receive the second input sub-signal VIN. The second end of the third switch S3 is connected to the upper plate of the third capacitor C3 and the second linear step-down unit 202, respectively. The control end of the third switch S3 is used to receive the first clock signal CK1. The lower plate of the third capacitor C3 is grounded.

[0052] Specifically, the third switch S3 is controlled by the first clock signal CK1. When the first clock signal CK1 is high, the third switch S3 is turned on, and the third capacitor C3 samples the second input sub-signal VIN to obtain the second sampled sub-signal Vy. When the first clock signal CK1 is low, the third switch S3 is turned off.

[0053] The third switch S3 is usually a gate voltage bootstrap switch to meet the high linearity sampling of the second input sub-signal VIN.

[0054] In one embodiment of this application, such as Figure 6 As shown, the first linear buck unit 201 includes a second switch S2 and a second capacitor C2. The first end of the second switch S2 is connected to the first sampling unit 101, and the second end of the second switch S2 is connected to the upper plate of the second capacitor C2, the first charging unit 301, the first acceleration unit 401 and the first comparison unit 501 respectively. The control terminal of the second switch S2 is used to receive the second clock signal CK2, and the lower plate of the second capacitor C2 is grounded.

[0055] Specifically, the second switch S2 is controlled by the second clock signal CK2. When the second clock signal CK2 is high, the second switch S2 is turned on. It should be noted that at this time, the first switch S1 is open, and the first capacitor C1 and the second capacitor C2 linearly reduce the voltage of the first sampling sub-signal Vx to obtain the first sub-signal V. P When the second clock signal CK2 is low, the second switch S2 is open. The second switch S2 is typically a transmission gate switch to simplify circuit design.

[0056] The first sub-signal V can be obtained. P =C1*Vx / (C1+C2). Wherein, the second capacitor C2 is a linear scaling capacitor, that is, the introduction of the second capacitor C2 reduces the swing of the first input sub-signal VIP to C1 / (C1+C2) times.

[0057] In one embodiment of this application, such as Figure 6 As shown, the second linear buck unit 202 includes a fourth switch S4 and a fourth capacitor C4. The first end of the fourth switch S4 is connected to the second sampling unit 102, and the second end of the fourth switch S4 is connected to the upper plate of the fourth capacitor C4, the second charging unit 302, the second acceleration unit 402, and the second comparison unit 502, respectively. The control terminal of the fourth switch S4 is used to receive the second clock signal CK2, and the lower plate of the fourth capacitor C4 is grounded.

[0058] Specifically, the fourth switch S4 is controlled by the second clock signal CK2. When the second clock signal CK2 is high, the fourth switch S4 is turned on. It should be noted that at this time, the third switch S3 is turned off, and the third capacitor C3 and the fourth capacitor C4 linearly reduce the voltage of the second sampling sub-signal Vy to obtain the second sub-signal V. N When the second clock signal CK2 is low, the fourth switch S4 is open. The fourth switch S4 is typically a transmission gate switch to simplify circuit design.

[0059] The second sub-signal V can be obtained. N =C3*Vy / (C3+C4). Wherein, the fourth capacitor C4 is a linear scaling capacitor, that is, the introduction of the fourth capacitor C4 reduces the swing of the second input sub-signal VIN to C3 / (C3+C4) times.

[0060] In one embodiment of this application, such as Figure 6 As shown, the first charging unit 301 includes a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The gate of the fourth transistor M4 is connected to the drain of the fifth transistor M5, the source of the sixth transistor M6, and the first acceleration unit 401. The source of the fourth transistor M4 receives the power supply voltage VDD. The drain of the fourth transistor M4 is connected to the source of the fifth transistor M5. The gate of the fifth transistor M5 receives the first bias voltage Vbias1. The gate of the sixth transistor M6 is used to receive the third clock signal CK3. The drain of the sixth transistor M6 is connected to the first linear buck unit 201, the first acceleration unit 401, and the first comparator unit 501.

[0061] Specifically, when the third clock signal CK3 is low, the sixth transistor M6 is turned on, and the common-source cascode current mirror composed of the fourth transistor M4 and the fifth transistor M5 affects the first sub-signal V. P The charging operation is performed; when the third clock signal CK3 is high, the sixth transistor M6 is turned off, and the cascode current mirror does not work.

[0062] In one embodiment of this application, such as Figure 6 As shown, the second charging unit 302 includes a twenty-second transistor M22, a twenty-third transistor M23, and a twenty-fourth transistor M24. The source of the twenty-second transistor M22 receives the power supply voltage VDD. The gate of the twenty-second transistor M22 is connected to the drain of the twenty-third transistor M23, the source of the twenty-fourth transistor M24, and the second acceleration unit 402. The drain of the twenty-second transistor M22 is connected to the source of the twenty-third transistor M23. The gate of the twenty-third transistor M23 receives the first bias voltage Vbias1. The gate of the twenty-fourth transistor M24 is used to receive the third clock signal CK3. The drain of the twenty-fourth transistor M24 is connected to the second linear buck unit 202, the second acceleration unit 402, and the second comparator unit 502.

[0063] Specifically, when the third clock signal CK3 is low, the twenty-fourth transistor M24 is turned on, and the common-source cascode current mirror composed of the twenty-second transistor M22 and the twenty-third transistor M23 affects the second sub-signal V. N The charging operation is performed; when the third clock signal CK3 is high, the twenty-fourth transistor M24 is turned off, and the cascode current mirror does not work.

[0064] In one embodiment of this application, such as Figure 6 As shown, the first acceleration unit 401 includes a first transistor M1, a second transistor M2, a third transistor M3, and a first OR gate OR1. The gate of the first transistor M1 is connected to the first charging unit 301. The source of the first transistor M1 receives the power supply voltage VDD. The drain of the first transistor M1 is connected to the source of the second transistor M2. The gate of the second transistor M2 receives the first bias voltage Vbias1. The drain of the second transistor M2 is connected to the source of the third transistor M3. The gate of the third transistor M3 is connected to the output terminal of the first OR gate OR1. The drain of the third transistor M3 is connected to the first linear buck unit 201, the first charging unit 301, and the first comparator unit 501. The first input terminal of the first OR gate OR1 is used to receive the third clock signal CK3. The second input terminal of the first OR gate OR1 is connected to the first comparator unit 501 and the second acceleration unit 402. The third input terminal of the first OR gate OR1 is connected to the second comparator unit 502 and the second acceleration unit 402.

[0065] Specifically, only when the third clock signal CK3 and the first time signal T P Second time signal T N When all transistors are at low levels, the third transistor M3 will be turned on and the first acceleration unit 401 will work.

[0066] In one embodiment of this application, such as Figure 6 As shown, the second acceleration unit 402 includes a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, and a second OR gate OR2. The source of the nineteenth transistor M19 receives the power supply voltage VDD, the gate of the nineteenth transistor M19 is connected to the second charging unit 302, the drain of the nineteenth transistor M19 is connected to the source of the twentieth transistor M20, the gate of the twentieth transistor M20 receives the first bias voltage Vbias1, and the drain of the twentieth transistor M20 is connected to the source of the twenty-first transistor M21. The drain of the twenty-first transistor M21 is connected to the second linear buck unit 202, the second charging unit 302, and the second comparator unit 502, respectively. The gate of the twenty-first transistor M21 is connected to the output of the second OR gate OR2. The first input of the second OR gate OR2 is used to receive the third clock signal CK3. The second input of the second OR gate OR2 is connected to the second comparator unit 502 and the first acceleration unit 401, respectively. The third input of the second OR gate OR2 is connected to the first comparator unit 501 and the first acceleration unit 401, respectively.

[0067] Specifically, only when the third clock signal CK3 and the first time signal T P Second time signal TN When all levels are low, the 21st transistor M21 will be turned on, and the second acceleration unit 402 will work.

[0068] In one embodiment of this application, such as Figure 6 As shown, the first comparison unit 501 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18. The sources of the seventh transistor M7, the fifteenth transistor M15, the sixteenth transistor M16, and the seventeenth transistor M17 all receive the power supply voltage VDD. The gate of the seventh transistor M7 receives the second bias voltage Vbias2. The drain of the seventh transistor M7 is connected to the source of the eighth transistor M8. The drain of the eighth transistor M8 is connected to the sources of the ninth transistor M9 and the eleventh transistor M11, respectively. The gate of the ninth transistor M9 is connected to the first linear buck unit 201, the first charging unit 301, and the first acceleration unit 401, respectively. The gate of the eleventh transistor M11 receives the threshold voltage VDD. TH The drain of the ninth transistor M9 is connected to the drain of the tenth transistor M10, the gate of the tenth transistor M10, and the gate of the thirteenth transistor M13. The drain of the eleventh transistor M11 is connected to the drain of the twelfth transistor M12, the gate of the twelfth transistor M12, and the gate of the fourteenth transistor M14. The drain of the thirteenth transistor M13 is connected to the drain of the fifteenth transistor M15, the gate of the fifteenth transistor M15, and the gate of the sixteenth transistor M16. The drain of the sixteenth transistor M16 is connected to the drain of the fourteenth transistor M14, the gate of the seventeenth transistor M17, and the gate of the eighteenth transistor M18. The drain of the seventeenth transistor M17 is connected to the drain of the eighteenth transistor M18, the first acceleration unit 401, and the second acceleration unit 402. The sources of the tenth transistor M10, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the eighteenth transistor M18 are all grounded.

[0069] Specifically, the first comparison unit 501 is a continuous-time comparator used to detect the first sub-signal V. P The potential state, when the first sub-signal V P The voltage is higher than the threshold voltage V TH At that time, the first time signal T P It flips to a high level.

[0070] In one embodiment of this application, such as Figure 6As shown, the second comparison unit 502 includes transistors M25 (25th), M26 (26th), M27 (27th), M28 (28th), M29 (29th), M30 (30th), M31 (31st), M32 (32nd), M33 (33rd), M34 (34th), M35 (35th), and M36 (36th). The sources of transistors M25, M33, M34, and M35 all receive power from the power supply. The gate of the 25th transistor M25 receives the second bias voltage Vbias2. The drain of the 25th transistor M25 is connected to the source of the 26th transistor M26. The gate of the 26th transistor M26 is used to receive the third clock signal CK3. The drain of the 26th transistor M26 is connected to the source of the 27th transistor M27 and the source of the 29th transistor M29. The gate of the 27th transistor M27 is connected to the second linear buck unit 202, the second charging unit 302, and the second acceleration unit 402. The gate of the 29th transistor M29 receives the threshold voltage V. TH The drain of the twenty-seventh transistor M27 is connected to the drain and gate of the twenty-eighth transistor M28 and the gate of the thirty-first transistor M31, respectively. The drain of the twenty-ninth transistor M29 is connected to the drain and gate of the thirtieth transistor M30 and the gate of the thirty-second transistor M32, respectively. The drain of the thirty-first transistor M31 is connected to the drain and gate of the thirty-third transistor M33 and the gate of the thirty-fourth transistor M34, respectively. The drain of transistor M32 is connected to the drain of transistor M34, the gate of transistor M35, and the gate of transistor M36, respectively. The drain of transistor M35 is connected to the drain of transistor M36, the first acceleration unit 401, and the second acceleration unit 402, respectively. The source of transistor M28, transistor M30, transistor M31, transistor M32, and transistor M36 are all grounded.

[0071] Specifically, the second comparison unit 502 is a continuous-time comparator used to detect the second sub-signal V. N The potential state, when the second sub-signal V N The voltage is higher than the threshold voltage V TH At that time, the second time signal T N It flips to a high level.

[0072] The following is combined Figure 6 , Figure 7 and Figure 8 Explain the working principle of this application.

[0073] Sampling Phase: The first clock signal CK1 is high, the second clock signal CK2 is low, and the third clock signal CK3 is high. The first switch S1 and the third switch S3 are closed, while the second switch S2 and the fourth switch S4 are open. The first input sub-signal VIP is sampled onto the upper plate of the first capacitor C1 to obtain the first sampled sub-signal Vx. The second input sub-signal VIN is sampled onto the upper plate of the third capacitor C3 to obtain the second sampled sub-signal Vy. The first capacitor C1 and the third capacitor C3 determine the sampling accuracy of the voltage-time conversion circuit. During this phase, the linear buck module 20, the charging module 30, the acceleration module 40, and the comparison module 50 are all inactive.

[0074] Linear step-down stage: The first clock signal CK1 is low, the second clock signal CK2 is high, and the third clock signal CK3 is high. The second switch S2 and the fourth switch S4 are closed, and the first switch S1 and the third switch S3 are open. The first capacitor C1 and the second capacitor C2 linearly step down the first sampling sub-signal Vx to obtain the first sub-signal V. P The third capacitor C3 and the fourth capacitor C4 linearly reduce the voltage of the second sampled sub-signal Vy to obtain the second sub-signal V. N At this time, the charging module 30, the acceleration module 40, and the comparison module 50 are all not working.

[0075] During the transition phase: the first clock signal CK1 is low, the second clock signal CK2 is high, and the third clock signal CK3 is low. The second switch S2 and the fourth switch S4 are closed, while the first switch S1 and the third switch S3 are open. At this time, the first time signal T... P Second time signal T N All are at low levels, and acceleration module 40 starts working, such as Figure 8 As shown, the first acceleration unit 401 and the first charging unit 301 together form the first sub-signal V. P Charging begins, first sub-signal V P Charging is performed at a faster incline; simultaneously, the first comparison unit 501 detects the first sub-signal V. P The potential state, when the first sub-signal V P Above the threshold voltage V TH At that time, the first time signal T P The toggle switches to a high level. Similarly, as... Figure 8 As shown, the second acceleration unit 402 and the second charging unit 302 together constitute the second sub-signal V. N Charging begins, second sub-signal V N Charging is performed at a faster incline; simultaneously, the second comparison unit 502 detects the second sub-signal V. NThe potential state, when the second sub-signal V N Above the threshold voltage V TH At that time, the second time signal T N The signal flips to a high level. When the first time signal T... P Or the second time signal T N When the signal flips to a high level, the acceleration module 40 stops working, while the charging module 30 continues to work, and the charging rate decreases until the first time signal T... P Second time signal T N All are toggled to high level. According to Figure 8 It can be concluded that the introduction of acceleration module 40 reduces the "useless time", thereby improving the voltage-time conversion speed of the circuit.

[0076] In summary, the voltage-time conversion circuit provided in this application linearly reduces the input signal VI before charging and threshold voltage detection operations by introducing a linear scaling capacitor. This ensures that even under full-swing input from rail to rail, the charging module 30, acceleration module 40, and comparison module 50 all operate in the saturation region, resulting in high linearity. Simultaneously, the introduction of the OR-gate-controlled acceleration module 40 accelerates the input signal VI to the threshold voltage V. TH The time required to complete the voltage-time conversion is significantly reduced, shortening the "useless time" during the charging process of the input signal VI, allowing the circuit to enter the target conversion range more quickly. Therefore, the voltage-time conversion circuit provided in this application can achieve high voltage-time conversion speed and linearity even with a high input swing.

[0077] This application also provides an analog-to-digital converter, including the voltage-time conversion circuit described above. Since the analog-to-digital converter provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated upon here.

[0078] This application also provides a chip including the analog-to-digital converter described above. Since the chip provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated upon here.

[0079] This application also provides an electronic device including the chip described above. Since the electronic device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated upon here.

[0080] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0081] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A voltage-time conversion circuit, characterized in that, The system includes a sampling module, a linear buck module, a charging module, an acceleration module, and a comparison module. The linear buck module is connected to the sampling module, the charging module, the acceleration module, and the comparison module, respectively. The acceleration module is connected to the charging module and the comparison module, respectively. The sampling module is used to receive a first clock signal, the linear buck module is used to receive a second clock signal, and both the charging module and the acceleration module are used to receive a third clock signal. When the first clock signal is high, the second clock signal is low, and the third clock signal is high, the sampling module is used to sample the input signal to obtain the sampled signal. When the first clock signal is low, the second clock signal is high, and the third clock signal is high, the sampling module stops sampling; the linear buck module is used to linearly buck the sampled signal to obtain the first signal. When the first clock signal is low, the second clock signal is high, and the third clock signal is low, the sampling module stops sampling; the linear buck module continues to output the first signal; the charging module outputs a first charging current and mirrors the first charging current to the acceleration module; the acceleration module outputs a second charging current based on the first time signal, the second time signal, and the mirrored first charging current; the first charging current and the second charging current jointly charge the first signal; the comparison module outputs a first time signal and a second time signal based on the threshold voltage and the first signal; when the first time signal or the second time signal flips to a high level, the acceleration module stops working, and the charging module continues working until both the first time signal and the second time signal flip to a high level.

2. The voltage-time conversion circuit according to claim 1, characterized in that, The sampling module includes a first sampling unit and a second sampling unit; the linear buck module includes a first linear buck unit and a second linear buck unit; the charging module includes a first charging unit and a second charging unit; the acceleration module includes a first acceleration unit and a second acceleration unit; and the comparison module includes a first comparison unit and a second comparison unit. The first linear buck unit is connected to the first sampling unit, the first charging unit, the first acceleration unit, and the first comparison unit, respectively. The second linear buck unit is connected to the second sampling unit, the second charging unit, the second acceleration unit, and the second comparison unit, respectively. The first comparison unit is connected to the first acceleration unit and the second acceleration unit, respectively. The second comparison unit is connected to the first acceleration unit and the second acceleration unit, respectively. The acceleration unit is connected to the first charging unit, and the second acceleration unit is connected to the second charging unit. Both the first and second sampling units are used to receive a first clock signal, both the first and second linear buck units are used to receive a second clock signal, and the first, second, first, and second acceleration units are all used to receive a third clock signal. The input signal includes a first input sub-signal and a second input sub-signal. The first signal includes a first sub-signal and a second sub-signal. The sampling signal includes a first sampling sub-signal and a second sampling sub-signal. The first charging current includes a first charging sub-current and a second charging current. The second charging current includes a third charging sub-current and a fourth charging sub-current. When the first clock signal is high, the second clock signal is low, and the third clock signal is high, the first sampling unit is used to sample the first input sub-signal to obtain the first sampled sub-signal; the second sampling unit is used to sample the second input sub-signal to obtain the second sampled sub-signal. When the first clock signal is low, the second clock signal is high, and the third clock signal is high, the first sampling unit and the second sampling unit stop sampling; the first linear buck unit is used to linearly buck the first sampled sub-signal to obtain the first sub-signal; the second linear buck unit is used to linearly buck the second sampled sub-signal to obtain the second sub-signal; When the first clock signal is low, the second clock signal is high, and the third clock signal is low, the first sampling unit and the second sampling unit stop sampling; the first linear buck unit continues to output the first sub-signal; the second linear buck unit continues to output the second sub-signal; the first charging unit outputs the first charging sub-current and mirrors the first charging sub-current to the first accelerating unit; the second charging unit outputs the second charging sub-current and mirrors the second charging sub-current to the second accelerating unit; the first accelerating unit outputs the third charging sub-current based on the first time signal, the second time signal, and the mirrored first charging sub-current; the second accelerating unit outputs the third charging sub-current based on the first time signal, the second time signal, and the mirrored first charging sub-current; the second accelerating unit outputs the third charging sub-current based on the first time signal, the second time signal, and the mirrored first charging sub-current. The first charging current is output from the second charging current, the second time signal, and the mirrored second charging current; the first charging current and the third charging current jointly charge the first sub-signal; the second charging current and the fourth charging current jointly charge the second sub-signal; the first comparison unit is used to output a first time signal based on the threshold voltage and the first sub-signal; the second comparison unit is used to output a second time signal based on the threshold voltage and the second sub-signal; when the first time signal or the second time signal flips to a high level, the first acceleration unit and the second acceleration unit stop working, and the first charging unit and the second charging unit continue working until both the first time signal and the second time signal flip to a high level.

3. The voltage-time conversion circuit according to claim 2, characterized in that, The first acceleration unit includes a first transistor, a second transistor, a third transistor, and a first OR gate. The gate of the first transistor is connected to the first charging unit. The source of the first transistor receives a power supply voltage. The drain of the first transistor is connected to the source of the second transistor. The gate of the second transistor receives a first bias voltage. The drain of the second transistor is connected to the source of the third transistor. The gate of the third transistor is connected to the output of the first OR gate. The drain of the third transistor is connected to the first linear buck unit, the first charging unit, and the first comparator unit. The first input of the first OR gate is used to receive a third clock signal. The second input of the first OR gate is connected to the first comparator unit and the second acceleration unit. The third input of the first OR gate is connected to the second comparator unit and the second acceleration unit.

4. The voltage-time conversion circuit according to claim 2, characterized in that, The first sampling unit includes a first switch and a first capacitor. The first terminal of the first switch is used to receive a first input sub-signal. The second terminal of the first switch is connected to the upper plate of the first capacitor and the first linear buck unit, respectively. The control terminal of the first switch is used to receive a first clock signal. The lower plate of the first capacitor is grounded.

5. The voltage-time conversion circuit according to claim 2, characterized in that, The first linear buck unit includes a second switch and a second capacitor. The first end of the second switch is connected to the first sampling unit, and the second end of the second switch is connected to the upper plate of the second capacitor, the first charging unit, the first acceleration unit, and the first comparison unit, respectively. The control terminal of the second switch is used to receive a second clock signal, and the lower plate of the second capacitor is grounded.

6. The voltage-time conversion circuit according to claim 2, characterized in that, The first charging unit includes a fourth transistor, a fifth transistor, and a sixth transistor. The gate of the fourth transistor is connected to the drain of the fifth transistor, the source of the sixth transistor, and the first acceleration unit. The source of the fourth transistor receives a power supply voltage, the drain of the fourth transistor is connected to the source of the fifth transistor, the gate of the fifth transistor receives a first bias voltage, the gate of the sixth transistor receives a third clock signal, and the drain of the sixth transistor is connected to the first linear buck unit, the first acceleration unit, and the first comparator unit.

7. The voltage-time conversion circuit according to claim 2, characterized in that, The first comparison unit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor. The sources of the seventh, fifteenth, sixteenth, and seventeenth transistors all receive a power supply voltage. The gate of the seventh transistor receives a second bias voltage. The drain of the seventh transistor is connected to the source of the eighth transistor. The drain of the eighth transistor is connected to the sources of the ninth and eleventh transistors, respectively. The gate of the ninth transistor is connected to the first linear buck unit, the first charging unit, and the first acceleration unit, respectively. The gate of the eleventh transistor receives a threshold voltage. The drain of the ninth transistor is connected to... The drain, gate, and gate of the tenth transistor are connected. The drain of the eleventh transistor is connected to the drain, gate, and gate of the twelfth transistor, respectively. The drain of the thirteenth transistor is connected to the drain, gate, and gate of the fifteenth transistor, respectively. The drain of the sixteenth transistor is connected to the drain, gate, and gate of the fourteenth transistor, respectively. The drain of the sixteenth transistor is connected to the drain, gate, and gate of the fourteenth transistor, respectively. The drain of the seventeenth transistor is connected to the drain of the eighteenth transistor, the first acceleration unit, and the second acceleration unit, respectively. The sources of the tenth, twelfth, thirteenth, fourteenth, and eighteenth transistors are all grounded.

8. An analog-to-digital converter, characterized in that, Includes the voltage-time conversion circuit according to any one of claims 1-7.

9. A chip, characterized in that, Includes the analog-to-digital converter as described in claim 8.

10. An electronic device, characterized in that, Includes the chip described in claim 9.

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