A programmable multi-mode precision time triggered system and method based on ptp

Abstract

The application discloses a programmable multi-mode precision time trigger system and method based on PTP, and relates to the field of time synchronization control.The system adopts a soft and hard cooperative architecture of a master control FPGA, and realizes nanosecond-level marking of a PTP protocol and local clock locking by combining an Ethernet PHY, a high-precision DAC and a voltage-controlled crystal oscillator in the FPGA internal hardware logic; a soft core processor is embedded to run Kalman filtering and PID algorithm to output a smooth correction amount.Based on the high-precision reference, a hardware trigger generates an IP core to support three trigger modes of immediate, absolute and relative, and can read a timing table from a memory to output a single pulse, an equal-interval pulse train and an unequal-interval pulse train waveform.Meanwhile, an event queue is built-in to support group management of more than one hundred events and quick cancellation of unexecuted events.The application overcomes the defects that the precision and flexibility of a traditional timing scheme are difficult to be considered, and meets the extremely high standard cooperative synchronization demand of a large scientific experiment and an industrial system with an accuracy of better than ± 50 ns.

Description

Technical Field

[0001] This invention relates to the field of time synchronization control, and specifically to a programmable multi-mode precision time triggering system and method based on PTP. Background Technology

[0002] The statements in this section are provided only as background information in connection with this disclosure and may not constitute prior art.

[0003] In large-scale scientific experimental facilities (such as tokamak nuclear fusion experimental devices, particle accelerators, and synchrotron radiation sources) and industrial automation scenarios, precise event synchronization and timing control are key technologies for achieving collaborative operation of multiple systems. For example, during the discharge process of a tokamak nuclear fusion experiment, hundreds of diagnostic measurement systems and control systems need to perform specific operations at precise time points, and these operations require extremely high precision and reliability in time triggering.

[0004] Existing time synchronization and timing control technologies mainly include the following solutions: The first type is a hardware trigger bus-based solution, which uses a dedicated timing trigger bus to distribute trigger signals from the central timing system to each subsystem. This solution has high trigger accuracy, but requires dedicated hardware and wiring, has poor system scalability, and high deployment costs.

[0005] The second type is a software timer-based solution. After each subsystem obtains time synchronization through the network, the software timer triggers the operation at a specified time. This solution is flexible, but it is limited by operating system scheduling delay and network jitter, and the triggering accuracy is usually in the millisecond range.

[0006] The third type is based on GPS / BeiDou timing, which uses satellite signals to achieve time synchronization and generate trigger signals locally. It can achieve trigger accuracy at the level of hundreds of nanoseconds, but the signal is limited in a closed experimental environment and the flexible configuration capability of timed triggering is insufficient.

[0007] In summary, the existing technology objectively has the following shortcomings: (1) Single triggering mode: Existing solutions usually only support triggering at a specified UTC time, or triggering after a specified delay after receiving the start command, lacking unified support for multiple modes such as immediate triggering, absolute time triggering, and relative time triggering.

[0008] (2) Limited types of trigger output waveforms: Existing solutions mainly output single-pulse trigger signals, which are difficult to meet the needs of complex experimental scenarios that require equally spaced pulse trains (such as periodic sampling) or unequally spaced pulse trains (such as output according to a predefined timing table).

[0009] (3) Weak event management capabilities: The existing solution lacks advanced unified management capabilities for multiple triggering events, making it difficult to achieve events grouping, batch enabling / cancellation, etc., and the response is slow when dealing with complex experimental plan changes or abnormal termination.

[0010] (4) Triggering accuracy and flexibility are difficult to balance: Existing pure hardware triggering schemes have poor flexibility and pure software triggering schemes have low accuracy, making it difficult to meet the system-level application requirements of nanosecond-level high precision and high flexibility at the same time. Summary of the Invention

[0011] The purpose of this invention is to overcome the shortcomings of existing technologies, such as poor scalability of pure hardware triggering, low accuracy of pure software triggering, and single triggering modes and fixed waveforms. This invention aims to provide a programmable multi-mode precision time triggering system and method based on PTP. By constructing a hardware-software co-working underlying architecture, this invention aims to simultaneously solve the problems of limited application scenarios and difficulties in managing complex events under single-mode conditions, achieving a precision triggering accuracy better than ±50ns while maintaining high scalability and flexibility.

[0012] The technical solution of the present invention is as follows: A programmable multi-mode precision time triggering system based on PTP, comprising: The main control FPGA, and a gigabit Ethernet PHY chip, a voltage-controlled crystal oscillator, a digital-to-analog converter, and a memory respectively connected to the main control FPGA; The main control FPGA has an embedded soft core processor and is configured with hardware logic. The soft core processor and the hardware logic work together to form a PTP clock synchronization module, an event management module, a trigger mode control module, a trigger waveform generation module, and a clock signal generation module. The PTP clock synchronization module is used to receive PTP protocol messages through the Gigabit Ethernet PHY chip to establish a local time reference, calculate control quantities based on clock deviation, and adjust the frequency of the voltage-controlled crystal oscillator through the digital-to-analog converter to achieve synchronization with the PTP master clock. The event management module is used to maintain an event queue sorted by trigger time in the memory. Each event record in the event queue contains at least an event ID, trigger mode, trigger time or delay parameter, waveform type and group ID, and supports cancellation operations for events that have not yet entered the execution state based on the event ID or the group ID. The trigger mode control module is used to perform trigger determination according to the trigger mode in the event record. The trigger modes include immediate trigger mode, absolute time trigger mode and relative time trigger mode. For the absolute time trigger mode, the current local time base is continuously matched with the target trigger time by the hardware comparator in the hardware logic to generate a trigger signal. The trigger waveform generation module is used to output a trigger waveform according to the waveform type in the event record when the trigger signal is received. The trigger waveform includes a single pulse, an equally spaced pulse train, and an unequally spaced pulse train. For the unequally spaced pulse train, the trigger waveform generation module drives the output according to a timing table stored in the memory. The timing table includes the interval parameter and pulse width parameter of adjacent pulses. The clock signal generation module is used to output a clock signal with a configurable frequency.

[0013] Furthermore, the specific implementation of the PTP clock synchronization module includes: The IEEE 1588 IP core embedded in the hardware logic of the main control FPGA is used to provide a real-time clock module including a time counter, as well as a receive timestamp generation module and a send timestamp generation module. The PTP software protocol stack running on the soft-core processor is used to process PTP protocol messages and calculate clock offset and frequency deviation. The soft-core processor is also equipped with a Kalman filter and a PID controller. The Kalman filter is used to filter the clock offset and the frequency deviation to suppress measurement noise. The PID controller is used to calculate the digital control voltage based on the filtered frequency deviation and adjust the frequency of the voltage-controlled crystal oscillator by outputting the control voltage through the digital-to-analog converter.

[0014] Furthermore, when the trigger mode control module executes the relative time trigger mode: Monitor the start signal, start a delay count upon receiving the start signal, and generate the trigger signal after the configured delay time parameter is reached; The sources of the start signal include network command signals, external general purpose input / output (GPIO) signals, or trigger signals output by another triggered event in the system, so as to realize cascading triggering between events.

[0015] Furthermore, it also includes a multi-channel output driver module, which provides multiple independent trigger output channels; The trigger waveform generation module supports configuring pulse polarity and generates a single pulse signal of specified polarity according to the configured pulse width parameter when outputting the single pulse; When outputting the equally spaced pulse train, a pulse sequence with a fixed period is generated according to the preset pulse interval parameter, pulse width parameter, and pulse number parameter, and output through the specified trigger output channel.

[0016] Furthermore, the event management module is also used to update the event status of each event record in the event queue, the event status including waiting, executing, completed, canceled, and error; The main control FPGA is also configured to record the actual execution time and execution result of each event to generate an event execution log, and store the event execution log in the memory.

[0017] This invention also proposes a PTP-based programmable multi-mode precision time triggering method, applied to the aforementioned PTP-based programmable multi-mode precision time triggering system, comprising the following steps: Step S1: Receive PTP protocol messages from the PTP master clock through the Gigabit Ethernet PHY chip, calculate the clock deviation, and adjust the frequency of the voltage-controlled crystal oscillator through a digital-to-analog converter to establish a local time reference synchronized with the PTP master clock; Step S2: Receive trigger configuration information, maintain an event queue sorted by trigger time in the memory, generate an event record containing event ID, trigger mode, trigger time or delay parameter, waveform type and group ID; and when a cancellation instruction is received, cancel the event that has not yet entered the execution state based on the event ID or the group ID. Step S3: Execute trigger scheduling according to the trigger mode in the event record. The trigger modes include immediate trigger mode, absolute time trigger mode, and relative time trigger mode. For absolute time trigger mode, the current local time base is continuously matched with the target trigger time through a hardware comparator, and a trigger signal is generated when the time matches. Step S4: Upon receiving the trigger signal, output a trigger waveform containing a single pulse, an equally spaced pulse train, or an unequally spaced pulse train according to the waveform type in the event record; wherein, when outputting the unequally spaced pulse train, the output is driven by reading a timing table containing adjacent pulse interval parameters and pulse width parameters stored in the memory.

[0018] Furthermore, in step S1, the specific process of establishing a synchronized local time base includes: The generation of timestamps and the maintenance of real-time clocks are achieved through hardware logic in the main control FPGA. Clock skew and frequency deviation are calculated by running the PTP software protocol stack on a soft-core processor. The clock offset and frequency deviation are filtered using a Kalman filter, and the filtering result is input into a PID controller to calculate the digital control voltage, which drives the digital-to-analog converter to adjust the output frequency of the voltage-controlled crystal oscillator.

[0019] Furthermore, in step S3, when executing the relative time trigger mode, the specific steps include: Monitor startup signals, including network command signals, external GPIO signals, or cascaded trigger event signals; After the start signal is captured, hardware delay counting is started based on the local time base; The trigger signal is generated when the delay count reaches the time interval defined by the delay parameter.

[0020] Furthermore, the specific process of outputting the equally spaced pulse train in step S4 includes: Parse the pulse interval parameter, pulse width parameter, and pulse count parameter in the event record; Generate a pulse sequence with a fixed period based on the analyzed parameters; According to the configured pulse polarity and channel allocation instructions, the pulse sequence is output to the corresponding physical channel through the multi-channel output driver module.

[0021] Furthermore, the method also includes: During the triggering and scheduling process, the event status of each event record in the event queue is updated in real time to the status of waiting, executing, completed, canceled, or error. When an event enters a completed or error state, the actual execution time and execution result are recorded, an execution log is generated and written to the memory for export verification.

[0022] Compared with existing technologies, the advantages of this invention are: 1. Wide range of application scenarios. This invention, through a combination of hardware logic and soft core configuration, breaks through the single triggering limitation of traditional solutions, supporting three modes: immediate triggering, absolute time triggering, and relative time triggering, meeting the triggering needs of all scenarios from immediate emergency response to nanosecond-level precise timing.

[0023] 2. High system integration and low deployment cost. This invention supports three output waveforms at the underlying hardware level: single pulse, equally spaced pulse train, and unequally spaced pulse train based on a memory timing table. This mechanism can directly replace traditional independent pulse generators and arbitrary waveform generators, reducing the number of system devices and wiring complexity, and significantly lowering system integration and hardware deployment costs.

[0024] 3. High efficiency in controlling and tolerating complex experiments. This invention designs an advanced event queue and group management mechanism based on memory, which supports the simultaneous management of more than 256 trigger events. Through enable / batch cancellation operations based on group ID, it significantly improves the scheduling and control efficiency of complex experiments in multiple subsystems, and shortens the cancellation response time of abnormal events to less than 100μs.

[0025] 4. Achieving a perfect balance between high precision and high flexibility. This invention abandons pure software timing and pure hardware bus solutions, adopting a hardware-software co-engineering architecture of "main control FPGA + voltage-controlled crystal oscillator". The soft core executes the network protocol and Kalman filter PID closed-loop algorithm, while the hardware comparator performs nanosecond-level time comparison and triggering. Compared with software timer solutions, the triggering accuracy is improved by four orders of magnitude (better than ±50ns); at the same time, it adopts a standard gigabit Ethernet interface and PTP protocol, fully compatible with existing network infrastructure, and completely solves the technical problem of limited scalability. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0027] Figure 1 This is an architecture diagram of a programmable multi-mode precision time-triggered system based on PTP; Figure 2 This is a schematic diagram of three trigger output waveforms of the present invention. Detailed Implementation

[0028] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0029] The features and performance of the present invention will be further described in detail below with reference to embodiments.

[0030] Example 1 This embodiment provides a precision time synchronization and timing triggering system for large-scale scientific experimental facilities (such as tokamak nuclear fusion experimental devices). To overcome the problems of low timing accuracy of pure software and poor scalability of pure hardware bus in the prior art, this embodiment adopts a "main control FPGA software and hardware co-processing" architecture.

[0031] Please see Figure 1 This embodiment proposes a programmable multi-mode precision time triggering system based on PTP, comprising: The main control FPGA, and a gigabit Ethernet PHY chip, a voltage-controlled crystal oscillator, a digital-to-analog converter, and a memory, which are respectively connected to the main control FPGA.

[0032] Specifically, in this embodiment, the main control FPGA adopts the Xilinx Spartan-6 series (such as XC6SLX45) or a chip with equivalent performance; The Gigabit Ethernet PHY chip provides a Gigabit Ethernet physical layer interface for PTP protocol communication and configuration command reception. It connects to the main control FPGA through the GMII interface and supports IEEE 1588v2 hardware timestamp marking (timestamp accuracy better than 8ns). The voltage-controlled crystal oscillator uses a high-precision temperature-controlled crystal oscillator (OCXO) as the local clock source, with a frequency stability better than ±0.1ppb. The crystal oscillator frequency is fine-tuned through a digital-to-analog converter (DAC) to achieve frequency locking with the PTP master clock. The digital-to-analog converter uses a 16-bit or higher resolution digital-to-analog converter (DAC), whose output voltage range covers the adjustment range of the voltage-controlled crystal oscillator, achieving sub-ppb level frequency adjustment accuracy; The memory uses DDR4 memory with a capacity of 512MB or higher to store event queues, pulse sequence tables, and operation logs; through the physical connection of the above core hardware, a physical foundation for nanosecond-level precision is constructed.

[0033] In this embodiment, specifically, the main control FPGA has an embedded soft core processor and is configured with hardware logic. The soft core processor and the hardware logic work together to form a PTP clock synchronization module, an event management module, a trigger mode control module, a trigger waveform generation module, and a clock signal generation module. Specifically, the soft-core processor is preferably a MicroBlaze soft-core processor, running embedded software and an operating system (such as an RTOS with an LWIP protocol stack), and equipped with peripheral communication interfaces such as UART (Universal Asynchronous Receiver / Transmitter), as well as an SPI (Serial Peripheral Interface) bus for controlling peripheral digital-to-analog converters. Furthermore, the main control FPGA is internally configured with a command configuration module mounted on the AXI bus. This command configuration module acts as a bridge between hardware and software, used to parse clock signals and trigger parameters from Ethernet or UART, and is responsible for handling complex network protocols, local communication, and control algorithms. The hardware logic is built from the logic gates within the FPGA (specifically including...). Figure 1 The IEEE 1588 IP core, trigger generation IP core, frequency generation IP core, etc. (shown) are responsible for nanosecond-level comparisons and triggering actions that are extremely sensitive to time. This hardware-software partitioning architecture provides solid physical support for the above functional modules, completely avoiding millisecond-level errors caused by pure operating system scheduling delays.

[0034] In this embodiment, specifically, the PTP clock synchronization module implements the IEEE 1588v2 slave clock function, establishing a local time reference synchronized with the master clock. The specific implementation includes: The IEEE 1588 IP core, embedded in the hardware logic of the main control FPGA, implements the PTP hardware protocol stack within the FPGA, including a receive timestamp generation module, a transmit timestamp generation module, a real-time clock (RTC) module, and an AXI bus register interface module. The real-time clock module maintains a 96-bit time counter with a resolution of 1 ns. The PTP software protocol stack (such as the PTPd protocol stack) running on the soft-core processor realizes functions such as PTP message transmission and reception, clock offset calculation, and delay measurement, and works with the IEEE 1588 IP core to achieve high-precision and high-determinism timing synchronization. The soft-core processor is also equipped with a Kalman filter and a PID controller; the Kalman filter is used to filter the clock offset and frequency deviation obtained from PTP measurement, suppress the influence of network jitter and measurement noise, and output a smooth clock correction amount. The PID controller calculates the digital control voltage based on the filtered frequency deviation using a PID algorithm. The soft-core processor then sends this digital control voltage to the high-precision DAC via the SPI interface for digital-to-analog conversion, thereby outputting a control voltage to adjust the frequency of the voltage-controlled crystal oscillator, ensuring that the local clock and the PTP master clock are synchronized in frequency and phase. Long-term operation achieves a synchronization accuracy better than ±50ns (measured at ±38ns), reaching an extremely high level.

[0035] In this embodiment, specifically, the event management module provides advanced management functions for triggered events, which is used to maintain an event queue sorted by trigger time in the memory. Each event record in the event queue includes information such as: event ID, trigger mode, trigger time / delay, output channel, waveform type, waveform parameters, event status, and group ID.

[0036] It also supports event group management, allowing multiple events to be grouped into the same group, with group IDs ranging from 1 to 255. Events within a group can be enabled / disabled, canceled, and their status queried uniformly. This feature is used to manage sets of related events in complex experiments, such as grouping all trigger events of a diagnostic system into one group.

[0037] It should be noted that the event management module supports canceling events that have not yet been executed. Individual events can be canceled by event ID, or events awaiting execution can be quickly marked as "cancelled" by comparing data using a mask based on the group ID. Cancellation operations take effect immediately with a response time better than 100μs. Events already in the execution state cannot be canceled. This feature is used to handle scenarios involving changes to experimental plans or abnormal termination.

[0038] In addition, the event management module provides an event status query interface, with statuses including: waiting, executing, completed, canceled, and error. It also supports event execution logging, recording the actual execution time and results of each event for post-event analysis and accuracy verification. The logs are stored in DDR4 memory and can be exported and printed via network or the UART interface.

[0039] In this embodiment, specifically, the trigger generation IP core in the hardware logic works together to implement the functions of the trigger mode control module and the trigger waveform generation module, and the frequency generation IP core works together to implement the function of the clock signal generation module.

[0040] The trigger mode control module supports three trigger modes: (1) Immediate Trigger Mode: Upon receiving a trigger command, the device immediately outputs a high-level, low-level, or single-pulse trigger signal within the shortest possible response delay. This mode is used for scenarios requiring immediate response, such as emergency stop triggering or manual test triggering. Trigger commands can be input via network.

[0041] (2) Absolute Time Trigger Mode: Outputs the corresponding trigger signal at the specified absolute UTC time. The trigger time is expressed in PTP time format (seconds + nanoseconds) with a resolution of 1 ns. To ensure nanosecond-level accuracy, the underlying 96-bit wide hardware comparator continuously performs parallel XOR comparisons between the current PTP time (the 96-bit timestamp of the real-time clock RTC) and the target trigger time, and triggers the output immediately once the times match. This mode is used for operations that need to be performed at precise times, such as experiment start triggering, synchronous sampling triggering, etc.

[0042] (3) Relative Time Trigger Mode: After receiving the start signal, the trigger signal is output after a specified time interval. The delay time is configurable from 40ns to 1000s, with a resolution of 1ns. The start signal can be a network command, an external GPIO input, or the output of another trigger event. After channel 1 is triggered, its signal can be used to start subsystem 2 to system N through the FPGA's internal routing matrix for operations that need to be executed sequentially.

[0043] In this embodiment, specifically, the clock signal generation module and the trigger waveform generation module are used for low-level precision signal output: Among them, the clock signal generation module (i.e. Figure 1 The frequency generation IP core supports 8 clock signal outputs, each with a range of 1KHz to 100MHz, which can be configured by setting parameters.

[0044] Trigger waveform generation module (i.e.) Figure 1 The trigger-generating IP core supports 4 groups of 16 event signal outputs, each group containing 4 TTL signal outputs, and supports three output waveform types (e.g., Figure 2 (as shown) (1) Single pulse output: Outputs a single trigger pulse. The pulse width is configurable (8-byte unsigned integer, unit: ns). The pulse polarity can be configured as positive (low → high → low) or negative (high → low → high).

[0045] (2) Equal-interval pulse train output: Outputs a pulse sequence with a fixed period, including parameters such as pulse interval (8-byte unsigned integer, in ns), pulse width (8-byte unsigned integer, in ns), and number of pulses (2-byte unsigned integer). This mode is used for scenarios such as periodic sampling triggering and PWM signal generation.

[0046] (3) Unequal-interval pulse train output: Outputs pulse sequences according to a predefined timing table. The timing table supports a maximum of 65536 records, each record containing: the interval between adjacent pulses (4-byte unsigned integer, in μs) and the pulse width (4-byte unsigned integer, in μs). When a trigger occurs, the internal AXI DMA master control engine is activated, and the timing table is read directly from DDR4 via the AXI high-speed bus and sent to the logic generator. This mode is used for complex experimental processes executed according to a predetermined timing sequence, and can achieve precise output of arbitrarily complex pulse sequences.

[0047] Finally, the generated clock and waveform are output through a multi-channel output driver module, providing multiple independent trigger output channels. Each channel supports multiple level standards such as TTL, LVDS, and RS422, and the output polarity can be configured.

[0048] Based on the same inventive concept, this embodiment also proposes a programmable multi-mode precision time triggering method (device operation flow) based on PTP. The specific operation flow of this method is described in detail below in conjunction with the system architecture: Step S1: PTP Clock Synchronization: After the device is powered on, it establishes a physical connection with the PTP master clock through the Ethernet port and the Gigabit Ethernet PHY chip, runs the PTPd protocol to complete clock synchronization, and establishes a local time reference with an accuracy better than ±20ns with the master clock under the hardware and software Kalman filtering and PID closed-loop regulation.

[0049] Step S2: Clock and Event Trigger Configuration: Clock and event trigger configuration commands (including clock signal frequency and output channel, trigger mode selection, trigger time / delay setting, output channel allocation, waveform type and parameter configuration, group affiliation, etc.) issued by the host computer are input via Ethernet port or UART interface. These commands are then uniformly parsed and verified by the command configuration module. The verified configuration information is written to the event queue in DDR4 memory via the internal AXI bus by the soft core. If the system detects an anomaly, it can also execute commands to cancel the trigger output of a single channel, group, or all events, thus canceling the corresponding unexecuted trigger events.

[0050] Step S3: Clock signal configuration output: After power-on, the system's eight clock channels output a 10MHz clock signal by default. Subsequently, the clock output channel and output frequency can be specified through the received clock configuration command, thereby changing the clock signal output of each channel.

[0051] Step S4: Event Scheduling and Trigger Configuration Output: The hardware scheduler continuously scans the event queue and executes scheduling according to the trigger mode: For absolute time-triggered events, the target time is compared with the current PTP time; for relative time-triggered events, the start signal is monitored and the target time is calculated; for immediate-triggered events, the command is executed immediately upon arrival. When the event reaches its trigger time, the waveform generation module outputs the corresponding waveform on the designated channel according to the configuration parameters (single pulse, equally spaced pulse train, or unequal interval timing table).

[0052] Finally, status feedback is provided: after the configuration command is executed, the device operating status is updated, the execution log is recorded and written to the memory, and optionally, the configuration output status notification is sent to the host computer via the network.

[0053] Example 2 To further illustrate the customizability and high scalability of the system architecture of this invention in different application scenarios, this invention also provides a precision time synchronization and timing triggering system for tokamak devices. This embodiment, based on the system architecture described in Embodiment 1, provides a central timing system (i.e., a high-performance configuration version) for use in a tokamak nuclear fusion experimental device.

[0054] In this application scenario, due to the need to coordinate hundreds of diagnostic measurement and control systems during plasma discharge, extremely high time accuracy is required. Therefore, in this embodiment, the specific selection and configuration of each core hardware component are as follows: The main control FPGA uses a single Xilinx Spartan-6 XC6SLX45 chip as the core processing unit. The voltage-controlled crystal oscillator is a high-precision temperature-controlled crystal oscillator (OCXO), which has extremely high frequency stability (better than 5×10⁻⁶). -10 ); The digital-to-analog converter employs a 16-bit high-resolution DAC; The memory uses 512MB of DDR4 memory to support large event queues and complex unequal interval pulse timing tables; The clock signal generation module is configured to output 8 clock frequencies, and the trigger waveform generation module is configured to output 4 groups of event trigger signals, totaling 16 channels.

[0055] When operating internally, the main control FPGA calls the MicroBlaze soft-core processor, and deploys hardware modules such as a gigabit MAC module, IEEE 1588 IP core, trigger generation IP core, frequency generation IP core, and GPIO (general purpose input / output) on its internal logic periphery. Simultaneously, the soft core runs the LWIP network protocol stack, PTPd protocol, Kalman filter algorithm, and PID control algorithm. The device establishes a connection with the PTP master clock via gigabit Ethernet, providing precise time synchronization and event triggering services for approximately 200 diagnostic measurement subsystems within the device.

[0056] Experimental data demonstrates that after 30 days of continuous operation testing in a real-world environment, the PTP clock synchronization accuracy of this embodiment is stable at ±38 ns, the absolute time triggering accuracy is ±45 ns, the relative time triggering accuracy is better than ±40 ns, and the cancellation response time for events not yet executed is better than 100 μs. These data indicate that this embodiment effectively overcomes the time delay bottleneck in hardware-software integrated systems and fully meets the stringent requirements of multi-system coordinated control in tokamak plasma physics experiments.

[0057] Example 3 This embodiment also provides a low-cost configuration version for industrial automation scenarios based on the system architecture described in Embodiment 1.

[0058] In some industrial control and communication system timing scenarios, the requirements for extreme accuracy are slightly relaxed, but the cost per unit and deployment scale remain extremely sensitive. Based on the programmable hardware-software co-engineering architecture of this invention, high-performance synchronous control can be achieved through hardware downsizing and logic customization. Specific configurations are as follows: The main control FPGA was replaced with a Xilinx Spartan-6 XC6SLX25 chip with fewer logic resources. The voltage-controlled crystal oscillator uses a temperature-compensated crystal oscillator (TCXO) to replace the high-cost OCXO; The digital-to-analog converter is downgraded to a 14-bit DAC; The memory uses a 56MB DDR3 memory. The external physical channels have also been streamlined accordingly, configured as 2 clock signal output channels and 2 event trigger output channels.

[0059] In this embodiment, although the PTP clock synchronization accuracy is slightly lower than in Embodiment 2 due to the decreased crystal oscillator stability and reduced DAC resolution, it still meets the needs of most industrial high-speed synchronous control applications. More importantly, based on this customizable architecture, the hardware cost of a single device can be reduced by more than 40%, greatly improving the economic efficiency and promotional value of the system in large-scale industrial deployment.

[0060] The embodiments described above merely illustrate specific implementation methods of this application, and while the descriptions are detailed and specific, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the technical solution of this application, and these modifications and improvements all fall within the scope of protection of this application.

[0061] This background section is provided to generally present the context of the invention. The work of the currently named inventors, the work to the extent described in this background section, and aspects of this section that did not constitute prior art at the time of application are neither expressly nor impliedly acknowledged as prior art to the invention.

Claims

1. A programmable multi-mode precision time triggering system based on PTP, characterized in that, include: The main control FPGA, and a gigabit Ethernet PHY chip, a voltage-controlled crystal oscillator, a digital-to-analog converter, and a memory respectively connected to the main control FPGA; The main control FPGA has an embedded soft core processor and is configured with hardware logic. The soft core processor and the hardware logic work together to form a PTP clock synchronization module, an event management module, a trigger mode control module, a trigger waveform generation module, and a clock signal generation module. The PTP clock synchronization module is used to receive PTP protocol messages through the Gigabit Ethernet PHY chip to establish a local time reference, calculate control quantities based on clock deviation, and adjust the frequency of the voltage-controlled crystal oscillator through the digital-to-analog converter to achieve synchronization with the PTP master clock. The event management module is used to maintain an event queue sorted by trigger time in the memory. Each event record in the event queue contains at least an event ID, trigger mode, trigger time or delay parameter, waveform type and group ID, and supports cancellation operations for events that have not yet entered the execution state based on the event ID or the group ID. The trigger mode control module is used to perform trigger determination according to the trigger mode in the event record. The trigger modes include immediate trigger mode, absolute time trigger mode and relative time trigger mode. For the absolute time trigger mode, the current local time base is continuously matched with the target trigger time by the hardware comparator in the hardware logic to generate a trigger signal. The trigger waveform generation module is used to output a trigger waveform according to the waveform type in the event record when the trigger signal is received. The trigger waveform includes a single pulse, an equally spaced pulse train, and an unequally spaced pulse train. For the unequally spaced pulse train, the trigger waveform generation module drives the output according to a timing table stored in the memory. The timing table includes the interval parameter and pulse width parameter of adjacent pulses. The clock signal generation module is used to output a clock signal with a configurable frequency.

2. The programmable multi-mode precision time triggering system based on PTP according to claim 1, characterized in that, The specific implementation of the PTP clock synchronization module includes: The IEEE 1588 IP core embedded in the hardware logic of the main control FPGA is used to provide a real-time clock module including a time counter, as well as a receive timestamp generation module and a send timestamp generation module. The PTP software protocol stack running on the soft-core processor is used to process PTP protocol messages and calculate clock offset and frequency deviation. The soft-core processor is also equipped with a Kalman filter and a PID controller. The Kalman filter is used to filter the clock offset and the frequency deviation to suppress measurement noise. The PID controller is used to calculate the digital control voltage based on the filtered frequency deviation and adjust the frequency of the voltage-controlled crystal oscillator by outputting the control voltage through the digital-to-analog converter.

3. The programmable multi-mode precision time triggering system based on PTP according to claim 1, characterized in that, When the trigger mode control module executes the relative time trigger mode: Monitor the start signal, start a delay count upon receiving the start signal, and generate the trigger signal after the configured delay time parameter is reached; The sources of the start signal include network command signals, external general purpose input / output (GPIO) signals, or trigger signals output by another triggered event in the system, so as to realize cascading triggering between events.

4. The programmable multi-mode precision time triggering system based on PTP according to claim 1, characterized in that, It also includes a multi-channel output driver module, which provides multiple independent trigger output channels; The trigger waveform generation module supports configuring pulse polarity and generates a single pulse signal of specified polarity according to the configured pulse width parameter when outputting the single pulse; When outputting the equally spaced pulse train, a pulse sequence with a fixed period is generated according to the preset pulse interval parameter, pulse width parameter, and pulse number parameter, and output through the specified trigger output channel.

5. A programmable multi-mode precision time triggering system based on PTP according to claim 1, characterized in that, The event management module is also used to update the event status of each event record in the event queue, including waiting, executing, completed, canceled, and error; The main control FPGA is also configured to record the actual execution time and execution result of each event to generate an event execution log, and store the event execution log in the memory.

6. A programmable multi-mode precision time triggering method based on PTP, applied to the programmable multi-mode precision time triggering system based on PTP as described in any one of claims 1 to 5, characterized in that, Includes the following steps: Step S1: Receive PTP protocol messages from the PTP master clock through the Gigabit Ethernet PHY chip, calculate the clock deviation, and adjust the frequency of the voltage-controlled crystal oscillator through a digital-to-analog converter to establish a local time reference synchronized with the PTP master clock; Step S2: Receive trigger configuration information, maintain an event queue sorted by trigger time in the memory, generate an event record containing event ID, trigger mode, trigger time or delay parameter, waveform type and group ID; and when a cancellation instruction is received, cancel the event that has not yet entered the execution state based on the event ID or the group ID. Step S3: Execute trigger scheduling according to the trigger mode in the event record. The trigger modes include immediate trigger mode, absolute time trigger mode, and relative time trigger mode. For absolute time trigger mode, the current local time base is continuously matched with the target trigger time through a hardware comparator, and a trigger signal is generated when the time matches. Step S4: Upon receiving the trigger signal, output a trigger waveform containing a single pulse, an equally spaced pulse train, or an unequally spaced pulse train according to the waveform type in the event record; wherein, when outputting the unequally spaced pulse train, the output is driven by reading a timing table containing adjacent pulse interval parameters and pulse width parameters stored in the memory.

7. The programmable multi-mode precision time triggering method based on PTP according to claim 6, characterized in that, In step S1, the specific process of establishing a synchronized local time base includes: The generation of timestamps and the maintenance of real-time clocks are achieved through hardware logic in the main control FPGA. Clock skew and frequency deviation are calculated by running the PTP software protocol stack on a soft-core processor. The clock offset and frequency deviation are filtered using a Kalman filter, and the filtering result is input into a PID controller to calculate the digital control voltage, which drives the digital-to-analog converter to adjust the output frequency of the voltage-controlled crystal oscillator.

8. A programmable multi-mode precision time triggering method based on PTP according to claim 6, characterized in that, In step S3, when executing the relative time trigger mode, the specific steps include: Monitor startup signals, including network command signals, external GPIO signals, or cascaded trigger event signals; After the start signal is captured, hardware delay counting is started based on the local time base; The trigger signal is generated when the delay count reaches the time interval defined by the delay parameter.

9. A programmable multi-mode precision time triggering method based on PTP according to claim 6, characterized in that, The specific process of outputting the equally spaced pulse train in step S4 includes: Parse the pulse interval parameter, pulse width parameter, and pulse count parameter in the event record; Generate a pulse sequence with a fixed period based on the analyzed parameters; According to the configured pulse polarity and channel allocation instructions, the pulse sequence is output to the corresponding physical channel through the multi-channel output driver module.

10. A programmable multi-mode precision time triggering method based on PTP according to claim 6, characterized in that, The method further includes: During the triggering and scheduling process, the event status of each event record in the event queue is updated in real time to the status of waiting, executing, completed, canceled, or error. When an event enters a completed or error state, the actual execution time and execution result are recorded, an execution log is generated and written to the memory for export verification.

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