A computing power and power cooperative scheduling method, system, device and computer program product for a data center cluster

Abstract

The present application relates to the technical field of data center heterogeneous computing power scheduling, and discloses a computing power and power collaborative scheduling method, system, device and computer program product for a data center cluster, wherein the method comprises: constructing a power consumption performance proxy model; estimating a task migration cost parameter; allocating a target power quota for each heterogeneous computing power hardware; performing matching scheduling of task instances and heterogeneous computing power hardware; and performing closed-loop correction on the power consumption performance proxy model. Compared with the prior art which relies on rule thresholds for coarse-grained scheduling, especially under the condition that the power consumption performance difference of heterogeneous hardware is obvious and the task migration exists cache preheating energy consumption rebound, the technical problem that throughput improvement and migration cost suppression cannot be considered. Due to the power consumption performance proxy modeling, task migration cost estimation, power budget allocation, marginal utility matching scheduling and closed-loop model correction, the effective throughput and running stability of the data center cluster under the limited power condition are improved.

Description

Technical Field

[0001] This invention relates to the field of heterogeneous computing power scheduling technology in data centers, and in particular to a method, system, device and computer program product for the coordinated scheduling of computing power and power for data center clusters. Background Technology

[0002] With the rapid development of cloud computing and artificial intelligence applications, data centers are undertaking a large number of heterogeneous computing tasks. Data center clusters typically deploy various computing hardware, including GPUs, CPUs, FPGAs, and ASICs, which differ significantly in computing power, power consumption characteristics, and energy efficiency. To improve overall resource utilization and energy efficiency, different computing tasks need to be rationally allocated to appropriate hardware while meeting the power capacity limits and thermal safety constraints of the entire cluster. However, in actual operation, the operating status of the hardware (such as temperature and frequency) and load patterns change dynamically, resulting in a non-fixed relationship between power consumption and performance, posing challenges to precise scheduling.

[0003] Existing scheduling methods often employ static or rule-based power budget allocation strategies, such as allocating fixed power quotas according to hardware specifications or simply limiting the frequency of some hardware when power limits are exceeded. These methods fail to fully consider the characteristics of task loads and the real-time power consumption performance of each hardware component, easily leading to some hardware remaining idle while others experience performance degradation due to insufficient power. Furthermore, when tasks migrate between hardware with different architectures, differences in instruction sets, cache structures, and data layouts can cause additional transient power consumption spikes and a period of performance recovery. This migration cost is ignored or handled with fixed penalties in existing scheduling methods, causing the cluster's instantaneous total power to exceed the preset limit, affecting power supply safety and system stability. Moreover, hardware power consumption performance models gradually shift with usage time and ambient temperature, making it difficult for fixed offline models to maintain accuracy over long periods. Therefore, there is an urgent need for a method that can characterize power consumption performance online, predict migration costs, and perform closed-loop collaborative optimization of power allocation and task scheduling. Summary of the Invention

[0004] To address the aforementioned technical shortcomings, the present invention aims to propose a computing power and power collaborative scheduling method, system, device, and computer program product for data center clusters. This invention aims to solve the technical problem that existing technologies rely on rule thresholds for coarse-grained scheduling, especially under conditions where there are significant differences in power consumption and performance of heterogeneous hardware and energy consumption rebound during task migration due to cache warm-up. This makes it impossible to simultaneously improve throughput and suppress migration costs.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: The present invention provides a method for the coordinated scheduling of computing power and power for data center clusters.

[0006] The aforementioned method for coordinated scheduling of computing power and power for data center clusters includes: Step S10: Obtain hardware operating status data of each heterogeneous computing hardware, perform power consumption performance characterization task based on hardware operating status data, and output power consumption performance proxy model; Step S20: Based on the power consumption performance proxy model, the task migration cost estimation task is performed using Hamming distance matching and exponential moving average prediction method, and the task migration cost parameters are output. Step S30: Based on the task migration cost parameters and the power consumption performance proxy model, perform power budget allocation and output the target power quota for each heterogeneous computing hardware. Step S40: Based on the target power quota, use the marginal utility greedy algorithm to perform the matching and scheduling task between task instances and heterogeneous computing hardware, and output the task instance and device binding relationship; Step S50: Based on the task instance and device binding relationship, task issuance and execution status monitoring are performed, and the Bellman residual update method is used to perform closed-loop correction on the power consumption performance proxy model, and the updated power consumption performance proxy model is output.

[0007] Preferably, step S10, which involves acquiring hardware operating status data for each heterogeneous computing hardware, performing a power consumption performance characterization task based on the hardware operating status data, and outputting a power consumption performance proxy model, specifically includes: Step S101: Collect the operating frequency, voltage, chip junction temperature, computing unit utilization, on-chip cache hit rate, video memory utilization, and input / output bandwidth utilization of each heterogeneous computing hardware in the current scheduling cycle, and combine the collected results into hardware operating status data. Step S102: Based on the hardware operating status data, the operating frequency, voltage and chip junction temperature are used as gray box power consumption mechanism variables, and the computing unit utilization, on-chip cache hit rate, video memory occupancy rate and input / output bandwidth occupancy rate are used as online correction variables to construct the power consumption prediction function for each heterogeneous computing hardware. Step S103: Obtain historical throughput samples. Based on the power consumption prediction function and the historical throughput samples, use a multi-task online learning method to jointly train the power consumption prediction relationship and throughput prediction relationship corresponding to GPU, CPU, FPGA and ASIC, and obtain the power consumption performance proxy model.

[0008] Preferably, step S20, which involves performing the task migration cost estimation task based on the power consumption performance proxy model using Hamming distance matching and exponential moving average prediction method, and outputting the task migration cost parameters, specifically includes: Step S201: Obtain the operator type, model size, number of parameters, input / output data throughput, memory access density, and separable granularity, and generate a task semantic hash code based on the operator type, model size, number of parameters, input / output data throughput, memory access density, and separable granularity; Step S202: Calculate the Hamming distance between the task semantic hash code and the historical task semantic hash code corresponding to the most recently executed task of each heterogeneous computing hardware, and combine the historical idle time, data migration amount, cache retention degree and architecture reconstruction cost of the target heterogeneous computing hardware to obtain the task switching difference. Step S203: Based on the task switching difference, call the power performance proxy model output in step S10, and use the exponential moving average prediction method to estimate the power rebound degree and performance recovery time after task migration, so as to obtain the task migration cost parameter.

[0009] Preferably, in step S202, the Hamming distance is calculated between the task semantic hash code and the historical task semantic hash code corresponding to the most recently executed task of each heterogeneous computing hardware, and combined with the historical idle time, data migration amount, cache retention degree and architecture reconstruction cost of the target heterogeneous computing hardware, to obtain the task switching difference, including: The task switching difference is calculated using the following formula:

[0010] in, Represents a task instance Migration to heterogeneous computing hardware Task switching difference during the time Represents a task instance Task semantic hash code heterogeneous computing hardware Semantic hash code of recently executed tasks Hamming distance between them Represents a task instance The sum of the number of model parameters, input data, and intermediate cache data that need to be moved. Indicates heterogeneous computing hardware Available data transmission bandwidth in the current scheduling period Indicates heterogeneous computing hardware Historical idle time Represents a task instance Migrating from the original execution architecture to heterogeneous computing hardware The cost of architectural adaptation at that time Indicates heterogeneous computing hardware The degree to which the current on-chip cache or video memory cache retains hits on data of the same type of task. This represents a constant used to prevent the denominator from being zero. , , , and These represent the weight coefficients of the corresponding items; Among them, the architecture adaptation cost The architecture adaptation cost is determined based on the operator type of the task instance and the execution structure of the target heterogeneous computing hardware. When the task instance is migrated from a general-purpose CPU to a GPU, the architecture adaptation cost includes at least the tensor execution graph reconstruction cost; when the task instance is migrated from a GPU to an FPGA, the architecture adaptation cost includes at least the computation pipeline reconfiguration cost; and when the task instance is migrated from a GPU or FPGA to an ASIC, the architecture adaptation cost includes at least the fixed operator mapping constraint cost. Based on the aforementioned task switching difference, the migration bounce power is estimated using the following formula:

[0011] in, Represents a task instance Migration to heterogeneous computing hardware The resulting migration rebound power, Indicates heterogeneous computing hardware The baseline power predicted by the power performance surrogate model at the current frequency and voltage. This represents the bounce amplification factor obtained by mapping the task switching difference. Indicates heterogeneous computing hardware The normalized value of the chip junction temperature. This indicates the temperature amplification weight.

[0012] Preferably, step S30, which involves allocating power budget based on the task migration cost parameter and the power consumption performance proxy model, and outputting the target power quota for each heterogeneous computing hardware, specifically includes: Step S301: Obtain the cluster power limit, the measured total power of the cluster in the current scheduling period, the current chip junction temperature of each heterogeneous computing hardware, and the migration bounce power obtained in step S20, and construct a temperature-coupled power deviation virtual queue. Step S302: Call the power performance proxy model output in step S10 to predict the throughput gain of each heterogeneous computing hardware under different candidate power allocation values, and calculate the drift penalty target value for each candidate power allocation value based on the temperature-coupled power deviation virtual queue and throughput gain. Step S303: Under the condition of meeting the cluster power limit and the preset single device temperature safety threshold, select the candidate power allocation value with the smallest drift penalty target value as the target power quota of each heterogeneous computing hardware, and send the target power quota to step S40; The temperature-coupled power deviation virtual queue is updated according to the following formula:

[0013] in, Indicates the first Temperature-coupled power deviation virtual queue for each scheduling cycle Indicates the first The measured total power of the cluster over a scheduling cycle. Indicates the first heterogeneous computing hardware within a scheduling cycle Migration bounce power caused by task switching Indicates heterogeneous computing hardware In the Normalized chip junction temperature value within a scheduling cycle Indicates heterogeneous computing hardware The corresponding safe temperature threshold, This represents the weighting factor used to convert temperature exceedances into power risk. Indicates the maximum power of the cluster. Indicates the number of heterogeneous computing hardware units. This represents the temperature-coupled power deviation virtual queue in the (t+1)th scheduling cycle, where t+1 represents the next scheduling cycle after the t-th scheduling cycle. This indicates taking the larger value between the number inside the parentheses and 0; The drift penalty target value is determined according to the following formula:

[0014] in, Indicates the first The target value for drift penalty per scheduling cycle. Indicates the throughput revenue weight. This represents the heterogeneous computing power hardware predicted by the power consumption performance proxy model. throughput, This indicates the attenuation weight of temperature on effective throughput.

[0015] Preferably, step S40, which involves using a marginal utility greedy algorithm to perform a matching and scheduling task between task instances and heterogeneous computing hardware based on the target power quota, and outputting the task instance-device binding relationship, specifically includes: Step S401: Divide the online arrival tasks into multiple task instances and generate a set of task instances to be scheduled; Step S402: Based on the target power quota output in step S30, calculate the marginal throughput gain, marginal power consumption, migration bounce penalty, data dependency waiting penalty and parallel fragmentation penalty for each task instance when bound to GPU, CPU, FPGA and ASIC respectively, and obtain the marginal utility value of the task instance relative to each heterogeneous computing power hardware. Step S403: Perform greedy matching on the set of task instances to be scheduled according to the marginal utility value, and determine the binding relationship between the task instance and the device under the condition that the target power quota is not exceeded and the preset data dependency relationship is not violated.

[0016] Preferably, in step S40, the marginal utility value is determined according to the following formula:

[0017] in, Represents a task instance Binding to heterogeneous computing hardware The marginal utility value at that time Represents a task instance Task priority weights Represents a task instance Binding to heterogeneous computing hardware Marginal throughput gain at that time Represents a task instance Binding to heterogeneous computing hardware Marginal power consumption at that time Represents a task instance Migration to heterogeneous computing hardware The resulting migration rebound power, Represents a task instance Binding to heterogeneous computing hardware The waiting time caused by data dependencies Represents a task instance Binding to heterogeneous computing hardware The degree of parallel fragmentation caused by this This indicates the migration bounce power penalty weight. This indicates the data dependency waiting penalty weight. Indicates the weight of the parallel fragmentation penalty. This represents a constant to prevent the denominator from being zero; Wherein, the degree of parallel fragmentation The degree of mismatch between the remaining computing power capacity of heterogeneous computing hardware after task instance binding and the demand of subsequent task instances is determined according to the following formula:

[0018] in, Indicates heterogeneous computing hardware Bind task instance The remaining available computing power capacity after that, This indicates the pre-computational power requirement for subsequent high-priority task instances in the set of task instances to be scheduled.

[0019] This invention also provides a computing power and power coordinated scheduling system for data center clusters, comprising: The power consumption performance characterization module is used to acquire hardware operating status data of various heterogeneous computing hardware, perform power consumption performance characterization tasks based on hardware operating status data, and output a power consumption performance proxy model. The migration cost estimation module is used to perform the task migration cost estimation task based on the power consumption performance proxy model using Hamming distance matching and exponential moving average prediction method, and output the task migration cost parameters. The power budget allocation module is used to allocate power budget based on the task migration cost parameter and the power consumption performance proxy model, and output the target power quota for each heterogeneous computing hardware. The matching and scheduling module is used to perform matching and scheduling tasks between task instances and heterogeneous computing hardware based on the target power quota and using a marginal utility greedy algorithm, and output the task instance and device binding relationship. The closed-loop correction module is used to issue tasks and monitor their execution status based on the task instance and device binding relationship, and to perform closed-loop correction on the power performance proxy model using the Bellman residual update method, outputting the updated power performance proxy model.

[0020] The present invention also provides a computing power and power coordinated scheduling device for data center clusters. The computing power and power coordinated scheduling device for data center clusters includes: a memory, a processor, and a computing power and power coordinated scheduling program for data center clusters stored in the memory and executable on the processor. When the computing power and power coordinated scheduling program for data center clusters is executed by the processor, it implements the above-mentioned method.

[0021] The present invention also provides a computer program product, which includes a computing power and power coordinated scheduling program for data center clusters, wherein the computing power and power coordinated scheduling program for data center clusters implements the above-mentioned method when executed by a processor.

[0022] The beneficial effects of this invention are as follows: By collecting multi-dimensional operating data such as operating frequency, voltage, chip junction temperature, and computing unit utilization of various heterogeneous computing hardware, a gray-box power consumption prediction function combining mechanistic variables and online correction variables is constructed. Multi-task online learning is then used to jointly train power consumption and throughput prediction models for different hardware, enabling the power performance proxy model to reflect the real energy efficiency relationship of hardware under different loads in real time. Based on this, subsequent migration cost estimation and power budget allocation can be based on predictions that more closely resemble actual conditions, helping to improve the rationality of decision-making.

[0023] By matching the semantic hash codes of the task with Hamming distance and those of historical tasks, the differences between tasks in terms of operator type, model size, etc., are quantified. Combined with data migration volume, cache retention, and architecture adaptation costs, the potential power rebound magnitude and performance recovery time after task migration can be estimated. Incorporating this migration cost parameter into the calculation of power budget and target power quota allows power allocation and scheduling decisions to predict the additional power demand caused by migration, thereby reducing the probability of exceeding the cluster power limit. Simultaneously, the Bellman residual update method is used to perform online correction of the proxy model based on actual monitoring data after scheduling execution, enabling the model to continuously adapt to hardware state changes and maintain the effectiveness of collaborative scheduling. Attached Figure Description

[0024] Figure 1 This is a flowchart illustrating the first embodiment of a computing power and power coordinated scheduling method for data center clusters according to the present invention. Detailed Implementation

[0025] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0026] Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0027] Example 1: As Figure 1 The diagram shown is a flowchart of the first embodiment of a computing power and power coordinated scheduling method for data center clusters according to the present invention. The first embodiment of the computing power and power coordinated scheduling method for data center clusters according to the present invention is presented.

[0028] In the first embodiment, the computing power and power coordinated scheduling method for data center clusters includes: Step S10: Obtain hardware operating status data of each heterogeneous computing hardware, perform power consumption performance characterization task based on hardware operating status data, and output power consumption performance proxy model; The hardware operating status data includes parameters such as operating frequency, core voltage, chip junction temperature, computing unit utilization, on-chip cache hit rate, video memory utilization, and input / output bandwidth utilization, all collected in real time during the operation of each heterogeneous computing hardware. The power consumption performance characterization task refers to constructing a power consumption prediction function that can adjust with changes in operating status, based on this status data and using gray-box modeling. This function uses operating frequency, voltage, and chip junction temperature as basic variables reflecting the physical power consumption mechanism of the hardware, and computing unit utilization and cache hit rate as online correction variables. Simultaneously, historical throughput samples are acquired, and a multi-task online learning method is used to establish mapping relationships between power consumption and throughput for GPUs, CPUs, FPGAs, and ASICs respectively. Different hardware models are jointly trained to share underlying features, ultimately obtaining a power consumption performance proxy model. This proxy model outputs the predicted power consumption and predicted throughput of each heterogeneous hardware in the current or candidate states, providing input for step S20 to estimate the baseline power after task migration and for step S30 to evaluate the throughput gains under different power allocations.

[0029] Further, in step S10, the current scheduling period is divided into multiple consecutive time segments according to a preset time granularity, and hardware operating status data of each heterogeneous computing hardware is collected in each time segment. For any heterogeneous computing hardware, the state estimate of the previous time segment and the measured state value of the current time segment are used as inputs, and exponential smoothing, recursive filtering, or online gradient update methods are used to iteratively update the operating frequency, voltage, chip junction temperature, computing unit utilization, on-chip cache hit rate, video memory utilization, and input / output bandwidth utilization, forming a hardware operating status sequence with time indexes. The power consumption performance proxy model outputs predicted power consumption and predicted throughput under different time segments based on the hardware operating status sequence with time indexes, enabling steps S20 to S40 to perform migration cost estimation, power budget allocation, and task matching scheduling based on the hardware state of the latest time segment. The current scheduling period can be divided into multiple time segments, for example, forming a time segment every few seconds. For the k-th time slice, the state vectors of each GPU, CPU, FPGA, and ASIC are recorded. These state vectors include at least the operating frequency, voltage, chip junction temperature, computing unit utilization, on-chip cache hit rate, memory occupancy, and input / output bandwidth occupancy. Then, the state estimation results of the (k-1)-th time slice are fused with the acquisition results of the k-th time slice to obtain the updated state estimation results for the k-th time slice. If a piece of hardware experiences frequency reduction, frequency increase, task migration in, task migration out, or rapid temperature changes in an adjacent time slice, the power consumption prediction relationship and throughput prediction relationship correction terms corresponding to that hardware are recalculated in the next time slice, and the corrected time slice state is used as the input for subsequent power budgeting and matching scheduling. Therefore, step S10 does not only form a static hardware profile at the beginning of the scheduling cycle, but continuously iterates and updates according to the hardware's operating state in specific time slices, enabling the proxy model to reflect the temporal evolution of the hardware state.

[0030] By comprehensively considering the hardware physical mechanism and real-time load status, and by utilizing multi-task online learning to adapt to the characteristics of various heterogeneous hardware, the power consumption performance proxy model can more accurately reflect the power consumption and performance relationship of different hardware in the cluster under actual mixed loads, reducing the possibility of subsequent scheduling decision errors caused by model bias.

[0031] Traditional methods often employ independent offline models or rely on simple linear mappings based on only a few metrics (such as utilization), making it difficult to capture the non-linear changes in hardware power consumption under different temperature and load modes. This approach, however, utilizes gray-box modeling and multi-task online learning. This leverages physical priors to reduce the training difficulty and overfitting risk of pure black-box models, while simultaneously tracking hardware state changes through online variable correction, thereby achieving more stable representation capabilities in dynamic data center environments.

[0032] For example, in a data center node that manages multiple GPUs and FPGAs of different models, when the utilization rate of a GPU's computing unit increases from 50% to 80% and the chip junction temperature rises simultaneously, a simple power consumption model based solely on utilization may underestimate the increase in leakage power consumption caused by temperature. However, the proxy model constructed in this step can automatically adjust the predicted power consumption value according to the junction temperature change, so that step S30 can reserve sufficient margin when allocating power to avoid the actual power consumption of the GPU exceeding expectations and causing the node power to exceed the limit.

[0033] Step S20: Based on the power consumption performance proxy model, the task migration cost estimation task is performed using Hamming distance matching and exponential moving average prediction method, and the task migration cost parameters are output. The task semantic hash code is a fixed-length binary code generated by a hash function based on meta-information such as the operator type, model size, number of parameters, input / output data throughput, memory access density, and separable granularity of the task instance. Hamming distance matching refers to calculating the Hamming distance between the current task semantic hash code and the historical semantic hash codes of the most recently executed tasks on each heterogeneous hardware. This distance reflects the similarity of the two tasks in terms of computational features. Combining the target hardware's current available data transmission bandwidth, historical idle time, required data migration amount, cache hit retention rate, and architecture adaptation cost when migrating from the original architecture to the target architecture, the task switching difference is obtained. Then, the power performance proxy model from step S10 is called to obtain the baseline power of the target hardware at the current frequency and voltage. Combined with the switching difference, an exponential moving average method is used, based on power bounce and performance recovery data from similar migration events in the hardware's history, to predict the possible migration bounce power and performance recovery time of this task migration, forming the task migration cost parameters. These parameters are directly used as part of the power deviation virtual queue in step S30 and the marginal utility calculation in step S40.

[0034] By hashing and comparing task semantics with Hamming distance, the computational differences between different tasks can be automatically quantified, avoiding the incompleteness and subjectivity of manually defined features. Based on this, by comprehensively estimating migration costs by considering hardware state and architectural differences, fine-grained transient overhead information can be provided for scheduling, which is beneficial for considering these short-lived but impactful additional power consumption in advance when allocating power budgets.

[0035] Traditional schedulers typically calculate task migration costs using constant or fixed latency as the price, failing to reflect the actual differences between different tasks and hardware combinations. This leads to power surges on some migration paths that are far greater than the estimates, resulting in power violations. This new approach, however, uses semantic hash distance matching and exponential moving average prediction based on historical data to give migration cost estimation task-aware and hardware-aware capabilities, thus approximating real transient characteristics.

[0036] For example, when a graphics rendering task is migrated from a GPU to an FPGA, the FPGA needs to reload the bitstream configuration and computation pipeline. Furthermore, the task involves a large amount of texture data migration, resulting in a significant difference between its task semantic hash code and the hash code of tasks executed on the GPU historically. This leads to a high calculated Hamming distance. Combined with the FPGA's currently empty cache and the cost of architecture reconstruction, the switching difference is substantial. Therefore, by using an exponential moving average and referencing historical migration events with similar differences, it is estimated that the power will momentarily increase by approximately 20% after the migration, requiring a 2-second recovery time. This parameter is considered in subsequent power allocation to ensure that the allocated quota is conservative within the migration window.

[0037] Step S30: Based on the task migration cost parameters and the power consumption performance proxy model, perform power budget allocation and output the target power quota for each heterogeneous computing hardware. The temperature-coupled power deviation virtual queue is a virtual quantity that records historical cumulative power deviation. Its update formula integrates the current measured total power of the cluster, the migration bounce power of each hardware due to task migration, and the junction temperature exceedance of each hardware chip. Temperature exceedances are converted into equivalent power risks and added to the queue, forming a comprehensive measure of power and temperature constraints. The drift penalty target value is an optimization objective composed of the quadratic drift term of the virtual queue (reflecting queue stability) and the negative value of throughput gain with temperature decay. By minimizing this objective, a target power quota is determined for each heterogeneous hardware under the constraints of the cluster power limit and the preset single-device safe temperature threshold. This quota indicates the maximum power that each hardware is allowed to consume in the next scheduling cycle and serves as the power boundary when performing task instance matching in step S40.

[0038] By utilizing virtual queues and a drift penalty framework, long-term power constraints and thermal constraints can be loosely coupled into online optimization, enabling a balance between maximizing current throughput and maintaining controllable long-term power deviation in power allocation. At the same time, proactive management of hardware thermal state can be achieved through temperature coupling terms.

[0039] Traditional power budget allocation often relies on proportional allocation or meeting current demands, neglecting the cumulative effect of historical overruns. This can lead to temporary overruns being tolerated but accumulating into long-term heat dissipation issues; it also fails to directly incorporate temperature into power allocation targets. This step, by accumulating deviations through a virtual queue and using temperature overrun conversion, achieves online optimization of joint power and temperature constraints, enhancing the safety of cluster operation.

[0040] For example, during a certain scheduling cycle, due to the large number of tasks migrating in the previous cycle, the bounce power is high, and the junction temperature of several GPUs is close to the safe threshold, and the virtual queue length is large. At this time, the drift penalty optimization tends to reduce the target power quota of these GPUs and instead allocate the power quota to ASICs or CPUs with lower junction temperatures and higher expected throughput benefits, thereby maintaining a high total throughput without exceeding the overall power limit.

[0041] Step S40: Based on the target power quota, use the marginal utility greedy algorithm to perform the matching and scheduling task between task instances and heterogeneous computing hardware, and output the task instance and device binding relationship; The set of task instances to be scheduled is obtained by splitting online arriving tasks into subdivisible granularities. The marginal utility greedy algorithm calculates the marginal utility value of each task instance allocated to a GPU, CPU, FPGA, or ASIC, while satisfying the target power quotas and data dependencies of each heterogeneous hardware. This value is weighted by task priority, marginal throughput gain, marginal power consumption, migration bounce power penalty, data dependency waiting penalty, and parallel fragmentation penalty. The algorithm greedily matches according to the utility value from high to low, selecting the instance-hardware pair with the highest current utility at each step and updating the remaining power quota and hardware state until all instances are allocated or the power quota is exhausted. Finally, it outputs the task instance and device binding relationship.

[0042] By incorporating various practical scheduling constraints into the marginal utility function as penalty terms, greedy matching can provide a better binding scheme in polynomial time, avoiding the difficulty of solving integer programming when the scale is large. At the same time, it takes into account factors that are easily overlooked, such as migration cost and parallel fragmentation, which helps to improve the overall execution efficiency of heterogeneous hardware clusters.

[0043] Traditional scheduling often employs load balancing or greedy strategies based solely on throughput, failing to consider migration bounce power and data dependency waiting as utility factors. This can lead to power fluctuations due to frequent migrations and wasted hardware computing power caused by parallel fragmentation. This step introduces these penalty terms explicitly into the utility function, making the scheduling results more consistent with physical constraints and operational stability requirements.

[0044] For example, suppose a deep learning inference task has two instances and two candidate hardware options: a GPU and an FPGA. GPUs offer higher throughput gain but also higher power consumption and limited remaining power allowances; migrating to a GPU incurs a migration bounce penalty. FPGAs, on the other hand, have lower power consumption but slightly lower throughput gain and less fragmentation. Through marginal utility calculations, if the GPU's utility value is lower than the FPGA's, the algorithm will bind the instance to the FPGA, thus completing more instances within power constraints and preventing the GPU from exceeding its power limit.

[0045] Step S50: Based on the task instance and device binding relationship, task issuance and execution status monitoring are performed, and the Bellman residual update method is used to perform closed-loop correction on the power consumption performance proxy model, and the updated power consumption performance proxy model is output.

[0046] The Bellman residual update method involves continuously monitoring the actual power consumption and task throughput of heterogeneous hardware after task execution, and calculating the temporal difference residual between the actual observations and the predicted values ​​of the power performance surrogate model. Then, with the objective of minimizing the square of this residual, the parameters of the surrogate model are incrementally updated using methods such as gradient descent or recursive least squares, resulting in an updated power performance surrogate model. This updated model replaces the original model and is used in the next scheduling cycle, forming a closed loop.

[0047] Through closed-loop correction, the power performance proxy model can track the impact of hardware performance degradation, changes in ambient temperature, and load mode migration online, ensuring that the model predictions remain accurate and providing a reliable basis for scheduling decisions.

[0048] In traditional methods, models are typically trained offline and then fixed. As hardware characteristics change over time, model errors increase, leading to a decline in scheduling quality. This step employs Bellman residual updates, enabling the model to adapt online without requiring extensive offline retraining and ensuring scheduling continuity while achieving model evolution.

[0049] For example, if a GPU's heat dissipation module accumulates dust due to continuous high-load operation, its actual power consumption at the same frequency will be 3% higher than the model's prediction. By continuously monitoring and updating the Bellman residual, the proxy model gradually increases the power consumption prediction parameters of the GPU. In subsequent power budget allocation, the GPU will receive a relatively conservative quota, thereby avoiding power overrun events caused by model inaccuracies.

[0050] Example 2: Furthermore, the present invention provides a computing power and power coordinated scheduling system for data center clusters, employing a computing power and power coordinated scheduling method for data center clusters as described in the above embodiments, which can solve a technical problem related to computing power and power coordinated scheduling for data center clusters. The beneficial effects of the computing power and power coordinated scheduling system for data center clusters provided by the present invention are the same as those of the computing power and power coordinated scheduling method for data center clusters provided in the above embodiments, and other technical features of the computing power and power coordinated scheduling system for data center clusters are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0051] Example 3: This invention provides a computing power and power coordinated scheduling device for data center clusters. The device includes: at least one processor; and a memory communicatively connected to the at least one processor. The memory stores instructions executable by the at least one processor, which are then executed to enable the at least one processor to perform the computing power and power coordinated scheduling method for data center clusters described in Example 1. The computing power and power coordinated scheduling device for data center clusters in this embodiment may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital radio receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), and vehicle terminals (e.g., vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. This computing power and power coordinated scheduling device for data center clusters is merely an example and should not limit the functionality or scope of the invention. A computing power and power coordination scheduling device for data center clusters may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes based on a program stored in read-only memory or a program loaded from a storage device into random access memory. The random access memory also stores various programs and data required for the operation of the computing power and power coordination scheduling device for data center clusters. The processing unit, read-only memory, and random access memory are interconnected via a bus. I / O interfaces are also connected to the bus. Typically, the following systems can be connected to the I / O interface: input devices including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices including, for example, magnetic tapes, hard disks, etc.; and communication devices. The communication device allows the computing power and power coordination scheduling device for data center clusters to communicate wirelessly or wiredly with other devices to exchange data. While a computing power and power coordination scheduling device for data center clusters with various systems has been described, it should be understood that implementation or possession of all the described systems is not required. It can be implemented alternatively or with more or fewer systems.

[0052] Example 4: This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described method for coordinated scheduling of computing power and power for data center clusters. The computer program product provided by this invention can solve a technical problem related to coordinated scheduling of computing power and power for data center clusters. Compared with the prior art, the beneficial effects of the computer program product provided by this invention are the same as those of the method for coordinated scheduling of computing power and power for data center clusters provided in the above embodiments, and will not be repeated here.

[0053] In particular, according to the embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from a read-only memory. When the computer program is executed by a processing device, it performs the functions defined in the methods of the embodiments disclosed in this invention.

[0054] It should be understood that the various parts disclosed in this invention can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0055] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A method for coordinated scheduling of computing power and power for data center clusters, characterized in that, The data center cluster includes various heterogeneous computing hardware, which includes at least GPUs, CPUs, FPGAs, and ASICs. The method includes: Step S10: Obtain hardware operating status data of each heterogeneous computing hardware, perform power consumption performance characterization task based on hardware operating status data, and output power consumption performance proxy model; Step S20: Based on the power consumption performance proxy model, the task migration cost estimation task is performed using Hamming distance matching and exponential moving average prediction method, and the task migration cost parameters are output. Step S30: Based on the task migration cost parameters and the power consumption performance proxy model, perform power budget allocation and output the target power quota for each heterogeneous computing hardware. Step S40: Based on the target power quota, use the marginal utility greedy algorithm to perform the matching and scheduling task between task instances and heterogeneous computing hardware, and output the task instance and device binding relationship; Step S50: Based on the task instance and device binding relationship, task issuance and execution status monitoring are performed, and the Bellman residual update method is used to perform closed-loop correction on the power consumption performance proxy model, and the updated power consumption performance proxy model is output.

2. The computing power and power coordinated scheduling method for data center clusters as described in claim 1, characterized in that, Step S10, which involves acquiring hardware operating status data for each heterogeneous computing hardware, performing a power consumption performance characterization task based on the hardware operating status data, and outputting a power consumption performance proxy model, specifically includes: Step S101: Collect the operating frequency, voltage, chip junction temperature, computing unit utilization, on-chip cache hit rate, video memory utilization, and input / output bandwidth utilization of each heterogeneous computing hardware in the current scheduling cycle, and combine the collected results into hardware operating status data. Step S102: Based on the hardware operating status data, the operating frequency, voltage and chip junction temperature are used as gray box power consumption mechanism variables, and the computing unit utilization, on-chip cache hit rate, video memory occupancy rate and input / output bandwidth occupancy rate are used as online correction variables to construct the power consumption prediction function for each heterogeneous computing hardware. Step S103: Obtain historical throughput samples. Based on the power consumption prediction function and the historical throughput samples, use a multi-task online learning method to jointly train the power consumption prediction relationship and throughput prediction relationship corresponding to GPU, CPU, FPGA and ASIC, and obtain the power consumption performance proxy model.

3. The computing power and power coordinated scheduling method for data center clusters as described in claim 1, characterized in that, Step S20, which involves performing the task migration cost estimation task based on the power consumption performance proxy model using Hamming distance matching and exponential moving average prediction method, and outputting the task migration cost parameters, specifically includes: Step S201: Obtain the operator type, model size, number of parameters, input / output data throughput, memory access density, and separable granularity, and generate a task semantic hash code based on the operator type, model size, number of parameters, input / output data throughput, memory access density, and separable granularity; Step S202: Calculate the Hamming distance between the task semantic hash code and the historical task semantic hash code corresponding to the most recently executed task of each heterogeneous computing hardware, and combine the historical idle time, data migration amount, cache retention degree and architecture reconstruction cost of the target heterogeneous computing hardware to obtain the task switching difference. Step S203: Based on the task switching difference, call the power performance proxy model output in step S10, and use the exponential moving average prediction method to estimate the power rebound degree and performance recovery time after task migration, so as to obtain the task migration cost parameter.

4. The computing power and power coordinated scheduling method for data center clusters as described in claim 3, characterized in that, In step S202, the Hamming distance is calculated between the task semantic hash code and the historical task semantic hash code corresponding to the most recently executed task of each heterogeneous computing hardware. Combined with the historical idle time, data migration amount, cache retention level, and architecture reconstruction cost of the target heterogeneous computing hardware, the task switching difference is obtained, including: The task switching difference is calculated using the following formula: in, Represents a task instance Migration to heterogeneous computing hardware Task switching difference during the time Represents a task instance Task semantic hash code heterogeneous computing hardware Semantic hash code of recently executed tasks Hamming distance between them Represents a task instance The sum of the number of model parameters, input data, and intermediate cache data that need to be moved. Indicates heterogeneous computing hardware Available data transmission bandwidth in the current scheduling period Indicates heterogeneous computing hardware Historical idle time Represents a task instance Migrating from the original execution architecture to heterogeneous computing hardware The cost of architectural adaptation at that time Indicates heterogeneous computing hardware The degree to which the current on-chip cache or video memory cache retains hits on data of the same type of task. This represents a constant used to prevent the denominator from being zero. , , , and These represent the weight coefficients of the corresponding items; Among them, the architecture adaptation cost The architecture adaptation cost is determined based on the operator type of the task instance and the execution structure of the target heterogeneous computing hardware. When the task instance is migrated from a general-purpose CPU to a GPU, the architecture adaptation cost includes at least the tensor execution graph reconstruction cost; when the task instance is migrated from a GPU to an FPGA, the architecture adaptation cost includes at least the computation pipeline reconfiguration cost; and when the task instance is migrated from a GPU or FPGA to an ASIC, the architecture adaptation cost includes at least the fixed operator mapping constraint cost. Based on the aforementioned task switching difference, the migration bounce power is estimated using the following formula: in, Represents a task instance Migration to heterogeneous computing hardware The resulting migration rebound power, Indicates heterogeneous computing hardware The baseline power predicted by the power performance surrogate model at the current frequency and voltage. This represents the bounce amplification factor obtained by mapping the task switching difference. Indicates heterogeneous computing hardware The normalized value of the chip junction temperature. This indicates the temperature amplification weight.

5. A method for coordinated scheduling of computing power and power for data center clusters as described in claim 4, characterized in that, Step S30, which involves allocating power budget based on the task migration cost parameters and the power consumption performance proxy model, and outputting the target power quota for each heterogeneous computing hardware, specifically includes: Step S301: Obtain the cluster power limit, the measured total power of the cluster in the current scheduling period, the current chip junction temperature of each heterogeneous computing hardware, and the migration bounce power obtained in step S20, and construct a temperature-coupled power deviation virtual queue. Step S302: Call the power performance proxy model output in step S10 to predict the throughput gain of each heterogeneous computing hardware under different candidate power allocation values, and calculate the drift penalty target value for each candidate power allocation value based on the temperature-coupled power deviation virtual queue and throughput gain. Step S303: Under the condition of meeting the cluster power limit and the preset single device temperature safety threshold, select the candidate power allocation value with the smallest drift penalty target value as the target power quota of each heterogeneous computing hardware, and send the target power quota to step S40; The temperature-coupled power deviation virtual queue is updated according to the following formula: in, Indicates the first Temperature-coupled power deviation virtual queue for each scheduling cycle Indicates the first The measured total power of the cluster over a scheduling cycle. Indicates the first heterogeneous computing hardware within a scheduling cycle Migration bounce power caused by task switching Indicates heterogeneous computing hardware In the Normalized chip junction temperature value within a scheduling cycle Indicates heterogeneous computing hardware The corresponding safe temperature threshold, This represents the weighting factor used to convert temperature exceedances into power risk. Indicates the maximum power of the cluster. Indicates the number of heterogeneous computing hardware units. This represents the temperature-coupled power deviation virtual queue in the (t+1)th scheduling cycle, where t+1 represents the next scheduling cycle after the t-th scheduling cycle. This indicates taking the larger value between the number inside the parentheses and 0; The drift penalty target value is determined according to the following formula: in, Indicates the first The target value for drift penalty per scheduling cycle. Indicates the throughput revenue weight. This represents the heterogeneous computing power hardware predicted by the power consumption performance proxy model. throughput, This indicates the attenuation weight of temperature on effective throughput.

6. The computing power and power coordinated scheduling method for data center clusters as described in claim 1, characterized in that, Step S40, based on the target power quota, employs a marginal utility greedy algorithm to perform matching and scheduling tasks between task instances and heterogeneous computing hardware, and outputs the task instance-device binding relationship. Specifically, this includes: Step S401: Divide the online arrival tasks into multiple task instances and generate a set of task instances to be scheduled; Step S402: Based on the target power quota output in step S30, calculate the marginal throughput gain, marginal power consumption, migration bounce penalty, data dependency waiting penalty and parallel fragmentation penalty for each task instance when bound to GPU, CPU, FPGA and ASIC respectively, and obtain the marginal utility value of the task instance relative to each heterogeneous computing power hardware. Step S403: Perform greedy matching on the set of task instances to be scheduled according to the marginal utility value, and determine the binding relationship between the task instance and the device under the condition that the target power quota is not exceeded and the preset data dependency relationship is not violated.

7. A method for coordinated scheduling of computing power and power for data center clusters as described in claim 6, characterized in that, In step S40, the marginal utility value is determined according to the following formula: in, Represents a task instance Binding to heterogeneous computing hardware The marginal utility value at that time Represents a task instance Task priority weights Represents a task instance Binding to heterogeneous computing hardware Marginal throughput gain at that time Represents a task instance Binding to heterogeneous computing hardware Marginal power consumption at that time Represents a task instance Migration to heterogeneous computing hardware The resulting migration rebound power, Represents a task instance Binding to heterogeneous computing hardware The waiting time caused by data dependencies Represents a task instance Binding to heterogeneous computing hardware The resulting degree of parallel fragmentation This indicates the migration bounce power penalty weight. This indicates the data dependency waiting penalty weight. Indicates the weight of the parallel fragmentation penalty. This represents a constant to prevent the denominator from being zero; Wherein, the degree of parallel fragmentation The degree of mismatch between the remaining computing power capacity of heterogeneous computing hardware after task instance binding and the demand of subsequent task instances is determined according to the following formula: in, Indicates heterogeneous computing hardware Bind task instance The remaining available computing power capacity after that, This indicates the pre-computational power requirement for subsequent high-priority task instances in the set of task instances to be scheduled.

8. A computing power and power coordinated scheduling system for data center clusters, applied to the computing power and power coordinated scheduling method for data center clusters as described in any one of claims 1 to 7, characterized in that, The computing power and power coordinated scheduling system for data center clusters includes: The power consumption performance characterization module is used to acquire hardware operating status data of various heterogeneous computing hardware, perform power consumption performance characterization tasks based on hardware operating status data, and output a power consumption performance proxy model. The migration cost estimation module is used to perform the task migration cost estimation task based on the power consumption performance proxy model using Hamming distance matching and exponential moving average prediction method, and output the task migration cost parameters. The power budget allocation module is used to allocate power budget based on the task migration cost parameter and the power consumption performance proxy model, and output the target power quota for each heterogeneous computing hardware. The matching and scheduling module is used to perform matching and scheduling tasks between task instances and heterogeneous computing hardware based on the target power quota and using a marginal utility greedy algorithm, and output the task instance and device binding relationship. The closed-loop correction module is used to issue tasks and monitor their execution status based on the task instance and device binding relationship, and to perform closed-loop correction on the power performance proxy model using the Bellman residual update method, outputting the updated power performance proxy model.

9. A computing power and power coordinated scheduling device for data center clusters, characterized in that, The computing power and power coordinated scheduling device for data center clusters includes: a memory, a processor, and a computing power and power coordinated scheduling program for data center clusters stored in the memory and executable on the processor. When the computing power and power coordinated scheduling program for data center clusters is executed by the processor, it implements a computing power and power coordinated scheduling method for data center clusters according to any one of claims 1 to 7.

10. A computer program product, characterized in that, The computer program product includes a computing power and power coordinated scheduling program for data center clusters. When the computing power and power coordinated scheduling program for data center clusters is executed by the processor, it implements a computing power and power coordinated scheduling method for data center clusters according to any one of claims 1 to 7.

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