LDMOS device and method of forming the same

Abstract

The application provides an LDMOS device, which comprises a substrate, a drift region and a body region formed on the substrate, a gate formed on adjacent partial regions of the drift region and the body region, a drain region formed in the drift region away from the gate, and a buffer drain region layer formed on the drain region, the buffer drain region layer being located on the top of partial drift regions and on the top of all the drain regions. By adding the buffer drain region layer at the end of the drain region, the conductivity is enhanced, the on-resistance is reduced, the electric field under the field plate is reduced, the impact ionization effect of the high electric field under the field plate region near the end of the drain region is reduced, and the reliability of the LDMOS device is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an LDMOS device and a method for forming the same. Background Technology

[0002] High-voltage LDMOS is a key technology and core power switching device in high-voltage integrated circuits and power integrated circuits. In high-voltage LDMOS, to withstand high Vds, RESURF (reducing surface electric field) technology is typically used to design the drift region and field plate. Under turn-off or high voltage conditions, this results in a wide but imperfectly distributed depletion layer in the drift region (especially below the field plate edge near the drain). At the drain contact edge, field plate edge, or regions with high PN junction curvature, electric field lines converge densely, causing the local electric field peak to be much higher than the average electric field of an ideal parallel planar junction. In other words, for high-voltage LDMOS, under high Vds (drain voltage) conditions, there is a very high electric field below the field plate region near the drain. This high electric field is the source of harmful impulse ionization effects. Summary of the Invention

[0003] The purpose of this invention is to provide an LDMOS device and its formation method to solve the problem of harmful shock ionization effects caused by the very high electric field below the field plate region near the drain terminal.

[0004] To solve the above-mentioned technical problems, the present invention provides an LDMOS device, comprising:

[0005] A substrate on which drift regions and volume regions are formed;

[0006] A gate, the gate being located in an adjacent portion of the drift region and the body region;

[0007] A drain region, the drain region being located within the drift region on the side away from the gate;

[0008] A buffer leak layer is located on top of a portion of the drift region and on top of all the leak regions.

[0009] Optionally, the width of the buffer leak layer is greater than the width of the leak.

[0010] Optionally, it may also include a field plate located on the drift region and adjacent to the gate.

[0011] Optionally, the buffer leak layer extends from the top of the leak area to below the field plate and does not exceed the side of the field plate away from the leak area.

[0012] Optionally, the doping type of the buffer drain layer is the same as the doping type of the drain region and the doping type of the drift region.

[0013] Optionally, the doping concentration of the buffer drain layer is less than the doping concentration of the drain region and the doping concentration of the buffer drain layer is greater than the doping concentration of the drift region.

[0014] Based on the same inventive concept, the present invention also provides a method for forming an LDMOS device, comprising:

[0015] A substrate is provided on which drift regions and volume regions are formed;

[0016] A gate is formed, the gate being located in an adjacent portion of the drift region and the body region;

[0017] A drain region is formed, the drain region being located within the drift region on the side away from the gate;

[0018] A buffer leak layer is formed, which is located on top of a portion of the drift region and on top of all the leak regions.

[0019] Optionally, during the step of forming the drain region, a source region is also formed simultaneously, the source region being located within the body region.

[0020] Optionally, the drain region and the source region are formed using a first ion implantation process, and the buffer drain region layer is formed using a second ion implantation process.

[0021] Optionally, after forming the drain region, a metal silicide is formed on the drain region, the source region, and the gate region, with the metal silicide on the drain region covering only the drain region.

[0022] In the LDMOS device provided by this invention, the LDMOS device includes a substrate on which a drift region and a body region are formed. A gate is formed on an adjacent portion of the drift region and the body region. A drain region is formed in the drift region away from the gate. A buffer drain layer is formed on the drain region, and the buffer drain layer is located on top of a portion of the drift region and on top of all the drain regions. By adding a buffer drain layer at the drain end, this invention not only enhances conductivity and reduces on-resistance, but also reduces the electric field below the field plate, thereby reducing the impact ionization effect of the high electric field below the field plate region near the drain end and improving the reliability of the LDMOS device. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of an LDMOS device according to an embodiment of the present invention.

[0024] Figure 2 This is a flowchart of the method for forming an LDMOS device according to an embodiment of the present invention.

[0025] Figure 3This is a schematic diagram of the structure of an LDMOS device after the formation of the drift region and the body region according to an embodiment of the present invention.

[0026] Figure 4 This is a schematic diagram of the structure of the LDMOS device after the formation of the field plate according to an embodiment of the present invention.

[0027] Figure 5 This is a schematic diagram of the structure of an LDMOS device after gate oxide formation according to an embodiment of the present invention.

[0028] Figure 6 This is a schematic diagram of the structure of an LDMOS device after the gate is formed according to an embodiment of the present invention.

[0029] Figure 7 This is a schematic diagram of the structure of an LDMOS device after the source and drain regions are formed according to an embodiment of the present invention.

[0030] Figure 8 This is a schematic diagram of the structure of an LDMOS device after forming a buffer drain layer according to an embodiment of the present invention.

[0031] Figure 9 This is a schematic diagram of the structure of an LDMOS device after the formation of the barrier layer according to an embodiment of the present invention.

[0032] In the figure, 10-substrate; 11-buried layer; 12-drift region; 13-body region; 14-field plate; 14a-contact plug; 15-gate oxide; 16-gate; 17a-drain region; 17b-source region; 18-buffered drain layer; 19-barrier layer. Detailed Implementation

[0033] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present application. Repeated reference numerals may be used in the various embodiments; these repeated reference numerals are for simplicity and clarity only and do not indicate a relationship between the various embodiments.

[0034] Furthermore, in this application, spatial relationship terms such as "below," "under," "above," and "over" can be used to describe the relationship between one element and another in the accompanying drawings. In addition to the orientations shown in the drawings, these spatial relationship terms may also include different orientations of the device / structure during use (e.g., rotation of 90 degrees). The interpretation of the aforementioned spatial relationship terms should be adjusted accordingly for these different orientations.

[0035] In the description of this application, the term "connection" or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. For example, in this application, the formation of a first feature on a second feature can include direct or indirect contact between the first and second features.

[0036] In the embodiments described in this application, the term "about" or a term with an equivalent meaning can refer to a given number of values ​​that vary within, for example, 10% of the value. It is understood that for numerical values ​​not defined by terms such as "about" in this application, the numerical value may also have a certain range of fluctuation, provided that the desired technical effect of the embodiments of this application can be achieved, and the numerical values ​​described in the embodiments are merely exemplary.

[0037] Figure 1 This is a schematic diagram of the structure of an LDMOS device according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides an LDMOS device, including:

[0038] Substrate 10, on which drift region 12 and body region 13 are formed;

[0039] Gate 16, the gate 16 being located in an adjacent portion of the drift region 12 and the body region 13;

[0040] Drain region 17a, the drain region 17a being located within the drift region 12 on the side away from the gate 16;

[0041] A buffer leak layer 18 is located on top of a portion of the drift region 12 and on top of all the leak regions 17a.

[0042] In some embodiments, the substrate 10 further includes a buried layer 11, which includes a first buried layer and a second buried layer. The second buried layer is located on the first buried layer. The first buried layer is, for example, a buried layer of a first doping type, and the second buried layer is a buried layer of a second doping type. If the first doping type is, for example, N-type, then the second doping type is P-type. The first buried layer is an N-type buried layer (NBL), also known as a deep N-well (DNW). The second buried layer is a P-type buried layer (PBL). The first and second buried layers are used to modulate the surface electric field, helping the device achieve low on-resistance while maintaining high breakdown voltage. Drift region 12 and body region 13 are located on the second buried layer. The drift region 12 is of the first doping type and is an N-type drift region (NDFT). The N-type drift region is located between the gate edge and the drain and has a low doping concentration. While withstanding high voltage, the N-type drift region provides a low-resistance conduction path for majority carriers. The body region 13 is doped with the second doping type and is a P-body. A source region 17b is also formed within the body region 13. The source region 17b and the drain region 17a have the same doping type, both being N-type.

[0043] In some embodiments, sidewalls are formed on both sides of the gate 16, and the sidewalls include an ON (silicon oxide layer-silicon nitride layer) or an ONO (silicon oxide layer-silicon nitride layer-silicon oxide layer) stack.

[0044] In some embodiments, the LDMOS device further includes a field plate 14 located on the drift region 12 and adjacent to the gate 16. The field plate 14 is used to modulate the electric field distribution inside the LDMOS device to improve the breakdown voltage.

[0045] In some embodiments, the doping type of the buffer drain layer 18 is the same as that of the drain region 17a and the drift region 12. The doping type of the buffer drain layer 18 is a first doping type, that is, the doping type of the buffer drain layer 18 is N-type, and the buffer drain layer 18 is an N-type buffer drain (N-Buried Drain, NBD) layer. The doping concentration of the buffer drain layer 18 is less than that of the drain region 17a and greater than that of the drift region 12. The width of the buffer drain layer 18 is greater than that of the drain region 17a. The buffer drain layer 18 extends from the top of the drain region 17a to below the field plate 14. This embodiment, by adding an N-type buffer drain (NBD) layer at the drain end, not only enhances conductivity and reduces on-resistance, but also reduces the electric field below the field plate, reducing the impact ionization effect of the high electric field below the field plate region near the drain end, and improving the reliability of the LDMOS device.

[0046] Figure 2 This is a flowchart illustrating the method for forming an LDMOS device according to an embodiment of the present invention. Figure 2 As shown, this embodiment also provides a method for forming an LDMOS device, including:

[0047] Step S10: Provide a substrate on which a drift region and a bulk region are formed;

[0048] Step S20: Form a gate, the gate being located in an adjacent region of the drift region and the body region;

[0049] Step S30: Form a drain region, the drain region being located in the drift region on the side away from the gate;

[0050] Step S40: A buffer leak layer is formed, which is located on top of a portion of the drift regions and on top of all the leak regions.

[0051] Figures 3 to 9 This is a schematic diagram showing the structural steps corresponding to the formation method of the LDMOS device according to an embodiment of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 3 to 9 Specific embodiments of the present invention will be described in detail below.

[0052] Figure 3 This is a schematic diagram of the LDMOS device structure after the formation of the drift region and body region according to an embodiment of the present invention. Figure 3 As shown, a substrate 10 is provided. In some embodiments, the substrate 10 can be a semiconductor substrate, made of any semiconductor material suitable for semiconductor devices (such as Si, SiC, SiGe, etc.). In other embodiments, the substrate 10 can also be various composite substrates such as silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGOI). The electron mobility of the silicon-germanium layer is higher than that of pure silicon. This high electron mobility can not only reduce noise, bias current, and feed power, but also increase the operating frequency. Compared with pure silicon, silicon-germanium can also achieve stable operating characteristics over a very wide temperature range. Therefore, silicon-germanium is widely used in bipolar and advanced CMOS devices. Those skilled in the art will understand that the substrate is not limited in any way, but can be selected according to the actual application.

[0053] Please continue to refer to this. Figure 3 The substrate 10 includes a buried layer 11, which comprises a first buried layer and a second buried layer. The second buried layer is located on the first buried layer. The first buried layer is, for example, a buried layer of a first doping type, and the second buried layer is a buried layer of a second doping type. If the first doping type is, for example, N-type, then the second doping type is P-type. The first buried layer is an N-type buried layer (NBL), also known as a deep N-well (DNW). The second buried layer is a P-type buried layer (PBL). The first and second buried layers are used to modulate the surface electric field, helping the device achieve low on-resistance while maintaining high breakdown voltage. A drift region 12 and a body region 13 are formed on the substrate 10. The drift region 12 and the body region 13 are located on the second buried layer. The drift region 12 is doped with the first doping type and is an N-type drift region (NDFT). The body region 13 is doped with the second doping type and is a P-type body region (P-body).

[0054] Figure 4 This is a schematic diagram of the structure of an LDMOS device after the formation of the field plate according to an embodiment of the present invention. Figure 4 As shown, a field plate 14 is formed, located above the drift region 12. The drift region 12 provides a depletable semiconductor region for the field plate 14, allowing the modulation effect of the field plate 14 to be fully utilized. The field plate is made of silicon oxide and can be formed using a chemical vapor deposition process.

[0055] Figure 5This is a schematic diagram of the structure of an LDMOS device after gate oxide formation according to an embodiment of the present invention. As shown, gate oxide 15 is formed, which covers the drift region 12, the body region 13, and the field plate 14. Gate oxide 15, together with the subsequently formed gate and channel, constitutes a metal-oxide-semiconductor (MOS) capacitor. By modulating the channel carrier concentration through the gate voltage, the source and drain currents are controlled, thereby realizing the switching or amplification function of the transistor. The material of gate oxide 15 is, for example, silicon oxide, which can be formed by thermal oxidation or chemical vapor deposition.

[0056] Figure 6 This is a schematic diagram of the LDMOS device after gate formation according to an embodiment of the present invention. Figure 6 As shown, a gate 16 and a contact plug 14a are formed above the field plate 14. The gate 16 is located in an adjacent region of the drift region 12 and the body region 13. The gate 16 and the contact plug 14a are made of, for example, polysilicon and can be formed using a chemical vapor deposition process. Sidewalls are formed on both sides of the gate 16 to protect it.

[0057] Figure 7 This is a schematic diagram of the structure of an LDMOS device after the source and drain regions are formed according to an embodiment of the present invention. Figure 7 As shown, a drain region 17a is formed within the drift region 12 on the side away from the gate 16; the drain region 17a is formed using a first ion implantation process. The doping type of the drain region 17a is the same as that of the drift region 12, and the doping type of the drain region 17a is the first doping type, that is, the doping type of the drain region 17a is N-type. Simultaneously with the formation of the drain region 17a within the drift region 12 using the first ion implantation process, a source region 17b is formed within the body region 13. The doping type of the source region 17b is the same as that of the drain region 17a, and the doping type of the source region 17b is also N-type.

[0058] Figure 8 This is a schematic diagram of the LDMOS device structure after forming the buffer drain layer according to an embodiment of the present invention. Figure 8As shown, a buffer drain layer 18 is formed, which is located on top of a portion of the drift regions 12 and on top of all the drain regions 17a. The buffer drain layer 18 is formed using a second ion implantation process. The doping type of the buffer drain layer 18 is the same as that of the drain regions 17a and the drift regions 12. The doping type of the buffer drain layer 18 is a first doping type, that is, the doping type of the buffer drain layer 18 is N-type, and the buffer drain layer 18 is an N-type buffer drain (N-Buried Drain, NBD) layer. The doping concentration of the buffer drain layer 18 is less than that of the drain regions 17a and greater than that of the drift regions 12. The doping concentration of the buffer drain layer 18 is, for example, 1E10. 12 ~ 1E10 13 The energy of the second ion implantation process is, for example, 20 keV to 200 keV. The width of the buffer drain layer 18 is greater than the width of the drain region 17a. The buffer drain layer 18 extends from the top of the drain region 17a toward the side away from the drain region 17a, extending below the field plate definition region (the field plate will be formed on the drift region later). The width (critical dimension) of the buffer drain layer 18 is, for example, 0.1 μm to 0.2 μm. In this embodiment, by adding an N-type buffer drain layer (NBD) at the drain region 17a end, the high electric field at the drain region end accelerates the carriers to become "hot carriers," and the N-type buffer drain layer (NBD) can reduce the collisional ionization rate of the "hot carriers." Compared to the absence of an N-type buffer drain (NBD) layer, the N-type buffer drain (NBD) layer in this embodiment, with a certain concentration of doping, can reduce the electric field strength. In other words, adding an N-type buffer drain (NBD) layer at the drain region 17a not only enhances conductivity and reduces on-resistance, but also reduces the electric field below the field plate, thereby reducing the impact ionization effect of the high electric field below the field plate region near the drain region and improving the reliability of the LDMOS device.

[0059] Figure 9 This is a schematic diagram of the LDMOS device after the formation of the barrier layer according to an embodiment of the present invention. Figure 9 As shown, a barrier layer 19 is formed, which covers part of the gate oxide 15 on the buffer drain layer 18 and exposes the gate oxide 15 on the drain region 17a. That is, the gate oxide 15 on the drain region 17a and the source region 17b is subsequently removed, a metal layer is deposited, and metal silicide is formed on the gate 16, the source region 17b, and the drain region 17a through an annealing process. In other words, in this embodiment, although a buffer drain layer 18 with a width greater than that of the drain region 17a is formed on the drain region 17a, the width of the metal silicide on the drain region 17a remains unchanged, that is, the length of the drift region 12 is maintained.

[0060] It is worth emphasizing that during the first ion implantation process to form the source region 17a and the drain region 17b, and during the second ion implantation process to form the buffer drain layer 18, the gate oxide 15 on the drift region 12 and the body region 13 protects the top surfaces of the drift region 12 and the body region 13 during the first and second ion implantation processes, preventing damage to the top surfaces of the drift region 12 and the body region 13 caused by ion bombardment. After the first and second ion implantation processes, the gate oxide 15 on the original top surfaces of the drift region 12 and the body region 13 is removed to form a new oxide layer, thereby protecting the areas where metal silicide formation is not required during the formation of metal silicides.

[0061] In summary, the LDMOS device provided in this embodiment includes a substrate on which a drift region and a body region are formed. A gate is formed on an adjacent portion of the drift region and the body region. A drain region is formed in the drift region away from the gate. A buffer drain layer is formed on the drain region, located on top of a portion of the drift region and on top of all the drain regions. By adding a buffer drain layer at the drain end, this invention not only enhances conductivity and reduces on-resistance but also reduces the electric field below the field plate, thereby reducing the impact ionization effect of the high electric field below the field plate region near the drain end and improving the reliability of the LDMOS device.

[0062] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, the different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0063] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An LDMOS device, characterized in that, include: A substrate on which drift regions and volume regions are formed; A gate, the gate being located in an adjacent portion of the drift region and the body region; A drain region, the drain region being located within the drift region on the side away from the gate; A buffer leak layer is located on top of a portion of the drift region and on top of all the leak regions.

2. The LDMOS device as described in claim 1, characterized in that, The width of the buffer leak layer is greater than the width of the leak.

3. The LDMOS device as described in claim 2, characterized in that, It also includes a field plate located on the drift region and adjacent to the gate.

4. The LDMOS device as described in claim 3, characterized in that, The buffer leak layer extends from the top of the leak area to below the field plate and does not exceed the side of the field plate away from the leak area.

5. The LDMOS device as described in claim 1, characterized in that, The doping type of the buffer drain layer is the same as the doping type of the drain region and the doping type of the drift region.

6. The LDMOS device as described in claim 5, characterized in that, The doping concentration of the buffer drain layer is less than that of the drain region and greater than that of the drift region.

7. A method for forming an LDMOS device, characterized in that, include: A substrate is provided on which drift regions and volume regions are formed; A gate is formed, the gate being located in an adjacent portion of the drift region and the body region; A drain region is formed, the drain region being located within the drift region on the side away from the gate; A buffer leak layer is formed, which is located on top of a portion of the drift region and on top of all the leak regions.

8. The method for forming an LDMOS device as described in claim 7, characterized in that, In the step of forming the drain region, a source region is also formed simultaneously, the source region being located within the body region.

9. The method for forming an LDMOS device as described in claim 8, characterized in that, The drain region and the source region are formed using a first ion implantation process, and the buffer drain region layer is formed using a second ion implantation process.

10. The method for forming an LDMOS device as described in claim 8, characterized in that, After the step of forming the drain region, a metal silicide is formed on the drain region, the source region, and the gate region, and the metal silicide on the drain region only covers the drain region.

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