Interconnect substrate manufacturing method
By locally roughening the surface of the glass substrate and forming a conductive layer, the problem of insufficient adhesion of the conductive layer is solved, achieving a balance between high adhesion and transparency, which is suitable for optical circuits and simplifies the process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-03
- Publication Date
- 2026-07-24
AI Technical Summary
Existing technologies make it difficult to form a conductive layer with good adhesion on the surface of glass substrates, and traditional roughening methods can affect the transparency of the substrate or cause environmental pollution, failing to meet the needs of special optical circuits.
The surface of the insulating substrate is locally roughened by multiple openings in the pattern layer, including laser and plasma roughening, to form an irregular roughened surface. Then, a conductive layer is formed on the locally roughened surface. The pattern layer and the suction plate can be reused.
It improves the adhesion between the conductive layer and the surface of the insulating substrate, maintains the transparency of the substrate, is suitable for optical circuits, reduces environmental pollution, and simplifies the process.
Smart Images
Figure CN122458795A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing an interconnect substrate. Background Technology
[0002] Inside the chip, the interconnect structure includes horizontal wirings formed on the surface of the interlayer dielectric layer and vertical vias penetrating the interlayer dielectric layer, used to achieve electrical connections between multiple circuit elements. Horizontal wirings serve as conductive lines on the same layer, while vertical vias connect wirings between different layers, enabling signal transmission and power distribution. With the increasing functionality and complexity of chips, the application of three-dimensional integration and stacked packaging technologies for multiple chips is becoming increasingly widespread.
[0003] In state-of-the-art chip packaging processes, separate interconnect substrates are used to connect chips at different levels. These interconnect substrates include, for example, an insulating substrate and conductive vias penetrating the insulating substrate. Because they are used to connect chips at different levels, these interconnect substrates are also called interposer substrates.
[0004] For example, in 3D integration technology, through-silicon vias (TSVs) are used to provide vertical channels between circuit elements at different levels. In system-in-package (SIP), a processor chip is mounted on one surface of a silicon substrate, and a memory chip is mounted on the other surface. High-density vias are formed in the silicon substrate to achieve electrical connections between the processor chip and the memory chip. The silicon substrate is secured to the processor chip and memory chip, for example, through wafer bonding.
[0005] Due to the high cost and limited area of silicon substrates by silicon wafers, MiniLED display technology employs through-glass vias (TGVs) to provide vertical channels between circuit elements at different levels. A large number of micro-LED chips are formed on one surface of the glass substrate, while multiple driver circuit chips are mounted on the other surface. High-density vias are formed within the glass substrate to achieve electrical connections between the micro-LED chips and the driver circuits. The glass substrate not only serves as a substrate for the micro-LED chips but also functions as part of the interconnect structure, providing vertical interconnect vias to shorten the signal transmission path between the micro-LED chips and the driver circuits, thereby reducing latency and line losses.
[0006] To provide conductive paths in the horizontal direction or other specific angular directions, circuitry needs to be laid out on the surface of the glass substrate. One existing method for laying out circuitry on the surface of a glass substrate involves sputtering a seed layer onto the surface, electroplating a metal layer on the seed layer, and etching to obtain a conductive layer. However, due to the excessive smoothness and low polarity of the glass surface, it is difficult to form a conductive layer with good adhesion on the glass substrate surface. Summary of the Invention
[0007] In view of the above problems, the object of the present invention is to provide a method for manufacturing an insulating substrate, thereby enabling the conductive layer to have a strong adhesion to the surface of the insulating substrate.
[0008] According to one aspect of the present invention, a method for manufacturing an interconnect substrate is provided, comprising locally roughening the surface of an insulating substrate through a plurality of openings in a patterned layer; and forming a conductive layer on the locally roughened surface of the insulating substrate.
[0009] Optionally, the pattern layer is adsorbed onto the surface of the insulating substrate by a suction plate, and the suction plate and the pattern layer respectively cover the opposite surfaces of the insulating substrate.
[0010] Optionally, the suction plate is implemented using a magnetic coil or a magnet, and the pattern layer is implemented using a soft magnetic material.
[0011] Optionally, the thickness of the suction plate is 0.5-2 times the thickness of the pattern layer.
[0012] Optionally, the local roughening of the surface of the insulating substrate through the multiple openings in the pattern layer includes a first local roughening of the surface of the insulating substrate through the multiple openings in the pattern layer; and a second local roughening of the surface of the insulating substrate through the multiple openings in the pattern layer.
[0013] Optionally, the first local roughening is performed using laser roughening, and the second local roughening is performed using plasma roughening.
[0014] Optionally, the plasma roughening includes one of radio frequency plasma roughening, microwave plasma roughening, and atmospheric pressure plasma roughening.
[0015] Optionally, forming a conductive layer on the locally roughened surface of the insulating substrate includes filling a plurality of openings in the patterned layer with a conductive material.
[0016] Optionally, forming a conductive layer on the locally roughened surface of the insulating substrate includes removing the patterned layer; sputtering a seed layer on the surface of the insulating substrate; covering the surface of the insulating substrate with the sputtered seed layer with a patterned film; electroplating a metal layer on the seed layer through a plurality of openings in the patterned film; and removing the patterned film and excess seed layer.
[0017] Optionally, the insulating substrate is selected from any one of silicon substrate, glass substrate, ceramic substrate, and resin substrate.
[0018] The interconnect substrate manufacturing method provided by this invention forms multiple openings in a pattern layer corresponding to the conductive layer to be formed on the surface of an insulating substrate. These openings in the pattern layer locally roughen the surface of the insulating substrate, resulting in strong adhesion between the conductive layer and the surface of the insulating substrate. When the insulating substrate is a glass substrate, this method of locally roughening the surface of the insulating substrate, compared to the prior art's method of completely roughening the surface, reduces the impact of roughening on the insulating properties of the insulating substrate, while preserving its transparency. This allows the insulating substrate to be used in some special optical circuit substrates, such as transparent display circuits or photoelectric receiving circuits.
[0019] In a preferred embodiment, the surface of the insulating substrate is roughened twice sequentially through multiple openings in the pattern layer. The first roughening uses laser roughening, and the second roughening uses plasma roughening. This results in an irregularly roughened surface on the insulating substrate. After a conductive layer is formed on the locally roughened surface, strong adhesion between the conductive layer and the insulating substrate surface is ensured, preventing separation under any peeling force. Furthermore, this roughening method causes minimal environmental pollution and is suitable for insulating substrates where conductive channels have already been formed in the through-holes.
[0020] In a preferred embodiment, the insulating substrate includes a first surface and a second surface opposite to each other. The pattern layer is adsorbed onto the second surface of the insulating substrate by a suction plate covering the first surface of the insulating substrate, and the pattern layer is adsorbed onto the first surface of the insulating substrate by a suction plate covering the second surface of the insulating substrate, so that the pattern layer can be easily removed in subsequent steps, and both the suction plate and the pattern layer can be reused. Attached Figure Description
[0021] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:
[0022] Figure 1 A schematic cross-sectional view of a chip packaging structure using glass through-hole technology is shown.
[0023] Figure 2 A flowchart of an interconnect substrate manufacturing method according to an embodiment of the present invention is shown;
[0024] Figures 3a to 3d A schematic cross-sectional view showing the detailed steps of an interconnect substrate manufacturing method according to an embodiment of the present invention;
[0025] Figure 4The diagram shows a comparison of the surface roughening effects of the present invention and existing technologies on the insulating substrate. Detailed Implementation
[0026] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.
[0027] Figure 1 A schematic cross-sectional view of a chip package structure employing through-glass via technology is shown. The chip package structure 100 is, for example, part of a backlight in a MiniLED display system, wherein miniature LEDs are used as the light-emitting elements of the backlight to provide high-brightness backlighting and fine contrast control capabilities.
[0028] The chip package structure 100 includes a stacked lower package 110, an upper package 130, and an interconnect substrate 120 sandwiched between them. The lower package 110 includes, for example, a driver chip 111, and the upper package 130 includes, for example, a plurality of LEDs 131. The driver chip 111 provides drive current to the plurality of LEDs 131, thereby controlling the lighting state of the plurality of LEDs 131. The driver chip 111 can selectively control the lighting state of the plurality of LEDs 131, thereby enabling zoned control of the backlight.
[0029] In the lower package 110, a driver chip 111 is fixed to a substrate 112 using an adhesive layer 113. The substrate 112 may be composed of silicon, glass, polymer, or any other insulator with specific optical and electrical properties. The active surface of the driver chip 111 faces upward, and a plurality of conductive bumps 116 are formed on the active surface. The driver chip 111 is encapsulated in a package material 114, which is, for example, composed of a mixture of epoxy resin as the matrix resin. The plurality of conductive bumps 116 of the driver chip 111 are exposed on the surface of the package material 114. A dielectric layer 115 is formed on the package material 114. The dielectric layer 115 is, for example, composed of silicon oxide or silicon nitride. An interconnect structure 117 is formed in the dielectric layer 115. The interconnect structure 117 includes, for example, a plurality of horizontally extending wiring layers for redistribution, and a plurality of vertically extending conductive channels for connecting the plurality of wiring layers. A plurality of pads 123 are formed on the surface of the dielectric layer 115. Interconnect structure 117 electrically connects driver chip 111 to multiple pads 123 and redistributes wiring to form a pad layout that facilitates external electrical connections.
[0030] In the upper package 130, a plurality of LEDs 131 are formed on a dielectric layer 132. The dielectric layer 132 is composed, for example, silicon oxide or silicon nitride. An interconnect structure 133 is formed in the dielectric layer 132. The interconnect structure 133 includes, for example, a plurality of horizontally extending wiring layers for redistribution, and a plurality of vertically extending conductive channels for connecting the plurality of wiring layers. A plurality of pads 135 are formed on the surface of the dielectric layer 132. The interconnect structure 133 electrically connects the plurality of LEDs 131 to the plurality of pads 135, and redistributes the wiring to form a pad layout that facilitates external electrical connections.
[0031] Interconnect substrate 120 includes an insulating substrate 121, a plurality of conductive vias 122 penetrating the insulating substrate 121, and surface circuitry (not shown) disposed on the surface of the insulating substrate 121. The plurality of conductive vias 122 in the interconnect substrate 120 provide vertically extending conductive paths, enabling electrical connection between a driver chip 111 located on one side of the interconnect substrate 120 and a plurality of LEDs 131 located on the other side of the interconnect substrate 120. The surface circuitry of the insulating substrate 121 in the interconnect substrate 120 provides conductive paths in the horizontal direction or other specific angular directions, thereby achieving electrical connection between different regions within the plane of the interconnect substrate 120.
[0032] The insulating substrate 121 is composed of, for example, any material selected from glass, silicon, ceramic, or resin, and the conductive channel 122 is composed of, for example, any material selected from metal, alloy, a mixture of metal and resin, or a mixture of alloy and resin. The ends of the plurality of conductive channels 122 on the lower surface of the interconnect substrate 120 are soldered to the plurality of pads 123 of the lower package 110, and the ends on the upper surface of the interconnect substrate 120 are soldered to the plurality of pads 135 of the upper package 130, thereby electrically connecting the lower driving chip 111 and the plurality of upper LEDs 113 to each other.
[0033] Interconnect substrate 120 is used to realize a stacked chip packaging structure, extending chip integration from two-dimensional to three-dimensional, thereby improving the integration density of the entire packaging structure. Since chips at different levels are directly electrically connected to each other via the interconnect substrate, the conductive path can be shortened, thereby reducing line loss and signal delay. If a glass substrate is used to fabricate the interconnect substrate 120, the interconnect substrate 120 can also be free from the size limitations of silicon wafers, thereby integrating multiple small-sized chips on a large-sized interconnect substrate.
[0034] When it is necessary to lay out circuits on the surface of the insulating substrate 121 (i.e., to fabricate a conductive layer on the surface of the insulating substrate 121), the surface of the insulating substrate 121 needs to be roughened in order to improve the adhesion between the conductive layer and the surface of the insulating substrate 121. The following describes the prior art method for roughening the surface of the insulating substrate 121 using a glass substrate as an example.
[0035] One existing method for roughening the surface of glass substrates is chemical roughening. One approach involves using methods such as sandblasting to create microcracks and stress zones on the glass substrate surface. Then, an etchant with different etching rates for the microcracks, stress zones, and untreated areas is used to etch the glass substrate surface, achieving a roughened surface. Examples of etchants include hydrofluoric acid. Another method involves using modifiers to adjust the saturation concentration of etchants for different glass components on glass with complex compositions, creating a difference in surface etching rate and achieving a roughened surface. However, this roughness is directional and fails to effectively create an anchoring effect, resulting in limited improvement in adhesion. Furthermore, chemical etching can clog the inner walls of glass vias or corrode conductive channels 122.
[0036] One existing method for roughening the surface of a glass substrate is to increase the sputtering voltage during seed layer sputtering to accelerate the entry of the seed layer metal into the chemical bonds of the glass surface, thereby improving adhesion. However, due to the poor lattice matching between the heterogeneous material and the glass surface, this method of improving adhesion is not significant, the equipment is expensive, and there is also a risk of short circuits in the surface circuitry.
[0037] One existing method for roughening the surface of a glass substrate is physical roughening, such as scanning the surface of the glass substrate with a high-energy beam (e.g., a laser) to cause thermal ablation of different degrees on the surface, thereby forming better adhesion. However, this affects the transparency of the glass substrate.
[0038] One existing method for roughening the surface of glass substrates is frosting, which involves non-uniformly growing a layer of crystals on the surface of the glass substrate to roughen it. However, because the crystals grow in the same direction, the improvement in adhesion is limited. Furthermore, it can have a certain environmental impact.
[0039] One existing method for roughening the surface of a glass substrate involves coating the glass surface with a resin insulating layer, such as PI, ABF, or epoxy resin, followed by drilling or leaving holes in appropriate locations. The resin insulating layer is then roughened using chemical or plasma methods, or left unroughened, before a conductive seed layer is sputtered. This method effectively improves adhesion, but it involves numerous steps, introduces a new interface layer, and suffers from poor thermal expansion coefficient matching.
[0040] After roughening the glass substrate, the surface roughness is controlled to be above 0.1 μm, making the glass substrate no longer transparent and unsuitable for use in some special optical circuit substrates, such as transparent display circuits or photoelectric receiving circuits. In addition, after forming conductive channels 122 in the through holes of the glass substrate, the etching solution will corrode the conductive channels 122. Therefore, in this case, it is not suitable to use the above-mentioned chemical method to roughen the surface of the glass substrate.
[0041] Figure 2 A flowchart of an interconnect substrate manufacturing method according to an embodiment of the present invention is shown. The manufacturing method includes steps S01 and S02 performed sequentially.
[0042] In step S01, the surface of the insulating substrate is locally roughened through multiple openings in the pattern layer.
[0043] In this step, a pattern layer with multiple openings is applied to the surface of the insulating substrate 121. The surface of the insulating substrate 121 is then roughened through these openings, resulting in localized roughening. To improve the roughening effect, the surface of the insulating substrate 121 can be roughened twice through the openings in the pattern layer, using two different methods. The surface roughness Ra of the roughened insulating substrate 121 generally needs to be greater than 100 nm.
[0044] For example, the first roughening can be performed using any existing method, and the second roughening can be performed using plasma roughening. Preferably, the first roughening uses laser roughening, and the second roughening uses plasma roughening. During laser roughening, a laser beam irradiates the surface of the insulating substrate 121 through multiple openings in the patterned layer. Preferably, an infrared laser with a wavelength of 1035nm-1060nm or an ultraviolet picosecond laser with a wavelength of 343nm-355nm is used. The laser pulse energy is 30uJ-180uJ, and the pulse width is <15ps. The surface roughness of the insulating substrate 121 after laser roughening can reach 300nm-500nm. During plasma roughening, a plasma beam scans the surface of the insulating substrate 121 through multiple openings in the patterned layer. Plasma roughening methods include radio frequency plasma roughening, microwave plasma roughening, and atmospheric pressure plasma roughening. Taking radio frequency plasma roughening as an example, its principle is to use a radio frequency power supply to generate a high-frequency electromagnetic field, causing the reactive gas to ionize and form plasma. Preferably, the power of the radio frequency power supply is 6-15 kW, the atmosphere is sulfur hexafluoride (SF6), argon and oxygen, SF6 is the active etching gas, the carrier gas is argon and oxygen, the gas flow rate of SF6 is 10-30 sccm, the gas flow rate of the carrier gas is 30-50 sccm, the magnetic field strength is 8 mT-30 mT, the vacuum strength is 150-300 mtorr, and the plasma scanning time is 10-30 min.
[0045] See Figure 4 It can be seen that regardless of whether the surface roughness of the glass substrate is 300nm (i.e. 0.3um) or 100nm (i.e. 0.1um), the roughening effect of the roughening method of this application on the surface of the insulating substrate 121 is better than that of the traditional roughening method.
[0046] In step S02, a conductive layer is formed on the surface of the locally roughened insulating substrate.
[0047] In this step, a conductive layer can be formed by directly filling the multiple openings of the patterned layer with conductive material, for example, by scraping conductive paste onto the surface of the patterned layer, allowing the conductive paste to enter the multiple openings, and then curing the conductive paste. Alternatively, a conductive layer can be formed on the surface of the insulating substrate 121 after the patterned layer is removed. In this case, a patterned film also needs to be applied to the surface of the insulating substrate 121 during the formation of the conductive layer.
[0048] Figures 3a to 3d A schematic cross-sectional view showing the detailed steps of an interconnect substrate manufacturing method according to an embodiment of the present invention, wherein, Figures 3a to 3b The above step S01 is shown. Figures 3c to 3d The above step S02 is shown.
[0049] The insulating substrate 121 has opposing first and second surfaces. In this embodiment, patterned layers 210 and 230 and a suction plate 220 are used. The suction plate 220 adheres the patterned layers 210 / 230 to the other of the first and second surfaces of the insulating substrate 121 by covering one of them. The openings in the patterned layers 210 and 230 may be the same or different. Preferably, the thickness of the suction plate 220 is 0.5-2 times the thickness of the patterned layers 210 / 230.
[0050] For example, the suction plate 220 is implemented using a magnet or magnetic coil. The pattern layers 210 and 230 are implemented using soft magnetic materials such as steel plates or iron plates. Preferably, the pattern layers 210 and 230 are implemented using steel plates. Steel plates can be attracted by magnets or magnetic coils and also have a certain degree of toughness, rigidity, and magnetism. Using steel plates as pattern layers 210 and 230 can ensure the size and accuracy of the pattern layers.
[0051] See Figure 3a The pattern layer 210 is used to locally roughen the first surface of the insulating substrate 121 through multiple openings, where 121a refers to the roughened portion of the first surface of the insulating substrate 121. At this time, the pattern layer 210 covers the first surface of the insulating substrate 121, and the suction plate 220 covers the second surface of the insulating substrate 121. The pattern layer 210 is then adsorbed onto the first surface of the insulating substrate 121 by the suction plate 220. The multiple openings in the pattern layer 210 correspond to the conductive layer that needs to be formed on the first surface of the insulating substrate 121.
[0052] See Figure 3b The pattern layer 230 locally roughens the second surface of the insulating substrate 121 through multiple openings, where 121b refers to the roughened portion of the second surface of the insulating substrate 121. The pattern layer 230 covers the second surface of the insulating substrate 121, and a suction plate 220 covers the first surface of the insulating substrate 121, allowing the pattern layer 230 to be adsorbed onto the second surface of the insulating substrate 121. The multiple openings in the pattern layer 230 correspond to the conductive layer to be formed on the second surface of the insulating substrate 121.
[0053] After roughening, the roughness Ra of the roughened surface of the insulating substrate 121 is greater than 100 μm, preferably 300 nm-500 nm.
[0054] If the conductive channel 122 penetrating the insulating substrate 121 was already formed before the surface of the insulating substrate 121 was locally roughened, then in Figure 3a and Figure 3bIn order to avoid corrosion of the conductive channel 122, a non-chemical method is required to roughen the surface of the insulating substrate 121, such as laser roughening or plasma roughening. Preferably, the surface of the insulating substrate 121 can be roughened twice, with the first roughening using laser roughening and the second roughening using plasma roughening.
[0055] See Figure 3c The pattern layers 210 / 230 and the suction plate 220 are removed. A seed layer 240 is sputtered onto the surface of the insulating substrate 121, and then pattern films 250 and 260 are respectively covered on the first and second surfaces of the insulating substrate 121 with the seed layer 240 sputtered. A metal layer is then electroplated onto the seed layer 240 through multiple openings in the pattern films 250 and 260. For example, the pattern films 250 and 260 are photoresist films. The multiple openings of the pattern film 250 correspond one-to-one with the multiple openings of the pattern layer 210, and the multiple openings of the pattern film 260 correspond one-to-one with the multiple openings of the pattern layer 230.
[0056] See Figure 3d The pattern films 250 and 260 are removed, and the excess seed layer 240 is etched away, thereby forming a conductive layer 270 on the first surface of the insulating substrate 121 and a conductive layer 280 on the second surface of the insulating substrate 121.
[0057] It is understood that in other embodiments of the present invention, it is also possible to... Figure 3a Next, conductive material is directly filled into the multiple openings of pattern layer 210 to form conductive layer 270. Then, further processing is performed. Figure 3b The operation, and in Figure 3b Next, conductive material is directly filled into the multiple openings of patterned layer 230 to form conductive layer 280. The advantage of doing this is that there is no need to cover the patterned film during the formation of conductive layers 270 and 280, which can reduce process complexity and save costs.
[0058] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.
Claims
1. A method for manufacturing an interconnect substrate, comprising: The surface of the insulating substrate is locally roughened through multiple openings in the pattern layer; as well as A conductive layer is formed on the surface of the locally roughened insulating substrate.
2. The interconnect substrate manufacturing method according to claim 1, wherein, The pattern layer is adsorbed onto the surface of the insulating substrate by a suction plate, and the suction plate and the pattern layer respectively cover the opposite surfaces of the insulating substrate.
3. The interconnect substrate manufacturing method according to claim 2, wherein, The suction plate is implemented using a magnetic coil or a magnet, and the pattern layer is implemented using a soft magnetic material.
4. The interconnect substrate manufacturing method according to claim 2, wherein, The thickness of the suction plate is 0.5-2 times the thickness of the pattern layer.
5. The interconnect substrate manufacturing method according to claim 1, wherein, The local roughening of the surface of the insulating substrate through multiple openings in the patterned layer includes: The surface of the insulating substrate is initially locally roughened through multiple openings in the pattern layer; and The surface of the insulating substrate is locally roughened a second time through multiple openings in the pattern layer.
6. The method for manufacturing an interconnect substrate according to claim 5, wherein, The first local roughening was performed using laser roughening, and the second local roughening was performed using plasma roughening.
7. The interconnect substrate manufacturing method according to claim 6, wherein, The plasma roughening includes one of radio frequency plasma roughening, microwave plasma roughening, and atmospheric pressure plasma roughening.
8. The method for manufacturing an interconnect substrate according to claim 1, wherein, Forming a conductive layer on the surface of the locally roughened insulating substrate includes: A conductive material is filled into multiple openings in the patterned layer.
9. The method for manufacturing an interconnect substrate according to claim 1, wherein, Forming a conductive layer on the surface of the locally roughened insulating substrate includes: Remove the pattern layer; A seed layer is sputtered onto the surface of the insulating substrate; A patterned film is coated on the surface of an insulating substrate with a sputtered seed layer. A metal layer is electroplated onto the seed layer through multiple openings in the patterned film; and Remove the patterned film and any excess seed layer.
10. The method for manufacturing an interconnect substrate according to claim 1, wherein, The insulating substrate is selected from any one of silicon substrate, glass substrate, ceramic substrate, and resin substrate.