Memory layout optimization method, electronic device, vehicle and storage medium

Abstract

This application provides a memory layout optimization method, an electronic device, a vehicle, and a storage medium. The method includes: during the operation of an electronic control unit (ECU), collecting access data of variables in the memory of the ECU; extracting data features from the access data of the variables; generating a memory allocation scheme for the variables based on the data features; and updating the variable layout of the memory based on the memory allocation scheme. This application can dynamically generate a memory allocation scheme for variables based on the variable access data collected during the operation of the ECU, and optimize the memory layout based on the memory allocation scheme, effectively improving the performance of the ECU.

Description

Technical Field

[0001] This application relates to the field of embedded storage technology, and in particular to a memory layout optimization method, electronic devices, vehicles, and storage media. Background Technology

[0002] With the rapid development of vehicle electrification, intelligence, and connectivity, the software complexity of vehicle electronic control units (ECUs) has increased significantly. Under the AUTOSAR (Automotive Open System Architecture) standard, the memory of an onboard ECU stores a large amount of code and manages numerous global variables distributed across different memory regions. In related technologies, the memory layout of an onboard ECU is typically statically determined by the linker script, making dynamic optimization difficult and thus impacting the performance of the onboard ECU. Summary of the Invention

[0003] In view of the above, it is necessary to provide a memory layout optimization method, electronic device, vehicle, and storage medium to solve the problem that the memory layout of the vehicle ECU is usually statically determined by the linker script, which is not convenient for dynamic optimization and thus affects the performance of the vehicle ECU.

[0004] In a first aspect, embodiments of this application provide a memory layout optimization method, the method comprising: During the operation of the electronic control unit, access data of variables in the memory of the electronic control unit are collected; Extract the data characteristics of the access data of the variables; A memory allocation scheme for the variables is generated based on the data characteristics; The memory variable layout is updated based on the memory allocation scheme of the variables.

[0005] In one possible implementation, the method further includes: Before compiling the code in the memory, a first region and a second region are preset in the memory. The first region is used to store the variables, and the second region is used to store the redirection mapping table of variable addresses. After the code is compiled, the redirection mapping table is generated and stored in the second area; When the code runs, based on the redirection mapping table, the variable is transferred from its original storage address to a storage address in the random access memory (RAM).

[0006] In one possible implementation, the access data includes at least one of variable address, read count, write count, access time, and association with other variables, and the data features for extracting the access data of the variable include: Based on the number of reads and writes of the variable, the access frequency of the variable is calculated as the popularity of the variable; Based on the aforementioned relationships with other variables, determine the frequently accessed variables associated with the aforementioned variables; The frequently accessed variables corresponding to the variable are transferred to a storage address adjacent to the variable, and the correlation degree between the variable and the frequently accessed variables is calculated.

[0007] In one possible implementation, the memory allocation scheme for generating the variables based on the data features includes: Based on the aforementioned data characteristics, a memory allocation scheme for the variables is generated using a heat-aware heterogeneous memory data allocation algorithm, including: Multiple heat levels are determined based on multiple preset heat thresholds; Establish a mapping relationship between multiple popularity levels and multiple memory regions; Based on the target popularity level corresponding to the popularity of the variable and the mapping relationship, the target memory regions of the variable and other variables that are highly associated with the variable are determined, wherein the other variables that are highly associated with the variable are high-frequency access variables whose association degree is greater than or equal to a preset threshold.

[0008] In one possible implementation, the memory allocation scheme for generating the variables based on the data features further includes: If the target memory region does not meet the preset constraints of the variable, or the target memory region is incompatible with the variable, or the capacity of the variable is greater than the remaining capacity of the target memory region, the memory region corresponding to the next level of popularity of the target popularity level will be used as the updated target memory region until the updated target memory region meets the preset constraints of the variable, the updated target memory region is compatible with the variable, and the capacity of the variable is greater than the remaining capacity of the target memory region.

[0009] In one possible implementation, the memory allocation scheme for generating the variables based on the data features further includes: The target addresses of the variable and other variables highly associated with the variable are allocated in the target memory region. Based on the variable and other variables highly associated with the variable, the target memory region, and the target address, an updated redirection mapping table is generated.

[0010] In one possible implementation, updating the variable layout of memory based on the memory allocation scheme of the variable includes: The memory allocation scheme is updated to the memory using Over-the-Air (OTA) technology.

[0011] Secondly, embodiments of this application provide an electronic device, the electronic device including a memory and a processor; wherein, the memory is used to store program instructions; the processor is used to read and execute the program instructions stored in the memory, and when the program instructions are executed by the processor, the electronic device performs the memory layout optimization method described above.

[0012] Thirdly, embodiments of this application provide a memory layout optimization device, the device comprising: a collection module for collecting access data of variables in the memory of the electronic control unit during operation; an extraction module for extracting data features of the access data of the variables; a generation module for generating a memory allocation scheme for the variables based on the data features; and an update module for updating the variable layout of the memory based on the memory allocation scheme of the variables.

[0013] Fourthly, embodiments of this application provide a vehicle, the vehicle including a memory and a processor; wherein the memory is used to store program instructions; the processor is used to read and execute the program instructions stored in the memory, and when the program instructions are executed by the processor, the vehicle performs the memory layout optimization method described above.

[0014] Fifthly, embodiments of this application provide a computer storage medium that, when the program instructions are run on an electronic device or vehicle, causes the processor of the electronic device or vehicle to execute the memory layout optimization method described above.

[0015] The memory layout optimization method, apparatus, electronic device, and storage medium provided in this application can dynamically generate a memory allocation scheme for variables based on variable access data collected during the operation of the electronic control unit, and update and optimize the memory layout based on the memory allocation scheme, thereby effectively improving memory utilization and thus improving the performance of the electronic control unit. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0017] Figure 1 This is a schematic diagram illustrating an application scenario of the memory layout optimization method provided in one embodiment of this application.

[0018] Figure 2 This is a flowchart of a memory layout optimization method provided in an embodiment of this application.

[0019] Figure 3 This is a schematic diagram of the address mapping relationship between Flash and RAM provided in an embodiment of this application.

[0020] Figure 4 This application provides a table showing the correspondence between variables and memory regions in one embodiment.

[0021] Figure 5 This is a schematic diagram of an OTA security update and atomic rollback mechanism provided in an embodiment of this application.

[0022] Figure 6 This is a flowchart of a memory layout optimization method provided in another embodiment of this application.

[0023] Figure 7 This is a schematic diagram of memory allocation provided in an embodiment of this application.

[0024] Figure 8 This is a schematic diagram of the structure of a memory layout optimization device provided in an embodiment of this application.

[0025] Figure 9 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application.

[0026] Figure 10 This is a schematic diagram of the hardware structure of a vehicle provided in one embodiment of this application. Detailed Implementation

[0027] The terms "first" and "second" used in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to limit the application. It should be understood that, unless otherwise stated, " / " in this application means "or". For example, A / B can mean A or B. "And / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. "At least one" refers to one or more. "More than one" refers to two or more. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, and a, b, and c. Where there is no conflict, the following embodiments and features described herein can be combined with each other.

[0029] With the rapid development of vehicle electrification, intelligence, and connectivity, the software complexity of vehicle electronic control units has increased significantly. Under the AUTOSAR standard, the memory of an onboard ECU stores a large amount of code and manages a large number of global variables distributed across different memory regions.

[0030] For example, the memory areas of an automotive electronic control unit include tightly coupled memory (TCM), on-chip SRAM, and external SDRAM. Tightly coupled memory includes instruction TCM (ITCM) and data TCM (DTCM), offering the lowest access latency (typically 1-2 CPU cycles), but with limited capacity (typically 32-128KB). On-chip SRAM offers faster access speeds (3-5 CPU cycles), medium capacity (128KB-1MB), and some have cached regions; SRAM with cached regions offers even faster access speeds (2-3 CPU cycles). External SDRAM has larger capacity (over 1MB), but higher access latency (10+ CPU cycles).

[0031] In related technologies, the memory layout of automotive electronic control units (ECUs) is typically statically determined by the linker script, making it impossible to optimize the layout based on the actual operational characteristics of the program or code, thus affecting the performance of the ECU. For modern automotive-grade MCUs (such as NXP S32K and Infineon TC3xx) with multi-level storage (e.g., TCM, Cache SRAM, general SRAM, SDRAM), reliance on human experience is lacking intelligent allocation strategies. Static optimization easily overlooks variable relationships, potentially allocating frequently accessed variables to distant memory locations. ECU performance improvements require continuous updates and optimizations via Over-the-Air (OTA) technology, but OTA updates typically suffer from large update packages, long processing times, and high risks.

[0032] To address the issue that the memory layout of vehicle electronic control units is typically statically determined by the linker script, making dynamic optimization difficult and thus affecting the performance of the electronic control unit, this application provides a memory layout optimization method. This method dynamically generates a memory allocation scheme for variables based on variable access data collected during the operation of the electronic control unit, and updates and optimizes the memory layout based on the memory allocation scheme, effectively improving memory utilization and thus enhancing the performance of the electronic control unit.

[0033] See Figure 1 The diagram shown illustrates an application scenario of a memory layout optimization method provided in an embodiment of this application. The memory layout optimization method in this embodiment can be applied to... Figure 1 The memory layout optimization system 100 shown includes, but is not limited to, a vehicle-side 101 and a cloud-side 102. The vehicle-side 101 runs an in-vehicle embedded system, and the cloud-side 102 runs a cloud-based optimization platform. The cloud-side 102 can be a cloud server.

[0034] See Figure 2 The diagram shown is a flowchart of a memory layout optimization method provided in an embodiment of this application. The method is applied in electronic devices or vehicles, and includes: S101 collects access data of variables in the memory of the electronic control unit during operation.

[0035] In one embodiment of this application, during the construction of the application program in the electronic control unit, the linker script is specially processed during the compilation phase to prepare for dynamic memory optimization. The electronic control unit's memory includes a flash memory area. Before compiling the code in memory, a first area and a second area are preset in the flash memory area. The first area is used to store multiple variables, which are global variables. Global variables are variables defined outside of all functions, classes, or code blocks, whose scope covers the entire program (or module) and can be accessed and modified by any function or code block in the program. The second area is used to store a redirection mapping table of variable addresses. The second area includes a main area and a backup area, with data in the main area supporting independent updates.

[0036] See Figure 3The diagram shown illustrates the address mapping relationship between Flash and RAM according to an embodiment of this application. By processing the linker script, such as generating position-independent code or defining a global offset table, the compiler does not fix the storage address of variables during the compilation process. Consequently, when accessing variables, the code generated by the compiler does not directly use the absolute address in the Flash memory (e.g., 0x10210010), but instead uses the relative address in the RAM (e.g., 0x34210010). Since global variables are divided into two types: those with an initial value of 0 (.bss segment) and those with a non-zero initial value (.data segment), variables with an initial value of 0 or no initial value are also stored in the Flash area.

[0037] In one embodiment of this application, after the code is compiled, a redirection mapping table is generated based on the compiled file (e.g., .bin, .hex, .map), and the redirection mapping table is stored in the main area and backup area of ​​the second region. The redirection mapping table is stored in flash memory as a structure array. For example, the redirection mapping table for 1000 global variables of different sizes is shown in Table 1.

[0038] Table 1 In one embodiment of this application, when the application in the electronic control unit starts and runs the code in memory, the code in flash memory is loaded into RAM. At the same time, based on the redirection mapping table, the variables are transferred from the storage area corresponding to the original storage address in flash memory to the storage area corresponding to the storage address in RAM. The storage address in RAM can be dynamically accessed during operation.

[0039] In one embodiment of this application, during the operation of the electronic control unit, access data of variables in memory is collected using hardware-assisted methods or software probes. The hardware-assisted method utilizes the Data Watchpoint and Trace (DWT) unit built into the embedded processor to monitor access to key variables, automatically incrementing a counter upon access. The software probe uses lightweight instrumentation counting, inserting a small number of bytes of counter before the address space of each global variable.

[0040] In one embodiment of this application, the access data includes, but is not limited to: variable address, read count, write count, access time, and association with other variables. For example, variable address: 0x34201000, 4 bytes; read count: 1520, 2 bytes, upper limit 65535 times, equal to the upper limit when exceeded; write count: 235, 2 bytes, upper limit 65535 times, equal to the upper limit when exceeded; access time sequence: TT1=[Δt1+Δt3+Δt5+Δt8+...], total running time, 2 bytes, upper limit 60000ms; association: other variables accessed simultaneously: [[0x34201100, access count], [0x34201200, access count]...], up to 3, 3*(4*2)=24 bytes. The collected variable access data can be uploaded to the cloud every preset time interval (e.g., 1 minute) or stored locally.

[0041] S102, Extract the data characteristics of the accessed data of the variables.

[0042] In one embodiment of this application, the data characteristics of the access data of a variable include, but are not limited to, popularity and correlation with other variables. The access frequency of a variable is calculated based on the number of reads and writes, and is used as the popularity of the variable. For example, the formula (1) for calculating the popularity of a variable is: Popularity = (Number of reads × a + Number of writes × b) / Total running time TT (1).

[0043] In the calculation formula (1), a is the weight of the read operation, for example, 1, b is the weight of the write operation, for example, 1.2, and the total running time is the running time of the electronic control unit. For example, the popularity of some variables is shown in Table 2.

[0044] Table 2 In one embodiment of this application, high-frequency access variables associated with the variable are determined based on their correlation with other variables. These high-frequency access variables are other variables whose access frequency is greater than or equal to a preset threshold. For example, the preset threshold is 200. The high-frequency access variables corresponding to the variable are transferred to a storage address adjacent to the variable, and the correlation degree between the variable and the high-frequency access variables is calculated. The correlation degree between the variable and the high-frequency access variables is the ratio between the number of times the variable is accessed and the number of times the high-frequency access variables are accessed. The closer the correlation degree value is to 1, the stronger the correlation. Based on the number of times the variable is accessed, the number of times the high-frequency range variables are accessed, and the correlation degree, an access correlation matrix can be constructed, as shown in Table 3.

[0045] Table 3 In one embodiment of this application, the characteristics of the variables may further include preset constraints. These preset constraints include security conditions (e.g., read-only / private attributes), alignment requirements, cache line boundaries, and other constraints inherent to the variable's own attributes. Security conditions mean that read-only data is placed in a read-only access area to prevent abnormal rewriting, while private data is placed in an area accessible only to the local processor core to prevent abnormal rewriting by other processor cores. Alignment requirements mean that all variable data has alignment attributes, such as 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, etc. Based on the alignment attributes of the variables themselves, variables with the same alignment attribute are placed as close together as possible to reduce RAM gaps and make fuller use of RAM. Cache line boundaries are typically 32-bit or 16-bit; considering the above alignment requirements, variables should be laid out as multiples of 32-bit or 16-bit as possible.

[0046] S103, a memory allocation scheme for generating variables based on data characteristics.

[0047] In one embodiment of this application, a memory allocation scheme for variables is generated based on data characteristics using a heat-aware heterogeneous memory data allocation algorithm. This heat-aware heterogeneous memory data allocation algorithm, based on the runtime access frequency of variables and combined with the performance characteristics (e.g., access latency, bandwidth, security) of different storage media in the heterogeneous memory architecture, utilizes a multi-level threshold partitioning strategy to optimize the placement of data in heterogeneous memory spaces such as DTCM, Cache RAM, ordinary SRAM, and SDRAM, thereby minimizing average access latency and improving overall system performance.

[0048] The input data for the heat-aware heterogeneous memory data allocation algorithm includes a set of variables. Heat value :variable Access frequency / popularity; Popularity threshold set , ; for each variable Allocate to a storage area ,For example, For DTCM (Tightly Coupled Memory, Highest Performance). It is Cache RAM (lower performance). It is a standard SRAM (medium performance). For SDRAM (lowest performance, high capacity); each variable has the following attributes: address (current address and address to be allocated), Size (capacity). bit alignment requirements Constraint vectors Relationship degree The output data of the heat-aware heterogeneous memory data allocation algorithm includes a variable allocation map and RAM addresses. The allocation map includes the memory region to which each variable is allocated, and the RAM address is the specific RAM address assigned to each variable in the corresponding memory region.

[0049] In one embodiment of this application, multiple heat levels are determined based on multiple preset heat thresholds. For example, based on preset heat thresholds... The popularity of variables is divided into four levels: .

[0050] In one embodiment of this application, a mapping relationship is established between multiple popularity levels and multiple memory regions. For example, the mapping relationship between popularity levels and memory regions is established according to the principle that higher popularity is placed in memory with higher performance. For example, the mapping relationship between popularity levels and memory regions is shown in Table 4.

[0051] Table 4 In one embodiment of this application, the target memory region for the variable and other variables highly correlated with it is determined based on the target popularity level and mapping relationship corresponding to the popularity of the variable. The other variables highly correlated with the variable are frequently accessed variables with a correlation degree greater than or equal to a preset threshold. For example, the preset threshold is 0.8. In other embodiments of this application, the variables highly correlated with the variable can also be the frequently accessed variables with the highest correlation degree.

[0052] In one embodiment of this application, it is determined whether the target memory region meets the preset constraints of the variable, whether the target memory region is compatible with the variable, and whether the capacity of the variable is greater than the remaining capacity of the target memory region.

[0053] If the target memory region does not meet the preset constraints of the variable, or the target memory region is incompatible with the variable, or the capacity of the variable is greater than the remaining capacity of the target memory region, the memory region corresponding to the next level of popularity of the target popularity level will be used as the updated target memory region. The updated target memory region will be checked for preset constraints, compatibility, and capacity until the updated target memory region meets the preset constraints of the variable, is compatible with the variable, and the capacity of the variable is greater than the remaining capacity of the target memory region.

[0054] For each variable Check its relationship with the target memory region. Compatibility: .

[0055] if If it is, it will be downgraded to the next available memory region. (If it exists), repeat the check until a compatible memory region is found or the region is downgraded to the lowest possible level. .

[0056] For each memory region Maintain its remaining capacity When it is a variable distribute When checking the size of variables Is it less than or equal to the memory region? The remaining capacity, i.e. If the capacity is insufficient, that is, the size of the variable... Larger than memory area If the remaining capacity is not available, it will attempt to be downgraded to the next lower level of memory. .

[0057] For those with strong correlation (e.g., correlation degree > threshold) ) variables They are allocated to the same or adjacent memory regions to reduce the overhead of cross-memory access. The higher the degree of association, the greater the probability that the two variables will be accessed simultaneously.

[0058] For example, based on constraint awareness, compatibility checks, and capacity constraint processing, the correspondence between variables and memory regions is obtained as follows: Figure 4 As shown.

[0059] In one embodiment of this application, target addresses are allocated in the target memory region for the variable and other variables highly associated with the variable, and an updated redirection mapping table is generated based on the target memory region and target address of the variable and other variables highly associated with the variable.

[0060] Specifically, based on the alignment requirements (alignment bits) of the variables, address allocation is performed within the selected memory region to ensure that the starting address of the variables meets the alignment constraints. Allocation strategies can employ classic memory allocation algorithms such as sequential allocation, best fit, and first fit.

[0061] In one embodiment of this application, the final memory region and RAM address of each variable are recorded, and the allocation result mapped to the physical address is output to obtain the memory allocation scheme of the variable.

[0062] S104, Update the variable layout of memory based on the variable-based memory allocation scheme.

[0063] In one embodiment of this application, if the memory allocation scheme for variables is generated by analyzing variable access data in the cloud, then the memory allocation scheme is updated to memory using Over-the-Air (OTA) technology. During the update process, differential updates are used, transmitting only the updated redirection mapping table (variable memory layout description file), without transmitting code. The OTA update package also needs to be verified, including hash verification, signature verification, CRC verification, and compatibility checks. During the OTA update process, atomic switching is implemented, a dual-storage area design is adopted, safe rollback is supported, and layout_active (currently used) is switched to layout_backup (updatable). The optimized update of the variable layout includes transferring variables based on the memory allocation scheme and replacing the current redirection mapping table in memory with the updated redirection mapping table.

[0064] See Figure 5 The diagram illustrates an OTA secure update and atomic rollback mechanism provided in an embodiment of this application. After receiving an OTA update package, the electronic control unit (ECU) verifies the signature of the OTA update package. If the signature verification fails, the update package is cleared. If the signature verification passes, the status flag is updated, and an atomic operation is performed to write the update package to the backup area of ​​the flash memory. After writing, a CRC check is performed on the written data. If the CRC check fails, the status flag and the update package are cleared. If the CRC check succeeds, an atomic switch is performed, updating the pointer to the backup area so that the application can read data from the backup area during runtime. After the atomic switch is complete, functional tests, performance tests, and stability tests are performed during the operation of the ECU. If all three tests pass, the data in the backup area is copied to the main area. If any one of the three tests fails, a secure rollback is triggered, a reset is performed, and the original configuration is restored.

[0065] In other embodiments of this application, if the memory allocation scheme of the variables is generated by the electronic control unit through analysis of the access data of the variables, the variable layout in memory is directly updated based on the memory allocation scheme of the variables.

[0066] After the OTA update is completed, the variables are relocated during application runtime. Relocation methods may include MMU (Memory Management Unit) remapping, updating the indirect access table, and adjusting the base address register.

[0067] Understandably, S102-S104 can be executed locally or in the cloud.

[0068] See Figure 6The diagram shown is a flowchart of a memory layout optimization method provided in another embodiment of this application. The method is applied in an electronic device or vehicle, and includes: S201: During the operation of the electronic control unit, access data of variables in the memory of the electronic control unit is collected.

[0069] S202, Extracting data characteristics of accessed data from variables.

[0070] S203, a memory allocation scheme for generating variables based on data characteristics.

[0071] S204, Update the variable layout of memory based on the variable memory allocation scheme.

[0072] The specific implementation methods of S201-S204 are the same as those of S101-S104, and will not be described in detail here.

[0073] S205 measures the performance indicators of the electronic control unit and iteratively optimizes the memory layout based on these performance indicators.

[0074] In one embodiment of this application, the performance indicators of the electronic control unit include, but are not limited to, response time and memory utilization. The performance improvement value of each memory layout optimization process is determined based on the performance indicators after two consecutive memory layout optimization processes. It is then determined whether the performance improvement value after a preset number of consecutive memory layout optimization processes is greater than or equal to a preset improvement value. If the performance improvement value after a preset number of consecutive memory layout optimization processes is greater than or equal to the preset improvement value, steps S201-S204 are repeated for iterative optimization. If the performance improvement value after a preset number of consecutive memory layout optimization processes is less than the preset improvement value, iterative optimization is stopped. For example, the preset number of iterations is 2, and the performance improvement value is 1%. If the performance improvement value of the memory layout optimization process is negative, meaning performance has decreased, a safe rollback mechanism is executed to restore the original memory layout.

[0075] See Figure 7 The diagram shown illustrates memory allocation according to an embodiment of this application. In this embodiment, based on memory layout updates and optimizations, variables corresponding to real-time control data in memory can be stored in the Data Tightly Coupled DTCM (DTCM), variables corresponding to critical code in memory can be stored in the Instruction Tightly Coupled DTCM (DTCM), variables corresponding to hot data can be stored in the L1 Cache (L1 Cache), variables corresponding to communication cache data in memory can be stored in SRAM0 with a cache, variables corresponding to application state data in memory can be stored in SRAM0 without a cache, and variables corresponding to security-related data in memory can be stored in SRAM0 with ECC protection. Variables corresponding to large-capacity data are stored in SDRAM.

[0076] In this embodiment, the optimized memory layout update based on OTA significantly reduces the update package size, shortens the update time, lowers network requirements during updates, and effectively improves update efficiency. Through the optimized memory layout update, more high-frequency variables enter the L1 Cache area, improving cache hit rate and the utilization of fast memory. Furthermore, this embodiment can achieve continuous optimization throughout the entire lifecycle, such as continuous optimization based on actual vehicle usage patterns, customized optimization based on different driving habits and road conditions, and automatic re-optimization after software upgrades. This embodiment also boasts extremely high security and reliability. Atomic switching and rollback mechanisms improve update success rate, and post-optimization verification testing ensures that original functionality is not compromised. This embodiment also reduces development and maintenance costs, minimizes manual optimization work, increases automation, allows for rapid repair of some performance issues via OTA, and enables continuous improvement of vehicle performance through software updates.

[0077] See Figure 8 The diagram shown is a schematic representation of a memory layout optimization device according to an embodiment of this application. In one embodiment of this application, the memory layout optimization device 200 may include multiple functional modules composed of computer program segments. The computer program segments in the memory layout optimization device 200 may be stored in the memory of an electronic device or vehicle and executed by at least one processor to perform memory layout optimization functions.

[0078] In one embodiment of this application, the memory layout optimization device 200 can be divided into multiple functional modules based on the functions it performs. The functional modules of the memory layout optimization device 200 may include: a collection module 201, an extraction module 202, a generation module 203, and an update module 204. In this embodiment, a module refers to a series of computer program segments that can be executed by at least one processor and perform a fixed function, and which are stored in memory.

[0079] The acquisition module 201 is used to acquire access data of variables in the memory of the electronic control unit during the operation of the electronic control unit.

[0080] The extraction module 202 is used to extract the data characteristics of the access data of the variables.

[0081] The generation module 203 is used to generate memory allocation schemes for variables based on data characteristics.

[0082] Update module 204 is used to update the variable layout of memory based on the variable memory allocation scheme.

[0083] See Figure 9The diagram shown is a hardware structure schematic of an electronic device according to an embodiment of this application. The memory layout optimization method provided in this embodiment can be applied to electronic device 1, which may be a personal computer or the like. Electronic device 1 includes, but is not limited to, a processor 110 and a memory 120 connected via a communication bus 130. Figure 9 This is merely an example of an electronic device and does not constitute a limitation thereof. In other embodiments, the electronic device may include more components than those shown in the figure.

[0084] See Figure 10 The diagram shown is a schematic representation of the hardware structure of a vehicle according to an embodiment of this application. The memory layout optimization method provided in this embodiment can be applied to vehicle 2. Vehicle 2 includes, but is not limited to, a processor 210 and a memory 220 connected via a communication bus 230. For example, the processor 210 may be the electronic control unit in the above embodiment. Figure 10 This is merely an example of a vehicle and does not constitute a limitation thereof. In other embodiments, the vehicle may include more components than those shown in the figure.

[0085] Memory may include one or more Random Access Memory (RAM) and one or more Non-Volatile Memory (NVM). RAM can be directly read and written by the processor and can be used to store executable programs (such as machine instructions) of the operating system or other running programs, as well as user and application data. RAM may include Static Random-Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), and Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), etc.

[0086] Non-volatile memory can also store executable programs and user and application data, and can be pre-loaded into random access memory for direct read and write operations by the processor. Non-volatile memory can include disk storage devices and flash memory (RAM).

[0087] Memory is used to store one or more computer programs. These one or more computer programs are configured to be executed by a processor. The one or more computer programs include multiple instructions that, when executed by the processor, enable memory layout optimization methods for execution on an electronic device.

[0088] In other embodiments, the electronic device further includes an external memory interface for connecting to an external memory to expand the storage capacity of the electronic device.

[0089] A processor may include one or more processing units, such as an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0090] The processor provides computing and control capabilities; for example, the processor is used to execute computer programs stored in memory to implement the memory layout optimization methods described above.

[0091] A communication bus is used at least to provide a channel for communication between memory and processor in an electronic device.

[0092] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0093] This application also provides a computer storage medium storing computer instructions. When the computer instructions are executed on an electronic device, the electronic device performs the aforementioned related method steps to achieve the memory layout optimization method in the above embodiments.

[0094] This application also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned steps to implement the memory layout optimization method described in the above embodiments.

[0095] In addition, embodiments of this application also provide an apparatus, which may specifically be a chip, component or module. The apparatus may include a connected processor and a memory; wherein the memory is used to store computer execution instructions, and when the apparatus is running, the processor may execute the computer execution instructions stored in the memory to cause the chip to execute the memory layout optimization method in the above method embodiments.

[0096] In this application, the electronic devices, computer storage media, computer program products or chips provided in the embodiments are all used to execute the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0097] Through the above description of the implementation methods, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0098] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0099] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected based on actual needs to achieve the purpose of this embodiment.

[0100] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0101] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts or all or part of the technical solutions that contribute to the prior art, can be embodied in the form of a software product. The software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the spirit and scope of the technical solutions of this application.

Claims

1. A memory layout optimization method, characterized in that, The method includes: During the operation of the electronic control unit, access data of variables in the memory of the electronic control unit are collected; Extract the data characteristics of the access data of the variables; A memory allocation scheme for the variables is generated based on the data characteristics; The memory variable layout is updated based on the memory allocation scheme of the variables.

2. The memory layout optimization method according to claim 1, characterized in that, The method further includes: Before compiling the code in the memory, a first region and a second region are preset in the memory. The first region is used to store the variables, and the second region is used to store the redirection mapping table of variable addresses. After the code is compiled, the redirection mapping table is generated and stored in the second area; When the code runs, based on the redirection mapping table, the variable is transferred from its original storage address to a storage address in the random access memory (RAM).

3. The memory layout optimization method according to claim 1, characterized in that, The access data includes at least one of variable address, read count, write count, access time, and correlation with other variables. The data features for extracting the access data of the variables include: Based on the number of reads and writes of the variable, the access frequency of the variable is calculated as the popularity of the variable; Based on the aforementioned relationships with other variables, determine the frequently accessed variables associated with the aforementioned variables; The frequently accessed variables corresponding to the variable are transferred to a storage address adjacent to the variable, and the correlation degree between the variable and the frequently accessed variables is calculated.

4. The memory layout optimization method according to claim 3, characterized in that, The memory allocation scheme for generating the variables based on the data features includes: Based on the aforementioned data characteristics, a memory allocation scheme for the variables is generated using a heat-aware heterogeneous memory data allocation algorithm, including: Multiple heat levels are determined based on multiple preset heat thresholds; Establish a mapping relationship between multiple popularity levels and multiple memory regions; Based on the target popularity level corresponding to the popularity of the variable and the mapping relationship, the target memory regions of the variable and other variables that are highly associated with the variable are determined, wherein the other variables that are highly associated with the variable are high-frequency access variables whose association degree is greater than or equal to a preset threshold.

5. The memory layout optimization method according to claim 4, characterized in that, The memory allocation scheme for generating the variables based on the data features further includes: If the target memory region does not meet the preset constraints of the variable, or the target memory region is incompatible with the variable, or the capacity of the variable is greater than the remaining capacity of the target memory region, the memory region corresponding to the next level of popularity of the target popularity level will be used as the updated target memory region until the updated target memory region meets the preset constraints of the variable, the updated target memory region is compatible with the variable, and the capacity of the variable is greater than the remaining capacity of the target memory region.

6. The memory layout optimization method according to claim 4 or 5, characterized in that, The memory allocation scheme for generating the variables based on the data features further includes: The target addresses of the variable and other variables highly associated with the variable are allocated in the target memory region. Based on the variable and other variables highly associated with the variable, the target memory region, and the target address, an updated redirection mapping table is generated.

7. The memory layout optimization method according to claim 1, characterized in that, The memory allocation scheme based on the variables updates the variable layout of the memory, including: The memory allocation scheme is updated to the memory using Over-the-Air (OTA) technology.

8. An electronic device, characterized in that, The electronic device includes a memory and a processor: The memory is used to store program instructions; The processor is configured to read and execute the program instructions stored in the memory, and when the program instructions are executed by the processor, the electronic device performs the memory layout optimization method according to any one of claims 1 to 7.

9. A vehicle, characterized in that, The vehicle includes a memory and a processor: The memory is used to store program instructions; The processor is configured to read and execute the program instructions stored in the memory, and when the program instructions are executed by the processor, cause the vehicle to perform the memory layout optimization method according to any one of claims 1 to 7.

10. A computer storage medium, characterized in that, The computer storage medium stores program instructions that, when executed on an electronic device or vehicle, cause the processor of the electronic device or vehicle to perform the memory layout optimization method according to any one of claims 1 to 7.

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