Silicon wafers, solar cells and photovoltaic modules

Abstract

This invention discloses a silicon wafer, a solar cell, and a photovoltaic module, relating to the field of silicon wafer manufacturing technology, and is used to solve the problem of high silicon wafer breakage rate. The silicon wafer is rectangular, and the length-to-width ratio of the silicon wafer is 1:0.4 to 1:0.6; the silicon wafer includes two surfaces and four side surfaces located between the two surfaces; at least one surface has multiple dicing marks extending along the width direction of the silicon wafer, and the dicing marks are arc-shaped; along the direction parallel to the extension path of the dicing marks, the silicon wafer is sequentially divided into a first edge region, a central region, and a second edge region; the width of the first edge region and the second edge region in the direction parallel to the extension path of the dicing marks is greater than or equal to 5 mm and less than or equal to 20 mm; wherein, the average thickness of the first edge region and / or the average thickness of the second edge region is greater than the average thickness of the central region.

Description

[0001] This application claims priority to Chinese Patent Application No. 202510170252.7, filed on February 14, 2025, entitled "Silicon Wafers, Solar Cells and Photovoltaic Modules", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of silicon wafer manufacturing technology, and more particularly to a silicon wafer, a solar cell, and a photovoltaic module. Background Technology

[0003] With the development of the photovoltaic industry, half-wafers are widely used in photovoltaic module manufacturing. A half-wafer is typically half the size of a full-wafer (a nearly square rectangular wafer). Compared to a full-wafer, a half-wafer has a longer, strip-shaped structure, making it less resistant to stress and more prone to breakage due to stress concentration. As the size of photovoltaic silicon wafers continues to increase, the size of half-wafers also increases. During the manufacturing, transport, handling, and processing of silicon wafers, the breakage rate becomes increasingly prominent due to their own weight and the effects of minor external impacts or localized pressure. Summary of the Invention

[0004] The purpose of this invention is to provide a silicon wafer, a solar cell, and a photovoltaic module to improve the strength of the silicon wafer and reduce the breakage rate.

[0005] In a first aspect, the present invention provides a silicon wafer, the silicon wafer being rectangular, and the length-to-width ratio of the silicon wafer being 1:0.4 to 1:0.6; the silicon wafer comprising two opposing surfaces and four side surfaces located between the two surfaces; at least one of the surfaces having a plurality of dicing marks extending along the width direction of the silicon wafer, the dicing marks being arc-shaped; the silicon wafer having a first edge region, a central region, and a second edge region along a direction parallel to the extension path of the dicing marks; the width of the first edge region and the second edge region in the direction parallel to the extension path of the dicing marks being greater than or equal to 5 mm and less than or equal to 20 mm; the central region being located between the first edge region and the second edge region; wherein the average thickness of the first edge region and / or the average thickness of the second edge region is greater than the average thickness of the central region.

[0006] With the above technical solution, the length-to-width ratio of the rectangular silicon wafer is 1:0.4 to 1:0.6. The wafer shape is typically half of a full silicon wafer, approximately rectangular, and is a half-wafer. The dicing marks are mechanical damage generated on the silicon wafer surface during the dicing process. In this application, the dicing marks extend along the width of the silicon wafer to the two opposite long sides. Compared to the dimensions of the long sides of the silicon wafer, the length of a single dicing mark is significantly smaller, but it penetrates the entire width of the silicon wafer. The starting and ending positions of the dicing marks fall on the edge regions parallel to the long sides (the first edge region and the second edge region). In the manufacturing, transport, and handling of silicon wafers... During transportation and processing, the four corners of the silicon wafer and the middle section of the long edge (first edge region and second edge region) are key areas of stress concentration. Multiple cutting marks penetrate the edge region parallel to the long edge, further weakening the structural integrity of the long edge and making it more prone to cracking. In this application, by controlling the average thickness of at least one long edge region (first edge region and / or second edge region) to be greater than the average thickness of the central region located between the first edge region and the second edge region, the structural strength of the long edge is improved, thereby reducing the overall risk of silicon wafer cracking or microcracks, and thus reducing the breakage rate.

[0007] Optionally, the average thickness of the central region is between the average thickness of the first edge region and the average thickness of the second edge region. By sequentially increasing the average thickness of the first edge region, the central region, and the second edge region along the first direction L1, the overall strength of the silicon wafer can be improved while controlling the difference in average thickness between adjacent regions, thereby further reducing the risk of the silicon wafer breaking.

[0008] Optionally, the average thickness of the central region is less than the average thickness of the first edge region and the average thickness of the second edge region. By making the average thickness of the two long edge regions greater than the thickness of the central region, the structural strength of the two edges of the silicon wafer can be enhanced simultaneously, further reducing the risk of microcracks or fragmentation caused by edge stress concentration.

[0009] Optionally, the difference between the average thickness of the central region and the average thickness of the first edge region and / or the second edge region is greater than 0.1 μm and less than or equal to 1.5 μm. Setting the average thickness difference between the central region and the first edge region and / or the second edge region within this range significantly increases the average thickness of the long edge of the silicon wafer, thereby improving the structural strength of the long edge and reducing the likelihood of cracking at the center of the long edge. Simultaneously, the average thickness difference between the regions is not excessive, thus improving the overall strength of the silicon wafer. Furthermore, setting the average thickness difference between the central region and the first edge region and / or the second edge region within this range also minimizes the stress differences between silicon wafers during mass production, thereby reducing the breakage rate and the probability of microcracks during processing.

[0010] Optionally, the difference between the average thickness of the central region and the average thickness of the first edge region and / or the second edge region is greater than 0.3 μm and less than or equal to 0.8 μm.

[0011] Optionally, both ends of the first edge region and the second edge region have chamfers in the direction perpendicular to the extension path of the cut mark; the chamfers are either arc-shaped or straight. By setting the four corners of the silicon wafer as chamfers, stress concentration at the corners can be reduced, thereby lowering the risk of the silicon wafer fragmenting at the corners. Since this silicon wafer is a half-wafer, obtained by cutting the entire square silicon rod in half along a direction parallel to the slicing direction (i.e., vertically halving) and then slicing it again, a larger chamfer is typically formed on the original surface of the square silicon rod, while a smaller chamfer is formed on the new cut surface obtained after vertically halving the square silicon rod. On the one hand, a larger chamfer on the silicon wafer can reduce the amount of material removed from the original silicon rod, improving the utilization rate of the silicon rod; on the other hand, a smaller chamfer on the silicon wafer can save grinding time, improve processing efficiency, and increase the effective utilization area of ​​the silicon wafer.

[0012] Optionally, the size of the chamfer on the first edge region is greater than or equal to the size of the chamfer on the second edge region.

[0013] Optionally, the projected length of the chamfer on the first edge region and / or the second edge region on the edge length of the silicon wafer is greater than or equal to 0.05 mm and less than or equal to 9 mm; and / or, the projected length of the chamfer on the second edge region on the edge length of the silicon wafer is less than or equal to 8.5 mm.

[0014] Optionally, the length of the silicon wafer is 166mm-230mm; and / or, the average thickness of the silicon wafer is 100μm-150μm; and / or, the width of the silicon wafer is 80μm-140mm; and / or, the number of dicing marks is greater than 10; and / or, the spacing between adjacent dicing marks is greater than 1mm; and / or, the arc height of the dicing mark is greater than 1mm and less than 17mm; and / or, the depth of the dicing mark is greater than 1μm and less than 15μm.

[0015] In a second aspect, the present invention also provides a battery cell comprising a silicon substrate and electrodes formed on the silicon substrate, wherein the silicon substrate is a silicon wafer as described in any of the preceding claims, and has the same beneficial effects as the first aspect.

[0016] Thirdly, the present invention also provides a photovoltaic module comprising a plurality of interconnected solar cells, wherein the solar cells are those described above, and has the same beneficial effects as the second aspect. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the structure of a silicon wafer (half-wafer) provided in an embodiment of this application; Figure 2 This is a schematic diagram for measuring the thickness of a silicon wafer provided in an embodiment of this application.

[0018] The accompanying figure is labeled as follows: 100. Silicon wafers; 10. First edge region; 20. Central region; 30. Second edge region; S. Cutting mark; L1, first direction; L2, second direction. Detailed Implementation

[0019] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0020] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0022] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0023] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0024] like Figure 1 As shown, this embodiment of the invention provides a silicon wafer 100, which is approximately rectangular. The length-to-width ratio of the silicon wafer 100 is 1:0.4 to 1:0.6, and the specific ratio can be 1:0.4, 1:0.5, 1:0.6, etc. The silicon wafer 100 is approximately rectangular. A silicon wafer 100 with a relatively large difference between its length and width is called a half wafer. In this application, the length of the silicon wafer 100 is 166mm-230mm, and the width of the silicon wafer 100 is 80mm-140mm. For example, the dimensions of silicon wafer 100 can be 166mm×83mm; 166mm×91mm; 182mm×91mm; 182mm×105mm; 210mm×105mm; 210mm×110mm; 220mm×105mm; 220mm×110mm; 230mm×110mm; 230mm×115mm; 230mm×120mm. The average thickness of silicon wafer 100 is between 100μm and 150μm, for example, it can be 100μm, 105μm, 110μm, 115μm, 120μm, 125μm, 130μm, 135μm, 140μm, 145μm, or 150μm.

[0025] The silicon wafer 100 provided by the present invention includes two opposing surfaces and four side surfaces located between the two surfaces; at least one surface is provided with multiple cutting marks S extending along the width direction of the silicon wafer 100; the cutting marks S are arc-shaped; the cutting marks S are arc-shaped cutting marks formed along the surface of the silicon wafer 100 and approximately parallel to the short edge of the silicon wafer 100, and such cutting marks generally penetrate the two long sides of the entire silicon wafer 100. Because flexible cutting wires (such as diamond wire, steel wire, tungsten wire, etc.) are used to cut the silicon rod during the cutting process, there are tension differences at the inlet end, middle end and outlet end of the flexible cutting wire, resulting in uneven cutting force at different positions of the cutting wire, which in turn causes the cutting wire to form an arc-shaped cutting trajectory on the surface of the silicon rod. This trajectory is retained on the surface of the silicon wafer after the silicon rod is cut into a silicon wafer, that is, forming the arc-shaped cutting marks S.

[0026] The number of dicing marks S is typically greater than 10; the spacing between adjacent dicing marks S is greater than 1 mm; the arc height (distance from the bottom to the top of the arc) of dicing mark S is generally greater than 1 mm; the depth of dicing mark S is greater than 1 μm and less than 15 μm. It should be noted that dicing marks S form a protruding structure on the silicon wafer surface, and its depth refers to the vertical distance between the bottom of the recessed area and the apex of the protrusion. Because the depth of dicing marks S affects the subsequent cell fabrication, existing technologies control the depth of dicing marks S. If the depth of dicing mark S is greater than or equal to 15 μm, it is considered a defective product. The number of dicing marks S, the spacing between adjacent dicing marks S, and the arc height of dicing marks S are not controlled in normal products. The parameters of the number of dicing marks S, the spacing between adjacent dicing marks S, the arc height, and the depth can be measured using optical microscopy, SEM (scanning electron microscopy), AFM (atomic force microscopy), surface roughness testers, laser scanning microscopy, and image analysis software. Figure 1 Only a portion of the cut marks S are shown.

[0027] In this application, the extension direction of the cutting mark S on the surface of the silicon wafer 100 is used as a reference. The extension direction of the cutting mark S parallel to the surface of the silicon wafer 100 is set as the first direction L1, that is, the width direction of the silicon wafer; the extension direction of the cutting mark S perpendicular to the surface of the silicon wafer 100 is set as the second direction L2, that is, the length direction of the silicon wafer; in the first direction L1, the silicon wafer 100 is provided with a first edge region 10, a central region 20 and a second edge region 30. The first edge region 10 and the second edge region 30 are two edge regions parallel to the direction of the cutting mark S (first direction L1), that is, the first edge region 10 and the second edge region 30 are two edge regions parallel to the long side direction of the silicon wafer 100. The first edge region 10 is actually a portion extending a certain size from the first side of the silicon wafer 100 parallel to the second direction L2 along the first direction L1, and the second edge region 30 is actually a portion extending a certain size from the second side of the silicon wafer 100 parallel to the second direction L2 along the first direction L1. The first side and the second side are two sides of the silicon wafer 100 opposite each other in the first direction L1. The width of the edge region 30 in the direction parallel to the extension path of the cutting mark S is greater than or equal to 5 mm and less than or equal to 20 mm; the center region 20 is located between the first edge region 10 and the second edge region 30; wherein, the average thickness of the first edge region 10 and / or the average thickness of the second edge region 30 is greater than the average thickness of the center region 20, specifically, only the average thickness of the first edge region 10 is greater than the average thickness of the center region 20, or only the average thickness of the second edge region 30 is greater than the average thickness of the center region 20, or both the average thickness of the first edge region 10 and the average thickness of the second edge region 30 are greater than the average thickness of the center region 20.

[0028] When using the above technical solution, the length-to-width ratio of the rectangular silicon wafer is 1:0.4 to 1:0.6, such as... Figure 1As shown, the silicon wafer 100 is typically half the size of a full silicon wafer, approximately rectangular, and is a half-wafer. The dicing marks S are mechanical damage generated on the silicon wafer surface during the dicing process. In this application, the dicing marks S extend along the width of the silicon wafer 100 to its two opposite long sides. Compared to the dimensions of the long sides of the silicon wafer, the length of a single dicing mark S is significantly smaller, but it penetrates the entire width of the silicon wafer 100. The starting and ending positions of the dicing marks S fall on edge regions parallel to the long sides (first edge region 10 and second edge region 30). During the manufacturing, transport, handling, and processing of the silicon wafer, the four corners of the silicon wafer 100 and... The middle section of the long edge (first edge region 10 and second edge region 30) is a critical area of ​​stress concentration. Multiple cutting marks S penetrate the edge region parallel to the long edge, further weakening the structural integrity of the long edge and making it more prone to cracking. In this application, by controlling the average thickness of at least one long edge region (first edge region 10 and / or second edge region 30) to be greater than the average thickness of the central region 20 located between the first edge region 10 and the second edge region 30, the structural strength of the long edge is improved, thereby reducing the risk of silicon wafer cracking or microcracks as a whole, and thus reducing the fragmentation rate.

[0029] The width of the first edge region 10 or the second edge region 30 in the direction parallel to the extension path of the cutting mark S is greater than or equal to 5 mm and less than or equal to 20 mm. That is, the size of the first edge region 10 in the first direction L1 is 5mm-20mm, and the size of the second edge region 30 in the first direction L1 is 5mm-20mm. In other words, the first edge region 10 is actually a region greater than or equal to 5mm and less than or equal to 20mm from the first edge of the silicon wafer 100, such as a region 6mm, 7mm, 8mm, 9mm, 10mm, 11mm, 12mm, 13mm, 14mm, 15mm, 16mm, 17mm, 18mm, 19mm, or 20mm from the first edge; the second edge region 30 is actually a region greater than or equal to 5mm and less than or equal to 20mm from the second edge of the silicon wafer 100, such as a region 6mm, 7mm, 8mm, 9mm, 10mm, 11mm, 12mm, 13mm, 14mm, 15mm, 16mm, 17mm, 18mm, 19mm, or 20mm from the second edge. The central region 20 comprises all regions other than the first edge region 10 and the second edge region 30. The width of the first edge region 10 or the second edge region 30 is set within the range described above, ensuring that the width of the two edge regions is neither too wide nor too narrow, thereby effectively improving the structural strength of the two opposite edge regions in the first direction as well as the structural strength of the four corners.

[0030] It should be noted that the thickness of each part in this application can be measured using the following measuring equipment and methods. Please refer to [link / reference]. Figure 2 The device used is a high-precision laser displacement sensor. Three detection lines M1, M2, and M3 are spaced apart along the first direction L1 on the silicon wafer 100. These three detection lines correspond to three sets of laser probes (two probes per set, for a total of six probes). The starting detection point on each detection line (e.g., ...) Figure 2 (at n=1 in the middle) and end detection points (such as Figure 2 At n=5, the two nearest edges of the silicon wafer are 8mm apart, and the other three points are evenly distributed between the starting and ending detection points.

[0031] Specifically, at least 1000 points are measured on each detection line, and these 1000 points are divided into 5 equal parts. An average value is calculated for each part, resulting in 5 average values ​​for each detection line, for a total of 15 average values. The average thickness of the first edge region 10, the central region 20, and the second edge region 30 are respectively the average values ​​of the 5 points on M1, the average values ​​of the 5 points on M2, and the average values ​​of the 5 average values ​​on M3.

[0032] like Figure 1 As shown, for example, the ratio between the size of the silicon wafer 100 in the first direction L1 and the size of the silicon wafer 100 in the second direction L2 can be 0.4:1, 0.5:1, 0.6:1, etc. For example, the size of the silicon wafer 100 can be 91mm×210mm, 91mm×182mm, 105mm×210mm, 105mm×182mm, etc.

[0033] like Figure 1As shown, in some embodiments, the average thickness of the central region 20 is between the average thickness of the first edge region 10 and the average thickness of the second edge region 30. Specifically, when the average thickness of the first edge region 10 is less than the average thickness of the second edge region 30, the average thickness of the central region 20 is greater than the average thickness of the first edge region 10 and less than the average thickness of the second edge region 30; or, when the average thickness of the first edge region 10 is greater than the average thickness of the second edge region 30, the average thickness of the central region 20 is greater than the average thickness of the second edge region 30 and less than the average thickness of the first edge region 10. Therefore, by sequentially increasing the average thickness of the first edge region 10, the central region 20, and the second edge region 30 in the first direction L1, the strength of one of the long edges of the silicon wafer 100 can be improved while controlling the average thickness difference between adjacent regions, thereby increasing the overall strength of the silicon wafer 100 and further reducing the risk of breakage. Furthermore, based on the increased overall strength of the silicon wafer 100, the breakage rate and the probability of microcracks in the silicon wafer 100 are greatly reduced during mass production.

[0034] In other embodiments, the average thickness of the central region 20 is less than the average thickness of the first edge region 10 and the average thickness of the second edge region 30. Specifically, the average thickness of the central region 20 is less than both the average thickness of the first edge region 10 and the average thickness of the second edge region 30. By making the average thickness of the two long edge regions greater than the thickness of the central region, the structural strength of the two edges of the silicon wafer can be enhanced simultaneously, further reducing the risk of microcracks or fragmentation caused by edge stress concentration.

[0035] In some embodiments, the difference between the average thickness of the central region 20 and the average thickness of the first edge region 10 and / or the second edge region 30 is greater than 0.1 μm and less than or equal to 1.5 μm. That is, the difference between the average thickness of the central region 20 and the average thickness of the first edge region 10 is only greater than 0.1 μm and less than or equal to 1.5 μm; or, the difference between the average thickness of the central region 20 and the average thickness of the second edge region 30 is only greater than 0.1 μm and less than or equal to 1.5 μm; or, the difference between the average thickness of the central region 20 and the average thickness of both the first edge region 10 and the second edge region 30 is greater than 0.1 μm and less than or equal to 1.5 μm. For example, the difference between the average thickness of the central region 20 and the average thickness of the first edge region 10 and / or the second edge region 30 can be 0.11 μm, 0.2 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, etc.

[0036] Preferably, the difference between the average thickness of the central region 20 and the average thickness of the first edge region 10 and / or the second edge region 30 is greater than 0.3 μm and less than or equal to 0.8 μm. Specifically, the average thickness difference can be 0.31 μm, 0.4 μm, 0.45 μm, 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, 0.8 μm, etc.

[0037] In this embodiment, setting the average thickness difference between the central region 20 and the first edge region 10 and / or the second edge region 30 within the aforementioned range significantly increases the average thickness of the long edge of the silicon wafer. This improves the structural strength of the long edge, making it less prone to cracking at the center of the long edge, while minimizing the average thickness difference between regions, thereby enhancing the overall strength of the silicon wafer 100. Furthermore, setting the average thickness difference between the central region 20 and the first edge region 10 and / or the second edge region 30 within the aforementioned range also minimizes the stress differences between silicon wafers during mass production, thereby reducing the breakage rate and the probability of microcracks during processing.

[0038] like Figure 1 As shown, in some embodiments, both ends of the first edge region 10 and the second edge region 30 have chamfers in the direction perpendicular to the extension path of the dicing mark S. That is, the silicon wafer has a first side and a second side oppositely arranged along a first direction L1, and a third side and a fourth side oppositely arranged along a second direction L2, with chamfers formed between adjacent sides. The chamfers are either curved or straight. By setting the four corners of the silicon wafer 100 as chamfers, stress concentration at the corners can be reduced, thereby reducing the risk of the silicon wafer 100 fragmenting at the corners.

[0039] like Figure 1 As shown, in some embodiments, the chamfer size on the first edge region 10 is greater than or equal to the chamfer size on the second edge region 30. The chamfer size can be represented by the projection length of the chamfer onto the edge length of the silicon wafer. Since the silicon wafer 100 is a half wafer, it is obtained by cutting the entire square silicon rod in half along the cutting direction parallel to the slicing direction, i.e., vertically cutting it in half, and then slicing it again. Usually, the larger chamfer is formed on the original surface of the square silicon rod, and the smaller chamfer is formed on the new cut surface obtained after vertically cutting the square silicon rod in half. On the one hand, the larger chamfer on the silicon wafer can reduce the removal of the original silicon rod and improve the utilization rate of the silicon rod. On the other hand, the smaller chamfer on the silicon wafer 100 can save grinding time, improve processing efficiency, and increase the effective utilization area of ​​the silicon wafer.

[0040] In one alternative approach, the chamfer size on the first edge region 10 is equal to the chamfer size on the second edge region 30, thereby reducing stress concentration at the corners.

[0041] In some embodiments, the projected length of the chamfer on the first edge region 10 or the second edge region 30 onto the side length of the silicon wafer 100 is greater than or equal to 0.05 mm and less than or equal to 9 mm. For example, the projected length of each chamfer onto the side length of the silicon wafer 100 can be 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, or 9 mm.

[0042] In one alternative approach, the chamfer on the first edge region 10 is larger than the chamfer on the second edge region 30, thereby reducing stress concentration at the corner.

[0043] In some embodiments, such as Figure 1 As shown, the projected length of the chamfer on the first edge region 10 onto the side length of the silicon wafer 100 is greater than or equal to 0.05 mm and less than or equal to 9 mm. For example, it can be 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, or 9 mm.

[0044] The projection length of the chamfer on the second edge region 30 onto the side length of the silicon wafer 100 is greater than 0 and less than or equal to 8.5 mm; for example, it can be 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm or 8.5 mm.

[0045] In the aforementioned chamfering process, if the projected length of the chamfer is less than 0.05 mm, the chamfer size is too small, failing to effectively reduce stress concentration and resulting in an excessively large area to be removed from the silicon ingot, reducing silicon ingot utilization and increasing processing difficulty. If the projected length of the chamfer is greater than 9 mm, the chamfer size is too large, reducing the effective usable area of ​​the silicon wafer 100. Therefore, chamfering within the aforementioned range can reduce stress concentration at the corners of the silicon wafer 100, lowering the risk of chipping or microcracks at the corners, while also improving silicon ingot utilization and the effective usable area of ​​the silicon wafer 100, and reducing the difficulty of chamfering processing.

[0046] If the projected length of the chamfer is greater than 8.5mm, the chamfer size is too large, reducing the effective usable area of ​​the silicon wafer 100. Therefore, keeping the chamfer size within the above range can reduce stress concentration at the corners of the silicon wafer 100, thereby reducing the risk of chipping or microcracks at the corners of the silicon wafer 100, while also increasing the effective usable area of ​​the silicon wafer 100.

[0047] It should be noted that the projected length of the chamfer on the side of the silicon wafer 100 refers to the projected length of the chamfer on either the long or short side of the silicon wafer 100, and the projected lengths of all chamfers on the same silicon wafer 100 are uniformly the projected lengths of the chamfers on the side of the same direction on the silicon wafer. The projected length of a chamfer on the long side of the silicon wafer 100 can be equal to its projected length on the short side of the silicon wafer 100. Alternatively, when the projected length of a chamfer on the long side of the silicon wafer 100 is not equal to its projected length on the short side, the longer of the two projected lengths can be used as the projected length of the chamfer on the side of the silicon wafer 100.

[0048] The silicon wafer 100 described above in this application can be prepared by the following method, including steps S100 and S200.

[0049] S100 provides single-crystal rectangular silicon rods. Specifically, single-crystal rectangular silicon rods can be formed by Czochralski pulling of single crystals, truncating, squaring, and chamfering.

[0050] The process of Czochralski single crystal growth is as follows: raw materials and dopants are placed in a quartz crucible; the crystal growth furnace containing the quartz crucible is then evacuated; the raw materials are then melted by heating with an electric power source; after the raw materials have melted, a circular Czochralski single crystal silicon rod is obtained through crystal pulling, necking, constant diameter growth and tailing.

[0051] The cutting process is as follows: the head and tail of the Czochralski single crystal silicon rod are removed by cutting equipment (such as a diamond wire single crystal silicon rod cutting machine), and the long Czochralski single crystal silicon rod is cut into multiple short single crystal silicon rods.

[0052] The squaring process is as follows: A squaring machine feeds the truncated short monocrystalline silicon rod along its length and cuts four parallel planes around its circumference, making the monocrystalline silicon rod into a cuboid or cuboid shape. Then, the corresponding monocrystalline rectangular silicon rod is cut along the second direction (L2 direction), i.e., vertically halved, to obtain two monocrystalline rectangular silicon rods. The newly cut ends of each monocrystalline rectangular silicon rod are then chamfered again to obtain rounded or right-angled chamfers, thus obtaining the corresponding half-wafer monocrystalline rectangular silicon rod. It is understandable that there are no actual cutting marks during the squaring process; therefore, the L2 direction at this point is actually a pre-planned processing direction in subsequent processes based on target requirements.

[0053] In one optional embodiment, in the single-crystal rectangular silicon rod corresponding to the vertically cut half, the chamfer size of the second edge region 30 can be smaller than the chamfer size of the first edge region 10, such as... Figure 1 As shown.

[0054] The chamfering process: The length of the single-crystal silicon rod after square rooting is chamfered by a grinding wheel to obtain a single-crystal rectangular silicon rod with rounded or straight chamfered corners.

[0055] S200 involves bonding the monocrystalline rectangular silicon rod together and then fixing it onto a cutting device for cutting.

[0056] Specifically, the cutting equipment can be a diamond wire cutter, which forms a diamond wire cutting mesh on the main roller through the guidance of guide rollers. The diamond wire cutting mesh is then guided into the interior of the monocrystalline rectangular silicon rod through friction by the raising or lowering of the equipment, until the silicon wafer 100 in the above embodiment is obtained. The monocrystalline rectangular silicon rod is positioned directly above the cutting mesh, and spray devices can be installed on both sides of the rod. The spray devices spray cutting fluid from both sides towards the cutting mesh, and the cutting fluid enters the kerf at different positions along with the mesh to cool it.

[0057] When cutting a vertically cut silicon wafer, that is, when cutting along the width direction of a silicon rod, in order to control the average thickness of the first edge region 10 and / or the second edge region 30 to be greater than the average thickness of the center region 20, the thermal expansion of the cutting mesh in the edge region of the silicon wafer 100 can be controlled to be less than that in the center region; or the wire diameter at both ends of the cutting mesh can be controlled to be less than that in the middle by controlling the cutting speed. Specifically, by setting the spray position or spray angle, for example by controlling the distance between the single-crystal rectangular silicon rod and the cutting liquid surface, controlling the horizontal distance between the spray device and the silicon rod, or controlling the spray device to spray the cutting liquid from both sides toward the cutting wire mesh at a certain angle, the cutting liquid can be maximized to enter the cut, thereby making the thermal expansion degree of the central region greater than that of the edge region, and ultimately making the average thickness of the first edge region 10 and / or the second edge region 30 less than the average thickness of the central region 20.

[0058] Alternatively, the cutting speed of the wire mesh can be controlled, for example, by reducing the cutting speed of the wire mesh to a certain extent. This reduces the amount of wire mesh stretching during cutting, preventing the wire diameter in the central region from becoming thinner. On the other hand, it reduces the heat generated during cutting, preventing excessive thermal expansion of the wire diameter. Ultimately, this results in the average thickness of the first edge region 10 and / or the second edge region 30 being less than the average thickness of the central region 20.

[0059] In addition, after the silicon wafer 100 is obtained by cutting and before it is transported to the cell end, the silicon wafer 100 can be cleaned, sorted and inspected.

[0060] Specifically, the cleaning process involves using various acid and alkali tanks inside the cleaning machine to clean the dirt, damaged layers, and other impurities and defects on the cut silicon wafers, ultimately resulting in clean silicon wafers.

[0061] The sorting and inspection process involves measuring the resistivity, minority carrier lifetime, thickness, TTV, edge chipping, microcracks, and other defects of the silicon wafers using sorting and inspection equipment. Wafers with different properties are then graded to obtain the final silicon wafer product. Because this application utilizes the above-described preparation method, the overall strength of the silicon wafer 100 is improved, thereby reducing the risk of breakage during subsequent battery fabrication.

[0062] To make the objectives, technical solutions, and beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments 1-2 and comparative example 1. However, the specific embodiments described are only used to explain the present invention and are not intended to limit the present invention.

[0063] Examples 1-2 and Comparative Example 1 are half-wafers of silicon wafers that have been sorted and inspected using the same sorting machine to determine defects such as resistivity, minority carrier lifetime, thickness, TTV, edge chipping, and microcracks. They can be grouped according to their size and average thickness: The first group consists of 10,000 vertically sliced ​​halves, such as... Figure 1As shown, each silicon wafer 100 has a size of 182mm × 91mm. The direction of the extension path of the dicing mark S is along the width direction of the silicon wafer 100. The silicon wafer includes 4 chamfers. The dimensions of the two chamfers in the first edge region 10 are greater than the dimensions of the two chamfers in the second edge region 30. The dimensions of the two chamfers in the first edge region 10 are greater than or equal to 0.05mm and less than or equal to 9mm. The projection length of the dimensions of the two chamfers in the second edge region 30 on the side length of the silicon wafer 100 is greater than 0 and less than or equal to 8.5mm. The average thickness of each silicon wafer 100 is between 130-135μm.

[0064] The second group consists of 10,000 vertically sliced ​​halves, such as... Figure 1 As shown, each silicon wafer 100 has a size of 182mm × 91mm. The direction of the extension path of the dicing mark S is along the width direction of the silicon wafer 100. The silicon wafer 100 includes 4 chamfers. The dimensions of the two chamfers in the first edge region 10 are larger than the dimensions of the two chamfers in the second edge region 30. The dimensions of the two chamfers in the first edge region 10 are greater than or equal to 0.05mm and less than or equal to 9mm. The projected length of the dimensions of the two chamfers in the second edge region 30 on the side length of the silicon wafer 100 is greater than 0 and less than or equal to 8.5mm. The average thickness of each silicon wafer 100 is between 105-115μm.

[0065] In Examples 1-2 and Comparative Example 1, both sets of silicon wafers were again passed through a high-precision laser displacement sensor on the sorting machine. A first edge region 10, a central region 20, and a second edge region 30 were defined along a direction parallel to the cutting path. The first edge region 10 of the first and second sets of vertically cut halves was within 8 mm of the long side, the second edge region 30 was within 8 mm of the long side, and the central region 20 was located between the first edge region 10 and the second edge region 30. The number of cutting marks was between 10 and 50, the arc height of the cutting marks was greater than 1 mm and less than 17 mm, and the depth of the cutting marks was greater than 1 μm and less than 15 μm. Using the above... Figure 2 The average thickness of the first edge region 10, the central region 20, and the second edge region 30 was measured using the test method. Furthermore, the average thicknesses of the first edge region 10, the central region 20, and the second edge region 30 of the two sets of silicon wafers in Examples 1-3 and Comparative Example 1 are slightly different.

[0066] Example 1 In this embodiment, each silicon wafer in the two sets of vertically slicing halves is obtained according to the following criteria: The average thickness of the first edge region 10, the central region 20, and the second edge region 30 all exhibit the following pattern: The average thickness of the first edge region 10 is greater than the average thickness of the second edge region 30, and the difference is greater than 0.3 μm and less than 1.5 μm. The average thickness of the second edge region 30 is greater than the average thickness of the central region 20, and the difference is greater than 0.1 μm and less than 1 μm.

[0067] Example 2 In this embodiment, each silicon wafer in the two sets of vertically slicing halves is obtained according to the following criteria: The average thickness of the first edge region 10, the central region 20, and the second edge region 30 all exhibit the following pattern: The average thickness of the first edge region 10 is greater than the average thickness of the second edge region 30, and the difference is greater than 0.3 μm and less than 1.5 μm. The average thickness of the first edge region 10 is greater than the average thickness of the central region 20, and the difference is greater than 0.1 μm and less than 1 μm. The average thickness of the second edge region 30 is less than the average thickness of the central region 20, and the difference is greater than 0.1 μm and less than 1 μm.

[0068] Comparative Example 1 In this embodiment, each silicon wafer in the two sets of vertically slicing halves is obtained according to the following criteria: The average thickness of the central region 20 is greater than the average thickness of the first edge region 10, and the difference is greater than 0.1 μm and less than 1 μm.

[0069] The average thickness of the central region 20 is greater than the average thickness of the second edge region 30, and the difference is greater than 0.1 μm and less than 1 μm.

[0070] The three groups of silicon wafers from Examples 1-2 and Comparative Example 1 were transported to the battery workshop for battery cell fabrication, and the fragmentation rate of the three groups of silicon wafers was counted. The results showed that, compared with the two groups of vertically cut half wafers in Comparative Example 1, the fragmentation rate of the two groups of vertically cut half wafers in Examples 1-2 was reduced to varying degrees.

[0071] To further illustrate the reduction, this application presents a relative proportion: using the fragmentation rate of the two groups of silicon wafers 100 in Comparative Example 1 as a baseline (set as 100%), the fragmentation rate ratio of the embodiments relative to this baseline and their reduction ratio are calculated, wherein: The relative proportion of fragmentation rate in the embodiment = (fragmentation rate of each group in the embodiment / fragmentation rate of each group corresponding to Comparative Example 1) × 100%; The reduction rate of fragmentation rate in the embodiment = (fragmentation rate of each group corresponding to Comparative Example 1 - fragmentation rate of each group in the embodiment) / fragmentation rate of each group corresponding to Comparative Example 1 × 100%.

[0072] The results are shown in Table 1 below, with detailed explanations below.

[0073] (1) Compared with the first group of vertically cut half pieces in Comparative Example 1, the first group of vertically cut half pieces in Examples 1-2 have a reduction of nearly 15-40%; compared with the second group of vertically cut half pieces in Comparative Example 1, the second group of vertically cut half pieces in Examples 1-2 have a reduction of nearly 15-50%.

[0074] (2) In the first and second groups, the fragmentation rate of Example 1 compared with Example 2 shows that the average thickness of the central region 20 of the vertically cut half is greater than that of the second edge region 30 and less than that of the first edge region 10, which can more effectively reduce the fragmentation rate.

[0075] Table 1 The relative proportion of fragmentation rate The percentage reduction in fragmentation rate Comparative Example 1 - Group 1 100% -- Example 1 - Group 1 61% 39% Example 2 - Group 1 76% 24% Comparative Example 1 - Group 2 100% -- Example 1 - Group 2 51% 49% Example 2 - Group 2 75% 25% The test results above show that for vertically cut half wafers, by controlling the average thickness of at least one long edge region (first edge region 10 and / or second edge region 30) to be greater than the average thickness of the central region 20, the structural strength of the long edge is improved, thereby reducing the risk of silicon wafer breakage or microcracks as a whole, and thus reducing the breakage rate.

[0076] In some embodiments, this application also provides a solar cell, which includes a silicon substrate and electrodes formed on the silicon substrate, wherein the silicon substrate is the silicon wafer in the above embodiments or the silicon wafer prepared by the above preparation method.

[0077] In some embodiments, this application also provides a photovoltaic module, which includes a plurality of interconnected solar cells, wherein the solar cells are those described in the above embodiments.

[0078] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0079] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A silicon wafer, characterized in that, The silicon wafer is rectangular, and the ratio of its length to its width is 1:0.4 to 1:0.6; the silicon wafer includes two opposing surfaces and four side surfaces located between the two surfaces; At least one of the surfaces is provided with multiple dicing marks extending along the width direction of the silicon wafer, the dicing marks being arc-shaped; along a direction parallel to the extension path of the dicing marks, the silicon wafer is provided with a first edge region, a central region, and a second edge region; the width of the first edge region and the second edge region in the direction parallel to the extension path of the dicing marks is greater than or equal to 5 mm and less than or equal to 20 mm; the central region is located between the first edge region and the second edge region; wherein, the average thickness of the first edge region and / or the average thickness of the second edge region is greater than the average thickness of the central region.

2. The silicon wafer according to claim 1, characterized in that, The average thickness of the central region is between the average thickness of the first edge region and the average thickness of the second edge region; or, the average thickness of the central region is less than the average thickness of the first edge region and the average thickness of the second edge region.

3. The silicon wafer according to claim 2, characterized in that, The difference between the average thickness of the central region and the average thickness of the first edge region and / or the second edge region is greater than 0.1 μm and less than or equal to 1.5 μm.

4. The silicon wafer according to claim 3, characterized in that, The difference between the average thickness of the central region and the average thickness of the first edge region and / or the second edge region is greater than 0.3 μm and less than or equal to 0.8 μm.

5. The silicon wafer according to claim 1, characterized in that, Both the first edge region and the second edge region have chamfers at both ends in a direction perpendicular to the extension path of the cutting mark; the chamfers are either arc-shaped chamfers or straight chamfers.

6. The silicon wafer according to claim 5, characterized in that, The size of the chamfer on the first edge region is greater than or equal to the size of the chamfer on the second edge region.

7. The silicon wafer according to claim 6, characterized in that, The projection length of the chamfer on the first edge region and / or the second edge region onto the edge length of the silicon wafer is greater than or equal to 0.05 mm and less than or equal to 9 mm; and / or, the projection length of the chamfer on the second edge region onto the edge length of the silicon wafer is less than or equal to 8.5 mm.

8. The silicon wafer according to any one of claims 1-7, characterized in that, The length of the silicon wafer is 166mm-230mm; and / or, the average thickness of the silicon wafer is 100μm-150μm; and / or, the width of the silicon wafer is 80μm-140mm; and / or, the number of dicing marks is greater than 10; and / or, the spacing between adjacent dicing marks is greater than 1mm; and / or, the arc height of the dicing mark is greater than 1mm and less than 17mm; and / or, the depth of the dicing mark is greater than 1μm and less than 15μm.

9. A type of battery cell, characterized in that, It includes a silicon substrate and electrodes formed on the silicon substrate, wherein the silicon substrate is a silicon wafer as described in any one of claims 1-8.

10. A photovoltaic module, characterized in that, It includes a plurality of interconnected battery cells, wherein the battery cells are those described in claim 9.

Images