Temperature sensitive sensor digital calibration circuit and calibration method

Abstract

This application discloses a digital calibration circuit and calibration method for a temperature-sensitive sensor, including a temperature acquisition module, a non-volatile storage module, a computation module, an output processing module, and a finite state machine for coordinating the time-sharing operation of each module. The temperature acquisition module is configured to acquire the analog temperature signal output by the temperature sensor and convert it into an N-bit temperature raw code. The non-volatile storage module stores multiple sets of temperature boundary codes and their corresponding calibration values ​​in ascending order of temperature. The computation module is configured to, under the scheduling of the finite state machine, first coarsely locate the target interval through sequential traversal, and then converge to obtain the final calibration value through synchronous binary search iteration. The output processing module is configured to process the final calibration value and output a calibration signal to the sensor's analog front end. This application adopts a processorless pure hardware architecture, does not rely on a CPU or software, has fewer circuit gates, and significantly reduces chip area and power consumption.

Description

Technical Field

[0001] This invention relates to the field of digital calibration technology for sensors, and in particular to a digital calibration circuit and calibration method for a temperature-sensitive sensor. Background Technology

[0002] Temperature-sensitive sensors are widely used in industrial control, consumer electronics, automotive electronics, medical testing, and other fields. With the rapid development of system-on-chip (SoC) integration technology, the industry generally integrates the analog front-end of the sensor and the digital processing circuitry onto the same chip.

[0003] Semiconductor CMOS transistors, on-chip resistors and capacitors, and bandgap reference circuits inherently possess temperature characteristics, and their electrical parameters drift when the ambient temperature changes. Simultaneously, the highly integrated layout of the chip creates a complex thermal environment, further amplifying the temperature drift effect of these devices. This combined effect directly causes distortion in the sensor's output signal, significantly reducing measurement accuracy across the entire temperature range.

[0004] To compensate for measurement errors introduced by temperature drift, existing mainstream calibration and compensation schemes suffer from multiple drawbacks, including processor dependence, high storage overhead, poor process adaptability, and high hardware area and power consumption. Summary of the Invention

[0005] This application provides a digital calibration circuit and calibration method for a temperature-sensitive sensor.

[0006] In a first aspect, this application provides a digital calibration circuit for a temperature-sensitive sensor, including a temperature acquisition module, a non-volatile storage module, a computation module, an output processing module, and a finite state machine for coordinating the time-sharing operation of each module.

[0007] The temperature acquisition module is configured to acquire the analog temperature signal output by the temperature sensor and convert the analog temperature signal into an N-bit temperature raw code; The non-volatile storage module stores multiple sets of temperature boundary codes and corresponding calibration values ​​in order of increasing temperature. The computation module is connected to the temperature acquisition module, the non-volatile storage module and the finite state machine respectively. It is configured to, under the scheduling of the finite state machine, first roughly locate the target interval consisting of two adjacent temperature boundary codes where the N-bit original temperature code is located by sequential traversal, and then converge to obtain the final calibration value by synchronous binary search iteration based on the upper and lower temperature boundary codes and calibration upper and lower boundary values ​​corresponding to the target interval. The output processing module receives the final calibration value, is configured to process the final calibration value, and output a calibration signal to the sensor analog front end.

[0008] In conjunction with the first aspect, in one possible implementation, the arithmetic module includes a multiplexer, a synchronous counter, a first numerical comparator, and a boundary register group; The multiplexer is configured with multiple data input terminals, an address selection terminal, a single data output terminal, and an enable terminal; the multiple data input terminals are connected to the non-volatile memory module and receive all temperature boundary codes and corresponding calibration values ​​output by the non-volatile memory module in parallel; the enable terminal is connected to the finite state machine and configured to operate under the control of the finite state machine; the single data output terminal is connected to the first input terminal of the first numerical comparator; the address selection terminal is connected to the counting output terminal of the synchronous counter. The synchronous counter increments cycle by cycle under the drive of the system clock, and is used to output a continuously increasing strobe address to the address selection terminal, so as to select each group of data buffered at the multiplexer's multiple data input terminal one by one; when the synchronous counter is full, it sends a full count flag to the finite state machine. The second input terminal of the first numerical comparator is connected to the original temperature code output by the temperature acquisition module. The first numerical comparator is used to compare the values ​​of the first input terminal and the second input terminal. When the value input to the first input terminal is greater than the value input to the second input terminal, the first numerical comparator outputs a target interval positioning success flag signal to the finite state machine and writes the upper and lower temperature boundary codes and calibration upper and lower boundary values ​​corresponding to the target interval into the boundary register group.

[0009] In conjunction with the first aspect, in one possible implementation, the arithmetic module further includes an adder group, a midpoint generation circuit, and a second numerical comparator; The adder group is connected to the boundary register group respectively, and is used to perform summation operations on the registered upper and lower temperature boundary codes and upper and lower calibration boundary values ​​respectively, and output the temperature sum value and the calibration sum value; The midpoint generation circuit is connected to the output of the adder group, and generates a temperature midpoint code and a calibration midpoint value based on the temperature sum and calibration sum. The input of the second numerical comparator is connected to the temperature midpoint code and the original temperature code respectively, which are used to compare the magnitude of the two values, and feed back the generated interval update flag to the finite state machine to update the temperature upper and lower boundary codes and calibration upper and lower boundary values ​​stored in the boundary register group, and perform the next round of binary search iteration process.

[0010] In conjunction with the first aspect, in one possible implementation, the midpoint generation circuit is a shift circuit that performs a right shift operation on the sum output by the adder by one bit, and adds the least significant bit of the sum as a carry compensation to the right shift result.

[0011] In conjunction with the first aspect, in one possible implementation, the finite state machine includes a state register and a combinational logic decoding circuit; The status register is a multi-bit D flip-flop array. The data terminal of the D flip-flop is connected to the next state output terminal of the combinational logic decoding circuit. The clock terminal is uniformly connected to the system clock, the reset terminal is connected to the global reset signal, and the Q terminal is connected to the input terminal of the combinational logic decoding circuit for outputting the current state code. The combinational logic decoding circuit generates the next state code and enable, clear, and start / stop control signals for each module based on the current state code and the output signal of the arithmetic module.

[0012] In conjunction with the first aspect, in one possible implementation, the finite state machine has seven sequentially transitioning working states, and its transition logic is as follows: In the idle waiting state, the system continuously monitors the valid data signal output by the temperature acquisition module and the ready signal output by the non-volatile storage module. When both the valid data signal and the ready signal are valid, the system jumps to the scan initialization state; otherwise, it remains in the idle waiting state. After scanning the initialization state, clearing the counter and loading the initial boundary data, jump unconditionally to the sequential traversal state. The system sequentially traverses the states, reads data from the non-volatile storage module group by group, and jumps to the scan completion state when the interval positioning is successful or the counter is full; otherwise, it maintains the current state and continues to traverse. Once the scan is complete, the boundary register, after completing the coarse positioning interval latch, unconditionally jumps to the binary refinement initialization state. After the binary refinement initialization state is completed and the iteration counter is cleared, the system unconditionally jumps to the binary iteration state. In the binary iteration state, the boundary register is dynamically updated according to the comparison result. If the counter is full, the process jumps to the iteration completion state; otherwise, the current state is maintained and the iteration continues. After the iteration is complete and the calibration value is latched and output, it unconditionally jumps back to the idle waiting state.

[0013] In conjunction with the first aspect, in one possible implementation, the digital calibration circuit of this application further includes a preprocessing module, which includes a limiting clamping circuit for limiting the temperature raw code within the temperature boundary range of the non-volatile storage module.

[0014] In conjunction with the first aspect, in one possible implementation, the preprocessing module further includes a bit-width extension circuit, which performs a logical left shift of K bits on the clamped original temperature code to generate a high-bit-width extended temperature code.

[0015] In conjunction with the first aspect, in one possible implementation, the bit-width extension circuit is a pure interconnect combination circuit that logically shifts the N-bit original temperature code left by K bits and fills the low bits with logic zeros to generate an N+K-bit high-width extended temperature code.

[0016] Secondly, this application provides a digital calibration method for a temperature-sensitive sensor, applied to the digital calibration circuit described in any of the above claims, comprising the following steps: S1. Temperature Acquisition: The sensor analog front end acquires the temperature signal, which is then converted from analog to digital to generate an N-bit raw temperature code. S2. Preprocessing: Perform amplitude limiting and clamping processing on the original temperature code to constrain the value within the effective temperature boundary range; then logically shift the clamped data to the left by a preset bit width to generate a high bit width extended temperature code; S3. Initialization Waiting: The finite state machine is in an idle state, waiting for the temperature data to be valid and the non-volatile storage module to be ready; S4. Sequential Traversal Coarse Positioning: The finite state machine enters the scan initialization state, loads the initial boundary data and clears the counter; then it reads the temperature boundary code and calibration value in the non-volatile storage module point by point, traverses to find the temperature range where the current temperature is located, and locks the upper and lower boundaries of the range; S5. Synchronous binary iterative interpolation: Simultaneously sum, shift and divide by two the locked upper and lower temperature boundaries and calibration upper and lower boundaries to generate the temperature midpoint and calibration midpoint; compare the temperature midpoint with the high-bit-width extended temperature code, and synchronously update the upper and lower boundaries of temperature and calibration according to the comparison result; repeat the iteration until the preset number of iterations is reached. S6. Output calibration value: After the iteration is completed, the final calibration value is truncated and the sign is converted to generate a standard calibration signal and output to the sensor analog circuit to complete the single temperature calibration. S7. The circuit is reset to the idle state, waiting for the next round of temperature acquisition and calibration.

[0017] Compared with existing technologies, the advantages of this application are as follows: First, by adopting a sparse temperature boundary storage method, it eliminates the need for dense storage of massive calibration data at extremely small temperature granularity across the entire temperature range. Instead, it deploys sparse temperature boundary points at fixed temperature intervals, significantly reducing the storage capacity requirements of the non-volatile storage module and saving chip storage resources. Second, by adopting a fully hardware-independent timing control architecture, it eliminates the need for integrated processor cores and firmware compensation algorithms, saving the large amount of chip logic gate area occupied by the processor and significantly reducing circuit power consumption. Third, the overall architecture is a general-purpose pure digital hardware architecture, independent of special analog reference circuits and special... The process parameters are fixed, eliminating the need for redesign and tape-out verification as semiconductor process nodes change. Furthermore, the number of temperature boundaries and iterations can be flexibly increased or decreased based on actual temperature measurement range and calibration accuracy requirements, adapting to different models and application scenarios of temperature sensors, demonstrating excellent versatility and scalability. Fourthly, a synchronous finite state machine is used to complete time-sharing scheduling of all modules, with clear division of each working stage and rigorous state transition logic. Combined with pre-processing logic for temperature limiting and bit width expansion, it effectively avoids problems such as abnormal values ​​beyond the measurement range and truncation errors in iterative calculations, ensuring that the circuit can stably and reliably complete automatic calibration under various extreme high and low temperature conditions. Attached Figure Description

[0018] Figure 1 A block diagram of a digital calibration circuit for a temperature-sensitive sensor provided in this application embodiment; Figure 2 This is a timing control diagram of a digital calibration circuit for a sensitive sensor according to this application; Figure 3 This is a flowchart of a digital calibration method for a temperature-sensitive sensor according to this application.

[0019] Explanation of reference numerals in the attached figures: 1. Temperature acquisition module; 2. Finite state machine; 3. Non-volatile memory module; 4. Calculation module; 5. Output processing module; 6. Preprocessing module. Detailed Implementation

[0020] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The technical problem to be solved by this application is explained below.

[0022] Temperature-sensitive sensors are widely used in industrial control, consumer electronics, and medical testing. With the rapid development of System-on-Chip (SoC) integration technology, the industry generally integrates multiple functional modules such as the sensor's analog front-end, analog-to-digital conversion circuit, and digital processing unit into a single chip. The core components inside the chip, such as CMOS transistors, on-chip capacitors, and bandgap references, all have inherent temperature characteristics. Changes in ambient temperature can cause temperature drift in the electrical parameters of these components. Simultaneously, the high integration density of the chip creates a complex thermal environment, further amplifying the temperature drift effect of these components. Ultimately, this leads to distortion of the sensor's output signal and a significant reduction in the accuracy of full-temperature-range measurements.

[0023] To compensate for measurement errors caused by temperature drift, existing mainstream temperature calibration and compensation schemes all have inherent technical flaws and cannot meet the application requirements of small-area, low-power, and high-precision on-chip sensors. Specifically: One approach is a software calibration scheme based on the processor and firmware. This scheme relies on on-chip temperature acquisition devices to obtain temperature information, and the CPU runs a compensation algorithm to complete the numerical correction. This scheme requires the integration of a processor core, resulting in a large number of hardware gates and a large chip footprint, making it unsuitable for small sensor digital IPs with stringent area and power consumption requirements.

[0024] Secondly, the non-volatile memory pure lookup table scheme pre-stores the calibration parameters corresponding to discrete temperature points in the NVM. To achieve high-precision full-temperature compensation, massive amounts of data need to be stored in extremely small granularities such as 1℃, which significantly increases the storage hardware overhead. Moreover, it can only perform single-point compensation for discrete temperature points, with no smooth transition between adjacent temperature ranges and large interpolation errors.

[0025] Third, there is the analog segmented compensation circuit scheme, which compensates for temperature errors by modifying analog circuits such as bandgap references. This type of circuit is highly dependent on the process technology; changing the process node requires redesigning and fabricating for verification. Furthermore, the circuit parameters are fixed after fabrication, making it impossible to flexibly adjust calibration rules based on measured deviations, resulting in poor portability of the solution.

[0026] In summary, existing temperature calibration schemes suffer from numerous problems, including reliance on processor cores, high storage resource consumption, poor process adaptability, and high hardware area and power consumption. To address these issues, this application proposes a pure hardware temperature calibration circuit and method without a CPU or dedicated divider. This method enables high-precision automatic segmented linear calibration of temperature sensors across the entire temperature range under extremely small chip area and low power consumption conditions, making it suitable for applications of highly integrated on-chip sensors.

[0027] Example 1 Combination Figure 1As shown, the temperature-sensitive sensor digital calibration circuit provided in this embodiment mainly consists of a temperature acquisition module 1, a preprocessing module 6, a non-volatile storage module 3, a calculation module 4, an output processing module 5, and a finite state machine 2 for coordinating the time-sharing operation of each module.

[0028] Temperature acquisition module 1 is used to acquire the analog temperature signal output by the temperature sensor and convert it into an N-bit raw temperature code. Its output terminal sends the N-bit raw temperature code to the subsequent preprocessing module and also outputs a valid data signal to the finite state machine. It is important to emphasize that this circuit uses the raw temperature code for storage, calculation, and calibration, rather than the converted Celsius value. This eliminates the need for multi-level conversions between temperature, voltage, and code value, avoiding additional calculation errors caused by secondary conversions, simplifying the hardware chain while improving calibration accuracy.

[0029] The non-volatile memory module 3 can be any one of OTP, eFuse, embedded EEPROM, or Flash, and stores multiple sets of temperature boundary codes B0~B in ascending order of temperature at equal intervals. M And the calibration values ​​C0~C corresponding one-to-one with each group of temperature boundary codes. M In this embodiment, a partitioning mapping rule can be used for the non-volatile memory module 3: temperature boundary codes B0~B0 are stored sequentially from address 0 to M. M Addresses M+1 to 2M+1 sequentially store calibration values ​​C0~C that match the temperature boundary codes. M This circuit implements partitioned storage of temperature boundary codes and calibration value addresses within the same group, facilitating unified hardware reading and matching. For example, the effective temperature measurement range of this circuit covers -40 to 150℃, with a set of boundary parameters set every 10℃, totaling 20 sets of temperature boundary parameters. B0 corresponds to the temperature code value for -40℃, B1 to -30℃, B2 to -20℃, and so on, with B19 corresponding to the temperature code value for 150℃. In practical applications, the number of boundaries and the temperature interval between adjacent boundaries can be flexibly configured according to calibration accuracy and storage resource capacity: a denser number of boundaries results in higher calibration accuracy, but also increases the data storage capacity overhead of the non-volatile storage module.

[0030] The preprocessing module 6 includes a limiting clamping circuit and a bit-width expansion circuit. The input of the limiting clamping circuit is connected to the output of the temperature acquisition module. It limits the N-bit raw temperature code, forcing it within the maximum and minimum temperature boundaries of the non-volatile storage module. Temperatures exceeding the range are clamped to the nearest boundary value, ensuring controllable circuit behavior under extreme temperature conditions and guaranteeing the normal execution of subsequent interval positioning and interpolation calculations. The input of the bit-width expansion circuit is connected to the output of the limiting clamping circuit. It performs a logical left shift of K bits on the clamped N-bit raw temperature code, generating an N+K bit-width expanded temperature code. The high N bits are the integer part, and the low K bits are the fractional part, providing a basis for fractional operations in subsequent high-precision iterative interpolation and avoiding accumulated truncation errors during multiple iterations.

[0031] The operation module 4 is interconnected with the preprocessing module, the non-volatile storage module, and the finite state machine. Under the timing scheduling of the finite state machine, it completes two levels of operation: the first level is a sequential traversal coarse positioning operation, which uses a synchronous counter and a multiplexer to traverse the boundary parameters group by group to lock the pair of adjacent temperature boundary code intervals and the corresponding calibration value intervals where the current temperature original code is located; the second level is a synchronous binary iterative operation, which uses hardware addition and shifting iterative convergence to obtain a high-precision final calibration value based on the locked pair of adjacent temperature boundary code intervals and the corresponding calibration value intervals.

[0032] Specifically, in combination Figure 2 As shown, the arithmetic module includes a multiplexer, a synchronous counter, a first numerical comparator, a second numerical comparator, a boundary register group, an adder group, and a midpoint generation circuit.

[0033] The multiplexer (MUX) is configured with multiple data input terminals D0~DM, an address selection terminal, a single data output terminal, and a first enable terminal. Each data input terminal corresponds one-to-one with the stored data in the non-volatile memory module. After the NVM is powered on and initialized, it outputs all temperature boundary codes B0~BM and their corresponding calibration values ​​C0~CM in parallel to the multiplexer's multiple data input terminals D0~DM. Specifically, the temperature boundary code B0 stored at NVM address 0 and the calibration value C0 stored at address M+1 are connected to data input terminal D0, the temperature boundary code B1 stored at NVM address 1 and the calibration value C1 stored at address M+2 are connected to data input terminal D1, and so on for the remaining channels. The first enable terminal of the multiplexer receives a start / stop control signal output from the finite state machine. This start / stop control signal controls the multiplexer (MUX) to operate only during the sequential traversal phase and to disable the output during the other phases.

[0034] The synchronous counter is configured with a system clock terminal, a synchronous clear terminal, a second enable terminal, and a parallel output terminal. The system clock terminal is connected to the system clock. The synchronous clear terminal and the second enable terminal are respectively connected to the corresponding control signals output by the finite state machine. The parallel output terminal is connected to the address selection terminal of the multiplexer (MUX). Driven by the system clock, the synchronous counter increments cycle by cycle, outputting a continuously increasing binary address code as the selection basis for the multiplexer's multiple data input terminals D0~DM. It sequentially selects the temperature boundary codes and corresponding calibration values ​​stored in D0~DM, and sends a full count flag to the finite state machine when the count value is full. It should be noted that the multiplexer and synchronous counter are selected and matched as needed. In this embodiment, taking the storage of 16 sets of boundary temperature codes and corresponding calibration values ​​in a non-volatile memory module as an example, a 16-to-1 multiplexer and a 4-bit synchronous binary counter are used. The hardware architecture is simple and highly scalable. Increasing or decreasing the number of boundary groups only requires adjusting the counter bit width and the number of MUX data input terminals, without reconstructing the overall circuit.

[0035] The two inputs of the first numerical comparator are connected to the single-channel output of the multiplexer and the output of the bit-width expansion circuit, respectively, to perform temperature value comparison and determination. The temperature boundary code output by the multiplexer needs to be bit-width expanded to a data format completely consistent with the high-bit-width expanded temperature code output by the bit-width expansion circuit before being fed into the first numerical comparator for value comparison. After the value comparison is completed, the first numerical comparator generates the corresponding interval positioning flag and feeds it back to the finite state machine as the basis for terminating the sequential traversal process. When the interval positioning success flag or the count value full flag is detected, the finite state machine outputs a control signal to control the boundary register group to latch the current temperature upper and lower boundary codes and calibration upper and lower boundary values, completing the storage of coarse positioning interval parameters.

[0036] The adder group is connected to the output of the boundary register group, and is used to sum the upper and lower boundary codes of temperature and the upper and lower boundary values ​​of calibration locked by the boundary register group in parallel, outputting the temperature sum and the calibration sum. The midpoint generation circuit adopts a pure shift combinational logic circuit, performs a right shift operation of one bit on the two sums respectively, and superimposes the least significant bit (LSB) of the sum as carry compensation, so as to achieve accurate division by two without truncation error without the use of a dedicated hardware divider, and synchronously generates the temperature midpoint code and the calibration midpoint value. The input of the second numerical comparator is respectively connected to the temperature midpoint code after the bit width is uniformly processed and the high bit width extended temperature code output by the bit width extension circuit. By comparing the two sets of temperature values, an interval update flag is generated and fed back to the finite state machine. The finite state machine synchronously updates the upper and lower boundary codes of temperature and the upper and lower boundary values ​​of the flag in the boundary register group according to the flag, and completes multiple rounds of binary search iterative convergence.

[0037] Furthermore, the finite state machine in this embodiment adopts a synchronous timing architecture, consisting of a state register and a combinational logic decoding circuit. The state register is a multi-bit D flip-flop array. The clock inputs of all D flip-flops are uniformly connected to the system clock CLK, and the reset inputs are uniformly connected to the global reset signal. The data inputs (D) of each D flip-flop are connected to the next state output of the combinational logic decoding circuit. When the global reset signal is valid, the outputs (Q) of all D flip-flops are forcibly cleared to zero, and the finite state machine latches into the idle state S0. After the reset signal is released, the state register only performs state latching and transition on the rising edge of the system clock CLK, ensuring timing stability without metastability risk. The inputs of the combinational logic decoding circuit are connected to the outputs of the state register, receiving the current state code output by the state register, responding in real-time to changes in the current state code and internal and external flag signals, and instantly generating the next state code and control signals for each module.

[0038] The output Q of the state register is connected to the input of the combinational logic decoder circuit, providing the current state code to the circuit and serving as a reference for state transition logic determination. The combinational logic decoder circuit is the core of conditional judgment and state transition, capable of real-time acquisition of the current state code and various external and internal flags. Once the input signal changes, the circuit immediately calculates and generates the corresponding next state code, as well as enable, start, and stop control signals for each module. It should be noted that the next state code output by the combinational logic decoder circuit is only a pre-decision logic signal; the actual operating state of the finite state machine does not change immediately. A state transition can only be completed after the rising edge of the system clock CLK arrives, triggering the state register latch update, to ensure consistent circuit timing and stable, reliable operation.

[0039] Specifically, this embodiment uses a finite state machine with seven sequentially transitioning working states S0 to S6. A 3-bit D flip-flop is used to implement state encoding storage, and the state codes are defined as follows: Idle state S0=000, Scan initialization state S1=001, Sequential traversal state S2=010, Scan completed state S3=011, Binary refinement initialization state S4=100, Binary synchronous iteration state S5=101, and Iteration output state S6=110. The specific working logic and transition rules for each state are as follows: The idle state S0 is the initial steady state of the circuit. When the global reset signal is valid, it triggers a global reset, clearing all 3-bit D flip-flops and locking the status register to state S0. After the global reset is released, the combinational logic decoding circuit continuously monitors the valid temperature data signal output by the temperature acquisition module and the ready signal output by the non-volatile memory module. Only when both signals are valid at the same time, the combinational logic decoding circuit generates the next state code S1=001. When the rising edge of the next system clock CLK arrives, it triggers the 3-bit D flip-flops to latch the pre-loaded data at their respective data terminals D to the output terminal Q, causing the finite state machine to jump to the scan initialization state S1. The initialization state S1 is a single-clock-cycle unconditional jump state. After the finite state machine jumps to S1, it completes the synchronization counter clearing and boundary register initialization configuration. Specifically, the boundary register is initialized [temperature boundary code code_min=B0, temperature upper boundary code code_max=B1; calibration lower boundary value trim_min=C0, calibration upper boundary code trim_max=C1]. Subsequently, the combinational logic decoding circuit directly outputs the next state code S2=010. When the rising edge of the system clock CLK arrives, it triggers the 3-bit D flip-flop to latch the 010 preloaded at the data terminal D to the output terminal Q. The finite state machine jumps to the sequential traversal state S2. At the same time, the combinational logic decoding circuit outputs a valid enable signal to enable the working permissions of the multiplexer and the synchronization counter. The multiple sets of temperature boundary codes and corresponding calibration values ​​stored in the non-volatile memory module are output in parallel to the data input terminal of the multiplexer at one time, avoiding frequent switching of the NVM random address during operation, effectively reducing memory read / write pressure and timing instability risks.

[0040] Sequential traversal state S2 is the core working state for coarse interval positioning. After the finite state machine jumps to this state, it sequentially performs a linear scan of all temperature boundary codes cached by the multiplexer MUX to locate the target temperature interval containing the current original temperature code. The circuit completes a complete interval update and logic determination in each system clock cycle. The specific execution steps are as follows: The first step is to update the lower boundary of the boundary register: assign the temperature upper boundary code stored in the previous round to the current lower lower boundary, and simultaneously assign the calibration upper boundary value of the previous round to the current calibration lower boundary, that is, update the upper boundary of the previous round interval to the lower boundary of the current round interval. The second step is to read and expand the boundary parameters corresponding to the current index: based on the index address output by the synchronization counter, the multiplexer outputs a set of temperature boundary codes and matching calibration values. After the two data are expanded by bit width, they are written into the temperature upper boundary code and calibration upper boundary value of the boundary register. Step 3, interval determination: Compare the upper temperature boundary code output by the multiplexer with the original temperature code T. There are two termination conditions for traversal: One is that the extended temperature boundary code output by the multiplexer is greater than the high-order extended temperature code, indicating that the high-order extended temperature code is within the temperature interval stored in the current boundary register, that is, the upper and lower boundary values of the temperature stored in the boundary register are the target temperature interval; The other is that the counter reaches the maximum value, indicating that all boundaries have been traversed, and the target temperature interval falls within the highest temperature interval. When either termination condition is met, the finite state machine jumps to the S3 scan completion state; If neither is met, the synchronous counter increments by 1, and the S state is maintained to continue the next clock traversal.

[0041] Exemplarily, assume that the original temperature code T falls between the upper temperature boundary codes B2 and B3. When the initial value of the synchronous counter is 0, the lower temperature boundary code stored in the boundary register is B0, and the upper temperature boundary is B1. The first numerical comparator compares the upper temperature boundary code B1 and the original temperature code T, determines that B1 < T, and continues traversal; When the synchronous counter counts to 1, the lower temperature boundary code of the boundary register is updated to B1, and the upper temperature boundary code is updated to B2. The first numerical comparator compares the current upper temperature boundary code B2 and the original temperature code T, determines that B2 < T, and continues traversal; When the synchronous counter counts to 2, the lower temperature boundary code of the boundary register is updated to B2, and the upper temperature boundary code is updated to B3. The first numerical comparator compares the current upper temperature boundary code B3 and the original temperature code T, determines that B2 > T, the interval is successfully located, and the state jumps to S3. The scan completion state S3 is a single-cycle transition state. After entering this state, the boundary register group solidifies the upper and lower temperature boundary codes obtained by coarse positioning and the calibration upper and lower boundary values. Subsequently, the combinational logic decoding circuit directly outputs the next state encoding S4 = 100. When the rising edge of the system clock CLK arrives, the finite state machine jumps to the binary refinement initialization state S4.

[0042] The binary refinement initialization state S4 is a preparatory state for iteration. After entering this state, the synchronous counter is reset to zero, the boundary register maintains the value locked at the end of S2 unchanged, and the combinational logic decoding circuit unconditionally outputs the next state encoding S5 = 101. When the rising edge of CLK arrives, the finite state machine jumps to the binary synchronous iteration state S5 to start the high-precision interpolation operation process.

[0043] The binary synchronous iteration state S5 is the core state for high-precision calibration. Relying on the linear mapping relationship between temperature boundary codes and calibration values, it completes one synchronous binary iteration per clock cycle. After the finite state machine jumps to the binary synchronous iteration state S5, relying on the inherent linear correspondence between temperature boundary codes and calibration parameters, it synchronously completes parallel counting and interval shrinking of the temperature midpoint and calibration midpoint in each system clock cycle, without requiring hardware multipliers or dedicated dividers. The complete iteration logic in a single clock cycle is as follows: First, parallel midpoint summation and precise midpoint calculation are performed. This step is combinational logic, with two calculations completed synchronously in the same clock cycle. Next, addition operations are performed on the upper and lower boundary values ​​of the temperature and calibration values ​​of the target interval in the boundary register to obtain the temperature midpoint and calibration midpoint. After each round of midpoint calculation and numerical comparison, the temperature interval and calibration interval undergo completely symmetrical boundary update logic. If the midpoint temperature code mid_code is greater than the real-time extended temperature code temp_code_sh8, and the actual temperature code falls in the lower half of the interval, the upper boundary is updated synchronously. code_max_new=(code_max+code_min) / 2 trim_max_new=(trim_min+trim_max) / 2 If the midpoint temperature code is less than or equal to the real-time extended temperature code, and the target temperature falls within the upper half of the interval, the lower boundary is updated synchronously. code_min_new=(code_max+code_min) / 2 trim_min_new=(trim_min+trim_max) / 2 The temperature range and the calibration range are always halved synchronously, and their linear mapping relationship remains unchanged throughout.

[0044] Interval Convergence Law: Assuming the initial temperature interval width W0 = BH - BL, the interval width shrinks to half its original value in each iteration. After K iterations, the remaining interval width satisfies: When the number of iterations K is equal to the number of decimal places introduced by the bit width expansion, the temperature range width will be reduced to less than 1 LSB, and the upper and lower boundaries of the range will approach the target temperature T.

[0045] The iterative output state S6 is the single-cycle final state, requiring no external detection signals or conditional judgments. Upon entering this state, the circuit latches the precise calibration value generated in the final iteration, and the output processing module performs bit width truncation and sign conversion, outputting a standard calibration signal to the sensor's analog front end. Subsequently, the combinational logic decoding circuit fixes the initial state code S0=000. Upon the rising edge of CLK, the finite state machine jumps back to the idle waiting state S0, completing a single complete temperature calibration process and awaiting the next round of temperature sampling to trigger calibration.

[0046] The core of this scheme is to abandon one-time multiplication and division operations and decompose linear interpolation into multiple rounds of midpoint iteration operations. All numerical convergence is completed by adding and shifting connections alone. The temperature range and calibration range are updated synchronously to ensure that the linear proportion is not lost. The iteration process parses the binary decimal bit by bit. Under the condition of no dedicated multiplier or divider, a high-precision calibration result that is completely equivalent to the standard linear interpolation formula is achieved.

[0047] Example 2 Combination Figure 3 As shown, this embodiment provides a digital calibration method for a temperature-sensitive sensor, including the following steps: S1. Temperature Acquisition: The sensor analog front end acquires the temperature signal, which is then converted from analog to digital to generate an N-bit raw temperature code. S2. Preprocessing: Perform amplitude limiting and clamping processing on the original temperature code to constrain the value within the effective temperature boundary range; then logically shift the clamped data left by K bits to generate a high-bit-width extended temperature code. S3. Initialization Waiting: The finite state machine is in an idle state, waiting for the temperature data to be valid and the non-volatile storage module to be ready; S4. Sequential Traversal Coarse Positioning: The finite state machine enters the scan initialization state, loads the initial boundary data and clears the counter; then it reads the temperature boundary code and calibration value in the non-volatile storage module point by point, traverses to find the temperature range where the current temperature is located, and locks the upper and lower boundaries of the range; S5. Synchronous binary iterative interpolation: Simultaneously sum, shift and divide by two the locked upper and lower temperature boundaries and calibration upper and lower boundaries to generate the temperature midpoint and calibration midpoint; compare the temperature midpoint with the high-bit-width extended temperature code, and synchronously update the upper and lower boundaries of temperature and calibration according to the comparison result; repeat the iteration until the preset number of iterations is reached. S6. Output calibration value: After the iteration is completed, the final calibration value is truncated and the sign is converted to generate a standard calibration signal and output to the sensor analog circuit to complete the single temperature calibration. S7. The circuit is reset to the idle state, waiting for the next round of temperature acquisition and calibration.

[0048] It should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. A digital calibration circuit for a temperature-sensitive sensor, characterized in that, It includes a temperature acquisition module, a non-volatile storage module, a computation module, an output processing module, and a finite state machine for coordinating the time-sharing operation of each module; The temperature acquisition module is configured to acquire the analog temperature signal output by the temperature sensor and convert the analog temperature signal into an N-bit temperature raw code; The non-volatile storage module stores multiple sets of temperature boundary codes and corresponding calibration values ​​in order of increasing temperature. The computation module is connected to the temperature acquisition module, the non-volatile storage module and the finite state machine respectively. It is configured to, under the scheduling of the finite state machine, first roughly locate the target interval consisting of two adjacent temperature boundary codes where the N-bit original temperature code is located by sequential traversal, and then converge to obtain the final calibration value by synchronous binary search iteration based on the upper and lower temperature boundary codes and calibration upper and lower boundary values ​​corresponding to the target interval. The output processing module receives the final calibration value, is configured to process the final calibration value, and output a calibration signal to the sensor analog front end.

2. The temperature-sensitive sensor digital calibration circuit according to claim 1, characterized in that, The arithmetic module includes a multiplexer, a synchronous counter, a first numerical comparator, and a boundary register group; The multiplexer is configured with multiple data input terminals, an address selection terminal, a single data output terminal, and an enable terminal; the multiple data input terminals are connected to the non-volatile memory module and receive all temperature boundary codes and corresponding calibration values ​​output by the non-volatile memory module in parallel; the enable terminal is connected to the finite state machine and configured to operate under the control of the finite state machine; the single data output terminal is connected to the first input terminal of the first numerical comparator; the address selection terminal is connected to the counting output terminal of the synchronous counter. The synchronous counter increments cycle by cycle under the drive of the system clock, and is used to output a continuously increasing strobe address to the address selection terminal, so as to select each group of data buffered at the multiplexer's multiple data input terminal one by one; when the synchronous counter is full, it sends a full count flag to the finite state machine. The second input terminal of the first numerical comparator is connected to the original temperature code output by the temperature acquisition module. The first numerical comparator is used to compare the values ​​of the first input terminal and the second input terminal. When the value input to the first input terminal is greater than the value input to the second input terminal, the first numerical comparator outputs a target interval positioning success flag signal to the finite state machine and writes the upper and lower temperature boundary codes and calibration upper and lower boundary values ​​corresponding to the target interval into the boundary register group.

3. The digital calibration circuit for the temperature-sensitive sensor according to claim 2, characterized in that, The arithmetic module also includes an adder group, a midpoint generation circuit, and a second numerical comparator; The adder group is connected to the boundary register group respectively, and is used to perform summation operations on the registered upper and lower temperature boundary codes and upper and lower calibration boundary values ​​respectively, and output the temperature sum value and the calibration sum value; The midpoint generation circuit is connected to the output of the adder group, and generates a temperature midpoint code and a calibration midpoint value based on the temperature sum and calibration sum. The input of the second numerical comparator is connected to the temperature midpoint code and the original temperature code respectively, which are used to compare the magnitude of the two values, and feed back the generated interval update flag to the finite state machine to update the temperature upper and lower boundary codes and calibration upper and lower boundary values ​​stored in the boundary register group, and perform the next round of binary search iteration process.

4. The temperature-sensitive sensor digital calibration circuit according to claim 3, characterized in that, The midpoint generation circuit is a shift circuit that performs a right shift operation on the temperature sum and calibration sum output by the adder group by one bit, and adds the least significant bit of the temperature sum and calibration sum as carry compensation to the corresponding right shift result.

5. The temperature-sensitive sensor digital calibration circuit according to claim 3, characterized in that, The finite state machine includes a state register and a combinational logic decoding circuit. The status register is a multi-bit D flip-flop array. The data terminal of the D flip-flop is connected to the next state output terminal of the combinational logic decoding circuit. The clock terminal is uniformly connected to the system clock, the reset terminal is connected to the global reset signal, and the Q terminal is connected to the input terminal of the combinational logic decoding circuit for outputting the current state code. The combinational logic decoding circuit generates the next state code and enable, clear, and start / stop control signals for each module based on the current state code and the output signal of the arithmetic module.

6. The digital calibration circuit for a temperature-sensitive sensor according to claim 5, characterized in that, The finite state machine has seven sequentially transitioning working states, and its transition logic is as follows: In the idle waiting state, the system continuously monitors the valid data signal output by the temperature acquisition module and the ready signal output by the non-volatile storage module. When both the valid data signal and the ready signal are valid, the system jumps to the scan initialization state; otherwise, it remains in the idle waiting state. After scanning the initialization state, clearing the counter and loading the initial boundary data, jump unconditionally to the sequential traversal state. The system sequentially traverses the states, reads data from the non-volatile storage module group by group, and jumps to the scan completion state when the interval positioning is successful or the counter is full; otherwise, it maintains the current state and continues to traverse. Once the scan is complete, the boundary register, after completing the coarse positioning interval latch, unconditionally jumps to the binary refinement initialization state. After the binary refinement initialization state is completed and the iteration counter is cleared, the system unconditionally jumps to the binary iteration state. In the binary iteration state, the boundary register is dynamically updated according to the comparison result. If the counter is full, the process jumps to the iteration completion state; otherwise, the current state is maintained and the iteration continues. Iteration complete state: After completing the calibration value latch output, it unconditionally jumps back to the idle waiting state.

7. The digital calibration circuit for a temperature-sensitive sensor according to claim 1, characterized in that, It also includes a preprocessing module, which includes a limiting clamping circuit for limiting the temperature raw code within the temperature boundary range of the non-volatile storage module.

8. The digital calibration circuit for a temperature-sensitive sensor according to claim 7, characterized in that, The preprocessing module also includes a bit-width extension circuit, which performs a logical left shift operation of K bits on the clamped original temperature code to generate a high-bit-width extended temperature code.

9. The digital calibration circuit for a temperature-sensitive sensor according to claim 8, characterized in that, The bit-width extension circuit is a pure interconnect combination circuit that shifts the N-bit original temperature code left by K bits and fills the low bits with logic zeros to generate an N+K-bit high-bit-width extended temperature code.

10. A digital calibration method for a temperature-sensitive sensor, applied to the digital calibration circuit according to any one of claims 1-9, characterized in that, Includes the following steps: S1. Temperature Acquisition: The sensor analog front end acquires the temperature signal, which is then converted from analog to digital to generate an N-bit raw temperature code. S2. Preprocessing: Perform amplitude limiting clamping processing on the N-bit temperature raw code to constrain the value within the effective temperature boundary range; then logically shift the clamped data to the left by a preset bit width to generate a high bit width extended temperature code. S3. Initialization Waiting: The finite state machine is in an idle state, waiting for the temperature data to be valid and the non-volatile storage module to be ready; S4. Sequential Traversal Coarse Positioning: The finite state machine enters the scan initialization state, loads the initial boundary data and clears the counter; then it reads the temperature boundary code and calibration value in the non-volatile storage module point by point, traverses to find the temperature range where the current temperature is located, and locks the upper and lower boundaries of the range; S5. Synchronous binary iterative interpolation: Simultaneously sum, shift and divide by two the locked upper and lower temperature boundaries and calibration upper and lower boundaries to generate the temperature midpoint and calibration midpoint; compare the temperature midpoint with the high-bit-width extended temperature code, and synchronously update the upper and lower boundaries of temperature and calibration according to the comparison result; repeat the iteration until the preset number of iterations is reached. S6. Output calibration value: After the iteration is completed, the final calibration value is truncated and the sign is converted to generate a standard calibration signal and output to the sensor analog circuit to complete the single temperature calibration. S7. The circuit is reset to the idle state, waiting for the next round of temperature acquisition and calibration.

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