Voltage sampling circuit, method of operating a voltage sampling circuit, device and vehicle

Abstract

The embodiment of the application relates to the technical field of vehicles, and discloses a voltage sampling circuit, an operating method and device of the voltage sampling circuit, and a vehicle, a shunt, a voltage collection chip and a voltage regulating device. The shunt is used for being connected in series with a to-be-measured battery group. The voltage collection chip is connected with a first end of the shunt through a first sampling pin and connected with a second end of the shunt through a second sampling pin. The voltage regulating device is connected between the first end of the shunt and the first sampling pin of the voltage collection chip, and / or connected between the second end of the shunt and the second sampling pin of the voltage collection chip. The voltage regulating device is used for receiving a first differential voltage generated at two ends of the shunt, attenuating the first differential voltage, and outputting a second differential voltage. In this way, the influence of common-mode interference on current collection accuracy in the battery pulse heating process can be inhibited.

Description

Technical Field

[0001] This invention relates to the field of vehicle technology, specifically to a voltage sampling circuit, a method for operating the voltage sampling circuit, an apparatus, and a vehicle. Background Technology

[0002] In low-temperature environments, electric pulse heating technology is required to rapidly heat the battery. However, this technology generates a high-frequency alternating large current. This current flows through the battery's main negative copper busbar, causing the alternating current in the main negative copper busbar to generate a magnetic field. This creates common-mode interference on the current sampling signal on the shunt, resulting in an abnormal increase in the voltage to ground at the input terminal of the battery management system used to collect the shunt voltage. Consequently, the voltage collected by the analog front-end chip connected to the input terminal exceeds its own tolerance limit, causing the current value collected by the analog front-end chip to deviate from the true value.

[0003] Therefore, how to suppress the impact of common-mode interference on the accuracy of current acquisition during battery pulse heating, so as to ensure that the current value acquired by the analog front-end chip is accurate, has become an urgent technical problem to be solved. Summary of the Invention

[0004] In view of the above shortcomings, the purpose of this application is to provide a voltage sampling circuit, a method for operating the voltage sampling circuit, an apparatus, and a vehicle, which aims to solve the technical problem of how to suppress the impact of common-mode interference on the accuracy of current acquisition during battery pulse heating.

[0005] In a first aspect, embodiments of this application provide a voltage sampling circuit, comprising: a shunt, a voltage acquisition chip, and a voltage regulation device. The shunt is connected in series with a battery cell assembly under test. The voltage acquisition chip is connected to a first terminal of the shunt via a first sampling pin and to a second terminal of the shunt via a second sampling pin. The voltage regulation device is connected between the first terminal of the shunt and the first sampling pin of the voltage acquisition chip; and / or; between the second terminal of the shunt and the second sampling pin of the voltage acquisition chip. The voltage regulation device receives a first differential voltage generated across the shunt and attenuates the first differential voltage to output a second differential voltage. The voltage acquisition chip controls the degree of attenuation of the first differential voltage by the voltage regulation device. Furthermore, it acquires the second differential voltage, which is used to determine the current flowing through the battery cell assembly under test.

[0006] During battery pulse heating, the magnetic field generated by the high-frequency alternating large current flowing through the battery's main negative copper busbar creates common-mode interference on the sampling signal of the shunt, causing an abnormal increase in the input voltage to ground of the voltage acquisition chip. Through the connection between the shunt, the voltage acquisition chip, and the voltage regulator, the voltage regulator attenuates the differential voltage, simultaneously reducing the voltage amplitude to ground at the first sampling pin and / or the second sampling pin. This ensures that the voltage input to the voltage acquisition chip remains within its allowable range, preventing chip sampling distortion or damage due to excessive input voltage and thus suppressing the impact of common-mode interference on current acquisition accuracy. Simultaneously, the voltage acquisition chip is configured to control the attenuation level of the voltage regulator, adjusting the attenuation factor according to the actual common-mode interference intensity or current magnitude. This ensures chip input safety while preserving the signal-to-noise ratio of the effective differential signal, balancing measurement reliability and accuracy.

[0007] In one possible embodiment, the voltage regulation device includes: a first series resistor voltage divider circuit and a second series resistor voltage divider circuit. A first terminal of the first series resistor voltage divider circuit is connected to a first terminal of a shunt, a second terminal of the first series resistor voltage divider circuit is grounded, and the voltage dividing node of the first series resistor voltage divider circuit is connected to a first sampling pin of a voltage acquisition chip. A first terminal of the second series resistor voltage divider circuit is connected to a second terminal of a shunt, a second terminal of the second series resistor voltage divider circuit is grounded, and the voltage dividing node of the second series resistor voltage divider circuit is connected to a second sampling pin of the voltage acquisition chip. The first series resistor voltage divider circuit includes a first adjustable potentiometer circuit configured to adjust the voltage division ratio of the first series resistor voltage divider circuit according to a first differential voltage. The second series resistor voltage divider circuit includes a second adjustable potentiometer circuit configured to adjust the voltage division ratio of the second series resistor voltage divider circuit according to the first differential voltage.

[0008] Each sampling signal is stepped down by a resistor divider network before being sent to the voltage acquisition chip. Thus, during the battery pulse heating process, even if the high-frequency alternating current generates a magnetic field that causes an abnormal increase in the common-mode voltage to ground at both ends of the shunt, this increased voltage to ground is reduced by the resistor divider network according to a predetermined ratio before entering the sampling pin. This ensures that the voltage to ground at the sampling pin is maintained within the allowable input range of the voltage acquisition chip, which helps to avoid chip saturation, distortion, or damage due to overvoltage at the input end, thereby suppressing the impact of common-mode interference on the accuracy of current acquisition.

[0009] In one possible embodiment, the voltage sampling circuit further includes a common-mode acquisition circuit. A first terminal of the common-mode acquisition circuit is connected to a first terminal of the shunt and a third sampling pin of the voltage acquisition chip, and a second terminal of the common-mode acquisition circuit is connected to a second terminal of the shunt and a fourth sampling pin of the voltage acquisition chip. The common-mode acquisition circuit is used to filter common-mode noise across the shunt. The voltage acquisition chip is also used to acquire a first differential voltage, which is the voltage across the shunt after attenuation by the common-mode acquisition circuit.

[0010] By connecting a common-mode acquisition circuit between the two ends of the shunt and the sampling pin of the voltage acquisition chip, common-mode noise at the two ends of the shunt can be filtered, reducing the residual common-mode component in the first differential voltage entering the voltage acquisition chip. The common-mode acquisition circuit has a certain degree of attenuation effect on the first differential voltage. The voltage acquisition chip acquires the first differential voltage after attenuation by the common-mode acquisition circuit, and further adjusts the amplitude of the differential signal by controlling the voltage regulation device. The common-mode acquisition circuit performs preliminary filtering and attenuation of the signal at the common-mode suppression level, while the voltage regulation device adjusts the amplitude at the differential signal level. This helps to suppress common-mode interference during battery pulse heating while ensuring a reasonable amplitude of the effective differential signal, thereby improving the sampling accuracy of the voltage acquisition chip in common-mode interference scenarios.

[0011] In one possible embodiment, the adjustable potentiometer circuit includes an adjustable resistor component and a voltage control component. The voltage control component is connected to both the voltage acquisition chip and the adjustable resistor component, and is configured to receive a first differential voltage. The resistance value of the adjustable resistor component is adjusted based on the first differential voltage.

[0012] The voltage control component is connected to both the voltage acquisition chip and the adjustable resistor component. It is configured to receive a first differential voltage and adjust the resistance value of the adjustable resistor component based on this voltage. The voltage control component dynamically changes the resistance value of the adjustable resistor component according to the amplitude of the first differential voltage actually generated across the shunt, thereby adjusting the attenuation ratio of the adjustable potentiometer circuit in real time. Local adjustment based on the first differential voltage allows for timely adjustment of the attenuation amount when the current changes rapidly during pulse heating, ensuring that the voltage input to the sampling pin of the voltage acquisition chip remains within its allowable linear input range. This avoids short-term overvoltage at the chip input due to adjustment lag, which could affect sampling accuracy. Simultaneously, it ensures the matching of the effective differential signal with the chip's analog-to-digital conversion range under different current amplitude conditions, improving the real-time performance and accuracy of current detection.

[0013] In one possible embodiment, the voltage sampling circuit further includes: a candidate attenuation circuit, a first switch, a second switch, a third switch, and a fourth switch. The candidate attenuation circuit is connected between the shunt and the voltage acquisition chip, and is connected in parallel with the voltage regulation device. The first switch is connected between the voltage regulation device and the first sampling pin of the voltage acquisition chip, and the second switch is connected between the voltage regulation device and the second sampling pin of the voltage acquisition chip. The third switch is connected between the candidate attenuation circuit and the first sampling pin of the voltage acquisition chip, and the fourth switch is connected between the candidate attenuation circuit and the second sampling pin of the voltage acquisition chip.

[0014] The voltage acquisition chip can select the signal path of the voltage regulator by controlling the on / off state of the first and second switches, or select the signal path of the backup attenuation circuit by controlling the on / off state of the third and fourth switches. When the path of the voltage regulator fails to operate normally due to a fault or insufficient adjustment range, it can switch to the path of the backup attenuation circuit. The backup attenuation circuit attenuates the first differential voltage across the shunt by a fixed ratio before outputting it to the voltage acquisition chip, thus providing a backup measurement path for current sampling. This helps improve the reliability and redundancy of the voltage sampling circuit under complex operating conditions such as pulse heating. Simultaneously, the voltage acquisition chip can select and switch between the adjustable attenuation path and the fixed attenuation path according to the actual operating conditions. For conditions requiring high measurement accuracy, the voltage regulator is used for flexible attenuation; for conditions requiring fast response or simplified control, the backup attenuation circuit is used for fixed attenuation, balancing sampling flexibility and system stability.

[0015] In one possible embodiment, when the voltage regulator is functioning correctly, the first and second switches are configured to be on, and the third and fourth switches are configured to be off. In the event of a voltage regulator malfunction, the first and second switches are configured to be off, and the third and fourth switches are configured to be on.

[0016] When the voltage regulator is functioning correctly, the first and second switches are on, while the third and fourth switches are off. The voltage acquisition chip obtains the differential signal through the path provided by the voltage regulator, utilizing the adjustable attenuation characteristics of the voltage regulator to ensure sampling accuracy under different current conditions. In the event of a voltage regulator failure, the first and second switches are off, while the third and fourth switches are on. The voltage acquisition chip switches to the path provided by the backup attenuation circuit. The backup attenuation circuit attenuates the first differential voltage across the shunt by a fixed ratio before outputting it to the voltage acquisition chip, thus maintaining the current sampling function. This provides a backup measurement path for the voltage sampling circuit in case of a failure, which helps improve the reliability of current sampling under complex conditions such as pulse heating.

[0017] Secondly, embodiments of this application provide an operation method for a voltage sampling circuit, applied to the voltage sampling circuit as described in the second aspect. The operation method includes: acquiring a first differential voltage generated across a shunt; controlling the attenuation degree of the first differential voltage by a voltage regulating device based on the first differential voltage; and acquiring a second differential voltage output by the voltage regulating device after attenuating the first differential voltage, the second differential voltage being used to determine the current flowing through the battery cell assembly under test.

[0018] The attenuation level of the voltage regulation device is determined based on the actual differential voltage amplitude generated across the shunt, rather than using a fixed attenuation ratio. During battery pulse heating, when common-mode interference causes an abnormal increase in the input-to-ground voltage, this method adjusts the attenuation based on the real-time acquired first differential voltage, ensuring that the attenuated second differential voltage is within the allowable input range of the voltage acquisition chip. Simultaneously, when the current amplitude changes, the closed-loop adjustment step based on the first differential voltage dynamically adapts to different current conditions, maintaining a match between the second differential voltage and the voltage acquisition chip's range. This helps suppress input overvoltage caused by common-mode interference while reducing the impact of quantization errors on the measurement results, thereby improving the accuracy and reliability of current detection.

[0019] In one possible embodiment, controlling the attenuation degree of the first differential voltage by the voltage regulating device based on the first differential voltage includes: determining a target voltage ratio based on the first differential voltage and a target common-mode voltage. The target voltage ratio is the ratio between the first differential voltage and the target common-mode voltage. Based on the target voltage ratio, controlling the attenuation degree of the first differential voltage by the voltage regulating device.

[0020] By introducing a target common-mode voltage as a reference and calculating its ratio to the first differential voltage, a normalized control quantity with the target common-mode voltage as a scale can be obtained. This control quantity is not affected by the absolute amplitude of the first differential voltage alone, but rather reflects the attenuation ratio required to bring the common-mode voltage back to the target value under the current differential signal conditions. Based on this, by controlling the attenuation degree according to the target voltage ratio, the input common-mode voltage corresponding to the attenuated second differential voltage can be made to approach the preset target common-mode voltage, thereby ensuring that the operating voltage at the sampling pin of the voltage acquisition chip is always within its optimized linear input range. During battery pulse heating, when the common-mode interference intensity changes, causing fluctuations in the first differential voltage, the attenuation amount can be dynamically adjusted based on the real-time ratio to avoid overvoltage at the input terminal due to insufficient attenuation or loss of effective signal due to excessive attenuation.

[0021] In one possible embodiment, after the voltage adjustment device attenuates the first differential voltage to output a second differential voltage, the operation method of the voltage sampling circuit further includes: determining an actual voltage division ratio based on the first differential voltage and the updated first differential voltage; determining a target gain value based on the actual voltage division ratio; and adjusting the chip gain of the voltage acquisition chip based on the target gain value to determine the adjusted second differential voltage.

[0022] By introducing a first differential voltage and an updated first differential voltage as feedback quantities to calculate the actual voltage division ratio, and mapping this ratio to the chip gain adjustment basis, a linkage relationship is formed between the external attenuation of the voltage regulation device and the internal gain of the voltage acquisition chip. Changes in the external attenuation can be reflected in real time as corresponding changes in the target gain value. The second differential voltage, after chip gain adjustment, can recover to the effective amplitude range of the analog-to-digital conversion based on the attenuated signal, avoiding insufficient utilization of the chip's internal quantization resolution due to fixed external attenuation. Simultaneously, dynamic gain adjustment based on the updated first differential voltage allows the chip gain to change accordingly with real-time changes in common-mode interference, which helps maintain the signal-to-noise ratio and measurement consistency of the sampling signal during battery pulse heating, further improving the accuracy of current detection.

[0023] In one possible embodiment, the operation method of the voltage sampling circuit further includes: in the event of a failure of the voltage regulation device, issuing a switch control command, the switch control command being used to control the first target switch to open and the second target switch to open.

[0024] By detecting the operating status of the voltage regulator and actively switching it in case of a fault, the voltage sampling path can be switched from the branch where the voltage regulator is located to the branch where the alternative attenuation circuit is located. This allows the first differential voltage across the shunt to be attenuated by a fixed ratio by the alternative attenuation circuit before being sent to the voltage acquisition chip. In this way, the basic operation of the current sampling function can be maintained even if the voltage regulator fails, avoiding the interruption of the entire sampling link due to a single attenuation path failure.

[0025] Thirdly, this application provides a voltage regulation device, wherein the operating device of the voltage sampling circuit includes: a first differential voltage acquisition module, a voltage control module, and a second differential voltage acquisition module.

[0026] The first differential voltage acquisition module is used to acquire the first differential voltage generated at both ends of the shunt.

[0027] The voltage control module is used to control the attenuation degree of the first differential voltage by the voltage regulating device based on the first differential voltage.

[0028] The second differential voltage acquisition module is used to acquire the second differential voltage output by the voltage regulation device after attenuating the first differential voltage. The second differential voltage is used to determine the current flowing through the battery cell group under test.

[0029] Fourthly, this application provides a vehicle that includes a voltage regulating device as described in the second aspect. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application will be described below.

[0031] Figure 1 This is a schematic diagram of a conventional voltage sampling circuit disclosed in an embodiment of this application; Figure 2 This is a schematic diagram of an improved voltage sampling circuit disclosed in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a voltage sampling circuit disclosed in an embodiment of this application; Figure 4 This is a schematic diagram of another voltage sampling circuit disclosed in an embodiment of this application; Figure 5 This is a schematic diagram of another voltage sampling circuit disclosed in an embodiment of this application; Figure 6 This is a schematic diagram of another voltage sampling circuit disclosed in an embodiment of this application; Figure 7 This is a schematic diagram of another voltage sampling circuit disclosed in an embodiment of this application; Figure 8 This is a schematic diagram of another voltage sampling circuit disclosed in an embodiment of this application; Figure 9 This is a schematic diagram of another voltage sampling circuit disclosed in an embodiment of this application; Figure 10 This is a schematic flowchart illustrating another operation method of a voltage sampling circuit disclosed in an embodiment of this application; Figure 11 This is a schematic diagram of the operating device of a voltage sampling circuit disclosed in an embodiment of this application; Figure 12 This is a schematic diagram of the operating device of another voltage sampling circuit disclosed in an embodiment of this application.

[0032] Figure label: 10000 - Vehicle; 1000 - Battery pack; 2000 - Load; 100 - Cell group under test; 200-Voltage sampling circuit; 10-Shunt; 11-Third filter circuit; 20-Voltage acquisition chip; 20a-First sampling pin; 20b-Second sampling pin; 20c-Third sampling pin; 20d-Fourth sampling pin; 30-Voltage regulation device; 40-First filter circuit; 50-Candidate attenuation circuit; 60-Common mode acquisition circuit; 1-First series resistor voltage divider circuit; 2-Second series resistor voltage divider circuit; 3-First adjustable potentiometer circuit; 4-Second adjustable potentiometer circuit; 5-Voltage control component; 5a-First GPIO pin; 5b-Second GPIO pin; 5c-Third GPIO pin; 5d-Fourth GPIO pin; 6-First adjustable resistor component; 7-Second adjustable resistor component; 8-Second filter circuit; 9-First optocoupler relay; 9a-First input pin of first optocoupler relay 9; 9b-Second input pin of first optocoupler relay 9; 9c-First optocoupler relay 9 First output pin; 9d - Second output pin of the first optocoupler relay 9; 9e - Third input pin of the first optocoupler relay 9; 9f - Fourth input pin of the first optocoupler relay 9; 9g - Third output pin of the first optocoupler relay 9; 9h - Fourth output pin of the first optocoupler relay 9; 11 - Second optocoupler relay; 11a - First input pin of the second optocoupler relay 11; 11b - Second input pin of the second optocoupler relay 11; 11c - First output pin of the second optocoupler relay 11; 11d - Second output pin of the second optocoupler relay 11; 11e - Third input pin of the second optocoupler relay 11; 11f - Fourth input pin of the second optocoupler relay 11; 11g - Third output pin of the second optocoupler relay 11; 11h - Fourth output pin of the second optocoupler relay 11; C1 - First capacitor; C c 1 - First conventional capacitor; K1 - First switch; R1 - First filter resistor; R c 1-First traditional resistor; R cdown 1-First traditional voltage divider resistor; R cup 1- First conventional circuit resistance; R down 1 - First voltage divider resistor; R up 1 - First circuit resistor; C2 - Second capacitor; C c 2 - Second conventional capacitor; K2 - Second switch; R2 - Second filter resistor; R c 2-Second traditional resistor; R cdown 2-Second traditional voltage divider resistor; R cup 2-Second conventional circuit resistance; R down2-Second voltage divider resistor; R up 2 - Second circuit resistor; C3 - Third capacitor; C c 3 - Third conventional capacitor; K3 - Third switch; R down 3-Third voltage divider resistor; R up 3 - Resistor of the third circuit; C4 - Capacitor of the fourth circuit; C c 4 - Fourth conventional capacitor; K4 - Fourth switch; R down 4 - Fourth voltage divider resistor; R up 4-Fourth circuit resistor; C c 5 - Fifth traditional capacitor; R down 5 - Fifth voltage divider resistor; R up 5 - Fifth circuit resistor; R down 6 - Sixth voltage divider resistor; R up 6 - Resistor of the sixth circuit; R in 1-First current-limiting resistor; R in 2-Second current-limiting resistor; R in 3-Third current-limiting resistor; R in 4-Fourth current-limiting resistor. Detailed Implementation

[0033] The terms “first,” “second,” etc., are used for descriptive purposes only and have no sequential or technical meaning, nor should they be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0034] In the embodiments of this application, "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0035] Furthermore, the terms "comprising" and "having," and any variations thereof, used in the description of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the steps or modules listed, but may optionally include other steps or modules not listed, or may optionally include other steps or modules inherent to such process, method, product, or device.

[0036] Furthermore, in the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplarily" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the words "exemplarily" or "for example" is intended to present concepts in a concrete manner.

[0037] First, a brief introduction to the application scenarios involved in this application will be given.

[0038] With the increasing prominence of low-temperature range issues in new energy vehicles, electric drive pulse heating technology, which generates a high-frequency alternating large current of 650Hz to 900Hz to raise the battery temperature, has become the mainstream solution for low-temperature range improvement. Under this condition, such as... Figure 1 As shown, the alternating current of the main negative copper busbar generates a high-frequency alternating magnetic field. This magnetic field couples near-field with the shunt acquisition circuit, causing common-mode voltages to be induced at both the positive and negative terminals of the shunt acquisition end. The measured peak value of this common-mode voltage can reach over 1V, far exceeding the 400mV rated common-mode input range of the BMA7318TAIAE chip, leading to current acquisition deviation (measured deviation 47.9A) and the risk of chip damage. The alternating current fluctuations with a pulse heating frequency of 650Hz to 900Hz cause continuous fluctuations in the common-mode voltage. The actual signal voltage is only the product of the bus current and the resistance of the main negative copper busbar. Taking a current of 753A and a resistance of 200μΩ as an example, the actual differential voltage is only about 150mV. The common-mode interference amplitude far exceeds the effective signal, resulting in a severely degraded signal-to-noise ratio.

[0039] For example, such as Figure 1 As shown, it illustrates the effect of pulse heating on the voltage across the acquisition shunt. Figure 1 The positive terminal of the cell assembly under test 100 serves as the positive output terminal (PACK+) of the power assembled cell kit (PACK) and is connected to the positive terminal of the electric drive unit. The negative terminal of the cell assembly under test 100 is connected to the high-voltage ground terminal of the battery management system (BMS). The high-voltage ground terminal of the BMS is connected to the first end of the copper busbar, and the second end of the copper busbar is connected to the first end of the shunt 10. The second end of the shunt 10 serves as the negative output terminal (PACK-) of the battery pack and is connected to the negative terminal of the electric drive unit. The voltage sampling chip 20 is connected in parallel with the shunt 10. The first sampling pin of the voltage sampling chip 20 is connected to the first end of the shunt 10, and the second sampling pin of the voltage sampling chip 20 is connected to the second end of the shunt 10. When the alternating current generates an induced electromotive force on the copper busbar, surges occur between the positive and negative terminals of the shunt 10 of the BMS and ground.

[0040] To address the issue of excessive common-mode voltage, a conventional solution involves adding fixed voltage-dividing resistors at the data acquisition front-end. These resistors, with a fixed resistance ratio, attenuate the common-mode voltage to within the chip's allowable range. For example, combining... Figure 1 ,like Figure 2 As shown, the resistance R of the first conventional circuit cup The first terminal of 1 is connected to the positive input terminal of shunt 10, and the first conventional loop resistor R cupThe second terminal of 1 is connected to the first conventional voltage divider resistor R. cdown The first terminal of 1 is connected to the first conventional voltage divider resistor R. cdown The second terminal of 1 is grounded. The first conventional circuit resistor R... cup The second terminal of 1 is connected to the first conventional capacitor C. c The first terminal of 1 is connected to the first conventional capacitor C. c The second terminal of 1 is grounded. The first conventional circuit resistor R... cup The second terminal of 1 is connected to the first conventional resistor R. c The first terminal of 1 is connected to the first conventional resistor R. c The second terminal of 1 is connected to the second conventional capacitor C. c The first end of 2 is connected to the second conventional capacitor C. c The second terminal of 2 is grounded, and the first conventional resistor R c The second terminal of 1 is connected to the voltage sampling chip 20. The second conventional capacitor C... c The first terminal of 2 is connected to the third conventional capacitor C. c The first terminal of 3 is connected. The third conventional capacitor C c The second terminal of 3 is connected to the fourth conventional capacitor C. c The first terminal of 4 is connected to the fourth conventional capacitor C. c The second terminal of 4 is grounded. The second conventional circuit resistor R... cup The first terminal of 2 is connected to the negative input terminal, and the second conventional circuit resistor R cup The second terminal of 2 is connected to the second conventional voltage divider resistor R. cdown The first terminal of 2 is connected to the second conventional voltage divider resistor R. cdown The second terminal of 2 is grounded. The second conventional circuit resistor R... cup The second terminal of 2 is connected to the fifth conventional capacitor C. c The first terminal of 5 is connected to the fifth conventional capacitor C. c The second terminal of 5 is grounded. The second conventional circuit resistor R... cup The second terminal of 2 is connected to the second conventional resistor R. c The first end of 2 is connected to the second conventional resistor R. c The second terminal of 2 is connected to the fourth conventional capacitor C. c The first end of 4 is connected to the second conventional resistor R. c The second terminal of 1 is connected to the voltage sampling chip 20.

[0041] However, this solution has the following problems: First, the fixed voltage divider resistor cannot sense the dynamic changes of the common-mode voltage in real time. It can only design a fixed voltage division ratio according to the maximum possible common-mode voltage, which leads to unnecessary loss of acquisition accuracy under normal operating conditions. Second, the resistance of the voltage divider resistor ages after long-term high and low temperature cycling, and the voltage division ratio deviates and cannot be automatically corrected, resulting in a continuous decline in acquisition accuracy throughout the entire life cycle. Third, in a low temperature environment of -40℃, the resistor temperature drift can reach more than 5%. After adding the chip's inherent zero drift, the small current detection error can reach 0.6A, which exceeds the requirement of less than or equal to 0.3A.

[0042] In summary, existing fixed voltage divider schemes suffer from drawbacks such as incomplete interference suppression, an inability to balance accuracy and cost, and the lack of closed-loop adaptive adjustment. Therefore, this embodiment provides a BMS current acquisition system, closed-loop adjustment method, and vehicle for suppressing common-mode interference during power battery pulse heating, addressing the following technical issues: Under pulse heating conditions, the common-mode voltage exceeds the limit due to near-field coupling between the high-frequency electromagnetic field of the main negative copper busbar and the shunt acquisition circuit, achieving source suppression and dynamic control of the common-mode voltage; overcoming the blind adjustment defect of traditional fixed voltage divider schemes, achieving adaptive adjustment of voltage divider parameters based on real-time common-mode voltage, while ensuring that the acquisition accuracy does not deteriorate across the entire temperature range and life cycle; establishing a complete system of hardware closed-loop adjustment, software accuracy compensation, and graded fault protection to avoid acquisition distortion and chip damage, meeting the mass production safety requirements of 400V and 800V high-voltage platforms. The core of this embodiment lies in upgrading passive fixed voltage divider to active closed-loop adaptive voltage divider, constructing a complete technical system combining dynamic suppression, signal recovery, multi-scenario scheduling, and dual-path redundancy protection.

[0043] To address the aforementioned issues, this application provides a voltage sampling circuit integrated into a vehicle's battery pack. During battery pulse heating, the magnetic field generated by the high-frequency alternating large current flowing through the battery's main negative copper busbar creates common-mode interference on the sampling signal of the shunt, causing an abnormal increase in the input voltage to ground of the voltage acquisition chip. Through the connection between the shunt, the voltage acquisition chip, and the voltage regulation device, the voltage regulation device attenuates the differential voltage, simultaneously reducing the voltage amplitude to ground at the first sampling pin and / or the second sampling pin. This ensures that the voltage input to the voltage acquisition chip remains within its allowable range, preventing chip sampling distortion or damage due to excessive input voltage, thereby suppressing the impact of common-mode interference on current acquisition accuracy. Simultaneously, the voltage acquisition chip is configured to control the attenuation level of the voltage regulation device, adjusting the attenuation factor according to the actual common-mode interference intensity or current magnitude. This ensures chip input safety while preserving the signal-to-noise ratio of the effective differential signal, balancing measurement reliability and accuracy.

[0044] The embodiments of this application are described below with reference to the accompanying drawings.

[0045] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of a vehicle disclosed in an embodiment of this application. The vehicle can be, but is not limited to, a pure electric vehicle (PEV / BEV), a hybrid electric vehicle (HEV), a range-extended electric vehicle (REEV), a plug-in hybrid electric vehicle (PHEV), or a new energy vehicle.

[0046] In this embodiment of the application, the vehicle 10000 includes a battery pack 1000 and a load 2000.

[0047] The battery pack 1000 is connected to the load 2000 to supply power to the load 2000 so that the vehicle 10000 can operate normally.

[0048] The battery pack 1000 typically includes a battery management system to detect its operating parameters and control and manage it. Specifically, the battery management system includes a voltage sampling circuit to detect the operating parameters of the battery pack 1000.

[0049] Combination Figure 3 ,like Figure 4 As shown, Figure 4 This is a schematic diagram of a battery pack according to an embodiment of this application. The battery pack 1000 includes a cell group under test 100 and a voltage sampling circuit 200. In the battery pack 1000, the voltage sampling circuit 200 is coupled to the cell group under test 100 and is used to detect the current flowing through the cell group under test 100.

[0050] Combination Figure 3 and Figure 4 ,like Figure 5 As shown, Figure 5 This is a schematic diagram of a battery pack according to an embodiment of this application. A copper busbar Cu is disposed in the main circuit of the battery pack 1000. A voltage sampling circuit 200 is connected to the copper busbar Cu. When current flows through the copper busbar Cu, it can generate a magnetic field around it, creating common-mode interference on the sampling signal of the voltage sampling circuit 200.

[0051] It should be noted that in this application, in order to illustrate the relationship between the voltage sampling circuit 200 and the copper busbar Cu, the copper busbar Cu is integrated into the battery pack 1000 as an example, but the position of the copper busbar Cu is not limited.

[0052] In some embodiments, such as Figure 6 As shown, the voltage sampling circuit 200 includes: a shunt 10, a voltage acquisition chip 20, and a voltage regulation device 30.

[0053] The shunt 10 has a resistance value, a rated current value, and an accuracy class. For example, the accuracy class of the shunt 10 is greater than or equal to 0.1. The accuracy class of the shunt 10 can be 0.1, 0.2, or 0.5. The specific accuracy class of the shunt 10 can be selected according to actual conditions, and this application does not limit the specific accuracy class of the shunt 10. The resistance value of the shunt 10 can be 75 μΩ and the rated current value can be 200 A; or, the resistance value of the shunt 10 can be 50 μΩ and the rated current value can be 300 A; or, the resistance value of the shunt 10 can be 100 μΩ and the rated current value can be 100 A. The specific resistance value and rated current value of the shunt 10 can be selected according to actual conditions, and this application does not limit the specific resistance value and rated current value of the shunt 10.

[0054] The voltage acquisition chip 20 can be a BMA7318TAIAE model chip, which has two built-in 12-bit analog-to-digital converter channels, and the gain of the programmable gain amplifier can be adjusted from 1 to 16 times. The voltage acquisition chip 20 can also be a chip from the same series as the BMA7318TAIAE, an upgraded model of the BMA7318TAIAE, or a current detection chip from other manufacturers that has both an analog-to-digital converter and a programmable gain amplifier. The specific model of the voltage acquisition chip 20 and the number of channels of the analog-to-digital converter can be selected according to actual needs; this application does not limit the specific model of the voltage acquisition chip 20 or the number of channels of the analog-to-digital converter.

[0055] The voltage acquisition chip 20 has a built-in analog-to-digital converter (ADC) for converting analog voltage signals into digital quantities. The number of bits in the ADC meets the preset accuracy requirements. Optionally, the number of bits in the ADC can be 12 bits, 14 bits, 16 bits, 8 bits, or 10 bits. The specific number of bits in the ADC can be selected according to the actual situation, and this application does not limit the specific number of bits in the ADC.

[0056] The voltage acquisition chip 20 integrates a programmable gain amplifier, which amplifies the analog voltage signal input to the analog-to-digital converter. The gain factor can be adjusted by an external control signal. The gain range of the programmable gain amplifier meets preset adjustment requirements. Optionally, the gain of the programmable gain amplifier can be adjusted within the range of 1 to 16 times, 1 to 8 times, 1 to 32 times, or 1 to 64 times. The specific gain range and adjustment step size of the programmable gain amplifier can be selected according to actual needs; this application does not impose any restrictions on the specific gain range and adjustment step size of the programmable gain amplifier.

[0057] For example, the shunt 10 can be a 75μΩ / 200A specification with an accuracy class of 0.1. The voltage acquisition chip 20 can be a BMA7318TAIAE chip, which has two built-in idle 12-bit ADC channels and an adjustable PGA gain from 1 to 16 times.

[0058] The voltage acquisition chip 20 is used to acquire the voltage across the shunt 10 to determine the current flowing through the battery cell assembly 100 under test. Specifically, the voltage acquisition chip 20 is used to control the attenuation of the first differential voltage by the voltage regulation device 30, and to acquire a second differential voltage, which is used to determine the current flowing through the battery cell assembly 100 under test.

[0059] The voltage regulation device 30 is mainly used to attenuate the first differential voltage generated across the shunt 10 when the voltage acquisition chip 20 acquires the differential voltage across the shunt 10, thereby reducing the voltage amplitude input to the voltage acquisition chip 20 and preventing the voltage at the sampling pin from exceeding the tolerance range of the voltage acquisition chip 20, which would affect the current detection accuracy. Specifically, the voltage regulation device 30 is used to receive the first differential voltage generated across the shunt 10, attenuate the first differential voltage, and output a second differential voltage.

[0060] In the voltage sampling circuit 200, the shunt 10 is connected in series with the battery cell assembly 100 under test. The voltage acquisition chip 20 is connected to the first end of the shunt 10 via a first sampling pin 20a and to the second end of the shunt 10 via a second sampling pin 20b. The voltage regulating device 30 is connected between the first end of the shunt 10 and the first sampling pin 20a of the voltage acquisition chip 20; and / or; is connected between the second end of the shunt 10 and the second sampling pin 20b of the voltage acquisition chip 20.

[0061] The voltage acquisition chip 20 is connected to the differential signal acquisition channel through the first sampling pin 20a and the second sampling pin 20b.

[0062] During the battery pulse heating process, the first differential voltage generated across the shunt 10 is attenuated by the voltage regulator 30 and then output to the voltage acquisition chip 20, thus forming the main circuit of the voltage sampling circuit 200. For example, under pulse heating conditions, the alternating current frequency is 650Hz to 800Hz, the peak current is 150A, and the peak value of the original common-mode voltage across the shunt 10 reaches 850mV.

[0063] During battery pulse heating, the magnetic field generated by the high-frequency alternating large current flowing through the battery's main negative copper busbar creates common-mode interference on the sampling signal of the shunt, causing an abnormal increase in the input voltage to ground of the voltage acquisition chip. Through the connection between the shunt, the voltage acquisition chip, and the voltage regulator, the voltage regulator attenuates the differential voltage, simultaneously reducing the voltage amplitude to ground at the first sampling pin and / or the second sampling pin. This ensures that the voltage input to the voltage acquisition chip remains within its allowable range, preventing chip sampling distortion or damage due to excessive input voltage and thus suppressing the impact of common-mode interference on current acquisition accuracy. Simultaneously, the voltage acquisition chip is configured to control the attenuation level of the voltage regulator, adjusting the attenuation factor according to the actual common-mode interference intensity or current magnitude. This ensures chip input safety while preserving the signal-to-noise ratio of the effective differential signal, balancing measurement reliability and accuracy.

[0064] In some embodiments, such as Figure 7 As shown, the voltage regulating device 30 includes: a first series resistor voltage divider circuit 1 and a second series resistor voltage divider circuit 2.

[0065] The first terminal of the first series resistor voltage divider circuit 1 is connected to the first terminal of the shunt 10, the second terminal of the first series resistor voltage divider circuit 1 is grounded, and the voltage dividing node of the first series resistor voltage divider circuit 1 is connected to the first sampling pin 20a of the voltage acquisition chip 20. The first terminal of the second series resistor voltage divider circuit 2 is connected to the second terminal of the shunt 10, the second terminal of the second series resistor voltage divider circuit 2 is grounded, and the voltage dividing node of the second series resistor voltage divider circuit 2 is connected to the second sampling pin 20b of the voltage acquisition chip 20.

[0066] The first series resistor voltage divider circuit 1 includes: a first loop resistor R up 1 and the first voltage divider resistor R down 1. Resistance R of the first circuit up The first terminal of 1 is connected to the first terminal of shunt 10, and the first loop resistor R up The second terminal of 1 is connected to the first voltage divider resistor R. down Terminal 1, first voltage divider resistor R down Terminal 1 is grounded. The first loop resistor R... upThe second terminal of 1 is connected to the first sampling pin 20a of the voltage acquisition chip 20. The second terminal of the first voltage divider circuit is connected to the first loop resistor R. up The connection point of the first end of 1 serves as the voltage dividing node of the first series resistor voltage divider circuit 1.

[0067] The second series resistor voltage divider circuit 2 includes: a second loop resistor R up 2 and second voltage divider resistor R down 2. Second circuit resistance R up The first terminal of 2 is connected to the second terminal of shunt 10, and the second loop resistor R up The second terminal of 2 is connected to the second voltage divider resistor R. down 2's first terminal, second voltage divider resistor R down The second terminal of 2 is grounded. The second circuit resistor R... up The second terminal of 2 is connected to the second sampling pin 20b of the voltage acquisition chip 20. The second terminal of the second voltage divider circuit is connected to the second loop resistor R. up The connection point of the first end of 2 serves as the voltage dividing node of the second series resistor voltage divider circuit 2.

[0068] The first series resistor voltage divider circuit 1 includes a first adjustable potentiometer circuit 3, which is configured to adjust the voltage division ratio of the first series resistor voltage divider circuit 1 according to the first differential voltage. The second series resistor voltage divider circuit 2 includes a second adjustable potentiometer circuit 4, which is configured to adjust the voltage division ratio of the second series resistor voltage divider circuit 2 according to the first differential voltage.

[0069] Each sampling signal is stepped down by a resistor divider network before being sent to the voltage acquisition chip 20. Thus, during the battery pulse heating process, even if the high-frequency alternating current excites a magnetic field that causes the common-mode voltage to ground at both ends of the shunt 10 to rise abnormally, the increased voltage to ground is reduced by the resistor divider network according to a predetermined ratio before entering the sampling pin. This ensures that the voltage to ground at the sampling pin is maintained within the allowable input range of the voltage acquisition chip 20, which helps to avoid chip saturation, distortion or damage due to overvoltage at the input end, thereby suppressing the impact of common-mode interference on the current acquisition accuracy.

[0070] In some embodiments, such as Figure 7 As shown, the adjustable potentiometer circuit includes: an adjustable resistor component and a voltage control component 5.

[0071] The adjustable resistor component can be a digital potentiometer (such as MCP41HV51-1), a digitally controlled variable resistor, a voltage-controlled resistor composed of a field-effect transistor, or a resistor network composed of multiple fixed resistors and analog switches. The specific form of the adjustable resistor component can be set according to the actual situation, and this application does not limit the specific form of the adjustable resistor component. The voltage control component 5 can be a microcontroller unit (MCU), a digital signal processor (DSP), a field-programmable gate array (FPGA), or an application-specific integrated circuit (ASIC). The specific type of the voltage control component 5 can be set according to the actual situation, and this application does not limit the specific type of the voltage control component 5.

[0072] The voltage control component 5 is connected to both the voltage acquisition chip 20 and the adjustable resistor component. The voltage control component 5 is configured to: receive a first differential voltage; and adjust the resistance value of the adjustable resistor component based on the first differential voltage.

[0073] Specifically, the voltage control component 5 is connected to the voltage acquisition chip 20 via an SPI bus, and also to the adjustable resistor component via an SPI bus. The SPI bus includes a serial clock (SCK) signal line, a serial data input (SII) signal line, and a chip select (CS) signal line. The power supply terminal of the adjustable resistor component is connected to the positive terminal VCC of the DC power supply, and the ground terminal of the adjustable resistor component is grounded.

[0074] For example, the first adjustable potentiometer circuit 3 includes a first adjustable resistor component 6 and a voltage control component 5. The second adjustable potentiometer circuit 4 includes a second adjustable resistor component 7 and a voltage control component 5. The voltage control component 5 is connected to the first adjustable resistor component 6 via an SPI bus, and the voltage control component 5 is connected to the second adjustable resistor component 7 via an SPI bus.

[0075] The voltage control component is connected to both the voltage acquisition chip and the adjustable resistor component. It is configured to receive a first differential voltage and adjust the resistance value of the adjustable resistor component based on this voltage. The voltage control component dynamically changes the resistance value of the adjustable resistor component according to the amplitude of the first differential voltage actually generated across the shunt, thereby adjusting the attenuation ratio of the adjustable potentiometer circuit in real time. Local adjustment based on the first differential voltage allows for timely adjustment of the attenuation amount when the current changes rapidly during pulse heating, ensuring that the voltage input to the sampling pin of the voltage acquisition chip remains within its allowable linear input range. This avoids short-term overvoltage at the chip input due to adjustment lag, which could affect sampling accuracy. Simultaneously, it ensures the matching of the effective differential signal with the chip's analog-to-digital conversion range under different current amplitude conditions, improving the real-time performance and accuracy of current detection.

[0076] In some embodiments, such as Figure 7 As shown, the voltage sampling circuit further includes a first filter circuit 40; the first filter circuit 40 includes a first capacitor C1, a second capacitor C2, and a first filter resistor R1. The first filter resistor R1 is connected between the voltage divider node of the first series resistor voltage divider circuit 1 and the first sampling pin 20a of the voltage acquisition chip 20; the first capacitor C1 is connected between the voltage divider node of the first series resistor voltage divider circuit 1 and the first filter resistor R1; and the second capacitor C2 is connected between the first filter resistor R1 and the first sampling pin 20a of the voltage acquisition chip 20.

[0077] Specifically, the first terminal of the first capacitor C1 is connected to the first terminal of the first filter resistor R1, and the second terminal of the first capacitor C1 is grounded. The first terminal of the second capacitor C2 is connected to the second terminal of the first filter resistor R1, and the second terminal of the second capacitor C2 is grounded. The connection point between the first terminal of the first capacitor C1 and the first terminal of the first filter resistor R1 serves as the first filter node, and the connection point between the first terminal of the second capacitor C2 and the second terminal of the first filter resistor R1 serves as the second filter node. The first voltage divider node is located between the first voltage divider circuit and the first loop resistor R1. up Between 1 and 2, the first filtering node is located between the input terminal of the first filtering resistor R1 and the first capacitor C1, and the second filtering node is located between the output terminal of the first filtering resistor R1 and the second capacitor C2. The signal path is as follows: the voltage signal after voltage division output by the first voltage divider node is transmitted to the second filtering node through the first filtering resistor R1, and then input to the first sampling pin 20a of the voltage acquisition chip 20; the first capacitor C1 performs high-frequency bypass filtering on the signal at the first filtering node, and the second capacitor C2 performs secondary high-frequency bypass filtering on the signal at the second filtering node.

[0078] The first filtering circuit also includes: a third capacitor C3, a fourth capacitor C4, and a second filtering resistor R2. The second filtering resistor R2 is connected between the voltage divider node of the second series resistor voltage divider circuit and the second sampling pin 20b of the voltage acquisition chip 20. The third capacitor C3 is connected between the voltage divider node of the second series resistor voltage divider circuit and the second filtering resistor R2. The fourth capacitor C4 is connected between the second filtering resistor R2 and the second sampling pin 20b of the voltage acquisition chip 20.

[0079] Specifically, the first terminal of the third capacitor C3 is connected to the first terminal of the second filter resistor R2, and the second terminal of the third capacitor C3 is grounded. The first terminal of the fourth capacitor C4 is connected to the second terminal of the second filter resistor R2, and the second terminal of the fourth capacitor C4 is grounded. The connection point between the first terminal of the third capacitor C3 and the first terminal of the second filter resistor R2 serves as the third filter node, and the connection point between the first terminal of the fourth capacitor C4 and the second terminal of the second filter resistor R2 serves as the fourth filter node. The second voltage divider node is located between the second voltage divider circuit and the second loop resistor R. up Between points 2 and 3, the third filtering node is located between the input terminal of the second filtering resistor R2 and the third capacitor C3, and the fourth filtering node is located between the output terminal of the second filtering resistor R2 and the fourth capacitor C4. The signal path is as follows: the voltage signal output by the second voltage divider node is transmitted to the fourth filtering node via the second filtering resistor R2, and then input to the second sampling pin of the voltage acquisition chip 20; the third capacitor C3 performs high-frequency bypass filtering on the signal at the third filtering node, and the fourth capacitor C4 performs secondary high-frequency bypass filtering on the signal at the fourth filtering node.

[0080] In some embodiments, combined with Figure 7 ,like Figure 8 As shown, the voltage sampling circuit also includes: a candidate attenuation circuit 50, a first switch K1, a second switch K2, a third switch K3, and a fourth switch K4.

[0081] The alternative attenuation circuit 50 includes: a second filter circuit 8 and a third loop resistor R. up 3. Third voltage divider resistor R down 3. Resistor R of the fourth circuit up 4 and the fourth voltage divider resistor R down 4. Resistor R of the third circuit up 3. Third voltage divider resistor R down 3. Resistor R of the fourth circuit up 4 and the fourth voltage divider resistor R down The circuit structure between 4, and the first loop resistor R up 1. First voltage divider resistor R down 1. Second circuit resistance R up 2 and second voltage divider resistor R downThe circuit structures between points 2 and 3 are the same, and the resistance of the third loop is R. up 3. Third voltage divider resistor R down 3. Resistor R of the fourth circuit up 4 and the fourth voltage divider resistor R down The connection method between 4 can be referenced from the first loop resistor R. up 1. First voltage divider resistor R down 1. Second circuit resistance R up 2 and second voltage divider resistor R down The connection method between 2. The circuit structure of the second filter circuit 8 is the same as that of the first filter circuit 40. The specific connection method of the second filter circuit 8 can refer to the specific connection method of the first filter circuit 40. This application specifies the third loop resistor R. up 3. Third voltage divider resistor R down 3. Resistor R of the fourth circuit up 4 and the fourth voltage divider resistor R down The connection method between 4 and the specific connection method of the second filter circuit 8 are not restricted.

[0082] The candidate attenuation circuit 50 is connected between the shunt 10 and the voltage acquisition chip 20, and is connected in parallel with the voltage regulator 30. The first switch K1 is connected between the voltage regulator 30 and the first sampling pin 20a of the voltage acquisition chip 20, and the second switch K2 is connected between the voltage regulator 30 and the second sampling pin 20b of the voltage acquisition chip 20. The third switch K3 is connected between the candidate attenuation circuit 50 and the first sampling pin 20a of the voltage acquisition chip 20, and the fourth switch K4 is connected between the candidate attenuation circuit 50 and the second sampling pin 20b of the voltage acquisition chip 20.

[0083] The first differential voltage generated across the shunt 10 is attenuated by the candidate attenuation circuit 50 and then output to the voltage acquisition chip 20, thus forming a bypass loop. For example, the ratio between the attenuated differential voltage across the shunt 10 and the differential voltage before attenuation in the bypass loop is 0.355, ensuring that the common-mode voltage is suppressed within a safe range under the worst operating conditions.

[0084] Among them, the first switch K1, the second switch K2, the third switch K3 and the fourth switch K4 can be metal-oxide-semiconductor field-effect transistors, or they can be insulated-gate bipolar transistors, or the first switch K1, the second switch K2, the third switch K3 and the fourth switch K4 can be the internal switch group of an optocoupler relay.

[0085] For example, the first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 are internal switch groups using two Panasonic AQW214 optocoupler relays. The first switch K1 and the second switch K2 correspond to the two internal switches of one Panasonic AQW214 optocoupler relay, and the third switch K3 and the fourth switch K4 correspond to the two internal switches of one Panasonic AQW214 optocoupler relay.

[0086] like Figure 7 As shown, the first optocoupler relay 9 includes a first internal switch and a second internal switch, wherein the first switch K1 is composed of the first internal switch and the third switch K3 is composed of the second internal switch. The second optocoupler relay 11 includes a third internal switch and a fourth internal switch, wherein the third switch K2 is composed of the third internal switch and the fourth switch K4 is composed of the fourth internal switch.

[0087] The first input pin 9a of the first optocoupler relay 9 is connected to the first general purpose input output (GPIO) pin 5a of the voltage control component 5. The voltage control component 5 controls the on / off state of the first switch K1 by pulling the level of the first GPIO pin 5a high or low. The second input pin 9b of the first optocoupler relay 9 is grounded. The first output pin 9c of the first optocoupler relay 9 is connected to the first terminal of the shunt 10, and the second output pin 9d of the first optocoupler relay 9 is connected to the first sampling pin 20a of the voltage acquisition chip 20.

[0088] The third input pin 9e of the first optocoupler relay 9 is connected to the second GPIO pin 5b of the voltage control component 5. The voltage control component 5 controls the on / off state of the third switch K3 by pulling the level of the second GPIO pin 5b high or low. The fourth input pin 9f of the first optocoupler relay 9 is grounded. The third output pin 9g of the first optocoupler relay 9 is connected to the second terminal of the shunt 10, and the fourth output pin 9h of the first optocoupler relay 9 is connected to the second sampling pin 20b of the voltage acquisition chip 20.

[0089] The first input pin 11a of the second optocoupler relay 11 is connected to the third GPIO pin 5c of the voltage control component 5. The voltage control component 5 controls the on / off state of the second switch K2 by pulling the level of the third GPIO pin 5c high or low. The second input pin 11b of the second optocoupler relay 11 is grounded. The first output pin 11c of the second optocoupler relay 11 is connected to the first end of the shunt 11, and the second output pin 11d of the second optocoupler relay 11 is connected to the first sampling pin 20a of the voltage acquisition chip 20.

[0090] The third input pin 11e of the second optocoupler relay 11 is connected to the fourth GPIO pin 5d of the voltage control component 5. The voltage control component 5 controls the conduction and cutoff of the fourth switch K4 by pulling the level of the fourth GPIO pin 5d high or low. The fourth input pin 11f of the second optocoupler relay 11 is grounded. The third output pin 11g of the second optocoupler relay 11 is connected to the second terminal of the shunt 11, and the fourth output pin 10h of the second optocoupler relay 11 is connected to the second sampling pin 20b of the voltage acquisition chip 20.

[0091] In some embodiments, the first input pin 9a of the first optocoupler relay 9 and the first GPIO pin 5a of the voltage control component 5 are connected by a first current-limiting resistor R. in 1. Connection: The third input pin 9e of the first optocoupler relay 9 is connected to the first GPIO pin 5b of the voltage control component 5 via a second current-limiting resistor R. in 2. The first input pin 11a of the first optocoupler relay 9 and the first GPIO pin 5c of the voltage control component 5 are connected by a first current-limiting resistor R. in 3. The third input pin 11e of the first optocoupler relay 9 is connected to the first GPIO pin 5d of the voltage control component 5 through the second current-limiting resistor R. in 4. Connections.

[0092] Specifically, the first output pin 9c of the first optocoupler relay 9 is connected to the second filter node of the first filter circuit 40. The third output pin 9g of the first optocoupler relay 9 is connected to the fourth filter node of the first filter circuit 40. The first output pin 11c of the second optocoupler relay 11 is connected to the second filter node of the second filter circuit 8. The third output pin 11g of the second optocoupler relay 11 is connected to the fourth filter node of the second filter circuit 8. This allows for switching between the main signal path and the bypass signal path acquisition channels.

[0093] By closing and opening the first switch K1, the second switch K2, the third switch K3 and the fourth switch K4, the signal path can be seamlessly switched from the main signal path to the bypass signal path, so that the system signal is not interrupted and an independent current acquisition link is provided in the event of a fault in the signal conditioning architecture.

[0094] Specifically, when the voltage regulator 30 is functioning correctly, the first switch K1 and the second switch K2 are configured to be on, and the third switch K3 and the fourth switch K4 are configured to be off. When the voltage regulator 30 malfunctions, the first switch K1 and the second switch K2 are configured to be off, and the third switch K3 and the fourth switch K4 are configured to be on.

[0095] The voltage control component 5 can determine whether the voltage regulator 30 has malfunctioned. For example, the voltage control component 5 writes a target resistance value to the voltage regulator 30 via the SPI bus, and performs a readback operation after each write to read the current actual resistance value of the digital potentiometer in the voltage regulator 30. The voltage control component 5 compares the readback actual resistance value with the previously written target resistance value. If the comparison results match, the voltage control component 5 determines that the voltage regulator 30 is currently in normal working condition; if the comparison results do not match, the voltage control component 5 records an abnormal event. The voltage control component 5 continuously performs the above write, readback, and comparison operations, and if the comparison results are inconsistent for three consecutive times, it determines that the voltage regulator 30 has malfunctioned. The voltage control component 5 controls the on / off states of the first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 according to the determination result.

[0096] When the voltage regulator 30 is determined to be in normal working condition, the voltage control component 5 outputs a high level through the first GPIO pin to control the first switch K1 to turn on, outputs a high level through the second GPIO pin to control the second switch K2 to turn on, outputs a low level through the third GPIO pin to control the third switch K3 to turn off, and outputs a low level through the fourth GPIO pin to control the fourth switch K4 to turn off. The voltage regulator 30 connects to the signal path to attenuate the first differential voltage.

[0097] When a fault is detected in the voltage regulation device 30, the voltage control component 5 outputs a low level through the first GPIO pin to control the first switch K1 to open, outputs a low level through the second GPIO pin to control the second switch K2 to open, outputs a high level through the third GPIO pin to control the third switch K3 to turn on, and outputs a high level through the fourth GPIO pin to control the fourth switch K4 to turn on. The alternative attenuation circuit 50 is connected to the signal path to attenuate the first differential voltage by a fixed ratio.

[0098] When the voltage regulator 30 is functioning correctly, the first switch K1 and the second switch K2 are on, while the third switch K3 and the fourth switch K4 are off. The voltage acquisition chip 20 acquires the differential signal through the path of the voltage regulator 30, utilizing the adjustable attenuation characteristics of the voltage regulator 30 to ensure sampling accuracy under different current conditions. When the voltage regulator 30 malfunctions, the first switch K1 and the second switch K2 are off, while the third switch K3 and the fourth switch K4 are on. The voltage acquisition chip 20 switches to the path of the backup attenuation circuit 50, which attenuates the first differential voltage across the shunt 10 by a fixed ratio before outputting it to the voltage acquisition chip 20, thus maintaining the current sampling function. This provides a backup measurement path for the voltage sampling circuit in case of a fault, which helps improve the reliability of current sampling under complex conditions such as pulse heating.

[0099] The voltage acquisition chip can select the signal path of the voltage regulator by controlling the on / off state of the first and second switches, or select the signal path of the backup attenuation circuit by controlling the on / off state of the third and fourth switches. When the path of the voltage regulator fails to operate normally due to a fault or insufficient adjustment range, it can switch to the path of the backup attenuation circuit. The backup attenuation circuit attenuates the first differential voltage across the shunt by a fixed ratio before outputting it to the voltage acquisition chip, thus providing a backup measurement path for current sampling. This helps improve the reliability and redundancy of the voltage sampling circuit under complex operating conditions such as pulse heating. Simultaneously, the voltage acquisition chip can select and switch between the adjustable attenuation path and the fixed attenuation path according to the actual operating conditions. For conditions requiring high measurement accuracy, the voltage regulator is used for flexible attenuation; for conditions requiring fast response or simplified control, the backup attenuation circuit is used for fixed attenuation, balancing sampling flexibility and system stability.

[0100] In some embodiments, such as Figure 9 As shown, the voltage sampling circuit also includes a common-mode acquisition circuit 60. The common-mode acquisition circuit (60) includes: The common-mode acquisition circuit (60) includes: a third filter circuit 11 and a fifth loop resistor R. up 5. Fifth voltage divider resistor R down 5. Resistor R of the sixth circuit up 6 and the sixth voltage divider resistor R down 6. Fifth circuit resistor R up 5. Fifth voltage divider resistor R down 5. Resistor R of the sixth circuit up 6 and the sixth voltage divider resistor R down The circuit structure between 6, and the first loop resistor R up 1. First voltage divider resistor R down 1. Second circuit resistance Rup 2 and second voltage divider resistor R down The circuit structures between points 2 and 3 are the same, with the fifth loop resistor R. up 5. Fifth voltage divider resistor R down 5. Resistor R of the sixth circuit up 6 and the sixth voltage divider resistor R down The connection method between 6 can be referenced from the first loop resistor R. up 1. First voltage divider resistor R down 1. Second circuit resistance R up 2 and second voltage divider resistor R down The connection method between 2 is introduced, and the circuit structure of the third filter circuit 11 is described. Figure 2 The first traditional capacitor C c 1. Second traditional capacitor C c 2. Third traditional capacitor C c 3. Fourth traditional capacitor C c 4. Fifth traditional capacitor C c 5. First traditional resistor R c 1 and the second conventional resistor R c The circuit structure is the same as that of circuit 2. The specific connection method of the third filter circuit 11 can be found in [reference needed]. Figure 2 The first traditional capacitor C c 1. Second traditional capacitor C c 2. Third traditional capacitor C c 3. Fourth traditional capacitor C c 4. Fifth traditional capacitor C c 5. First traditional resistor R c 1 and the second conventional resistor R c 2. A detailed description of the connection method is provided in this application regarding the fifth circuit resistor R. up 5. Fifth voltage divider resistor R down 5. Resistor R of the sixth circuit up 6 and the sixth voltage divider resistor R down The connection method between 6 and the specific connection method of the third filter circuit 11 are not restricted.

[0101] The first terminal of the common-mode acquisition circuit (60) is connected to the first terminal of the shunt 10 and the third sampling pin 20c of the voltage acquisition chip 20, and the second terminal of the common-mode acquisition circuit (60) is connected to the second terminal of the shunt 10 and the fourth sampling pin 20d of the voltage acquisition chip 20. The common-mode acquisition circuit (60) is used to filter the common-mode noise across the shunt 10. The voltage acquisition chip 20 is also used to acquire the first differential voltage, which is the voltage across the shunt 10 after attenuation by the common-mode acquisition circuit (60).

[0102] The voltage acquisition chip 20 is connected to the common-mode voltage monitoring channel through the third sampling pin 20c and the fourth sampling pin 20d.

[0103] Thus, by using the ADC channel of the voltage acquisition chip 20, the original common-mode voltage, i.e. the first differential voltage, can be acquired in real time across the shunt 10.

[0104] By connecting a common-mode acquisition circuit between the two ends of the shunt and the sampling pin of the voltage acquisition chip, common-mode noise at the two ends of the shunt can be filtered, reducing the residual common-mode component in the first differential voltage entering the voltage acquisition chip. The common-mode acquisition circuit has a certain degree of attenuation effect on the first differential voltage. The voltage acquisition chip acquires the first differential voltage after attenuation by the common-mode acquisition circuit, and further adjusts the amplitude of the differential signal by controlling the voltage regulation device. The common-mode acquisition circuit performs preliminary filtering and attenuation of the signal at the common-mode suppression level, while the voltage regulation device adjusts the amplitude at the differential signal level. This helps to suppress common-mode interference during battery pulse heating while ensuring a reasonable amplitude of the effective differential signal, thereby improving the sampling accuracy of the voltage acquisition chip in common-mode interference scenarios.

[0105] like Figure 10 The diagram illustrates an operation method for a voltage sampling circuit provided in this application. The method, applied to a voltage sampling circuit, includes: S101. Obtain the first differential voltage generated across the shunt.

[0106] As one possible implementation, S101 includes: acquiring the positive-to-ground voltage and negative-to-ground voltage of the differential signal line through the first sampling pin and the second sampling pin of the voltage acquisition chip at both ends of the shunt; determining the average voltage between the positive-to-ground voltage and the negative-to-ground voltage based on the positive-to-ground voltage and the negative-to-ground voltage; and performing a moving average filter on the average voltage to obtain the first differential voltage.

[0107] For example, the positive-to-ground voltage of the differential signal line is read through the first sampling pin of the voltage acquisition chip, and the negative-to-ground voltage of the differential signal line is read through the second sampling pin of the voltage acquisition chip. The first and second sampling pins are synchronously triggered to perform the reading operation at a sampling frequency of 1kHz. After determining the average voltage value, the average voltage value is stored in a preset 10-point data queue. Each time a new average voltage value is stored, the oldest value stored in the queue is removed, ensuring that the queue always contains the 10 most recently acquired and calculated average voltage values. When the queue is full of 10 average voltage values, all 10 average voltage values ​​in the queue are summed and divided by 10. The calculation result is used as the current moving average filter output value, and this current moving average filter output value is determined as the first differential voltage at the current moment. This eliminates high-frequency glitches.

[0108] S102. The attenuation degree of the first differential voltage is controlled by the voltage regulating device based on the first differential voltage.

[0109] The amplitude of the first differential voltage directly corresponds to the potential difference generated across the shunt due to the current flowing through the main circuit. The actual value of this potential difference reflects the magnitude range of the current being measured. Since voltage acquisition chips typically have a preset allowable input voltage window, if the original amplitude of the first differential voltage exceeds the upper limit of this window, direct input will lead to saturation of the sampling signal and inaccurate quantization. If the original amplitude is too small relative to the lower limit of the window, excessive attenuation must be avoided to prevent the effective signal from being buried in sampling noise. Therefore, based on the measured amplitude data of the first differential voltage, the direction and degree of deviation of the measured amplitude from the optimal sampling range of the voltage acquisition chip can be determined, and a corresponding attenuation control command can be generated based on this deviation. The voltage regulation device, in response to this control command, adjusts the parameters of its internal voltage divider network or adjustable impedance branch, thereby adjusting the first differential voltage to an amplitude range compatible with the input range of the voltage acquisition chip.

[0110] For details on the specific implementation of the attenuation of the first differential voltage by the voltage regulating device based on the first differential voltage, please refer to S201-S202.

[0111] S103. The voltage regulator attenuates the first differential voltage to output the second differential voltage.

[0112] The second differential voltage is used to determine the current flowing through the battery cell assembly under test.

[0113] As can be seen from S101-S103, in the solution provided by this application, the attenuation degree of the voltage regulation device is determined based on the actual differential voltage amplitude generated across the shunt, rather than using a fixed attenuation ratio. During battery pulse heating, when common-mode interference causes an abnormal increase in the input-to-ground voltage, this method can adjust the attenuation amount based on the real-time acquired first differential voltage, ensuring that the attenuated second differential voltage is within the allowable input range of the voltage acquisition chip. Simultaneously, when the current amplitude changes, the closed-loop adjustment step based on the first differential voltage included in this method can dynamically adapt to different current conditions, ensuring that the second differential voltage matches the range of the voltage acquisition chip. This helps to suppress input overvoltage caused by common-mode interference while reducing the impact of quantization error on the measurement results, thereby improving the accuracy and reliability of current detection.

[0114] As a feasible implementation method, S102 includes: S201. Determine the target voltage ratio based on the first differential voltage and the target common-mode voltage.

[0115] The target voltage ratio is the ratio between the first differential voltage and the target common-mode voltage. The target common-mode voltage is the upper limit of the common-mode voltage allowed to be input at the first and second sampling pins of the voltage acquisition chip. After the voltage regulator adjusts the voltage division ratio of the first and second series resistor voltage divider circuits according to the target voltage ratio, the common-mode voltage output to the first and second sampling pins after attenuation does not exceed the target common-mode voltage. The target common-mode voltage can be set to any voltage value within the input range of the voltage acquisition chip, specifically 200mV, 250mV, 300mV, 350mV, or 400mV. The specific value of the target common-mode voltage can be set according to the actual situation, and this application does not limit the specific value of the target common-mode voltage.

[0116] As one possible implementation, the target voltage ratio satisfies Formula 1.

[0117] Formula 1.

[0118] in, Used to indicate the proportion of the target voltage. Used to represent the target common-mode voltage. Used to represent the first differential voltage.

[0119] For example, if the maximum allowable common-mode voltage fluctuation of the voltage acquisition chip is 400mV, the target common-mode voltage is 300mV, and a voltage margin of 100mV is reserved so that the current detection error does not exceed 0.2A when the current calculation result is in a small current range (e.g., not exceeding 10% of the rated current range of the shunt), then the target voltage ratio satisfies Formula 2.

[0120] Formula 2.

[0121] In this way, the required voltage division ratio can be dynamically calculated based on the target safe voltage, and the resistance value of the voltage division resistor can be precisely adjusted by the high-voltage digital potentiometer, so that the voltage entering the voltage acquisition chip is the voltage after voltage division, thus avoiding damage to the voltage acquisition chip.

[0122] S202. Based on the target voltage ratio, control the attenuation degree of the first differential voltage by the voltage regulation device.

[0123] As one possible implementation, S202 includes: determining a target adjustable resistance value for the adjustable resistor component based on a target voltage ratio; and controlling the attenuation degree of the first differential voltage by the adjustable resistor component based on the target adjustable resistance value.

[0124] Specifically, the target adjustable resistance value of the adjustable resistor component is determined as follows: Formula 4 can be derived by reverse calculation based on Formula 1 and Formula 3 to determine the target adjustable resistance value of the adjustable resistor component.

[0125] Formula 3.

[0126] The target adjustment resistance value satisfies Formula 4.

[0127] Formula 4.

[0128] in, Used to indicate the target adjustment resistance value Used to represent loop resistance Used to indicate voltage divider resistors.

[0129] Specifically, adjusting the resistance of the adjustable resistor component to the target adjustable resistance value achieves the attenuation of the first differential voltage. The method for adjusting the resistance of the adjustable resistor component to the target adjustable resistance value is as follows: obtain the actual resistance value of the adjustable resistor component and determine the resistance difference between the actual resistance value and the target adjustable resistance value; if the resistance difference is greater than or equal to a first preset resistance difference threshold, output a first adjustment signal to the adjustable potentiometer; if the resistance difference is less than or equal to a second preset resistance difference threshold, output a second adjustment signal to the adjustable potentiometer.

[0130] The first preset resistance difference threshold is greater than the second preset resistance difference threshold. A first adjustment signal instructs the adjustable resistor component to adjust its resistance in a first resistance step size, and a second adjustment signal instructs the adjustable resistor component to adjust its resistance in a second resistance step size, where the first resistance step size is greater than the second resistance step size. Thus, through step-type resistance adjustment and a variable step size adjustment strategy, large resistance differences are quickly approximated, while small differences are finely adjusted, avoiding overshoot in resistance adjustment.

[0131] In some embodiments, since the calculated target adjustable resistance is only a theoretical value, it may exceed the physical capability of the adjustable resistor component. Therefore, software limiting is required to force the calculation result within the chip's allowed resistance range. For example, the chip's allowed resistance range is greater than or equal to 0 and less than or equal to 1 kiloohm. In the case of a calculated target adjustable resistance of 1200 ohms, the target adjustable resistance needs to be limited to 1 kiloohm. The limited target resistance is then mapped to an 8-bit tap value. The mapping method is to divide the target resistance by the maximum allowed resistance, multiply by 255, and round down to obtain an integer tap value in the range of 0 to 255. This tap value is written to the adjustable resistor component chip through the Serial Peripheral Interface (SPI) communication interface. The adjustable resistor component chip moves its internal sliding terminal to the corresponding tap position according to the received tap value, so that the actual resistance between the two ends of the adjustable resistor component is equal to the limited target resistance value.

[0132] In some embodiments, a first preset time is delayed after each output adjustment signal; after the delay, the voltage value after voltage division is read by a voltage acquisition chip; the read voltage value is compared with the target common-mode voltage to determine whether the read voltage value is within the allowable error range of the target common-mode voltage; if the voltage values ​​read for a first preset number of consecutive times are within the allowable error range, the controller determines that the resistance adjustment is complete and stops outputting adjustment signals; if any comparison result in the first preset number of consecutive times exceeds the allowable error range, the controller recalculates the difference between the current resistance value and the target resistance value and repeats the step adjustment and feedback verification steps until the determination condition that the first preset number of consecutive times are within the allowable error range is met. The first preset time can be 5 milliseconds, 6 milliseconds, 8 milliseconds, 9 milliseconds, or 10 milliseconds, and the first preset number of times can be 2, 3, 4, 5, or 6. The specific values ​​can be set according to the actual situation. This application does not limit the values ​​of the first preset time and the first preset number of times.

[0133] As can be seen from S201-S202, the solution provided in this application, by introducing a target common-mode voltage as a reference and calculating the ratio of the first differential voltage to it, can obtain a normalized control quantity with the target common-mode voltage as the scale. This control quantity is not affected by the single factor of the absolute amplitude of the first differential voltage, but reflects the attenuation ratio required to bring the common-mode voltage back to the target value under the current differential signal conditions. Based on this, by controlling the attenuation degree according to the target voltage ratio, the input common-mode voltage corresponding to the attenuated second differential voltage can be made to approach the preset target common-mode voltage, thereby ensuring that the operating voltage at the sampling pin of the voltage acquisition chip is always within its optimized linear input range. During battery pulse heating, when the common-mode interference intensity changes, causing fluctuations in the first differential voltage, the attenuation amount can be dynamically adjusted based on the real-time ratio to avoid overvoltage at the input terminal due to insufficient attenuation or loss of effective signal due to excessive attenuation.

[0134] In some embodiments, after the voltage acquisition and adjustment device attenuates the first differential voltage to output the second differential voltage, reverse gain compensation can be performed by the programmable gain amplifier (PGA) built into the voltage acquisition chip to offset the differential signal attenuation caused by voltage division.

[0135] As a feasible implementation method, after the voltage sampling circuit attenuates the first differential voltage to output the second differential voltage, the operation method of the voltage sampling circuit also includes: S301. Determine the actual voltage division ratio based on the first differential voltage and the updated first differential voltage.

[0136] The actual voltage division ratio is the ratio between the first differential voltage and the updated first differential voltage. For example, the actual voltage division ratio satisfies Formula 5.

[0137] Formula 5.

[0138] in, Used to indicate the actual partial pressure ratio Used to represent the updated first differential voltage, used to represent the first differential voltage.

[0139] Configure the AFE chip's built-in PGA gain to 1 / K_actual, and restore the differential signal amplitude to its pre-division level. S302. Determine the target gain value based on the actual voltage division ratio.

[0140] The target gain value is the ratio between the actual voltage division ratio and 1. For example, the target gain value satisfies Formula Six.

[0141] Formula Six.

[0142] S303. Based on the target gain value, adjust the chip gain of the voltage acquisition chip to determine the adjusted second differential voltage.

[0143] In this way, the differential signal attenuation can be compensated by adjusting the chip gain of the voltage acquisition chip.

[0144] As can be seen from S301-S303, the solution provided in this application calculates the actual voltage division ratio by introducing a first differential voltage and an updated first differential voltage as feedback quantities, and maps this ratio to the basis for adjusting the chip gain. This creates a linkage between the external attenuation of the voltage regulation device and the internal gain of the voltage acquisition chip. Changes in the external attenuation can be reflected in real time as corresponding changes in the target gain value. The second differential voltage, after chip gain adjustment, can recover to the effective amplitude range of the analog-to-digital conversion based on the attenuated signal, avoiding insufficient utilization of the chip's internal quantization resolution due to fixed external attenuation. Simultaneously, dynamic gain adjustment based on the updated first differential voltage allows the chip gain to change accordingly with real-time changes in common-mode interference, which is beneficial for maintaining the signal-to-noise ratio and measurement consistency of the sampling signal during battery pulse heating, further improving the accuracy of current detection.

[0145] In some embodiments, after obtaining the second differential voltage, it needs to be converted into the current calculation result of the battery cell assembly. Therefore, during operation, after completing the common-mode voltage closed-loop regulation and PGA signal amplitude recovery, the BMS main control unit can look up the mapping table between temperature and current correction coefficients based on the current temperature of the shunt to obtain the temperature compensation coefficient, thereby correcting the final current calculation result. In this way, temperature drift and aging errors of the entire shunt, resistor network, PGA, and AFE link can be compensated in one go.

[0146] For example, a one-dimensional mapping table between temperature and current correction coefficients can be established in advance to correct the calculated current value. Before the vehicle leaves the factory, the battery management system (BMS) board is placed in a high and low temperature test chamber, and the complete acquisition link from the shunt to the AFE output is calibrated at the system level at seven temperature points: -40℃, -20℃, 0℃, 25℃, 45℃, 65℃, and 85℃. A one-dimensional mapping table between temperature and current correction coefficients is established and stored in the BMS Flash. In this way, combined with the full-temperature-range pre-calibration model, errors caused by temperature drift and aging can be automatically corrected, realizing closed-loop control from dynamic changes in common-mode voltage to automatic tracking of the voltage divider ratio, and finally to maintaining optimal acquisition accuracy.

[0147] As a feasible implementation method, the operation method of the voltage sampling circuit also includes: in the event of a failure of the voltage regulation device, issuing a switch control command, which is used to control the first target switch to open and the second target switch to open.

[0148] For example, after each SPI write to the digital potentiometer, a readback operation is performed to read the current actual resistance value of the digital potentiometer and compare it with the written target adjustment resistance value. If the comparison results are inconsistent for a second preset number of consecutive times, the voltage regulation device is determined to be faulty. After determining that the voltage regulation device is faulty, a bypass relay drive signal is output to set the bypass relay drive to a high level, and the bypass signal path is connected. At this time, the main signal path and the bypass signal path are in a brief parallel state, and the signal acquisition channel always has a signal input. A second preset time is delayed to wait for the second switch K2 and the third switch K3 to be turned on. After the delay, the main relay drive is set to a low level, the first switch K1 and the second switch K2 are turned off, the main signal path is cut off, and the signal is completely provided by the bypass signal path. The signal is not interrupted and the sampling pin voltage does not change abruptly during the entire switching process. After the switching is completed, a three-level fault alarm message is periodically sent through the CAN bus to indicate that the digital potentiometer module needs maintenance, and the maintenance indicator light is lit on the instrument panel. In this degraded operating mode, the system continues to operate with a fixed voltage division ratio, the common-mode voltage is still suppressed within a safe range, and although the current acquisition accuracy decreases, it still meets basic monitoring requirements. The vehicle maintains charging or pulse heating functions. The second preset number of times can be 2, 3, 4, 5 or 6, and the second preset time can be 50 milliseconds, 60 milliseconds, 80 milliseconds, 100 microseconds or 120 milliseconds. The specific values ​​can be set according to the actual situation. This application does not limit the specific values ​​of the second preset number of times and the second preset time.

[0149] By detecting the operating status of the voltage regulator and actively switching it in case of a fault, the voltage sampling path can be switched from the branch where the voltage regulator is located to the branch where the alternative attenuation circuit is located. This allows the first differential voltage across the shunt to be attenuated by a fixed ratio by the alternative attenuation circuit before being sent to the voltage acquisition chip. In this way, the basic operation of the current sampling function can be maintained even if the voltage regulator fails, avoiding the interruption of the entire sampling link due to a single attenuation path failure.

[0150] In some embodiments, closed-loop regulation can be performed once every third preset time interval to track changes in common-mode voltage in real time. When a command is received via the CAN bus indicating that all operating conditions requiring common-mode suppression must be exited, and the common-mode voltage is below a preset safety threshold for a third consecutive preset number of times, the closed-loop regulation mode is exited, and the digital potentiometer maintains its current resistance value or is restored to its default value. The second preset time can be 50 milliseconds, 60 milliseconds, 80 milliseconds, 100 microseconds, or 120 milliseconds, and the third preset number of times can be 2, 3, 4, 5, or 6. The specific values ​​can be set according to the actual situation. This application does not limit the specific values ​​of the third preset time and the third preset number of times.

[0151] In some embodiments, to address the differences in electromagnetic interference characteristics under different operating conditions such as DC fast charging, AC slow charging, and pulse heating, a differentiated adjustment parameter library is pre-stored in the BMS non-volatile memory. The BMS main control unit parses the current operating condition via the CAN bus and automatically loads the corresponding target common-mode voltage, adjustment step size, adjustment dead zone, and other parameters to achieve adaptive scheduling. Thus, the BMS main control unit obtains the current operating condition type via the CAN bus and loads the corresponding target common-mode voltage, adjustment step size, sliding filter window length, and PGA compensation enable flag from the pre-stored operating condition parameter mapping table to achieve attenuation of the first differential voltage.

[0152] For example, as shown in Table 1, it illustrates a mapping table of operating parameters pre-stored in the non-volatile memory of the BMS main control unit.

[0153] Table 1

[0154] Specifically, for DC fast charging, the target common-mode voltage is 250mV, the adjustment step size is 5Ω, and the sliding filter window has 20 points. For AC slow charging, the target common-mode voltage is 300mV, the adjustment step size is 12Ω, and the sliding filter window has 10 points. For pulse heating, the target common-mode voltage is 300mV, the adjustment step size is 20Ω, and the sliding filter window has 5 points.

[0155] In some embodiments, the operating device of the voltage sampling circuit includes a common-mode monitoring submodule, a voltage divider submodule, an adjustable resistor component submodule, a closed-loop regulation submodule, and a full-temperature-range zero-drift calibration submodule.

[0156] The system comprises several modules: a common-mode monitoring submodule for acquiring the first differential voltage, a voltage divider submodule for acquiring the second differential voltage, and an adjustable resistor component submodule for adjusting the voltage division ratio to attenuate the first differential voltage. A closed-loop regulation submodule controls the second differential voltage within a preset voltage range, such as greater than or equal to 280mV and less than or equal to 300mV. A full-temperature-range zero-drift calibration submodule determines the mapping table between temperature and current correction coefficients and corrects the current calculation structure based on this one-dimensional mapping table to offset the effects of temperature drift and aging. This mapping table between temperature and current correction coefficients can be calibrated at the factory within a full temperature range from -40℃ to 85℃.

[0157] The following describes this application with specific examples. Before executing S101, after the vehicle is powered on, the factory calibration parameters stored in the Flash memory are read. The resistance value of the adjustable resistor component is initialized to the default resistance value, the PGA gain is initialized to the default value, the first switch K1 and the second switch are closed, and the third and fourth switches are open, with the main signal path connected by default. Subsequently, the current operating condition is identified through the CAN bus. When a common-mode suppression condition (including DC fast charging, AC slow charging, and pulse heating) is detected, the closed-loop regulation mode is activated, and the corresponding target common-mode voltage, adjustment step size, adjustment dead zone, filter parameters, and PGA compensation enable flag are loaded from the pre-stored operating condition parameter mapping table; then S101-S103 are executed. Subsequently, during the execution of S101-S103, the BMS main control unit periodically parses the operating condition messages on the CAN bus. When a change in the operating condition status word is detected, the complete set of regulation parameters for the corresponding operating condition is loaded from the NVM and written into the runtime parameter area of ​​the closed-loop regulation module. When switching operating conditions, the digital potentiometer does not jump immediately, but under the control of the new parameters, it gradually approaches the new target resistance value from the current resistance value with a new step size, thus achieving a smooth start-up transition.

[0158] As exemplified, Table 2 shows the results of a real-vehicle comparison test between the conventional technical solution and the technical solution of this application.

[0159]

[0160] Table 2 In the test item of common-mode voltage range after voltage division, the conventional technical solution has a range of 280mV to 395mV, meaning that the common-mode voltage range after voltage division of the conventional technical solution is close to the rated upper limit. In contrast, the common-mode voltage range after voltage division of the technical solution in this application is 285mV to 315mV, demonstrating that the technical solution of this application can achieve stable control. For the actual vehicle comparison test results of other test items in Table 1 between the conventional technical solution and the technical solution of this application, please refer to the introduction on the common-mode voltage range after voltage division; this application will not elaborate further here.

[0161] The foregoing mainly describes the solutions provided by the embodiments of this application from a methodological perspective. To achieve the above functions, the voltage regulation device includes corresponding hardware structures and / or software modules for performing each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0162] This application embodiment can divide the voltage regulation device into functional modules according to the above method. For example, the voltage regulation device may include functional modules corresponding to each functional division, or two or more functions may be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. The module division in this application embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0163] Reference Figure 11 The operating device of the voltage sampling circuit includes: a first differential voltage acquisition module 1101, a voltage control module 1102, and a second differential voltage acquisition module 1103.

[0164] The first differential voltage acquisition module 1101 is used to acquire the first differential voltage generated at both ends of the shunt.

[0165] The voltage control module 1102 is used to control the attenuation degree of the first differential voltage by the voltage regulating device based on the first differential voltage.

[0166] The second differential voltage acquisition module 1103 is used to acquire the second differential voltage output by the voltage regulation device after attenuating the first differential voltage. The second differential voltage is used to determine the current flowing through the battery cell group under test.

[0167] In some embodiments, the voltage regulation device further includes: a target voltage ratio determination module. The target voltage ratio determination module is configured to determine a target voltage ratio based on a first differential voltage and a target common-mode voltage. The target voltage ratio is the ratio between the first differential voltage and the target common-mode voltage. A voltage control module is configured to control the degree of attenuation of the first differential voltage by the voltage regulation device based on the target voltage ratio.

[0168] In some embodiments, the voltage regulation device further includes: an actual voltage division ratio determination module, a target gain value determination module, and a chip gain adjustment module. After acquiring the second differential voltage output by the voltage regulation device after attenuating the first differential voltage, the actual voltage division ratio determination module is used to determine the actual voltage division ratio based on the first differential voltage and the updated first differential voltage. The target gain value determination module is used to determine the target gain value based on the actual voltage division ratio. The chip gain adjustment module is used to adjust the chip gain of the voltage acquisition chip based on the target gain value to determine the adjusted second differential voltage.

[0169] In some embodiments, the voltage regulating device further includes a switch control module. The switch control module is configured to issue a switch control command in the event of a fault in the voltage regulating device. The switch control command is used to control a first target switch to open and a second target switch to open.

[0170] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0171] In an exemplary embodiment, this application also provides a computing device, which may include a processor and a memory. The processor may be a computing cluster composed of multiple computing nodes, and the memory may adopt a distributed memory architecture. The processor integrated into the computing device is configured to execute the operation method of the voltage sampling circuit of any of the above embodiments.

[0172] Figure 12 A schematic diagram of the operating device for another voltage sampling circuit provided in an embodiment of this application. (See attached diagram.) Figure 12 As shown, the operating device of the voltage sampling circuit includes: one or more memories 1220, one or more processors 1210, a communication bus 1240, and a communication interface 1230. The processors 1210 and memories 1220 are connected via the communication bus 1240; the one or more memories 1220 are used to store computer program code, which includes computer instructions; when the one or more processors 1210 execute the computer instructions, the computing device performs the operating method of the voltage sampling circuit provided in this embodiment.

[0173] Optionally, the memory 1220 may be a non-transitory computer-readable storage medium, such as a read-only memory (ROM), random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc. This application embodiment does not impose any restrictions on this.

[0174] The processor 1210 may be a central processing unit (CPU), a network processor (NP), a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic device (PLD), or any combination thereof, and the embodiments of this application do not impose any limitations on this.

[0175] The communication bus 1240 can be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, or an extended industry standard architecture (EISA) bus, etc. This communication bus 1240 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 12 It is represented by a single thick line, but this does not mean that there is only one bus or one type of communication bus.

[0176] Communication interface 1230 uses any transceiver-like device for communicating with other devices or communication networks, such as control systems, radio access networks (RAN), wireless local area networks (WLAN), etc.

[0177] This application also provides a computer-readable storage medium. All or part of the processes in the above method embodiments can be executed by computer instructions instructing related hardware; exemplarily, the related hardware can be a processor of a computing device. The program instructions can be stored in the above-described computer-readable storage medium, and when executed, the processes of the above method embodiments can be implemented. The computer-readable storage medium can be memory. The above-described computer-readable storage medium can also be an external storage device, such as a hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc. Further, the above-described computer-readable storage medium can include both memory and external storage devices. The above-described computer-readable storage medium is used to store the above-described computer program instructions and other programs and data required for the operation method of the above-described voltage sampling circuit.

[0178] This application also provides a vehicle that can perform the methods described in the above embodiments via a voltage regulating device.

[0179] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0180] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely illustrative descriptions of the application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

[0181] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A voltage sampling circuit, characterized in that, The voltage sampling circuit includes: a shunt (10), a voltage acquisition chip (20), and a voltage regulation device (30); The shunt (10) is used to connect in series with the battery cell assembly (100) under test; The voltage acquisition chip (20) is connected to the first end of the shunt (10) through the first sampling pin (20a) and to the second end of the shunt (10) through the second sampling pin (20b); The voltage regulating device (30) is connected between the first end of the shunt (10) and the first sampling pin (20a) of the voltage acquisition chip (20); and / or; is connected between the second end of the shunt (10) and the second sampling pin (20b) of the voltage acquisition chip (20); The voltage regulating device (30) is used to receive the first differential voltage generated at both ends of the shunt (10), attenuate the first differential voltage, and output a second differential voltage; the degree of attenuation of the first differential voltage by the voltage regulating device (30) is related to the voltage value of the first differential voltage; The voltage acquisition chip (20) is used to acquire the second differential voltage, which is used to determine the current flowing through the battery cell group (100) under test.

2. The voltage sampling circuit according to claim 1, characterized in that, The voltage regulating device (30) includes: a first series resistor voltage divider circuit (1) and a second series resistor voltage divider circuit (2); The first end of the first series resistor voltage divider circuit (1) is connected to the first end of the shunt (10), the second end of the first series resistor voltage divider circuit (1) is grounded, and the voltage divider node of the first series resistor voltage divider circuit (1) is connected to the first sampling pin (20a) of the voltage acquisition chip (20). The first end of the second series resistor voltage divider circuit (2) is connected to the second end of the shunt (10), the second end of the second series resistor voltage divider circuit (2) is grounded, and the voltage divider node of the second series resistor voltage divider circuit (2) is connected to the second sampling pin (20b) of the voltage acquisition chip (20). The first series resistor voltage divider circuit (1) includes a first adjustable potentiometer circuit (3), which is configured to adjust the voltage division ratio of the first series resistor voltage divider circuit (1) according to the first differential voltage. The second series resistor voltage divider circuit (2) includes a second adjustable potentiometer circuit (4), which is configured to adjust the voltage division ratio of the second series resistor voltage divider circuit (2) according to the first differential voltage.

3. The voltage sampling circuit according to claim 1 or 2, characterized in that, The voltage sampling circuit further includes: a common-mode acquisition circuit (60); The first end of the common-mode acquisition circuit (60) is connected to the first end of the shunt (10) and the third sampling pin (20c) of the voltage acquisition chip (20), and the second end of the common-mode acquisition circuit (60) is connected to the second end of the shunt (10) and the fourth sampling pin (20d) of the voltage acquisition chip (20). The common-mode acquisition circuit (60) is used to filter the common-mode noise at both ends of the shunt (10); The voltage acquisition chip (20) is also used to acquire the first differential voltage, which is the voltage across the shunt (10) after being attenuated by the common-mode acquisition circuit (60).

4. The voltage sampling circuit according to claim 3, characterized in that, The adjustable potentiometer circuit includes: an adjustable resistor assembly and a voltage control assembly (5); the voltage control assembly (5) is connected to the voltage acquisition chip (20) and the adjustable resistor assembly respectively, and the voltage control assembly (5) is configured as follows: Receive the first differential voltage; The resistance value of the adjustable resistor component is adjusted based on the first differential voltage.

5. The voltage sampling circuit according to claim 1, characterized in that, The voltage sampling circuit further includes: a candidate attenuation circuit (50), a first switch (K1), a second switch (K2), a third switch (K3), and a fourth switch (K4); The candidate attenuation circuit (50) is connected between the shunt (10) and the voltage acquisition chip (20), and is connected in parallel with the voltage regulation device (30); the first switch (K1) is connected between the voltage regulation device (30) and the first sampling pin (20a) of the voltage acquisition chip (20), the second switch (K2) is connected between the voltage regulation device (30) and the second sampling pin (20b) of the voltage acquisition chip (20); the third switch (K3) is connected between the candidate attenuation circuit (50) and the first sampling pin (20a) of the voltage acquisition chip (20), and the fourth switch (K4) is connected between the candidate attenuation circuit (50) and the second sampling pin (20b) of the voltage acquisition chip (20).

6. The voltage sampling circuit according to claim 5, characterized in that, When the voltage regulator (30) is not malfunctioning, the first switch (K1) and the second switch (K2) are configured to be on, and the third switch (K3) and the fourth switch (K4) are configured to be off; when the voltage regulator (30) is malfunctioning, the first switch (K1) and the second switch (K2) are configured to be off, and the third switch (K3) and the fourth switch (K4) are configured to be on.

7. An operation method for a voltage sampling circuit, characterized in that, Applied to the voltage sampling circuit as described in any one of claims 1-3; the operation method includes: Obtain the first differential voltage generated across the shunt; The voltage regulation device controls the attenuation degree of the first differential voltage based on the first differential voltage; The voltage regulator attenuates the first differential voltage to output a second differential voltage, which is used to determine the current flowing through the battery cell assembly under test.

8. The operation method of the voltage sampling circuit according to claim 7, characterized in that, The method of controlling the attenuation degree of the first differential voltage by the voltage regulation device based on the first differential voltage includes: Based on the first differential voltage and the target common-mode voltage, a target voltage ratio is determined; the target voltage ratio is the ratio between the first differential voltage and the target common-mode voltage. Based on the target voltage ratio, the attenuation degree of the first differential voltage by the voltage regulation device is controlled.

9. The operation method of the voltage sampling circuit according to claim 7, characterized in that, After acquiring the second differential voltage output by the voltage regulation device after attenuating the first differential voltage, the operation method of the voltage sampling circuit further includes: Based on the first differential voltage and the updated first differential voltage, the actual voltage division ratio is determined; Based on the actual voltage division ratio, determine the target gain value; Based on the target gain value, the chip gain of the voltage acquisition chip is adjusted to determine the adjusted second differential voltage.

10. The operation method of the voltage sampling circuit according to claim 7, characterized in that, The operation method of the voltage sampling circuit also includes: In the event of a malfunction in the voltage regulation device, a switch control command is issued to control the first target switch to open and the second target switch to open.

11. A battery pack, characterized in that, include: Power battery The voltage sampling circuit as described in any one of claims 1-6 is coupled to the power battery.

12. A vehicle, characterized in that, The vehicle includes a voltage sampling circuit as described in any one of claims 1-6.

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