Gate driver, display panel and display device

Abstract

The application discloses a gate driver, a display panel and a display device. In the gate drive circuit, a node control sub-circuit controls the signal of a first node according to the signal received by a signal input end of a current stage gate drive circuit and a corresponding clock signal, and an output sub-circuit controls the signal transmission between a signal output end of the current stage gate drive circuit and a first power supply end according to the signal of the first node. A stage transmission circuit is arranged between the first node of an Nth stage gate drive circuit and a signal input end of an N+Ath stage gate drive circuit, and the stage transmission circuit controls the signal received by the corresponding signal input end according to the signal of the corresponding first node, so that the signal received by the signal input end of the subsequent stage gate drive circuit is controlled by the signal change of the first node of the previous stage gate drive circuit, the corresponding load of the signal output end of the gate drive circuit is reduced, and the influence of the level change delay of the gate control signal on the working stability of the gate driver is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a gate driver, display panel, and display device. Background Technology

[0002] In gate drive circuits, to enable the output signal to drive a larger load, the channel width and capacitance of some transistors are increased. However, this increases the layout space occupied by the gate drive circuit. If the channel width and capacitance of some transistors are not increased, the output signal of the gate drive circuit will lack sufficient driving capability, easily leading to malfunctions. Summary of the Invention

[0003] This application provides a gate driver, a display panel, and a display device for reducing the load corresponding to the signal output terminal of the gate driving circuit and reducing the impact of the level change delay of the gate control signal output by the gate driving circuit on the working stability of the gate driver.

[0004] This application provides a gate driver, including multiple gate driving circuits and multiple stage transmission circuits. Each gate driving circuit includes a node control sub-circuit and an output sub-circuit. The node control sub-circuit is electrically connected to the signal input terminal of its own gate driving circuit and a first node. The node control sub-circuit is configured to control the signal of the first node according to the signal received at the signal input terminal and the corresponding clock signal. The output sub-circuit is electrically connected to the first node. The output sub-circuit is configured to control the signal transmission between the signal output terminal of its own gate driving circuit and a first power supply terminal according to the signal of the first node. A stage transmission circuit is provided between the first node of the Nth stage gate driving circuit and the signal input terminal of the (N+A)th stage gate driving circuit. Each stage transmission circuit is configured to control the signal received at the corresponding signal input terminal according to the signal of the corresponding first node, where N≥1 and A≥1.

[0005] This application also provides a display panel including a plurality of sub-pixels and any of the aforementioned gate drivers. The signal output terminal of each gate driver circuit is electrically connected to the plurality of sub-pixels, and each gate driver circuit is configured to provide a corresponding gate control signal to the corresponding sub-pixel.

[0006] This application also provides a display device, including any of the above-described display panels and a timing controller. The timing controller is electrically connected to a gate driver and is configured to transmit a frame start signal to the signal input terminal of the first-stage gate driver circuit among a plurality of gate driver circuits, and to output a corresponding clock signal to the plurality of gate driver circuits.

[0007] In the above technical solution, by including multiple gate driving circuits and multiple cascading circuits in the gate driver, the node control sub-circuit in each gate driving circuit controls the signal of the first node according to the signal received at the signal input terminal of the gate driving circuit of that stage and the corresponding clock signal. This allows the output sub-circuit in the gate driving circuit to control the signal transmission between the signal output terminal and the first power supply terminal of the gate driving circuit of that stage according to the signal of the first node. By setting a cascading circuit between the first node of the Nth stage gate driving circuit and the signal input terminals of the N+Ath stage gate driving circuits, and by having each cascading circuit control the signal received at its corresponding signal input terminal according to the signal of the corresponding first node, the signal received at the signal input terminal of the subsequent stage gate driving circuit is controlled by the change in the signal of the first node in the preceding stage gate driving circuit, thereby achieving output control of the subsequent stage gate driving circuit and realizing the cascading of multiple gate driving circuits. Using cascading circuits to achieve the cascading of multiple gate driving circuits reduces the load corresponding to the signal output terminal of the gate driving circuit and helps to reduce the impact of the level change delay of the gate control signal output from the signal output terminal of the gate driving circuit on the working stability of the gate driver. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0009] Figures 1A-1B This is a schematic diagram of the gate driver according to an exemplary embodiment of this application; Figures 2A-2E This is a schematic block diagram illustrating the connection between the gate drive circuit and the stage transmission circuit in an exemplary embodiment of this application. Figures 3A-3D This is a circuit diagram showing the connection between the gate drive circuit and the stage transmission circuit in an exemplary embodiment of this application. Figures 4A-4B This is a timing diagram corresponding to the gate drive circuit and the stage transmission circuit in an exemplary embodiment of this application; Figures 5A-5B This is a timing diagram corresponding to the gate driver in an exemplary embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of a display panel according to an exemplary embodiment of this disclosure; Figure 7 This is a schematic diagram of the structure of a display device according to an exemplary embodiment of the present disclosure.

[0010] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0011] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0012] It should be noted that the electrical connection referred to in this application can refer to a direct connection or an indirect connection. An indirect connection can be a connection between connected sub-circuits, devices, or nodes achieved through electrical components, wired or wireless media, etc. An electrical connection can refer to a physically existing connection or a connection established through signals. The descriptions of "first," "second," etc., involved in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" or "second" can explicitly or implicitly include at least one of those features. Furthermore, the various technical features in this application can be applied to achieve different combinations, and are not limited to the technical solutions formed by the combinations listed in the embodiments. The technical solutions between various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application. The terms "optionally" and "in some embodiments" used in this application indicate that the technical content they refer to can be selectively configured.

[0013] Furthermore, the descriptions provided in the Background section should not be presumed to be prior art simply because they are mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter, and the description in this section does not limit the invention.

[0014] Figures 1A-1B This is a schematic diagram of the gate driver according to an exemplary embodiment of this application. Figures 2A-2EThis is a schematic block diagram illustrating the connection between the gate drive circuit and the cascade circuit in an exemplary embodiment of this application. This application provides a gate driver GDC, including multiple gate drive circuits GA and multiple cascade circuits STA. Each gate drive circuit GA is configured to output a gate control signal Scan. The multiple cascade circuits STA are electrically connected to the multiple gate drive circuits GA, and the multiple cascade circuits STA are configured to implement a cascaded arrangement between the multiple gate drive circuits GA.

[0015] Optionally, each gate drive circuit GA may include a node control sub-circuit 10 and an output sub-circuit 20. The node control sub-circuit 10 is electrically connected to the signal input terminal GI of the gate drive circuit and the first node No1. The node control sub-circuit 10 is configured to control the signal of the first node No1 according to the signal received at the signal input terminal GI and the corresponding clock signal CK. The output sub-circuit 20 is electrically connected to the first node No1. The output sub-circuit 20 is configured to control the signal transmission between the signal output terminal GT of the gate drive circuit and the first power supply terminal VA according to the signal of the first node No1, so as to realize the control of the gate control signal Scan output by the gate drive circuit GA.

[0016] To achieve cascading of gate drive circuits (GAs), a transfer circuit (STA) can be set between two gate drive circuits (GAs). For example, a transfer circuit (STA) can be set between the first node No1 of the Nth stage gate drive circuit (GA(N)) and the signal input terminal GI(N+A) of the N+A stage gate drive circuit (GA(N+A)). At least one transfer circuit (STA) is configured to control the signal received at the corresponding signal input terminal GI according to the signal of the corresponding first node No1. This ensures that the signal received at the signal input terminal GI of the subsequent gate drive circuit (GA) is controlled by the change in the signal of the first node No1 in the preceding gate drive circuit (GA), thereby controlling the output of the subsequent gate drive circuit (GA). This achieves cascading between one gate drive circuit (GA) and another, reducing the load on the signal output terminal GT of the gate drive circuit (GA). Furthermore, since the gate control signal Scan output by the gate drive circuit (GA) is no longer used to achieve cascading between gate drive circuits (GAs), the level change delay of the gate control signal Scan output by the signal output terminal GT of the gate drive circuit (GA) will not accumulate due to cascading, thus preventing the gate driver (GDC) from malfunctioning. Therefore, the impact of the level change delay of the gate control signal Scan on the operating stability of the gate driver GDC is reduced.

[0017] It should be noted that N≥1 and A≥1, where N and A are both positive integers. At least one stage of the transmission circuit STA controls the signal received by the corresponding signal input terminal GI according to the signal of the corresponding first node No1, that is, the transmission circuit STA of this stage can control the potential of the corresponding signal input terminal GI according to the signal of the corresponding first node No1. The gate control signal Scan can be the first stage gate control signal Scan(1) output by the first stage gate drive circuit GA(1), the second stage gate control signal Scan(2) output by the second stage gate drive circuit GA(2), the third stage gate control signal Scan(3) output by the third stage gate drive circuit GA(3), or the signal output from the signal output terminal GT of the gate drive circuit GA of other stages. The "signal level change delay" in this application can refer to the longer transition time corresponding to the signal jumping from the first level to the second level, that is, the signal level change delay is manifested as the signal completing the level switch in a longer time. Among them, the first level is one of the high level and the low level, and the second level is the other of the high level and the low level. For the Nth stage gate drive circuit GA(N), the gate drive circuit of this stage is the Nth stage gate drive circuit GA(N) itself.

[0018] In some embodiments, the first power supply terminal VA can be a voltage terminal, and the first power supply terminal VA is configured to supply a first power signal.

[0019] Optionally, the Nth stage transmission circuit STA(N) of the multiple stage transmission circuits STA is connected between the first node No1 of the Nth stage gate drive circuit GA(N) and the signal input terminal GI(N+A) of the (N+A)th stage gate drive circuit GA(N+A), so that the multiple gate drive circuits GA are electrically connected through the multiple stage transmission circuits STA. The signal input terminal GI of the first A stage gate drive circuits in the multiple gate drive circuits can be configured to receive the corresponding start signal STV.

[0020] For example, let's take A equal to 1 as an example. Figure 1A As shown, the signal input terminal of the first-stage gate drive circuit GA(1) in multiple gate drive circuits GA can be configured to receive the start signal STV. A first stage transmission circuit STA(1) is provided between the first node No1 of the first-stage gate drive circuit GA(1) and the signal input terminal of the second-stage gate drive circuit GA(2). A second stage transmission circuit STA(2) is provided between the first node No1 of the second-stage gate drive circuit GA(2) and the signal input terminal of the third-stage gate drive circuit GA(3), and so on, to obtain the connection design of multiple stage transmission circuits STA and multiple gate drive circuits GA.

[0021] Optionally, the (N+1)th stage transmission circuit STA (N+1) of the plurality of stage transmission circuits STA is connected between the first node No1 of the Nth stage gate drive circuit GA (N) and the signal input terminal of the (N+A)th stage gate drive circuit GA (N+A), so that the plurality of gate drive circuits GA are electrically connected through the plurality of stage transmission circuits STA. The first A stage transmission circuits STA of the plurality of stage transmission circuits STA can be configured to receive the corresponding start signal STV.

[0022] For example, let's take A equal to 1 as an example. Figure 1B As shown, the first stage transmission circuit STA (1) of the multiple stage transmission circuits STA is connected to the start signal line of the transmission start signal STV and is electrically connected to the signal input terminal of the first stage gate drive circuit GA (1). A second stage transmission circuit STA (2) is provided between the first node No1 of the first stage gate drive circuit GA (1) and the signal input terminal of the second stage gate drive circuit GA (2), and a third stage transmission circuit STA (3) is provided between the first node No1 of the second stage gate drive circuit GA (2) and the signal input terminal of the third stage gate drive circuit GA (3), and so on, to obtain the connection design of multiple stage transmission circuits STA and multiple gate drive circuits GA.

[0023] It should be understood that, in practical applications, A is not limited to being equal to 1. In some embodiments, A can be equal to 1 or 2, etc.

[0024] Optionally, each stage of the transmission circuit STA is configured to control the signal received at the corresponding signal input terminal GI to be out of phase with the signal of the corresponding first node No1, so that when the gate control signal Scan output by the preceding gate drive circuit changes, the signal of the first node No1 of the subsequent gate drive circuit can also respond to the change of the first node No1 in the preceding gate drive circuit, causing the gate control signal Scan output by the subsequent gate drive circuit to change subsequently.

[0025] In some embodiments, the (N+1)th cascade circuit STA (N+1) is connected between the first node No1 of the Nth-stage gate drive circuit GA (N) and the signal input terminal GI (N+A) of the (N+A)th-stage gate drive circuit GA (N+A). The signal of the first node No1 of the Nth-stage gate drive circuit GA (N) is out of phase with the signal received at the signal input terminal GI (N+A) of the (N+A)th-stage gate drive circuit GA (N+A). When the signal of the first node No1 of the Nth-stage gate drive circuit GA (N) changes, the operating state of the output sub-circuit 20 of the Nth-stage gate drive circuit GA (N) changes accordingly, causing the Nth-stage gate control signal Scan (N) output by the Nth-stage gate drive circuit GA (N) to change. Furthermore, the signal change at the first node No1 of the Nth stage gate driver circuit GA(N) causes a synchronous change in the signal received at the signal input terminal of the (N+A)th stage gate driver circuit GA(N+A). This results in a subsequent change in the signal at the corresponding signal input terminal GI(N+A) and the corresponding clock signal CK, thereby causing a change in the N+Ath stage gate control signal Scan(N+A) output by the (N+A)th stage gate driver circuit GA(N+A). It should be noted that, relative to the Nth stage gate driver circuit GA(N), the (N+A)th stage gate driver circuit GA(N+A) corresponds to the subsequent gate driver circuit, while the Nth stage gate driver circuit GA(N) corresponds to the preceding gate driver circuit.

[0026] Optionally, to achieve potential control of the corresponding signal input terminal GI, at least one stage of the transmission circuit STA may include a first switching sub-circuit 301 and a second switching sub-circuit 302, such as... Figures 2A-2E As shown. The first switch sub-circuit 301 is electrically connected to the corresponding signal input terminal GI and the corresponding first node No1. The first switch sub-circuit 301 is configured to control the signal transmission between the second power supply terminal VB and the corresponding signal input terminal GI according to the signal from the corresponding first node No1. The second switch sub-circuit 302 is electrically connected to the corresponding signal input terminal GI and the corresponding first node No1. The second switch sub-circuit 302 is configured to control the signal transmission between the third power supply terminal VC and the corresponding signal input terminal GI according to the signal from the corresponding first node No1. Each stage transmission circuit STA is configured to control the corresponding signal input terminal GI to form a current path with the second power supply terminal VB and the third power supply terminal VC in a time-division manner according to the signal from the corresponding first node No1, thereby controlling the corresponding signal input terminal GI to receive the second power signal supplied by the second power supply terminal VB or the third power signal supplied by the third power supply terminal.

[0027] like Figure 2ATaking the Nth-stage gate drive circuit GA(N) as an example, in the cascade circuit STA electrically connected to the Nth-stage gate drive circuit GA(N), the first switch sub-circuit 301 and the second switch sub-circuit 302 are both electrically connected to the first node No1 of the Nth-stage gate drive circuit GA(N), and both the first switch sub-circuit 301 and the second switch sub-circuit 302 of this cascade circuit are electrically connected to the signal input terminal GI(N+A) of the N+A-stage gate drive circuit GA(N+A). The first switch sub-circuit 301 in this cascade circuit controls the second power supply terminal VB to switch with the Nth-stage gate drive circuit GA(N) according to the signal from the first node No1 of the Nth-stage gate drive circuit GA(N). The signal transmission between the signal input terminal GI(N+A) of the N+A level gate drive circuit GA(N+A) is controlled by the second switch sub-circuit 302 in the transmission circuit according to the signal of the first node No1 of the N-level gate drive circuit GA(N). This allows the transmission circuit to control the signal input terminal GI(N+A) of the N+A level gate drive circuit GA(N+A) to form a current path between the second power supply terminal VB and the third power supply terminal VC in a time-division manner according to the signal of the first node No1 of the N-level gate drive circuit GA(N).

[0028] Optionally, the second power supply terminal VB and the third power supply terminal VC can be voltage terminals, and the voltage of the second power supply signal supplied by the second power supply terminal VB can be greater than or less than the voltage of the third power supply signal supplied by the third power supply terminal VC.

[0029] Optionally, to control the signal of the first node No1, the node control sub-circuit 10 in the gate drive circuit GA may include a first control sub-circuit 101 and a second control sub-circuit 102, such as... Figures 2C-2E As shown. The first control sub-circuit 101 is electrically connected between the signal input terminal GI of the gate drive circuit GA and the second node No2. The first control sub-circuit 101 is configured to control the signal transmission between the signal input terminal GI and the second node No2 according to the corresponding clock signal CK. The second control sub-circuit 102 is electrically connected between the first node No1 and the second node No2 of the gate drive circuit GA. The second control sub-circuit 102 is configured to control the first node No1 to form a time-division current path with the first power supply terminal VA and the fourth power supply terminal VD according to the signal of the second node No2, so that the signal of the first node No1 receives the first power supply signal and the fourth power supply signal supplied by the fourth power supply terminal VD in a time-division manner, thereby realizing the control of the signal of the first node No1.

[0030] In some embodiments, the fourth power supply terminal VD can be a voltage terminal, and the voltage of the fourth power signal supplied by the fourth power supply terminal VD can be greater than or less than the voltage of the first power signal supplied by the first power supply terminal VA.

[0031] In some embodiments, the second control sub-circuit 102 may include a first sub-unit and a second sub-unit. The first sub-unit is configured to control the signal transmission between the first node No1 and the first power supply terminal VA according to the signal of the second node No2. The second sub-unit is configured to control the signal transmission between the first node No1 and the fourth power supply terminal VD according to the signal of the second node No2, so as to realize independent control of the signal transmission between the first node No1 and the first power supply terminal VA and the fourth power supply terminal VD.

[0032] In some embodiments, the time period during which the first subunit controls the formation of a current path between the first power supply terminal VA and the first node No1 does not overlap with the time period during which the second subunit controls the formation of a current path between the fourth power supply terminal VD and the first node No1, so that the first node No1 forms a current path between the first power supply terminal VA and the fourth power supply terminal VD in a time-division manner.

[0033] Optionally, in order to enable the gate control signal Scan output by the gate drive circuit GA to have a level change, the output sub-circuit 20 is electrically connected to the node control module at the second node No2 of the gate drive circuit GA. The output sub-circuit 20 can also be configured to control the signal transmission between the fourth power supply terminal VD and the signal output terminal GT according to the signal of the second node No2, so that the output terminal of the gate drive circuit GA can receive the first power supply signal or the fourth power supply signal, thereby realizing the level change control of the gate control signal Scan.

[0034] In some embodiments, the signal of the second node No2 of each gate drive circuit GA is in phase with the signal received by the signal input terminal GI of the stage transmission circuit 30 electrically connected to the first node No1 of the same stage gate drive circuit. This is so that when the gate control signal Scan output by the previous stage gate drive circuit changes according to the signal of the second node No2, the signal received by the signal input terminal GI of the subsequent stage gate drive circuit changes synchronously. As a result, the gate control signal Scan output by the subsequent stage gate drive circuit also changes under the action of the corresponding clock signal CK and the signal received by the signal input terminal GI.

[0035] Taking a transmission circuit 30 between the Nth-stage gate drive circuit GA(N) and the (N+A)th-stage gate drive circuit GA(N+A) as an example, the signal received by the signal input terminal GI(N+A) of the (N+A)th-stage gate drive circuit GA(N) is in phase with the signal of the second node No2 of the Nth-stage gate drive circuit GA(N). That is, when the signal of the second node No2 of the Nth-stage gate drive circuit GA(N) changes, the operating state of the output sub-circuit 20 of the Nth-stage gate drive circuit GA(N) changes accordingly, causing the Nth-stage gate control signal Scan(N) output by the Nth-stage gate drive circuit GA(N) to change. The signal change at the second node No2 of the Nth stage gate drive circuit GA(N) causes the signal received at the signal input terminal GI(N+A) of the N+A stage gate drive circuit GA(N+A) to change synchronously. This causes the signal at the first node No1 of the N+A stage gate drive circuit GA(N+A) to subsequently change under the influence of the signal received at the corresponding signal input terminal GI(N+A) and the corresponding clock signal CK. Consequently, the N+A stage gate control signal Scan(N+A) output by the N+A stage gate drive circuit GA(N+A) then changes.

[0036] Furthermore, the signal received by the corresponding signal input terminal GI of each stage transmission circuit STA is out of phase with the signal of the corresponding first node No1, and the signal of the second node No2 of each gate drive circuit GA is in phase with the signal received by the signal input terminal GI of the stage transmission circuit 30 electrically connected to the first node No1 of the same stage gate drive circuit. This can make the signal of the first node No1 in the same gate drive circuit GA out of phase with the signal of the second node No2, thereby reducing the probability that the signal output terminal GT of the current stage gate drive circuit receives the first power supply signal and the fourth power supply signal at the same time, which is beneficial to improving the working reliability of the gate drive circuit GA.

[0037] In some embodiments, to achieve independent control of signal transmission between the signal output terminal GT and the first power supply terminal VA and the fourth power supply terminal VD, the output sub-circuit 20 includes a first output sub-circuit 201 and a second output sub-circuit 202, such as... Figures 2A-2E As shown. The first output sub-circuit 201 is electrically connected to the first node No1 of the gate driver sub-circuit of this stage, and is also electrically connected to the signal output terminal GT. The first output sub-circuit 201 is configured to control the signal transmission between the first power supply terminal VA and the signal output terminal GT according to the signal from the first node No1. The second output sub-circuit 202 is electrically connected to the second node No2 of the gate driver sub-circuit of this stage, and is also electrically connected to the signal output terminal GT. The second output sub-circuit 202 is configured to control the signal transmission between the fourth power supply terminal VD and the signal output terminal GT according to the signal from the second node No2.

[0038] In some embodiments, the second control sub-circuit 102 is configured to control the signal of the first node No1 to be out of phase with the signal of the second node No2 according to the signal of the second node No2, so that the output sub-circuit 20 controls the signal output terminal GT to form a current path between the first power supply terminal VA and the fourth power supply terminal VD according to the signal of the first node No1 and the signal of the second node No2.

[0039] Optionally, during the period when the first sub-unit controls the formation of a current path between the first power supply terminal VA and the first node No1, the first output sub-circuit 201 disconnects the current path between the first power supply terminal VA and the signal output terminal GT according to the signal from the first node No1. During the period when the second sub-unit controls the formation of a current path between the fourth power supply terminal VD and the first node No1, the first output sub-circuit 201 connects the current path between the first power supply terminal VA and the signal output terminal GT according to the signal from the first node No1.

[0040] Optionally, at least one gate drive circuit GA further includes an isolation sub-circuit 40, such as Figures 2C-2E As shown, the isolation sub-circuit 40 is electrically connected between the second node No2 and the third node No3 of the gate drive circuit of this stage. The isolation sub-circuit 40 is configured to isolate the coupling effect of the potential change of the third node No3 on the potential of the second node No2. The second output sub-circuit 202 is electrically connected to the second node No2 through the third node No3, and the second output sub-circuit 202 controls the signal transmission between the fourth power supply terminal VD and the signal output terminal GT according to the signal from the third node No3.

[0041] In some embodiments, at least one gate drive circuit GA further includes a voltage regulator sub-circuit 50, such as Figure 2D As shown, the voltage regulator circuit 50 is electrically connected to the first node No1 and the second node No2 of the gate drive circuit of this stage. The voltage regulator circuit 50 is configured to connect the current path between the first power supply terminal VA and the first node No1 according to the signal of the first node No1 during the period when the second control circuit 102 connects the current path between the first power supply terminal VA and the first node No1. In order to accelerate the potential change rate of the second node No2 by utilizing the voltage regulator circuit 50, it is beneficial to accelerate the speed at which the second output circuit 202 connects the current path between the signal output terminal GT and the fourth power supply terminal VD when a current path needs to be formed between the signal output terminal GT and the fourth power supply terminal VD, thereby accelerating the potential change rate of the signal output terminal GT.

[0042] In some embodiments, at least one gate drive circuit GA further includes a reset sub-circuit 60, such as Figure 2EAs shown, the reset sub-circuit 60 is electrically connected to the first node No1 of the gate drive circuit GA of this stage. The reset sub-circuit 60 is configured to reset the potential of the first node No1 according to the reset control signal Res, so as to reduce the impact of the residual charge of the corresponding first node No1 on the working stability of the gate drive circuit GA.

[0043] In some embodiments, the gate driver GDC includes a reset control line electrically connected to a plurality of gate drive circuits GA. The reset control line is configured to transmit a reset control signal Res to the plurality of gate drive circuits GA so that the reset sub-circuits 60 of the plurality of gate drive circuits GA can share the same reset control signal, thereby reducing the power consumption of the gate driver GDC.

[0044] Optionally, multiple gate drive circuits GA can share clock signals CK transmitted through multiple clock lines to reduce the power consumption of the gate driver GDC. In some embodiments, the gate driver GDC further includes Z clock lines configured to transmit Z clock signals CK sequentially with the same phase difference. The Y-th clock line among the Z clock lines is electrically connected to the ZK+Y-th stage gate drive circuit GA (ZK+Y), and is configured to transmit the corresponding clock signal CK to the ZK+Y-th stage gate drive circuit GA (ZK+Y); Z ≥ 2, 1 ≤ Y ≤ Z, K ≥ 0.

[0045] like Figures 1A-1B As shown, taking Z=2 as an example, the two clock lines include a first clock line CL1 and a second clock line CL2. The first clock signal CKa transmitted by the first clock line CL1 and the second clock signal CKb transmitted by the second clock line CL2 have a phase difference. The 2K+1 stage gate drive circuit GA(2K+1) is electrically connected to the first clock line CL1, and the 2K+2 stage gate drive circuit GA(2K+2) is electrically connected to the second clock line CL2.

[0046] For example, taking Z=4 as an example, the four clock lines include the first clock line through the fourth clock line. The first clock signal transmitted on the first clock line, the second clock signal transmitted on the second clock line, the third clock signal transmitted on the third clock line, and the fourth clock signal transmitted on the fourth clock line all have the same phase difference. The 4K+1 stage gate driver circuit GA(4K+1) is electrically connected to the first clock line, the 4K+2 stage gate driver circuit GA(4K+2) is electrically connected to the second clock line, the 4K+3 stage gate driver circuit GA(4K+3) is electrically connected to the third clock line, and the 4K+4 stage gate driver circuit GA(4K+4) is electrically connected to the fourth clock line.

[0047] It should be understood that, Figures 1A-1B The clock line and gate drive circuit GA combination design shown is for illustrative purposes only and is not intended to limit this application. Any modifications to the clock line and gate drive circuit GA combination design made by those skilled in the art based on different actual applications are permitted and included in this application.

[0048] Optionally, the stage circuit STA and the gate drive circuit GA may each include at least one type of device such as a transistor and an energy storage element. The energy storage element may include at least one type of device such as a capacitor and an inductor.

[0049] like Figures 3A-3D This is a circuit diagram illustrating the connection between the gate drive circuit and the cascade circuit in an exemplary embodiment of this application. To facilitate understanding of the gate drive circuit GA and the cascade circuit STA of this application, [further details are provided]. Figures 3A-3D The gate drive circuit GA and the stage transmission circuit STA will be explained using an example.

[0050] The first switching sub-circuit 301 of the cascade circuit STA may include a first switching transistor Ts1. The first switching transistor Ts1 includes a control terminal electrically connected to the corresponding first node No1, a first source-drain terminal electrically connected to the second power supply terminal VB, and a second source-drain terminal electrically connected to the corresponding signal input terminal GI. The first switching transistor Ts1 is turned on or off according to the signal of the corresponding first node No1.

[0051] The following explanation uses the stage transmission circuit STA connected to the Nth stage gate drive circuit GA(N) and the N+A stage gate drive circuit GA(N+A) as an example. In the stage transmission circuit STA, which is electrically connected to the Nth stage gate drive circuit GA(N), the control terminal of the first switching transistor Ts1 is electrically connected to the first node No1 of the Nth stage gate drive circuit GA(N), so that the control terminal of the first switching transistor Ts1 receives the signal Nos1(N) from the first node of the Nth stage gate drive circuit GA(N). The second source-drain terminal of the first switching transistor Ts1 is electrically connected to the signal input terminal GI(N+A) of the N+A stage gate drive circuit GA(N+A).

[0052] The second switching sub-circuit 302 of the cascade circuit STA may include a second switching transistor Ts2. The second switching transistor Ts2 includes a control terminal electrically connected to the control terminal of the first switching transistor Ts1, a first source-drain terminal electrically connected to the third power supply terminal VC, and a second source-drain terminal electrically connected to the second source-drain terminal of the first switching transistor Ts1. The second switching transistor Ts2 is turned on or off according to the signal of the corresponding first node No1.

[0053] In some embodiments, to reduce the probability that the signal input terminal GI of the gate drive circuit GA simultaneously receives the second power supply signal and the third power supply signal, the first switching transistor Ts1 can be one of a P-type transistor and an N-type transistor, and the second switching transistor Ts2 can be the other of a P-type transistor and an N-type transistor.

[0054] In some embodiments, to reduce the layout size occupied by the stage circuit STA, at least one of the first switching transistor Ts1 and the second switching transistor Ts2 may be a low-temperature polysilicon transistor.

[0055] In some embodiments, the voltage of the second power signal is greater than the voltage of the first power signal. The first switching transistor Ts1 is a P-type low-temperature polysilicon transistor, and the second switching transistor Ts2 is an N-type oxide transistor. This is so that when the second power signal is applied to the corresponding signal input terminal GI via the first switching transistor Ts1, the voltage difference between the corresponding signal input terminal GI and the second power terminal VB is smaller. Furthermore, when the third power signal is applied to the corresponding signal input terminal GI via the second switching transistor Ts2, the voltage difference between the corresponding signal input terminal GI and the third power terminal VC is smaller, thereby improving power utilization efficiency.

[0056] In some embodiments, the second switching transistor Ts2 may include two control terminals. One control terminal of the second switching transistor Ts2 is electrically connected to the corresponding first node No1, and the other control terminal of the second switching transistor Ts2 is electrically connected to the third power supply terminal VC, so as to improve the operating stability of the second switching transistor Ts2.

[0057] Optionally, the first output sub-circuit 201 of the output sub-circuit 20 may include a first output transistor To1. The first output transistor To1 includes a control terminal electrically connected to the first node No1, a second source-drain terminal electrically connected to the first power supply terminal VA, and a second source-drain terminal electrically connected to the corresponding signal output terminal GT. The first output transistor To1 is turned on or off according to the signal from the first node No1.

[0058] Optionally, the second output sub-circuit 202 of the output sub-circuit 20 may include a second output transistor To2 and a first capacitor C1. The second output transistor To2 includes a control terminal electrically connected to the second node No2, a second source-drain terminal electrically connected to the fourth power supply terminal VD, and a second source-drain terminal electrically connected to the corresponding signal output terminal GT. The second output transistor To2 is turned on or off according to the signal from the second node No2. The first capacitor C1 is electrically connected between the control terminal of the second output transistor To2 and the corresponding signal output terminal GT.

[0059] Optionally, the first output transistor To1 and the second output transistor To2 can be N-type transistors or P-type transistors, respectively, and the first output transistor To1 and the second output transistor To2 can be low-temperature polycrystalline silicon transistors or oxide transistors, respectively.

[0060] Compared to low-temperature polysilicon (LTPS) transistors, oxide transistors (OPS) have lower carrier mobility and weaker driving capability. To achieve stronger driving capability in OPS transistors, the channel width-to-length ratio needs to be increased. Therefore, to achieve the same driving capability, the layout area occupied by an LPS transistor is smaller than that occupied by an OPS transistor. Furthermore, when using an OPS transistor as an output transistor, the size of the output transistor needs to be designed to be larger to output the required gate control signal Scan, which is detrimental to reducing the layout size occupied by the gate drive circuit GA. Therefore, to further reduce the size of the gate drive circuit GA, at least one of the first output transistor To1 and the second output transistor To2 can be a LPS transistor.

[0061] Optionally, the first power supply terminal VA and the second power supply terminal VB are both high-voltage terminals VGH, the third power supply terminal VC and the fourth power supply terminal VD are both low-voltage terminals VGL, and the first output transistor To1 and the first switching transistor Ts1 are both P-type transistors, so that the signal output by the stage transmission circuit STA to the corresponding signal input terminal GI is in phase with the gate control signal Scan output by the gate drive circuit GA electrically connected to the stage transmission circuit STA, so that the gate control signals Scan output by the multiple gate drive circuits GA have the same phase difference in sequence.

[0062] In some embodiments, to improve the operational stability of the first output sub-circuit 201, the first output sub-circuit 201 may include a second capacitor C2, such as... Figure 3D As shown, the second capacitor C2 is electrically connected between the control terminal of the first output transistor To1 and the first power supply terminal VA, so as to maintain the potential of the control terminal of the first output transistor To1 and improve the working stability of the first output sub-circuit 201.

[0063] Optionally, the first control sub-circuit 101 of the node control sub-circuit 10 may include a first transistor T1, such as Figures 3A-3D As shown, the first transistor T1 includes a control terminal configured to receive the corresponding clock signal CK, a first source-drain terminal electrically connected to the signal input terminal GI, and a second source-drain terminal electrically connected to the second node No2.

[0064] Optionally, the second control sub-circuit 102 of the node control sub-circuit 10 includes a second transistor T2 and a third transistor T3, such as Figures 3A-3DAs shown, the second transistor T2 includes a control terminal electrically connected to the second node No2, a first source-drain terminal electrically connected to the second power supply terminal VB, and a second source-drain terminal electrically connected to the first node No1; the third transistor T3 includes a control terminal electrically connected to the second node No2, a first source-drain terminal electrically connected to the third power supply terminal VC, and a second source-drain terminal electrically connected to the first node No1.

[0065] In some embodiments, in order to enable the first power signal and the fourth power signal to be transmitted to the first node No1 in a time-division manner, the second transistor T2 may be one of a P-type transistor and an N-type transistor, and the third transistor T3 may be the other of a P-type transistor and an N-type transistor.

[0066] In some embodiments, to further reduce the layout size occupied by the gate drive circuit GA, at least one of the second transistor T2 and the third transistor T3 may be a low-temperature polysilicon transistor.

[0067] In some embodiments, the voltage of the first power signal is greater than the voltage of the fourth power signal, the second transistor T2 is a P-type low-temperature polysilicon transistor, and the third transistor T3 is an N-type oxide transistor, so that when the first power signal is applied to the first node No1 through the second transistor T2, the voltage difference between the first node No1 and the first power supply terminal VA is smaller; and, when the fourth power signal is applied to the first node No1 through the third transistor T3, the voltage difference between the first node No1 and the third power supply terminal VC is smaller, thereby improving power utilization efficiency.

[0068] Optionally, the gate drive circuit GA may also include an isolator circuit 40, such as Figures 3A-3D As shown, the isolation sub-circuit 40 may include a fourth transistor T4, which includes a control terminal electrically connected to the fifth power supply terminal VE, a first source-drain terminal electrically connected to the second node No2, and a second source-drain terminal electrically connected to the control terminal of the second output transistor To2.

[0069] In some embodiments, to reduce the layout size of the gate drive circuit GA, the fourth transistor T4 can be a low-temperature polysilicon transistor. Optionally, the fourth transistor T4 is a P-type transistor, and the fifth power supply terminal VE is a low-voltage terminal VGL. Optionally, the fourth transistor T4 is an N-type transistor, and the fifth power supply terminal VE is a high-voltage terminal VGH. The voltage of the signal supplied at the low-voltage terminal VGL is less than the voltage of the signal supplied at the high-voltage terminal VGH.

[0070] In some embodiments, one of the first power supply terminal VA and the fourth power supply terminal VD can be multiplexed as the fifth power supply terminal VE to reduce the number of power supply terminals corresponding to the gate drive circuit GA, thereby reducing the power consumption of the gate drive circuit GA.

[0071] In some embodiments, the control terminals of the second transistor T2 and the third transistor T3 are both electrically connected to the first source-drain terminal of the fourth transistor T4, so that the second transistor T2 and the third transistor T3 are controlled by the same node signal, such as... Figures 3A-3C As shown.

[0072] In some embodiments, the control terminal of the second transistor T2 is electrically connected to the first source-drain terminal of the fourth transistor T4, and the control terminal of the third transistor T3 is electrically connected to the second source-drain terminal of the fourth transistor T4, such as... Figure 3D As shown, the control terminal of the third transistor T3 is electrically connected to the second node No2 through the fourth transistor T4.

[0073] In some embodiments, the third transistor T3 may include two control terminals. One control terminal of the third transistor T3 is electrically connected to the second node No2, and the other control terminal of the third transistor T3 is electrically connected to one of the fourth power supply terminal VD, the signal output terminal GT, and the third node No3, in order to improve the operating stability of the third transistor T3.

[0074] Optionally, the gate drive circuit GA may also include a voltage regulator sub-circuit 50, such as Figure 3C As shown, the voltage regulator circuit 50 includes a fifth transistor T5. The fifth transistor T5 includes a control terminal electrically connected to the first node No1, a first source-drain terminal electrically connected to the fourth power supply terminal VD, and a second source-drain terminal electrically connected to the second node No2. The fifth transistor T5 controls the signal transmission between the fourth power supply terminal VD and the second node No2 according to the signal from the first node No1.

[0075] In some embodiments, to reduce the leakage current between the fourth power supply terminal VD and the second node No2, the fifth transistor T5 may be an oxide transistor.

[0076] In some embodiments, the fifth transistor T5 may include two control terminals. One control terminal of the fifth transistor T5 is configured to receive the signal from the first node No1, and the other control terminal of the fifth transistor T5 is electrically connected to the fourth power supply terminal VD.

[0077] In some embodiments, to reduce the probability that the second node No2 receives signals with different voltages at the same time, the third transistor T3 and the fifth transistor T5 can both be P-type transistors or both are N-type transistors.

[0078] Optionally, the gate drive circuit GA may include a reset sub-circuit 60, such as Figure 3DAs shown, the reset sub-circuit 60 may include a sixth transistor T6, which includes a control terminal configured to receive a reset control signal Res, a first source-drain terminal electrically connected to the first node No1, and a second source-drain terminal electrically connected to the sixth power supply terminal VF.

[0079] Optionally, the sixth power supply terminal VF can be either the high-voltage terminal VGH or the low-voltage terminal VGL.

[0080] In some embodiments, a transmission circuit STA is provided between the second node No2 or the third node No3 of the Nth-stage gate drive circuit GA(N) and the signal input terminal GI(N+A) of the N+A-stage gate drive circuit GA(N+A). This transmission circuit STA may still include a first switching transistor Ts1 and a second switching transistor Ts2. The first switching transistor Ts1 is an N-type oxide transistor, and the second switching transistor Ts2 is a P-type low-temperature polysilicon transistor. The first switching transistor Ts1 controls the signal transmission between the second power supply terminal VB and the corresponding signal input terminal GI, and the second switching transistor Ts2 controls the signal transmission between the third power supply terminal VC and the corresponding signal input terminal GI. The voltage of the second power supply signal supplied by the second power supply terminal VB is greater than the voltage of the third power supply signal supplied by the third power supply terminal VC, so that the signal of the second node No2 of the Nth-stage gate drive circuit GA(N) is in phase with the signal received by the signal input terminal GI(N+A) of the N+A-stage gate drive circuit GA(N). However, because the first switching transistor Ts1 is controlled by the signal from the corresponding second node No2 or the signal from the corresponding third node No3, when the second power supply signal is applied to the corresponding signal input terminal GI through the first switching transistor Ts1, the voltage difference between the corresponding signal input terminal GI and the second power supply terminal VB is relatively large. Furthermore, because the second switching transistor Ts2 is controlled by the signal from the corresponding second node No2 or the signal from the corresponding third node No3, when the third power supply signal is applied to the corresponding signal input terminal GI through the second switching transistor Ts2, the voltage difference between the corresponding signal input terminal GI and the third power supply terminal VC is relatively large. Therefore, when the cascade circuit STA transmits a signal to the signal input terminal GI of the corresponding gate drive circuit GA, the corresponding gate drive circuit GA may not start up properly, leading to instability issues in the gate driver GDC. Therefore, in this application, the cascade circuit STA is no longer controlled by the signal from the second node No2 or the third node No3, but instead uses the signal from the first node No1 in the gate drive circuit GA to control the corresponding cascade circuit STA, thereby controlling the operating states of the first switching transistor Ts1 and the second switching transistor Ts2, and improving the operating stability of the gate driver GDC.

[0081] In some embodiments, Figure 3AThe cascaded transmission circuit STA and the gate drive circuit GA shown can be used as a gate repetition unit. Multiple gate repetition units can be cascaded to make the gate driver GDC include multiple gate repetition units. Similarly, Figure 3B The cascaded transmission circuit STA and gate drive circuit GA shown can also be used as a gate repetition unit. Multiple gate repetition units can be cascaded to make the gate driver GDC include multiple gate repetition units. Similarly, Figure 3C The stage transmission circuit STA and the gate drive circuit GA shown can also be used as a gate repeating unit. Figure 3D The staged transmission circuit STA and the gate drive circuit GA shown can also be used as a gate repetition unit. Multiple gate repetition units of the same gate driver GDC can adopt the same design to reduce manufacturing costs while making the operating characteristics of multiple gate repetition units similar, so that the gate control signals Scan output by multiple gate repetition units tend to be consistent.

[0082] It should be noted that the transistors included in the gate drive circuit GA and the stage transmission circuit STA can be either P-type or N-type transistors. Each transistor can be implemented as a bipolar junction transistor (BJT), field-effect transistor (FET), or thin-film transistor (TFT). When the transistor is implemented as an FET or TFT, the control terminal can be the gate, the first source / drain terminal can be one of the source and drain, and the second source / drain terminal can be the other of the source and drain. When the transistor is implemented as a BJT, the control terminal can be the base, the first source / drain terminal can be one of the collector and emitter, and the second source / drain terminal can be the other of the collector and emitter. Each transistor can employ a single-gate or dual-gate design. The active layer of each transistor can include silicon semiconductor materials or oxide semiconductor materials. The silicon semiconductor materials include monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The oxide semiconductor materials include indium gallium zinc oxide (IGNOW) or indium zinc oxide (IBO).

[0083] It should be understood that, Figure 3A Only the design of the stage transmission circuit STA and the corresponding gate drive circuit GA connected to the first node No.1 is shown. Figures 3B-3D This diagram only shows the electrical connection between the stage transmission circuit STA and the corresponding gate drive circuit GA's signal input terminal GI. (Refer to...) Figure 3A The design shown allows us to obtain the corresponding gate drive circuit GA. Figures 3C-3D In the design, the cascade circuit STA and the corresponding gate drive circuit GA are connected to the first node No.1. (Refer to...) Figures 3B-3D For any of the designs shown, the corresponding gate drive circuit GA can be obtained. Figure 3A In the design, the stage transmission circuit STA is electrically connected to the signal input terminal of the corresponding gate drive circuit GA. Furthermore, Figures 3A-3DThis is merely an illustrative diagram and is not limited to the gate drive circuit GA used in this application. Figures 3A-3D Based on the disclosure of this application, those skilled in the art can still modify the design of each sub-circuit of the gate drive circuit GA and the stage transmission circuit STA. Each sub-circuit of the gate drive circuit GA and the stage transmission circuit STA can also be implemented in a simpler or more complex form using a greater number of components. These components include, but are not limited to, transistors, capacitors, and other devices.

[0084] Figures 4A-4B This is a timing diagram corresponding to the gate drive circuit and the stage transmission circuit in an exemplary embodiment of this application. Figures 5A-5B This is a timing diagram corresponding to the gate driver in an exemplary embodiment of this disclosure. To facilitate understanding of the working principle of the gate driver GDC of this application, we take the following as an example: the first switching transistor Ts1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the first output transistor To1, and the second output transistor To2 are P-type transistors; the second switching transistor Ts2, the third transistor T3, and the fifth transistor T5 are N-type transistors; the first power supply terminal VA and the second power supply terminal VB are high-voltage terminals VGH; the third power supply terminal VC to the sixth power supply terminal VF are low-voltage terminals VGL; and multiple gate driving circuits GA share a clock signal CK transmitted via two clock lines. Figures 3A-3D The working principle of a single gate drive circuit (GA) and a single stage drive circuit (STA) will be explained first by way of example.

[0085] Wherein, GIS(N) represents the signal transmitted to the signal input terminal GI(N) of the Nth stage gate drive circuit GA(N), GIS(N+A) represents the signal transmitted to the signal input terminal GI(N+A) of the N+A stage gate drive circuit GA(N+A); Nos1(N) represents the signal of the first node No1 in the Nth stage gate drive circuit GA(N), Nos2(N) represents the signal of the second node No2 in the Nth stage gate drive circuit GA(N), and Nos3(N) represents the signal of the third node No3 in the Nth stage gate drive circuit GA(N).

[0086] Please continue reading. Figure 3A and Figure 4AIn the first stage t1, the signal GIS(N) received at the signal input terminal of the Nth stage gate drive circuit GA(N) and the clock signal CK corresponding to the Nth stage gate drive circuit GA(N) are at low level. In the Nth stage gate drive circuit GA(N), the first transistor T1, the second transistor T2, the second output transistor To2, and the second switching transistor Ts2 are turned on, while the third transistor T3, the first output transistor To1, and the first switching transistor Ts1 are turned off. The Nth stage gate control signal Scan(N) output by the Nth stage gate drive circuit GA(N) and the signal GIS(N+A) transmitted to the signal input terminal of the N+A stage gate drive circuit GA(N+A) are at low level. In the second stage t2, the signal GIS(N) received at the signal input terminal of the Nth stage gate drive circuit GA(N) is at a low level, and the clock signal CK corresponding to the Nth stage gate drive circuit GA(N) is at a high level. In the Nth stage gate drive circuit GA(N), the second transistor T2, the second output transistor To2, and the second switching transistor Ts2 are turned on, while the first transistor T1, the third transistor T3, the first output transistor To1, and the first switching transistor Ts1 are turned off. The Nth stage gate control signal Scan(N) output by the Nth stage gate drive circuit GA(N) and the signal GIS(N+A) transmitted to the signal input terminal of the N+A stage gate drive circuit GA(N+A) are at a low level.

[0087] In the third stage t3, the signal GIS(N) received at the signal input terminal of the Nth stage gate drive circuit GA(N) is at a high level, and the clock signal CK corresponding to the Nth stage gate drive circuit GA(N) is at a low level. In the Nth stage gate drive circuit GA(N), the first transistor T1, the third transistor T3, the first output transistor To1, and the first switching transistor Ts1 are turned on, while the second transistor T2, the second output transistor To2, and the second switching transistor Ts2 are turned off. The Nth stage gate control signal Scan(N) output by the Nth stage gate drive circuit GA(N) and the signal GIS(N+A) transmitted to the signal input terminal of the N+A stage gate drive circuit GA(N+A) are at a high level.

[0088] In the fourth stage t4, the signal GIS(N) received at the signal input terminal of the Nth stage gate drive circuit GA(N) is at a high level, and the clock signal CK corresponding to the Nth stage gate drive circuit GA(N) is at a high level. In the Nth stage gate drive circuit GA(N), the third transistor T3, the first output transistor To1, and the first switching transistor Ts1 are turned on, while the first transistor T1, the second transistor T2, the second output transistor To2, and the second switching transistor Ts2 are turned off. The Nth stage gate control signal Scan(N) output by the Nth stage gate drive circuit GA(N) and the signal GIS(N+A) transmitted to the signal input terminal of the N+A stage gate drive circuit GA(N+A) are at a high level.

[0089] In the fifth stage t5, the Nth stage gate drive circuit GA(N) performs the operation... Figure 4A The operation is the same as in the first stage t1 shown. The Nth stage gate control signal Scan(N) output by the Nth stage gate drive circuit GA(N) and the signal input signal GIS(N+A) transmitted to the N+A stage gate drive circuit GA(N+A) are both at a low level.

[0090] Please continue reading. Figures 3B-3D and Figure 4B In the first stage t1, the clock signal CK corresponding to the N+A stage gate drive circuit GA(N+A) is low, and the signal Nos1(N) of the first node of the Nth stage gate drive circuit GA(N) is high. Figure 3B and Figure 3D In the N+A level gate drive circuit GA(N+A) shown, the first transistor T1, the second transistor T2, the second output transistor To2, and the second switching transistor Ts2 are turned on, while the third transistor T3, the first output transistor To1, and the first switching transistor Ts1 are turned off. The N+A level gate control signal Scan(N+A) output by the N+A level gate drive circuit GA(N+A) is low. Figure 3C In the gate drive circuit GA shown, the fifth transistor T5 is turned on.

[0091] In the second stage t2, the signal Nos1(N) of the first node of the Nth stage gate drive circuit GA(N) and the clock signal CK corresponding to the N+A stage gate drive circuit GA(N+A) are at a high level. Figure 3B and Figure 3D In the N+A stage gate drive circuit GA(N+A) shown, the second transistor T2, the second output transistor To2, and the second switching transistor Ts2 are turned on, while the first transistor T1, the third transistor T3, the first output transistor To1, and the first switching transistor Ts1 are turned off. Therefore, the N+A stage gate control signal Scan(N+A) output by the N+A stage gate drive circuit GA(N+A) is low. Figure 3C In the gate drive circuit GA shown, the fifth transistor T5 is turned on.

[0092] In the third stage t3, the signal Nos1(N) of the first node of the Nth stage gate drive circuit GA(N) and the clock signal CK corresponding to the N+A stage gate drive circuit GA(N+A) are at a low level. Figure 3B and Figure 3D In the N+A level gate drive circuit GA(N+A) shown, the first transistor T1, the third transistor T3, the first output transistor To1, and the first switching transistor Ts1 are turned on, while the second transistor T2, the second output transistor To2, and the second switching transistor Ts2 are turned off. The N+A level gate control signal Scan(N+A) output by the N+A level gate drive circuit GA(N+A) is high. Figure 3C In the gate drive circuit GA shown, the fifth transistor T5 is turned off.

[0093] In the fourth stage t4, the signal Nos1(N) of the first node of the Nth stage gate drive circuit GA(N) is low, and the clock signal CK corresponding to the N+A stage gate drive circuit GA(N+A) is high. Figure 3B and Figure 3D In the N+A level gate drive circuit GA(N+A) shown, the third transistor T3, the first output transistor To1, and the first switching transistor Ts1 are turned on, while the first transistor T1, the second transistor T2, the second output transistor To2, and the second switching transistor Ts2 are turned off. The N+A level gate control signal Scan(N+A) output by the N+A level gate drive circuit GA(N+A) is at a high level.

[0094] In the fifth stage t5, the N+A stage gate drive circuit GA(N+A) performs the operation... Figure 4B The operation is the same as in the first stage t1 shown. The gate control signal Scan(N+A) output by the N+A stage gate drive circuit GA(N+A) is low.

[0095] Understandably, referring to Figures 4A-4B The related explanation also reveals the cooperation between multi-stage gate drive circuits (GA) and multiple stage drive circuits (STA) to achieve... Figures 5A-5B The timing design shown will not be elaborated further here. (Refer to...) Figures 4A-4B The relevant explanations also provide the design of a multi-stage gate drive circuit GA sharing more than two clock signals CK, which will not be elaborated here.

[0096] Based on the working principle of the gate drive circuit GA, by making the signal received at the corresponding signal input terminal GI of each stage transmission circuit STA out of phase with the signal of the corresponding first node No1, and the signal of the second node No2 of each gate drive circuit GA in phase with the signal received at the corresponding signal input terminal GI of the stage transmission circuit 30 electrically connected to the first node No1 of the same stage gate drive circuit, the gate control signals output by the multi-stage gate drive circuit GA can have the same trend of change. That is, the duration for which the signal output terminal GT of multiple gate drive circuits GA receives the first power supply signal is equal. For example, corresponding to... Figures 5A-5B The multiple gate control signals Scan shown correspond to the same high level duration.

[0097] Figure 6 This is a schematic diagram of the structure of a display panel according to an exemplary embodiment of this disclosure. This application provides a display panel including any of the above-described gate driver (GDC).

[0098] Optionally, the display panel may also include multiple sub-pixels Spx, which are electrically connected to multiple gate driving circuits GA. Each gate driving circuit GA is configured to provide a corresponding gate control signal Scan to the corresponding sub-pixel Spx, and the multiple sub-pixels Spx are configured to realize the display function of the display panel according to the received gate control signal Scan and data signal.

[0099] Optionally, the signal output terminal GT of each gate drive circuit GA is electrically connected to multiple sub-pixels Spx, so that multiple sub-pixels Spx share the same gate control signal Scan output by the same gate drive circuit GA, thereby reducing the number of gate drive circuits GA used in the display panel.

[0100] Optionally, the display panel can be a passive light-emitting display panel or a self-emissive display panel. Passive light-emitting display panels include liquid crystal display panels, while self-emissive display panels include display panels that use light-emitting devices as sub-pixels (Spx). The light-emitting devices can include at least one of organic light-emitting diodes (OLEDs), sub-millimeter light-emitting diodes (PMLEDs), and micro LEDs.

[0101] It should be noted that the aforementioned start signal STV can be the frame start signal.

[0102] In some embodiments, the reset sub-circuit 60 in a plurality of gate drive circuits GA can be controlled to reset the potential of the corresponding first node No1 before the end or beginning of each frame, so as to improve the display quality of the display panel in each frame.

[0103] It should be understood that the display panel provided by the present invention includes any of the above-mentioned gate driver GDCs, and therefore, the display panel also has all the beneficial effects of the above-mentioned gate driver GDCs, which will not be described in detail here.

[0104] Figure 7 This is a schematic diagram of the structure of a display device according to an exemplary embodiment of the present disclosure. This application also provides a display device including any of the above-described display panels.

[0105] The display device may also include a timing controller electrically connected to a gate driver GDC, the timing controller being configured to output corresponding clock signals CK to a plurality of gate drive circuits GA.

[0106] Optionally, the timing controller is configured to transmit a frame start signal to the signal input GI of the first A-stage gate drive circuit GA among the plurality of gate drive circuits GA. As in some embodiments, A equals 1, and the timing controller is configured to transmit the frame start signal to the signal input GI of the first-stage gate drive circuit GA among the plurality of gate drive circuits GA. Here, the first-stage gate drive circuit GA is the first-stage gate drive circuit GA (1).

[0107] Optionally, the (N+1)th cascade circuit STA (N+1) of the plurality of cascade circuits STA is connected between the first node No1 of the Nth stage gate drive circuit GA (N) and the signal input terminal GI (N+A) of the (N+A)th stage gate drive circuit GA (N+A). The timing controller is configured to transmit a frame start signal STV to the signal input terminal GI of the first A circuits in the plurality of cascade circuits STA. As in some embodiments, A equals 1, the first cascade circuit STA (1) of the plurality of cascade circuits STA is connected to the start signal line, and the timing controller is configured to transmit the frame start signal to the first cascade circuit STA (1) of the plurality of cascade circuits STA.

[0108] The display device may also include a source driver, and a timing controller electrically connected to the source driver. The timing controller can provide the source driver with the required clock signal CK. The source driver can generate a data signal based on the control signal output by the timing controller, and output it to multiple sub-pixels Spx, thereby controlling the display content of the multiple sub-pixels Spx.

[0109] It should be noted that the display device may also include components not shown, such as a graphics processor and a power manager. The source driver can be electrically connected to the timing controller via a flexible circuit board or other devices. The timing controller may be located on the same circuit board as the graphics processor or on a different circuit board. The gate driver may be integrated into the display panel using an on-array substrate.

[0110] It should be understood that the display device provided by the present invention includes any of the above-mentioned display panels, and therefore also has all the beneficial effects of the above-mentioned display panels, which will not be repeated here.

[0111] Display devices can be mobile phones, computers, virtual reality displays, augmented reality displays, and other similar devices. They can be used in fields such as education, entertainment, transportation, healthcare, and defense to achieve display functions.

[0112] The above description is merely an optional embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A gate driver, characterized in that, It includes multiple gate drive circuits and multiple stage transmission circuits, each of the gate drive circuits including: A node control sub-circuit, electrically connected to the signal input terminal of the gate drive circuit of this stage and the first node, is configured to control the signal of the first node according to the signal received at the signal input terminal and the corresponding clock signal; and... The output sub-circuit is electrically connected to the first node and is configured to control the signal transmission between the signal output terminal of the gate drive circuit of this stage and the first power supply terminal according to the signal of the first node. Wherein, a cascading circuit is provided between the first node of the Nth-level gate driving circuit and the signal input terminal of the N+A-level gate driving circuit, and at least one of the cascading circuits is configured to control the signal received by the corresponding signal input terminal according to the signal of the corresponding first node, where N≥1 and A≥1.

2. The gate driver according to claim 1, characterized in that, Each of the cascade circuits is configured to control the signal received at the corresponding signal input terminal to be out of phase with the signal of the corresponding first node.

3. The gate driver according to claim 1 or 2, characterized in that, At least one of the aforementioned transmission circuits includes: The first switch sub-circuit, electrically connected to the corresponding signal input terminal and the corresponding first node, is configured to control the signal transmission between the second power supply terminal and the corresponding signal input terminal according to the signal of the corresponding first node; The second switch sub-circuit, electrically connected to the corresponding signal input terminal and the corresponding first node, is configured to control the signal transmission between the third power supply terminal and the corresponding signal input terminal according to the signal of the corresponding first node; Each of the cascade circuits is configured to control the corresponding signal input terminal to form a current path with the second power supply terminal and the third power supply terminal in a time-division manner according to the signal of the corresponding first node.

4. The gate driver according to claim 3, characterized in that, The first switching sub-circuit includes a first switching transistor, which includes a control terminal electrically connected to the corresponding first node, a first source-drain terminal electrically connected to the second power supply terminal, and a second source-drain terminal electrically connected to the corresponding signal input terminal. The second switching sub-circuit includes a second switching transistor, which includes a control terminal electrically connected to the control terminal of the first switching transistor, a first source-drain terminal electrically connected to the third power supply terminal, and a second source-drain terminal electrically connected to the second source-drain terminal of the first switching transistor. The first switching transistor is one of a P-type transistor and an N-type transistor, and the second switching transistor is the other of a P-type transistor and an N-type transistor.

5. The gate driver according to claim 1 or 2, characterized in that, The node control sub-circuit includes: The first control sub-circuit is electrically connected between the signal input terminal and the second node of the gate drive circuit of this stage, and is configured to control the signal transmission between the signal input terminal and the second node according to the corresponding clock signal; The second control sub-circuit is electrically connected between the first node and the second node of the gate drive circuit of this stage, and is configured to control the first node to form a current path with the first power supply terminal and the fourth power supply terminal in a time-division manner according to the signal of the second node.

6. The gate driver according to claim 5, characterized in that, The output sub-circuit is electrically connected to the second node of the gate drive circuit of this stage, and the output sub-circuit is further configured to control the signal transmission between the fourth power supply terminal and the signal output terminal according to the signal of the second node.

7. The gate driver according to claim 6, characterized in that, The signal received at the signal input terminal of the N+A level gate drive circuit is in phase with the signal of the second node of the Nth level gate drive circuit.

8. The gate driver according to claim 6, characterized in that, The output sub-circuit includes: The first output transistor includes a control terminal electrically connected to the first node, a second source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the signal output terminal. The second output transistor includes a control terminal electrically connected to the second node, a second source-drain terminal electrically connected to the fourth power supply terminal, and a second source-drain terminal electrically connected to the signal output terminal. The first capacitor is electrically connected between the control terminal of the second output transistor and the signal output terminal.

9. The gate driver according to claim 8, characterized in that, The output sub-circuit includes: The second capacitor is electrically connected between the control terminal of the first output transistor and the first power supply terminal.

10. The gate driver according to claim 8, characterized in that, The first control sub-circuit includes a first transistor, which includes a control terminal configured to receive the corresponding clock signal, a first source-drain terminal electrically connected to the signal input terminal, and a second source-drain terminal electrically connected to the second node. The second control sub-circuit includes a second transistor and a third transistor. The second transistor includes a control terminal electrically connected to the second node, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the first node. The third transistor includes a control terminal electrically connected to the second node, a first source-drain terminal electrically connected to the fourth power supply terminal, and a second source-drain terminal electrically connected to the first node. The second transistor is either a P-type transistor or an N-type transistor, and the third transistor is either a P-type transistor or an N-type transistor.

11. The gate driver according to claim 10, characterized in that, At least one of the gate drive circuits further includes: An isolation sub-circuit is electrically connected between the second node of the gate drive circuit and the control terminal of the second output transistor, and is configured to isolate the coupling effect of the potential change of the control terminal of the first output transistor on the potential of the second node.

12. The gate driver according to claim 11, characterized in that, The isolation sub-circuit includes a fourth transistor, which includes a control terminal electrically connected to a fifth power supply terminal, a first source-drain terminal electrically connected to the second node, and a second source-drain terminal electrically connected to the control terminal of the second output transistor. The control terminal of the second transistor is electrically connected to the first source-drain terminal of the fourth transistor, and the control terminal of the third transistor is electrically connected to the second source-drain terminal of the fourth transistor.

13. The gate driver according to claim 5, characterized in that, At least one of the gate drive circuits further includes: The voltage regulator sub-circuit, electrically connected to the first node and the second node of the gate drive circuit of this stage, is configured to connect the current path between the second node and the fourth power supply terminal according to the signal of the first node during the period when the second control sub-circuit connects the current path between the first power supply terminal and the first node.

14. The gate driver according to claim 5, characterized in that, The gate driver further includes a reset control line electrically connected to a plurality of the gate drive circuits, the reset control line being configured to transmit a reset control signal to the plurality of the gate drive circuits; At least one of the gate drive circuits further includes a reset sub-circuit electrically connected to the first node of the gate drive circuit of this stage, the reset sub-circuit being configured to reset the potential of the first node according to the reset control signal.

15. The gate driver according to claim 1 or 2, characterized in that, It also includes Z clock lines, which are configured to transmit Z clock signals that have the same phase difference in sequence; Among them, the Yth clock line of the Z clock lines is electrically connected to the ZK+Yth stage gate drive circuit, and the Yth clock line is configured to transmit the corresponding clock signal to the ZK+Yth stage gate drive circuit; Z≥2, 1≤Y≤Z, K≥0.

16. A display panel, characterized in that, include: Multiple sub-pixels; as well as, According to any one of claims 1 to 15, the signal output terminal of each of the gate driving circuits is electrically connected to a plurality of the sub-pixels, and each of the gate driving circuits is configured to provide a corresponding gate control signal to the corresponding sub-pixel.

17. A display device, characterized in that, include: The display panel as described in claim 16; as well as, A timing controller, electrically connected to the gate driver, is configured to transmit a frame start signal to the signal input terminal of the first gate driver circuit among the plurality of gate driver circuits, and output the corresponding clock signal to the plurality of gate driver circuits.

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