Semiconductor device and method of manufacturing the same, electronic device

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, the semiconductor device comprising: a plurality of memory cells distributed in different layers, stacked and spaced along a direction perpendicular to a substrate; an insulating layer and a semiconductor layer alternately distributed in sequence from bottom to top along a direction perpendicular to the substrate; adjacent two layers of the memory cells are insulated by the insulating layer; the memory cell comprises the semiconductor layer; a side of the substrate close to the memory cell has a protective layer; an etching selection ratio of the insulating layer to the protective layer is not less than 5:1, and an etching selection ratio of the semiconductor layer to the protective layer is not less than 5:1. The semiconductor device of the embodiment of the application can avoid damage to the exposed substrate in the etching process by setting the protective layer on one side of the substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device. By providing a protective layer on one side of the substrate, the semiconductor device and manufacturing method can prevent damage to the exposed substrate during the etching process.

[0006] This application provides a semiconductor device, the semiconductor device comprising:

[0007] Multiple storage cells are distributed in different layers, stacked and spaced apart along a direction perpendicular to the substrate;

[0008] An insulating layer and a semiconductor layer are alternately distributed from bottom to top along a direction perpendicular to the substrate; adjacent memory cells are insulated from each other by the insulating layer; each memory cell includes the semiconductor layer;

[0009] The substrate has a protective layer on the side closest to the memory cell;

[0010] The etching selectivity ratio of the insulating layer to the protective layer is not less than 5:1, and the etching selectivity ratio of the semiconductor layer to the protective layer is not less than 5:1.

[0011] In some embodiments of this application, the protective layer contains any one or more of silicon nitride, silicon boron nitride, and silicon carbonitride.

[0012] In some embodiments of this application, the insulating layer includes a first end and a second end, the first end and the second end being an integral structure; the thickness of the first end is less than the thickness of the second end; the semiconductor layer surrounds the second end, and the semiconductor layer is exposed at the first end.

[0013] In some embodiments of this application, there is no overlap between the orthographic projection of the first end on the substrate and the orthographic projection of the semiconductor layer on the substrate.

[0014] In some embodiments of this application, the thickness of the protective layer is not less than 20 nm.

[0015] In some embodiments of this application, the storage cell includes a capacitor, and the protective layer is located between the capacitor and the substrate;

[0016] The capacitor includes a first capacitor electrode, a second capacitor electrode, and a dielectric layer located between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode is connected to the semiconductor layer.

[0017] The first capacitor electrode covers the opposing surfaces of the first ends of the two adjacent layers and the sidewalls of the semiconductor layer.

[0018] In some embodiments of this application, the first capacitor electrodes of a plurality of memory cells spaced apart along a direction perpendicular to the substrate are disconnected from each other;

[0019] The dielectric layer of the plurality of memory cells spaced apart along a direction perpendicular to the substrate is a single, integral structure; and / or,

[0020] The second capacitor electrodes of the plurality of memory cells, which are spaced apart along a direction perpendicular to the substrate, are an integral structure.

[0021] This application also provides a method for manufacturing a semiconductor device, the method comprising:

[0022] A stacked structure is obtained by sequentially and alternately forming a first film layer and a second film layer on a substrate.

[0023] An opening is formed in the stacked structure that extends toward the substrate, the opening exposing the first film layer located at the bottom layer;

[0024] An etching barrier layer is formed on the sidewall of the opening;

[0025] Remove the first film layer located at the bottom of the opening to expose the substrate;

[0026] Impurity ions are doped into the substrate to form a protective layer on the surface of the substrate.

[0027] Wherein, the etching selectivity ratio of the first film layer to the protective layer is not less than 5:1, and the etching selectivity ratio of the second film layer to the protective layer is not less than 5:1.

[0028] In some embodiments of this application, the doping of impurity ions into the substrate includes:

[0029] Nitrogen-containing impurities are doped into the substrate using a plasma implantation process.

[0030] In some embodiments of this application, the doping amount of the impurity ions is not less than 1076 ions / cm³. 2 .

[0031] In some embodiments of this application, the substrate is made of silicon, and the protective layer contains any one or more of silicon nitride, silicon boron nitride, and silicon carbonitride.

[0032] In some embodiments of this application, the first film layer is a sacrificial layer, and the second film layer is a semiconductor layer;

[0033] The manufacturing method further includes: after doping the substrate with impurity ions.

[0034] Replace the sacrificial layer with an insulating layer;

[0035] Laterally etch the exposed semiconductor layer within the opening to form a lateral groove between two adjacent insulating layers;

[0036] The insulating layer between two adjacent transverse grooves is thinned, and the transverse grooves are expanded in a direction perpendicular to the substrate.

[0037] A first capacitor electrode, a dielectric layer, and a second capacitor electrode are sequentially formed within the opening and the expanded transverse groove to obtain a capacitor.

[0038] In some embodiments of this application, replacing the sacrificial layer with an insulating layer includes:

[0039] Remove the etching barrier layer on the sidewall of the opening to expose the sacrificial layer and the semiconductor layer;

[0040] The exposed sacrificial layer is etched laterally within the opening to remove the sacrificial layer;

[0041] An insulating layer is formed on the substrate to fill the gap between two adjacent semiconductor layers and to cover the sidewalls of the opening;

[0042] Remove the insulating layer located on the sidewall of the opening, and retain the insulating layer located between two adjacent semiconductor layers.

[0043] This application also provides an electronic device, which includes the semiconductor device described above, or includes a semiconductor device obtained by the manufacturing method described above.

[0044] The semiconductor device and manufacturing method of the present application embodiment can protect the substrate from damage during the formation of memory cells, such as during the etching of the film layer, by providing a protective layer with a low etching rate on one side of the substrate, thereby avoiding substrate collapse.

[0045] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0046] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0047] Figure 1 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor device in a section perpendicular to the substrate, which is an exemplary embodiment of this application.

[0048] Figure 2 A process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application;

[0049] Figure 3 A schematic longitudinal section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a stacked structure;

[0050] Figure 4 This is a schematic longitudinal section view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of a sacrificial layer, on a section perpendicular to the substrate.

[0051] Figure 5 This is a schematic longitudinal section view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of an etch barrier layer, on a section perpendicular to the substrate.

[0052] Figure 6 A schematic longitudinal section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after removing a portion of the sacrificial layer at the bottom of a via, is shown in the diagram perpendicular to the substrate.

[0053] Figure 7 This is a schematic longitudinal section view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of a protective layer;

[0054] Figure 8 A schematic longitudinal section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the removal of the sacrificial layer, is shown in the cross section perpendicular to the substrate.

[0055] Figure 9 A schematic longitudinal section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after replacing the sacrificial layer with an insulating layer;

[0056] Figure 10 A schematic longitudinal section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a lateral groove, is shown in a cross section perpendicular to the substrate.

[0057] Figure 11 This is a schematic diagram of a longitudinal section perpendicular to the substrate, illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application, after thinning an insulating layer.

[0058] The meanings of the symbols in the attached diagram are as follows:

[0059] 10-Substrate; 11-Insulating layer; 111-First end; 112-Second end; 12-Semiconductor layer; 13-Protective layer; 14-Sacrificial layer; 15-Etching barrier layer; 21-First capacitor electrode; 22-Second capacitor electrode; 23-Dielectric layer. Detailed Implementation

[0060] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0061] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0062] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0063] The embodiments of this application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments, but other shapes and sizes are also possible. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this application are not limited to the shapes or values ​​shown in the drawings.

[0064] The size and proportional relationships between the various film layers or components in the accompanying drawings of this application can serve as a reference in actual processes and represent embodiments with better technical effects, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing can be adjusted according to actual needs.

[0065] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0066] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0067] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0068] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0069] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0070] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0071] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0072] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, unless otherwise specified, in this application, the "source electrode" and "drain electrode" can be interchanged.

[0073] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0074] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0075] In this application, "film" and "layer" can be interchanged. For example, "semiconductor layer" can sometimes be replaced with "semiconductor film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".

[0076] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected layers on a single film layer. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed with interconnected structures through the same patterning process, or B may be directly grown on A via epitaxy, and the materials of the two may not be exactly the same.

[0077] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functional circuits are already distributed. The devices involved in the inventive construction of the embodiments of this application are disposed on the main surface of the support structure.

[0078] In this application, the spacing distribution can be understood as a separate, independent distribution. This spacing can be achieved through physical structural breaks or electrical characteristic breaks. For example, the semiconductor layer between the effective channels of two transistors can be modified to achieve insulation, thus creating an electrical gap between the two channels.

[0079] This application provides a semiconductor device. Figure 1 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor device in a section perpendicular to the substrate, which is an exemplary embodiment of this application.

[0080] like Figure 1 As shown, the semiconductor device includes: a plurality of memory cells located on a substrate, a protective layer 13, an insulating layer 11 and a semiconductor layer 12 that are alternately distributed from bottom to top along a direction perpendicular to the substrate 10;

[0081] Multiple memory cells are distributed in different layers, stacked and spaced apart along a direction perpendicular to the substrate 10;

[0082] The adjacent storage cells are insulated from each other by an insulating layer 11; each storage cell includes a semiconductor layer 12.

[0083] The protective layer 13 is located between the substrate 10 and the memory cell;

[0084] The etching selectivity ratio of the insulating layer 11 to the protective layer 13 is not less than 5:1, and the etching selectivity ratio of the semiconductor layer 12 to the protective layer 13 is not less than 5:1.

[0085] The semiconductor device of this application embodiment protects the substrate from damage during the formation of memory cells (e.g., capacitors), bit lines, and word lines, for example, during the etching of the film layer to form holes or trenches that accommodate capacitors, bit lines, and word lines, thereby preventing substrate collapse.

[0086] In some embodiments of this application, the etching ratio of the insulating layer 11 to the protective layer 13 can be 5:1, 10:1, 15:1, or 20:1, etc. The etching ratio of the semiconductor layer 12 to the protective layer 13 can be 5:1, 10:1, 15:1, or 20:1, etc.

[0087] In some embodiments of this application, the protective layer 13 contains any one or more of silicon nitride (SiN), silicon boron nitride (SiBN), and silicon carbonitride (SiCN).

[0088] In some embodiments of this application, such as Figure 1 As shown, the insulating layer 11 includes a first end 111 and a second end 112, which are integral structures; the thickness of the first end 111 is less than the thickness of the second end 112; the semiconductor layer 12 surrounds the second end 112 and is exposed at the first end 111.

[0089] In some embodiments of this application, such as Figure 1 As shown, there is no overlap between the orthographic projection of the first end 111 on the substrate 10 and the orthographic projection of the semiconductor layer 12 on the substrate 10.

[0090] In some embodiments of this application, the thickness of the protective layer 13 is not less than 20nm. For example, the thickness of the protective layer 13 can be 20nm, 25nm, 30nm, 35nm, 40nm, 45nm or 50nm, etc.

[0091] In some embodiments of this application, such as Figure 1 As shown, the storage cell includes a capacitor C, and a protective layer 13 is located between the capacitor C and the substrate 10;

[0092] The capacitor C includes a first capacitor electrode 21, a second capacitor electrode 22, and a dielectric layer 23 located between the first capacitor electrode 21 and the second capacitor electrode 22; the first capacitor electrode 21 is connected to the semiconductor layer 12.

[0093] The semiconductor device in this application embodiment reduces the thickness of the first end 111 by thinning the first end 111 of the insulating layer 11, thereby increasing the area of ​​the first capacitor electrode 21 and the contact area between the first capacitor electrode 21 and the second capacitor electrode 22, thus improving the capacitance within a limited storage area.

[0094] The first capacitor electrode 21 covers the opposite surfaces of the first ends 111 of the two adjacent layers and the sidewalls of the semiconductor layer 12.

[0095] In some embodiments of this application, such as Figure 1 As shown, the first capacitor electrodes 21 of the plurality of memory cells, which are spaced apart along a direction perpendicular to the substrate 10, are disconnected from each other;

[0096] In some embodiments of this application, such as Figure 1 As shown, the dielectric layer 23 of the plurality of memory cells distributed at intervals along a direction perpendicular to the substrate 10 is an integral structure.

[0097] In some embodiments of this application, such as Figure 1 As shown, the second capacitor electrodes 22 of the plurality of memory cells distributed at intervals along a direction perpendicular to the substrate 10 are an integral structure.

[0098] In this application, the semiconductor layer can be understood as a semiconductor material, and its shape and structure are not emphasized, but only its function is emphasized.

[0099] For example, the material of the semiconductor layer can be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it can be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0100] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as N, Si, etc.; and may also contain other small amounts of doping elements.

[0101] In some embodiments, the material of the metal oxide semiconductor layer or channel may comprise any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.

[0102] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0103] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0104] In some embodiments of this application, the dielectric layer may be made of silicon oxide or a high-K dielectric material. High-K materials, in some embodiments, may include any one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0105] In some embodiments of this application, the semiconductor device may be a 3D memory, such as a 3D DRAM. The 3D memory may have a 1T1C or 2T1C structure.

[0106] This application also provides a method for manufacturing a semiconductor device. The semiconductor device described above can be obtained by this manufacturing method.

[0107] Figure 2 This is a process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application. Figure 2 As shown, the manufacturing method includes:

[0108] A stacked structure is obtained by sequentially and alternately forming a first film layer and a second film layer on a substrate.

[0109] An opening is formed in the stacked structure that extends toward the substrate, the opening exposing the first film layer located at the bottom layer;

[0110] An etching barrier layer is formed on the sidewall of the opening;

[0111] Remove the first film layer located at the bottom of the opening to expose the substrate;

[0112] Impurity ions are doped into the substrate to form a protective layer on the surface of the substrate.

[0113] Wherein, the etching selectivity ratio of the first film layer to the protective layer is not less than 5:1, and the etching selectivity ratio of the second film layer to the protective layer is not less than 5:1.

[0114] The semiconductor device manufacturing method of this application provides a protective layer with a low etching rate on one side of the substrate, which can protect the substrate from damage during the formation of memory cells, for example, during the etching of the film layer, thereby preventing substrate collapse.

[0115] In some embodiments of this application, the doping of impurity ions into the substrate includes:

[0116] Nitrogen-containing impurities are doped into the substrate using a plasma implantation process.

[0117] In some embodiments of this application, the nitrogen-containing impurity may include nitrogen and boron (B).

[0118] In some embodiments of this application, the doping amount of the impurity ions is not less than 1076 ions / cm³. 2 .

[0119] In some embodiments of this application, the substrate is made of silicon, and the protective layer contains any one or more of silicon nitride, silicon boron nitride, and silicon carbonitride.

[0120] In some embodiments of this application, the first film layer is a sacrificial layer, and the second film layer is a semiconductor layer;

[0121] The manufacturing method further includes: after doping the substrate with impurity ions.

[0122] Replace the sacrificial layer with an insulating layer;

[0123] Laterally etch the exposed semiconductor layer within the opening to form a lateral groove between two adjacent insulating layers;

[0124] The insulating layer between two adjacent transverse grooves is thinned, and the transverse grooves are expanded in a direction perpendicular to the substrate.

[0125] A first capacitor electrode, a dielectric layer, and a second capacitor electrode are sequentially formed within the opening and the expanded transverse groove to obtain a capacitor.

[0126] In some embodiments of this application, replacing the sacrificial layer with an insulating layer includes:

[0127] Remove the etching barrier layer on the sidewall of the opening to expose the sacrificial layer and the semiconductor layer;

[0128] The exposed sacrificial layer is etched laterally within the opening to remove the sacrificial layer;

[0129] An insulating layer is formed on the substrate to fill the gap between two adjacent semiconductor layers and to cover the sidewalls of the opening;

[0130] Remove the insulating layer located on the sidewall of the opening, and retain the insulating layer located between two adjacent semiconductor layers.

[0131] The technical solutions of the embodiments of this application are further illustrated below through the manufacturing process of a semiconductor device using exemplary embodiments. The "patterning etching" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.

[0132] like Figures 3 to 11 As shown, in one exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.

[0133] S10: A substrate 10 is provided, and multiple sacrificial layers 14 and multiple semiconductor layers 12 are sequentially and alternately deposited on the substrate 10 to obtain a stacked structure formed by alternating stacking of multiple sacrificial layers 14 and multiple semiconductor layers 12, such as... Figure 3 As shown.

[0134] For example, step S10 may further include: forming structures such as transistors, bit lines BL, and word lines in the stacked structure.

[0135] For example only. Figure 3 The stacked structure shown includes three sacrificial layers 14 and three semiconductor layers 12. In other embodiments, the stacked structure may include more or fewer sacrificial layers 14 and semiconductor layers 12 arranged alternately.

[0136] For example, the substrate 10 can be made of single-crystal silicon, the sacrificial layer 14 can be made of silicon germanium (SiGe), and the semiconductor layer 12 can be made of silicon.

[0137] S20: The stacked structure is etched along the direction toward the substrate 10 to form an opening extending in the direction toward the substrate 10, exposing the bottommost sacrificial layer 14, such as... Figure 4 As shown.

[0138] In this embodiment, the opening is a through hole K; in other embodiments, the opening may also be a groove.

[0139] S30: An etching barrier layer 15 is formed on the sidewall of the through-hole K, such as... Figure 5 As shown.

[0140] For example, step S30 may include:

[0141] S31: Deposit an etch barrier layer 15 on the surface of substrate 10 to cover the sidewalls and bottom of via K;

[0142] S32: Remove the etching barrier layer 15 on the bottom surface of the via K and the surface of the substrate 10 by etching, while retaining the etching barrier layer 15 on the sidewall of the via K.

[0143] For example, the material of the etch barrier layer 15 can be silicon oxide, etc., and the silicon oxide layer can be formed on the surface of the substrate 10 using an atomic layer deposition (ALD) process.

[0144] S40: Etching removes part of the sacrificial layer 14 located at the bottom of the via K, exposing the substrate 10, such as Figure 6 As shown.

[0145] S50: Impurity ions are doped into the exposed substrate 10 to form a protective layer 13 on the surface of the substrate 10, such as... Figure 7 As shown.

[0146] For example, a plasma implantation process can be used to dope nitrogen-containing impurity ions into the substrate 10.

[0147] The etching selectivity ratio of the sacrificial layer 14 to the protective layer 13 is not less than 5:1, and the etching selectivity ratio of the semiconductor layer 12 to the protective layer 13 is not less than 5:1.

[0148] S60: Replace the sacrificial layer 14 with the insulating layer 11.

[0149] For example, step S60 may include:

[0150] S61: Etch to remove the etching barrier layer 15 on the sidewall of via K, exposing the sacrificial layer 14 and the semiconductor layer 12;

[0151] S62: Laterally etch the exposed sacrificial layer 14 within the via K to remove the sacrificial layer 14, such as... Figure 8 As shown;

[0152] S63: An insulating layer 11 is deposited on the substrate 10 to fill the gap between two adjacent semiconductor layers 12 and cover the sidewalls of the via K;

[0153] S64: Remove the insulating layer 11 located on the sidewall of the via K, and retain the insulating layer 11 located between two adjacent semiconductor layers 12, as follows: Figure 9 As shown.

[0154] S70: Laterally etch the semiconductor layers 12 on both sides within the via K to form a lateral groove T between two adjacent insulating layers 11, such as... Figure 10 As shown.

[0155] S80: The insulating layer 11 between two adjacent transverse grooves T is thinned, and the transverse grooves T are expanded along a direction perpendicular to the substrate 10, such as... Figure 11 As shown.

[0156] like Figure 11 As shown, the thinned insulating layer 11 includes an integrally connected first end 111 and second end 112; the thickness of the first end 111 is less than the thickness of the second end 112; the semiconductor layer 12 surrounds the second end 112 and is exposed at the first end 111.

[0157] The semiconductor device of this application embodiment can increase the placement area of ​​the first capacitor electrode 21 subsequently formed at that end and the contact area between the first capacitor electrode 21 and the second capacitor electrode 22 by thinning one end of the insulating layer 11, thereby increasing the capacitance in a limited storage area.

[0158] S90: A first capacitor electrode 21, a dielectric layer 23, and a second capacitor electrode 22 are sequentially formed within the through-hole K and the expanded transverse groove T, resulting in the following: Figure 1 The semiconductor device shown.

[0159] This application also provides an electronic device, which includes the semiconductor device described above, or includes a semiconductor device obtained by the manufacturing method described above.

[0160] In some embodiments of this application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0161] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A semiconductor device, characterized in that, include: Multiple storage cells are distributed in different layers, stacked and spaced apart along a direction perpendicular to the substrate; An insulating layer and a semiconductor layer are alternately distributed from bottom to top along a direction perpendicular to the substrate; adjacent memory cells are insulated from each other by the insulating layer; each memory cell includes the semiconductor layer; The substrate has a protective layer on the side closest to the memory cell; The etching selectivity ratio of the insulating layer to the protective layer is not less than 5:1, and the etching selectivity ratio of the semiconductor layer to the protective layer is not less than 5:

1.

2. The semiconductor device according to claim 1, characterized in that, The protective layer contains any one or more of silicon nitride, silicon boron nitride, and silicon carbonitride.

3. The semiconductor device according to claim 1, characterized in that, The insulating layer includes a first end and a second end, which are integral structures; the thickness of the first end is less than the thickness of the second end; the semiconductor layer surrounds the second end and is exposed at the first end.

4. The semiconductor device according to claim 3, characterized in that, There is no overlap between the orthographic projection of the first end on the substrate and the orthographic projection of the semiconductor layer on the substrate.

5. The semiconductor device according to claim 1, characterized in that, The thickness of the protective layer is not less than 20 nm.

6. The semiconductor device according to claim 3 or 4, characterized in that, The storage cell includes a capacitor, and the protective layer is located between the capacitor and the substrate; The capacitor includes a first capacitor electrode, a second capacitor electrode, and a dielectric layer located between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode is connected to the semiconductor layer. The first capacitor electrode covers the opposing surfaces of the first ends of the two adjacent layers and the sidewalls of the semiconductor layer.

7. The semiconductor device according to claim 6, characterized in that, The first capacitor electrodes of the plurality of memory cells spaced apart along a direction perpendicular to the substrate are disconnected from each other; The dielectric layer of the plurality of memory cells spaced apart along a direction perpendicular to the substrate is a single, integral structure; and / or, The second capacitor electrodes of the plurality of memory cells, which are spaced apart along a direction perpendicular to the substrate, are an integral structure.

8. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure is obtained by sequentially and alternately forming a first film layer and a second film layer on a substrate. An opening is formed in the stacked structure that extends toward the substrate, the opening exposing the first film layer located at the bottom layer; An etching barrier layer is formed on the sidewall of the opening; Remove the first film layer located at the bottom of the opening to expose the substrate; Impurity ions are doped into the substrate to form a protective layer on the surface of the substrate. Wherein, the etching selectivity ratio of the first film layer to the protective layer is not less than 5:1, and the etching selectivity ratio of the second film layer to the protective layer is not less than 5:

1.

9. The manufacturing method according to claim 8, characterized in that, The doping of impurity ions into the substrate includes: Nitrogen-containing impurities are doped into the substrate using a plasma implantation process.

10. The manufacturing method according to claim 8, characterized in that, The doping concentration of the impurity ions is not less than 1076 ions / cm³. 2 .

11. The manufacturing method according to claim 9, characterized in that, The substrate is made of silicon, and the protective layer contains any one or more of silicon nitride, silicon boron nitride, and silicon carbonitride.

12. The manufacturing method according to any one of claims 8 to 11, characterized in that, The first film layer is a sacrificial layer, and the second film layer is a semiconductor layer; The manufacturing method further includes: after doping the substrate with impurity ions. Replace the sacrificial layer with an insulating layer; Laterally etch the exposed semiconductor layer within the opening to form a lateral groove between two adjacent insulating layers; The insulating layer between two adjacent transverse grooves is thinned, and the transverse grooves are expanded in a direction perpendicular to the substrate. A first capacitor electrode, a dielectric layer, and a second capacitor electrode are sequentially formed within the opening and the expanded transverse groove to obtain a capacitor.

13. The manufacturing method according to claim 12, characterized in that, The step of replacing the sacrificial layer with an insulating layer includes: Remove the etching barrier layer on the sidewall of the opening to expose the sacrificial layer and the semiconductor layer; The exposed sacrificial layer is etched laterally within the opening to remove the sacrificial layer; An insulating layer is formed on the substrate to fill the gap between two adjacent semiconductor layers and to cover the sidewalls of the opening; Remove the insulating layer located on the sidewall of the opening, and retain the insulating layer located between two adjacent semiconductor layers.

14. An electronic device, characterized in that, It includes the semiconductor device according to any one of claims 1 to 7, or the semiconductor device obtained by the manufacturing method according to any one of claims 8 to 13.

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