Method for forming an oxide layer of a cis

Abstract

This application provides a method for forming an oxide layer in a CIS (CMOS Image Sensor), comprising: providing a substrate having pixel trenches and logic trenches, wherein the pixel trenches isolate pixel units in the pixel region, and the logic trenches include a first trench and a second trench that isolates logic devices in the logic region, the bottom end of the first trench being lower than the top end of the substrate in the pixel region, and the planar area of ​​the top end of the substrate in the pixel region being larger than the area inside the trench of the logic region; forming an initial oxide layer on the surface of the substrate, the initial oxide layer filling the pixel trenches; forming a spin-coated dielectric layer on the initial oxide layer, the thickness of the spin-coated dielectric layer in the first trench being greater than the thickness of the spin-coated dielectric layer in the pixel region; performing a first dry etching until the initial oxide layer in the pixel region is exposed; performing a second dry etching, wherein the initial oxide layer in the pixel region is thinned, and during the second dry etching process, the spin-coated dielectric layer in the first trench protects the initial oxide layer below it. This application is beneficial for avoiding the short-circuit risk of the logic region while improving the optical performance of the CIS.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a method for forming an oxide layer in CIS. Background Technology

[0002] In the fabrication of complementary metal oxide semiconductor image sensors (CIS), taking backside illumination image sensors (BSI) as an example, BSI often uses a grid structure composed of insulating and metal layers to reduce optical crosstalk between adjacent pixel units. The closer the grid metal layer is to the back of the substrate, the more significant the optical crosstalk suppression effect. At the same time, BSI often uses a deep trench isolation (DTI) structure to fabricate on the back of the substrate to reduce electrical signal interference between adjacent pixel units.

[0003] As the performance requirements for CIS (Computer Integrated Systems) such as resolution and imaging quality continue to increase, the depth of DTI (Distributed Ionization Technology) is also gradually increasing. To ensure the white pixel (WP) performance of the product, DTI requires a thicker oxide layer. In addition, to increase the distance between the metal interconnects and the polysilicon interface and avoid the risk of short circuits, the CIS logic region requires a thicker oxide layer. If the oxide layer of the logic region is thickened by directly depositing and thickening the oxide layer of the entire substrate surface, the grid metal layer of the pixel region will be forced away from the substrate direction, weakening the optical crosstalk suppression capability of the grid structure, and thus reducing the optical performance of the CIS. Summary of the Invention

[0004] This application provides a method for forming an oxide layer in a CIS (Computer Integrated System). This method can reduce the oxide layer on top of the pixel area substrate while ensuring the thickness of the oxide layer in the logic area. This is beneficial for ensuring the insulation between the logic area metal lines and polysilicon, avoiding the risk of short circuits, and also for improving the optical performance of the CIS.

[0005] In view of this, this application provides a method for forming an oxide layer in a CIS, comprising:

[0006] A substrate is provided having pixel trenches and logic area recesses. The pixel trenches isolate pixel units of the pixel area, and the logic area recesses include a first recess and a second recess. The bottom end of the first recess is lower than the top end of the substrate of the pixel area, and the second recess is used to form a metal contact plug. The planar area of ​​the top end of the substrate of the pixel area is larger than the area inside the groove of the logic area recess.

[0007] An initial oxide layer is formed on the surface of the substrate, and the initial oxide layer fills the pixel area trenches;

[0008] A spin-coating medium layer is formed on the initial oxide layer, wherein the thickness of the spin-coating medium layer in the first groove is greater than the thickness of the spin-coating medium layer in the pixel area;

[0009] Perform the first dry etching until the initial oxide layer of the pixel area is exposed. After the first dry etching, spin-coat the remaining part of the first groove with a dielectric layer.

[0010] A second dry etching process is performed, which thins the initial oxide layer in the pixel area. During the second dry etching process, the remaining spin-coated dielectric layer in the first groove protects the initial oxide layer underneath. After the second dry etching process, the spin-coated dielectric layer in the logic area is removed.

[0011] Optionally, an opening is formed in the second groove after the initial oxide layer is formed.

[0012] Optionally, the spin coating medium layer of the logic area includes a first spin coating medium layer and a second spin coating medium layer, wherein the first spin coating medium layer is located in the first groove, and the second spin coating medium layer is located below the first spin coating medium layer and fills the opening.

[0013] Optionally, during the second dry etching process, the initial oxide layer in the pixel area is thinned until the initial oxide layer below the spin-coated dielectric layer in the first groove is exposed.

[0014] Optionally, the spin-coated medium layer includes a spin-coated carbon layer.

[0015] Optionally, the initial oxide layer includes a silicon oxide layer.

[0016] Optionally, the pixel area trench is a deep trench isolation structure.

[0017] Optionally, the initial oxide layer is formed on the back side of the substrate.

[0018] Optionally, the method is applied to the CSI fabrication process, and the method further includes: forming a grid structure on the oxide layer that has been thinned in the pixel area after a second dry etching.

[0019] The technical solution of this application has at least the following advantages:

[0020] This application forms an initial oxide layer on the exposed surface of a substrate with pixel trenches and logic trenches. The initial oxide layer fills the pixel trenches, which helps improve the stability of the pixel trench structure, ensures the white point performance of the product, and also helps ensure the insulation between the logic metal lines and polysilicon, avoiding the risk of short circuits. By forming a spin-coated dielectric layer on the surface of the initial oxide layer, the thickness of the spin-coated dielectric layer in the first trench is greater than the thickness of the spin-coated dielectric layer in the pixel area. A first dry etching is performed until the initial oxide layer in the pixel area is exposed. A second dry etching is then performed, thinning the initial oxide layer in the pixel area. During the second dry etching process, the spin-coated dielectric layer in the first trench protects the initial oxide layer below it. The initial oxide layer in the pixel area can be thinned without changing the thickness of the oxide layer in the logic area, thereby forming an oxide layer morphology with a thick oxide layer on top of the logic area substrate and a thin oxide layer on top of the pixel area substrate. This helps ensure the insulation between the logic metal lines and polysilicon, avoiding the risk of short circuits. At the same time, it also helps to bring the gate metal layer closer to the substrate, improving the optical performance of the CIS. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a process flow diagram of a method for forming an oxide layer of a CIS provided in an exemplary embodiment of this application;

[0023] Figure 2 This is a schematic cross-sectional view of a substrate with pixel area trenches and logic area recesses provided in an exemplary embodiment of the present application for the oxide layer formation method of CIS;

[0024] Figure 3 This is a cross-sectional schematic diagram of the oxide layer after formation in the CIS oxide layer formation method provided in an exemplary embodiment of this application;

[0025] Figure 4 This is a schematic cross-sectional view of the spin-coating medium after formation in the CIS oxide layer formation method provided in an exemplary embodiment of this application;

[0026] Figure 5 This is a schematic cross-sectional view after the first dry etching in the oxide layer formation method of CIS provided in an exemplary embodiment of this application;

[0027] Figure 6This is a schematic cross-sectional view after the second dry etching in the oxide layer formation method of CIS provided in an exemplary embodiment of this application;

[0028] Figure 7 This is a schematic cross-sectional view of the CIS oxide layer formation method provided in an exemplary embodiment of this application after the spin-coating medium has been completely removed;

[0029] The numbers in the diagram represent:

[0030] 100. Substrate; 110. Pixel area; 111. Pixel area trench; 120. Logic area; 121. First groove; 122. Second groove; 123. Opening;

[0031] 200. Initial oxide layer;

[0032] 300, Spin-coated medium layer; 310, First spin-coated medium layer; 320, Second spin-coated medium layer; Detailed Implementation

[0033] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0036] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0037] The following is combined Figures 1 to 7 This describes an embodiment of the present application.

[0038] refer to Figure 1 This illustrates an embodiment of the present application, providing a method for forming an oxide layer of a CIS, comprising:

[0039] S1, a substrate 100 is provided with a pixel area trench 111 and a logic area groove. The pixel area trench 111 isolates the pixel units of the pixel area 110. The logic area groove includes a first groove 121 and a second groove 122. The bottom end of the first groove 121 is lower than the top end of the substrate 100 of the pixel area. The second groove 122 is used to form a metal contact plug. The planar area of ​​the top end of the substrate 100 of the pixel area is larger than the groove area of ​​the logic area groove.

[0040] For example, the substrate 100 can be a silicon substrate, a germanium (Ge) substrate, a gallium arsenide (GaAs) substrate, or other materials suitable for CIS manufacturing. The pixel trench 111 can be a deep trench isolation structure, and the second groove 122 in the logic region groove can be a contact hole. The formation of the pixel trench 111 in the substrate 100 can be achieved using a DTI process, and the formation of the logic region groove in the substrate 100 can be achieved using photolithography and etching processes.

[0041] S2, an initial oxide layer 200 is formed on the surface of the substrate 100, and the initial oxide layer 200 fills the pixel area trench 111.

[0042] For example, the initial oxide layer 200 formed on the surface of the substrate 100 can be achieved by a deposition process, such as chemical vapor deposition (CVD).

[0043] It should be noted that the surface of the substrate 100 includes the inner surface of the pixel trench 111, the top surface of the substrate in the pixel area, and the inner surface of the logic area groove. The initial oxide layer 200 formed includes the oxide layer in the pixel trench, the oxide layer at the top surface of the substrate in the pixel area, and the oxide layer in the logic area groove.

[0044] In some embodiments, after the initial oxide layer 200 is formed, an opening 123 is formed in the second groove 122.

[0045] In some embodiments, the initial oxide layer 200 includes a silicon oxide (SiO2) layer.

[0046] In some embodiments, an initial oxide layer 200 is formed on the back side of the substrate 100.

[0047] S3, a spin coating medium layer 300 is formed on the initial oxide layer 200, wherein the thickness of the spin coating medium layer 300 in the first groove 121 is greater than the thickness of the spin coating medium layer 300 in the pixel area.

[0048] For example, the spin-coating dielectric layer 300 formed on the initial oxide layer 200 can be achieved using a spin coating process. Since the top plane area of ​​the substrate in the pixel region is larger than the groove area in the logic region, the thickness of the spin-coating dielectric layer 300 formed in the first groove 121 is greater than the thickness of the spin-coating dielectric layer 300 formed in the pixel region.

[0049] In some embodiments, the spin-coated medium layer 300 includes a spin-on carbon (SOC) layer.

[0050] In some embodiments, an opening 123 is formed in the second groove 122, and the spin coating medium layer 300 of the logic area includes a first spin coating medium layer 310 and a second spin coating medium layer 320. The first spin coating medium is located in the first groove 121, and the second spin coating medium layer 320 is located below the first spin coating medium layer 310 and fills the opening 123.

[0051] S4, perform the first dry etching until the initial oxide layer 200 of the pixel area is exposed. After the first dry etching, spin-coate the remaining portion of the first groove 121 with the dielectric layer 300.

[0052] The spin-coated medium layer 300 in the pixel area is completely removed by the first dry etching. The etching stops at the initial oxide layer 200 in the pixel area. Since the thickness of the spin-coated medium layer 300 in the first groove 121 is greater than the thickness of the spin-coated medium layer 300 in the pixel area, after the first dry etching, the remaining part of the spin-coated medium layer 300 in the first groove 121 is removed.

[0053] S5, a second dry etching is performed, and the initial oxide layer 200 of the pixel area is thinned. During the second dry etching process, the spin-coated medium layer 300 remaining in the first groove 121 protects the initial oxide layer 200 below it. After the second dry etching, the spin-coated medium layer 300 of the logic area is removed.

[0054] For example, by adjusting the etching selectivity ratio of the initial oxide layer 200 to the spin-coated dielectric layer 300, for example, by an etching selectivity ratio greater than 10:1, the initial oxide layer 200 in the pixel area is etched quickly, while the remaining spin-coated dielectric layer 300 in the first groove 121 is etched slowly. This allows the initial oxide layer 200 in the pixel area to be thinned without changing the thickness of the oxide layer in the logic area, forming an oxide layer morphology with a thick oxide layer on top of the logic area substrate and a thin oxide layer on top of the pixel area substrate. This morphology helps to ensure the insulation between the logic area metal lines and the polysilicon, avoiding the risk of short circuits. At the same time, it also helps to bring the grid metal layer closer to the substrate 100, improving the optical performance of the CIS.

[0055] In some embodiments, during the second dry etching process, the initial oxide layer 200 of the pixel region is thinned until the initial oxide layer 200 below the spin-coated medium layer in the first groove 121 is exposed.

[0056] In some embodiments, the oxide layer formation method of CIS provided in this application is applied to the CIS fabrication process. The method further includes: forming a grid structure on the oxide layer of the pixel area after a second dry etching.

[0057] Applying the oxide layer formation method of CIS provided in this application to the CIS fabrication process can form an oxide layer morphology of a thick oxide layer on top of the logic region substrate and a thin oxide layer on top of the pixel region substrate. This is beneficial to ensure the insulation performance between the logic region metal lines and polysilicon, while making the metal layer in the lattice structure closer to the substrate 100, thereby improving the optical performance of CIS.

[0058] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method of forming an oxide layer of a CIS, characterized by, include: A substrate is provided having pixel trenches and logic area recesses. The pixel trenches isolate pixel units of the pixel area, and the logic area recesses include a first recess and a second recess. The bottom end of the first recess is lower than the top end of the substrate of the pixel area, and the second recess is used to form a metal contact plug. The planar area of ​​the top end of the substrate of the pixel area is larger than the area inside the groove of the logic area recess. An initial oxide layer is formed on the surface of the substrate, and the initial oxide layer fills the pixel area trenches; A spin-coating medium layer is formed on the initial oxide layer, wherein the thickness of the spin-coating medium layer in the first groove is greater than the thickness of the spin-coating medium layer in the pixel area; Perform the first dry etching until the initial oxide layer of the pixel area is exposed. After the first dry etching, spin-coat the remaining part of the first groove with a dielectric layer. A second dry etching process is performed, which thins the initial oxide layer in the pixel area. During the second dry etching process, the remaining spin-coated dielectric layer in the first groove protects the initial oxide layer underneath. After the second dry etching process, the spin-coated dielectric layer in the logic area is removed.

2. The method of claim 1, wherein, include: After the initial oxide layer is formed, an opening is formed in the second groove.

3. The method according to claim 2, characterized in that, The spin coating medium layer of the logic area includes a first spin coating medium layer and a second spin coating medium layer. The first spin coating medium layer is located in the first groove, and the second spin coating medium layer is located below the first spin coating medium layer and fills the opening.

4. The method according to claim 1, characterized in that, During the second dry etching process, the initial oxide layer in the pixel area is thinned until the initial oxide layer below the spin-coated dielectric layer in the first groove is exposed.

5. The method according to claim 1, characterized in that, The spin-coated medium layer includes a spin-coated carbon layer.

6. The method according to claim 1, characterized in that, The initial oxide layer includes a silicon oxide layer.

7. The method according to claim 1, characterized in that, The pixel area trench is a deep trench isolation structure.

8. The method according to any one of claims 1-7, characterized in that, The initial oxide layer is formed on the back side of the substrate.

9. The method according to claim 8, characterized in that, The method is applied in the CSI fabrication process, and the method further includes: forming a grid structure on the oxide layer of the pixel area after the second dry etching.

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