Method for reducing loss of cutting efficiency of battery piece

Abstract

This application discloses a method for reducing the efficiency loss during solar cell cutting, relating to the field of solar cell technology. The method includes: providing an N-type silicon wafer; performing boron diffusion on the N-type silicon wafer; removing the PN junction in the laser-cut region of the boron-diffused silicon wafer; growing a tunneling layer on the surface of the N-type silicon wafer; growing a polycrystalline silicon layer on the surface of the tunneling layer; performing phosphorus diffusion on the polycrystalline silicon layer on the back side of the N-type wafer; and removing the PN junction in the laser-cut region of the phosphorus-diffused silicon wafer. The method provided in this application, by removing the PN junction in the laser-cut region in advance after both boron and phosphorus diffusion, can significantly reduce the probability of hole-electron recombination during the cutting process, thereby reducing the efficiency loss during solar cell cutting.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a method for reducing the efficiency loss during cell cutting. Background Technology

[0002] With the rapid development of photovoltaic technology, N-type TopCon (Tunnel Oxide Passivated Contact) solar cells have become one of the important technical routes in the photovoltaic industry due to their high conversion efficiency and low light-induced degradation characteristics. To improve the output power of photovoltaic modules and reduce the risk of hot spot effects, the conventional practice is to cut the finished N-type TopCon cells into half pieces along the central axis and then assemble them by stringing.

[0003] In existing production processes, laser cutting is the mainstream method for dividing solar cells. However, research has found that the laser cutting process can cause thermal damage to the cut surface area of ​​the solar cell, especially for N-type TopCon cells. Test data shows that carrier recombination generated at the cut surface can cause a 0.2%-0.4% decrease in half-cell conversion efficiency. Summary of the Invention

[0004] In view of this, this application provides a method for reducing the efficiency loss of solar cell cutting, with the aim of solving one of the technical problems in the prior art.

[0005] To achieve the above objectives, the technical solution adopted in this application is as follows: In a first aspect, the present invention provides a method for reducing the efficiency loss during solar cell cutting, comprising: Provide N-type silicon wafers and perform boron diffusion on the N-type silicon wafers; For boron-diffused silicon wafers, remove the PN junction in the laser-cut area; A tunneling layer is grown on the surface of an N-type silicon wafer, a polycrystalline silicon layer is grown on the surface of the tunneling layer, and phosphorus diffusion is performed on the polycrystalline silicon layer on the back side of the N-type wafer. For silicon wafers after phosphorus diffusion, remove the PN junction in the laser-cut area.

[0006] In an optional implementation, for a boron-diffused silicon wafer, removing the PN junction in the laser-cut region includes: On the front side of the boron-diffused silicon wafer, the back gate lines in the laser-cut area are removed, and the removed area is etched to remove the PN junction.

[0007] In an optional implementation, the back-side gate lines in the laser-cut area are removed from the back side of the boron-diffused silicon wafer, and the removed area is etched.

[0008] In an optional implementation, the back-side grid lines in the laser-cut area are removed, and the removed area is etched, including: Laser is used to remove the back grid lines in the cutting area, with a laser spot width of 200-400μm and a laser power of 65%-85%. The removed area was subjected to alkaline polishing etching to a depth of 1-2 μm.

[0009] In an optional embodiment, the alkaline polishing process involves 12-20L of NaOH, a temperature of 70-80℃, 3-6L of additives, and 450-500L of water. The additive components are: surfactant 2-3%, defoamer 2-3%, antifoamer 2-4%, glucose 2-3%, sodium polystyrene sulfonate 2-3%, and water 80-85%; the surfactant is sodium polyoxyethylene ether sulfate, the defoamer is oxypropylene glycerol ether, and the antifoamer is polydimethylsiloxane.

[0010] In an optional implementation, removing the PN junction in the laser-cut region of the phosphorus-diffused silicon wafer includes: On the back side of the phosphorus-diffused silicon wafer, the phosphorus-diffused polysilicon layer in the laser-cut area is removed, and the removed area is etched.

[0011] In an optional implementation, removing the PN junction in the laser-cut region of the phosphorus-diffused silicon wafer includes: On the front side of the phosphorus-diffused silicon wafer, the phosphorus-diffused polysilicon layer in the laser-cut area is removed, and the removed area is etched.

[0012] In an optional implementation, the polysilicon layer in the laser-cut area is removed to expose the surface of the N-type silicon wafer. The removed area is then etched to expose the surface of the N-type silicon wafer, with an etching depth of 4-8 μm. Remove the polysilicon layer in the laser-cut area to expose the surface of the back side of the N-type silicon wafer. Etch the removed area to etch the exposed N-type silicon wafer surface to a depth of 1-2 μm.

[0013] In an optional implementation, removing the phosphorus-diffused polysilicon layer in the laser-cut region and etching the removed region includes: The phosphorus-diffused polycrystalline silicon layer in the cutting area is removed using a laser with a laser spot width of 200-400 μm and a laser power of 50%-70%. The removed area is then subjected to wet chemical etching.

[0014] In an optional embodiment, the wet chemical etching setup includes 16-24L NaOH, 400-500L water, 3-7L additives, and a temperature of 70-85℃.

[0015] Compared to existing technologies, the beneficial effects of this application are as follows: This application proposes a method to reduce the efficiency loss during solar cell cutting, comprising: providing an N-type silicon wafer; performing boron diffusion on the N-type silicon wafer; removing the PN junction in the laser-cut region of the boron-diffused silicon wafer; growing a tunneling layer on the surface of the N-type silicon wafer; growing a polycrystalline silicon layer on the surface of the tunneling layer; performing phosphorus diffusion on the polycrystalline silicon layer on the back side of the N-type wafer; and removing the PN junction in the laser-cut region of the phosphorus-diffused silicon wafer. By removing the PN junction in the laser-cut region in advance after boron diffusion and phosphorus diffusion, the probability of hole-electron recombination can be greatly reduced during the cutting process, thereby reducing the efficiency loss during solar cell cutting. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 The diagram shows the structure of the battery cells after cutting in some embodiments of this application.

[0018] Explanation of key component symbols: 110 - N-type silicon wafer; 120 - tunneling layer; 130 - polysilicon layer; 140 - passivated emitter; 151 - aluminum oxide layer; 152 - silicon nitride layer; 160 - electrode layer; P1 - front laser-cut area; P2 - back laser-cut area. Detailed Implementation

[0019] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0020] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0022] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0023] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0024] For N-type TopCon cells, test data shows that carrier recombination generated at the cut surface can cause a 0.2%-0.4% decrease in half-cell conversion efficiency.

[0025] A systematic study of the damage mechanism at the cut surface revealed that the boron-doped PN junction on the front side of the TopCon battery accumulates a large number of hole-electron recombination centers after laser cutting. Experimental data shows that this carrier recombination phenomenon accounts for approximately 50% of the overall efficiency degradation of the battery. Simultaneously, the study also found that the phosphorus-doped polycrystalline silicon layer on the back side of the TopCon battery also forms a certain number of hole-electron recombination centers, and the resulting carrier recombination accounts for approximately 20% of the total efficiency degradation.

[0026] To address the aforementioned problems, embodiments of this application provide a method for reducing the efficiency loss during solar cell cutting, comprising: Step S10: Provide an N-type silicon wafer and perform boron diffusion on the N-type silicon wafer.

[0027] Step S11: Perform double-sided texturing on the N-type silicon wafer.

[0028] Choose a solution containing 12-20L NaOH, 3-6L of texturing additive, 450-500L of water, and a temperature of 75-85℃.

[0029] The composition of the flocking additive is 2-3% surfactant, 1-3% defoamer, 1-1.5% nucleating agent, 0.5-1% sodium citrate, 4-6% sodium benzoate, and 85-90% water; the surfactant includes sodium polyoxyethylene ether sulfate, the defoamer can be oxypropylene glycerol ether, and the nucleating agent can be sodium citrate.

[0030] The reflectivity of the velvet surface is 9%-10%.

[0031] Step S12: Boron diffusion is performed on the N-type silicon wafer.

[0032] Heat the silicon wafer to 830-870℃, introduce BCL3 at a flow rate of 160-220 sccm / min, oxygen at 700-900 sccm / min, pressure of 120-180 mbar, and nitrogen at 1500-3000 sccm / min, for a processing time of 10-15 min.

[0033] The silicon wafer is then heated to 1020-1050℃, oxygen is introduced at 15000-20000 sccm / min for 65 min (50-80 min), and the pressure is 700-950 mbar; the thickness of the back gate line is 80-100 nm, and the boron expansion sheet resistance is 300-400 Ω.

[0034] Step S20: Remove the PN junction in the laser-cut area of ​​the boron-diffused silicon wafer.

[0035] After boron diffusion, by removing the PN junction in the laser-cut area in advance, the probability of hole-electron recombination during the cutting process can be greatly reduced, thereby reducing the efficiency loss of the solar cell during cutting.

[0036] Step S30: A tunneling layer is grown on the surface of an N-type silicon wafer, a polycrystalline silicon layer is grown on the surface of the tunneling layer, and phosphorus diffusion is performed on the polycrystalline silicon layer on the back side of the N-type wafer.

[0037] Step S31: A tunneling layer is grown on the back side of an N-type silicon wafer, with an oxygen flow rate of 250-350L, an oxidation temperature of 600-640℃, a duration of 10-30min, and a pressure of 650-900mbar.

[0038] The thickness of the tunneling layer is 1.5-3 nm.

[0039] Step S32: A polycrystalline silicon layer and an aluminum oxide layer are grown on the surface of the tunneling layer.

[0040] Silane flow rate 800-1200 sccm / min, temperature 600-630℃, time 1700-2100 s, pressure 25-30 mabr.

[0041] The thickness of the polycrystalline silicon layer is 110-150nm.

[0042] Step S33: Phosphorus diffusion is performed on the polycrystalline silicon layer on the N-type back side.

[0043] Phosphorus oxychloride flow rate: 1200-1600 sccm / min; oxygen flow rate: 500-700 sccm / min; pressure: 120-180 mbar; duration: 14-20 min; temperature: 785-805℃. The silicon wafer is then heated to 870-890℃ and advanced for 25-35 minutes, resulting in a phosphorus atom surface concentration of 6.8E20 / cm². 3 The thickness of the phosphorus-diffused polycrystalline silicon layer is 35 nm.

[0044] Step S40: Remove the PN junction in the laser-cut area of ​​the phosphorus-diffused silicon wafer.

[0045] By removing the PN junction in the laser-cut area in advance, the finished solar cell is free of doped layers in the laser-cut area, reducing carrier recombination and decreasing the cutting efficiency loss of the solar cell from 0.3% to 0.1%, which means the cell efficiency is improved by 0.2% after cutting.

[0046] In some embodiments, removing the PN junction in the laser-cut region of a boron-diffused silicon wafer includes: Step S21: On the front side of the boron-diffused silicon wafer, remove the back gate lines in the laser-cut area and etch the removed area to remove the PN junction.

[0047] Step S22: On the back side of the boron-diffused silicon wafer, remove the back gate lines in the laser-cut area and etch the removed area.

[0048] Through systematic research on the damage mechanism of the cut surface, it was found that after the TopCon battery undergoes laser cutting, a large number of hole-electron recombination centers will accumulate in the PN junction formed by boron doping on the front side.

[0049] Based on the above, after boron diffusion, the back-side gate lines in the laser-cut area on the front side of the N-type silicon wafer need to be removed, and the removed area needs to be etched to reduce the probability of hole-electron recombination and decrease the efficiency loss of the solar cell. In some embodiments, the same operation can also be performed on the back side of the N-type silicon wafer, which also reduces the probability of hole-electron recombination and decreases the efficiency loss of the solar cell.

[0050] In some embodiments, removing the back-side grid lines in the laser-cut area and etching the removed area includes: First, the back grid lines in the cutting area are removed by laser, and then the back grid lines in the cutting area are removed by etching. The laser spot width is 200-400μm, the laser power is 65%-85%, and the etching uses a chain HF500-600L and water 50-100L.

[0051] Specifically, the laser spot width is 200μm, 220μm, 240μm, 260μm, 280μm, 300μm, 320μm, 340μm, 360μm, 380μm, 400μm, etc., and is not limited to the values ​​in the examples.

[0052] Specifically, the laser power is 65%, 66%, 67%, 68%, 69%, 70%, 71%, 72%, 73%, 74%, 75%, 76%, 77%, 78%, 79%, 80%, 81%, 82%, 83%, 84%, 85%, etc., and is not limited to the values ​​in the examples.

[0053] Specifically, the chain HF values ​​are 500L, 510L, 520L, 530L, 540L, 550L, 560L, 570L, 580L, 590L, 600L, etc., and are not limited to the values ​​in the examples.

[0054] Specifically, the water volume is 50L, 55L, 60L, 65L, 70L, 75L, 80L, 85L, 90L, 95L, 100L, etc., and is not limited to the values ​​in the examples.

[0055] In some embodiments, the removed area is subjected to alkaline polishing etching to a depth of 1-2 μm.

[0056] The etching depths are 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm, 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2μm, etc., and are not limited to the depths in the examples.

[0057] In some embodiments, the alkaline polishing corrosion setup is as follows: 12-20L NaOH, 70-80℃, 3-6L additives, and 450-500L water.

[0058] Specifically, the NaOH concentrations are 12L, 13L, 14L, 15L, 16L, 17L, 18L, 19L, 20L, etc., and are not limited to the values ​​in the examples.

[0059] Specifically, the temperatures are 70℃, 71℃, 72℃, 73℃, 74℃, 75℃, 76℃, 77℃, 78℃, 79℃, 80℃, etc., and are not limited to the values ​​in the examples.

[0060] Specifically, the water volume is 450 L, 460 L, 470 L, 480 L, 490 L, 500 L, etc., and is not limited to the values ​​in the examples.

[0061] Specifically, the additives are available in 3L, 4L, 5L, 6L, etc., and are not limited to the values ​​shown in the examples.

[0062] In one embodiment, the additive components are: 2-3% surfactant, 2-3% defoamer, 2-4% antifoamer, 2-3% glucose, 2-3% sodium polystyrene sulfonate, and 80-85% water; the surfactant is sodium polyoxyethylene ether sulfate, the defoamer is oxypropylene glycerol ether, and the antifoamer is polydimethylsiloxane.

[0063] Through systematic research on the damage mechanism of the cut surface, it was found that the phosphorus-doped polycrystalline silicon layer on the back of the TopCon battery also forms a certain number of hole-electron recombination centers, and the efficiency loss caused by the carrier recombination is about 20% of the total efficiency decay.

[0064] Based on the above, and in conjunction with the references Figure 1 After phosphorus diffusion, the phosphorus-diffused polysilicon in the laser-cut area needs to be removed from the back side of the N-type silicon wafer, and the removed area needs to be etched to reduce the probability of hole-electron recombination and reduce the efficiency loss of the solar cell. In some embodiments, the same operation can also be performed on the front side of the N-type silicon wafer, which also reduces the probability of hole-electron recombination and reduces the efficiency loss of the solar cell.

[0065] In one embodiment, removing the PN junction in the laser-cut region of the phosphorus-diffused silicon wafer includes: Step S41: On the back side of the phosphorus-diffused silicon wafer, remove the phosphorus-diffused polysilicon layer in the laser-cut area and etch the removed area.

[0066] Specifically, in step S411, the phosphorus-diffused polysilicon layer in the laser-cut area is first removed by laser, and then the phosphorus-diffused polysilicon layer in the laser-cut area is removed by etching.

[0067] The phosphorus-diffused polycrystalline silicon layer in the laser-cut area is removed by using a laser with a laser spot width of 200-400μm and a laser power of 50%-70%.

[0068] Specifically, the laser spot width is 200μm, 220μm, 240μm, 260μm, 280μm, 300μm, 320μm, 340μm, 360μm, 380μm, 400μm, etc., and is not limited to the values ​​in the examples.

[0069] Specifically, the laser power is 50%, 51%, 52%, 53%, 54%, 55%, 56%, 57%, 58%, 59%, 60%, 61%, 62%, 63%, 64%, 65%, 66%, 67%, 68%, 69%, 70%, etc., and is not limited to the values ​​in the examples.

[0070] The phosphorus-diffused polycrystalline silicon layer in the laser cutting area is then subjected to chain-type HF etching, with an HF concentration of 8-15%.

[0071] Step S412: Etch the removed area.

[0072] The wet chemical etching setup consists of 16-24L NaOH, 400-500L water, 3-7L additives, and a temperature of 70-85℃.

[0073] Specifically, the NaOH concentrations are 16L, 17L, 18L, 19L, 20L, 21L, 22L, 23L, 24L, etc., and are not limited to the values ​​shown in the examples.

[0074] Specifically, the water volume is 400 L, 410 L, 420 L, 430 L, 440 L, 450 L, 460 L, 470 L, 480 L, 490 L, 500 L, etc., and is not limited to the values ​​in the examples.

[0075] The additives are available in 3L, 4L, 5L, 6L, 7L, etc., and are not limited to the values ​​shown in the examples.

[0076] Specifically, the temperatures are 70℃, 71℃, 72℃, 73℃, 74℃, 75℃, 76℃, 77℃, 78℃, 79℃, 80℃, 81℃, 82℃, 83℃, 84℃, 85℃, etc., and are not limited to the values ​​in the examples.

[0077] Step S42: On the front side of the phosphorus-diffused silicon wafer, remove the phosphorus-diffused polysilicon layer in the laser-cut area and etch the removed area.

[0078] Specifically, in step S421, the phosphorus-diffused polysilicon layer in the laser-cut area is first removed by laser, and then the phosphorus-diffused polysilicon layer in the laser-cut area is removed by etching.

[0079] The phosphorus-diffused polycrystalline silicon layer in the laser-cut area is removed by using a laser with a laser spot width of 200-400μm and a laser power of 50%-70%.

[0080] Specifically, the laser spot width is 200μm, 220μm, 240μm, 260μm, 280μm, 300μm, 320μm, 340μm, 360μm, 380μm, 400μm, etc., and is not limited to the values ​​in the examples.

[0081] Specifically, the laser power is 50%, 51%, 52%, 53%, 54%, 55%, 56%, 57%, 58%, 59%, 60%, 61%, 62%, 63%, 64%, 65%, 66%, 67%, 68%, 69%, 70%, etc., and is not limited to the values ​​in the examples.

[0082] The phosphorus-diffused polycrystalline silicon layer in the laser cutting area is then subjected to chain-type HF etching, with an HF concentration of 8-15%.

[0083] Step S422: Etch the removed area.

[0084] The wet chemical etching setup consists of 16-24L NaOH, 400-500L water, 3-7L additives, and a temperature of 70-85℃.

[0085] Specifically, the NaOH concentrations are 16L, 17L, 18L, 19L, 20L, 21L, 22L, 23L, 24L, etc., and are not limited to the values ​​shown in the examples.

[0086] Specifically, the water volume is 400 L, 410 L, 420 L, 430 L, 440 L, 450 L, 460 L, 470 L, 480 L, 490 L, 500 L, etc., and is not limited to the values ​​in the examples.

[0087] The additives are available in 3L, 4L, 5L, 6L, 7L, etc., and are not limited to the values ​​shown in the examples.

[0088] Specifically, the temperatures are 70℃, 71℃, 72℃, 73℃, 74℃, 75℃, 76℃, 77℃, 78℃, 79℃, 80℃, 81℃, 82℃, 83℃, 84℃, 85℃, etc., and are not limited to the values ​​in the examples.

[0089] In some embodiments, the polysilicon layer in the laser-cut area is removed to expose the surface of the N-type silicon wafer. The removed area is then etched to expose the surface of the N-type silicon wafer, with an etching depth of 4-8 μm.

[0090] Specifically, etching depths of 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, etc., are not limited to the values ​​in the examples.

[0091] Remove the polysilicon layer in the laser-cut area to expose the surface of the back side of the N-type silicon wafer. Etch the removed area to etch the exposed N-type silicon wafer surface to a depth of 1-2 μm.

[0092] Specifically, etching depths of 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm, 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2μm, etc., are not limited to the values ​​in the examples.

[0093] The method for reducing the efficiency loss during solar cell cutting in this application also includes: Step S50: Perform ALD (Atomic Layer Deposition) on the front and back sides of the N-type silicon wafer, with a deposition thickness of 2.5-5nm, a silicon nitride thickness of 70-84nm on the front side, and a silicon nitride thickness of 75-90nm on the back side; print and sinter, with a sintering temperature of 780-840℃ and a sintering time of 40-70S.

[0094] The battery cells from steps S10 to S50 are sliced. (Refer to the reference.) Figure 1 The solar cell is cut along its central axis, removing the polycrystalline silicon layer 130 and passivated emitter 140 on the front side of the cell located in the laser-cut area. The tunneling layer 120 and polycrystalline silicon layer 130 on the back side of the cell, also located in the laser-cut area, are also removed. This achieves the goal of removing the PN junction at the corresponding laser-cut location in advance, greatly reducing the probability of hole-electron recombination and minimizing efficiency loss during cell cutting.

[0095] After the laser cutting process, the aluminum oxide layer 151 and silicon nitride layer 152 located in the laser cutting area on the front and back of the solar cell are removed, so that the two adjacent half solar cells are separated.

[0096] Example 1 Methods to reduce the efficiency loss during solar cell cutting include: Step S100: Double-sided texturing of the N-type silicon wafer is performed to ensure that the reflectivity of the texturized surface is between 9.5%. The selected solution is 16L NaOH, 4.0L texturing additive, 460L water, and the temperature is 75℃. The texturing additive consists of 2-3% surfactant, 1-3% defoamer, 1-1.5% nucleating agent, 0.5-1% sodium citrate, 4-6% sodium benzoate, and 85-90% water. The surfactant includes sodium polyoxyethylene ether sulfate, the defoamer can be oxypropylene glycerol ether, and the nucleating agent can be sodium citrate.

[0097] In step S200, the texturized silicon wafer is diffused. The silicon wafer is heated to 855°C, and the BCL3 flow rate is set to 180 sccm / min, oxygen to 750 sccm / min, pressure to 160 mbar, nitrogen to 2000 sccm / min, and time to 10 min. The silicon wafer is then heated to 1035°C, and the oxygen flow rate is set to 19000 sccm / min, heating time to 65 min, and pressure to 800 mbar.

[0098] The back-side gate line thickness is 90nm, and the boron-expanded sheet resistance is 350Ω.

[0099] Step S300: The diffused silicon wafer is subjected to laser removal of the back gate lines along the central axis. The laser area is a laser spot line with a width of 300um. The back gate lines in the spot area are removed; the back gate lines in the non-spot area have normal thickness; the laser power is 75%.

[0100] In step S400, the silicon wafer from step S300 is subjected to alkaline polishing to remove the back-side gate lines. The process involves using a chain of 550L HF and 50L water, followed by alkaline polishing with 16L NaOH at 70℃, 4.5L additives, and 470L water. After the back-side gate lines in the laser-cut area on the front side are removed, the area, lacking back-side gate line protection, is etched by alkaline polishing to a depth of 1.5µm.

[0101] In step S500, a 2.5nm tunnel oxide layer is grown on the silicon wafer from step S400, with an oxygen quantity of 330L, an oxidation temperature of 605℃, a growth time of 15min, and a pressure of 820mbar.

[0102] In step S600, a 135nm polycrystalline silicon passivation layer is grown on the silicon wafer from step S500, with the following settings: silane flow rate 1160 sccm / min, temperature 617℃, growth time 1800s, and pressure 29mabr.

[0103] In step S700, the silicon wafer from step S600 is phosphorus-doped with phosphorus oxychloride at a flow rate of 1550 sccm / min, oxygen at a flow rate of 600 sccm / min, a pressure of 170 mbar, for a duration of 17 min, and a temperature of 796°C. The silicon wafer is then heated to 886°C and advanced for 27 min, resulting in a phosphorus atom surface concentration of 6.8E20 / cm³. 3 The thickness of the phosphorus-diffused polycrystalline silicon is 35 nm.

[0104] In step S800, the back side of the silicon wafer in step S700 is subjected to laser dephosphorization diffusion polysilicon along the central axis. The laser area is a laser spot line with a width of 300um, which removes the phosphorus diffusion polysilicon in the spot area. The phosphorus diffusion polysilicon in the non-spot area has normal thickness. The laser power is 60%.

[0105] In step S900, the silicon wafer from step S800 is passed through a chain HF with the front side facing down, and the HF concentration is controlled at 9% to remove the phosphorus-diffused polysilicon on the front side; the silicon wafer is then subjected to wet chemical etching with 17L NaOH, 450L water, 4.0L additives, and a temperature of 75°C. Additive components: surfactant 1-2%, defoamer 2-3%, antifoamer 1-3%, glucose 2-4%, sodium dodecyl sulfonate 1-3%, water 80-85%; After the phosphorus-diffused polysilicon on the back side is removed, the polysilicon in the laser-cut area is completely removed by wet chemical etching, with an etching depth of 1.2 μm. The laser removal of the back gate lines and the phosphorus-diffused polysilicon area on the front side overlaps with the area of ​​subsequent laser cutting and dicing.

[0106] In step S1000, the silicon wafer is subjected to ALD deposition with a thickness of 3.5nm, a front silicon nitride thickness of 76nm, and a back silicon nitride thickness of 80nm. The wafer is then printed and sintered at a temperature of 810℃ for 50s.

[0107] In step S1100, the solar cell is laser-cut and diced along the central axis, and an efficiency test is performed. The dicing spot size is 50-150um. The position of the dicing area is consistent with the position of the area where the back grid lines and phosphorus-diffused polysilicon are removed. The width of the dicing area is smaller than the width of the area where the back grid lines and phosphorus-diffused polysilicon are removed, which reduces the appearance of new PN junctions. After the laser cutting process, the probability of hole-electron recombination is greatly reduced, and the efficiency loss of the solar cell is reduced.

[0108] Please refer to Table 1. The efficiency of half-cell cells prepared in steps S100 to S1100 is 26.65. Compared with conventional half-cell cells, the efficiency of cells in this application is improved by 0.23.

[0109] Furthermore, the efficiency of a half-cell cell with only the front side grid lines removed is 26.57, an improvement of 0.15 compared to a conventional half-cell cell; the efficiency of a half-cell cell with only the back polycrystalline silicon removed is 26.47, an improvement of 0.05 compared to a conventional half-cell cell. This indicates that either of these methods can effectively reduce the efficiency loss during cell cutting.

[0110] Table 1

[0111] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0112] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A method for reducing the efficiency loss during solar cell cutting, characterized in that, include: Provide N-type silicon wafers and perform boron diffusion on the N-type silicon wafers; For boron-diffused silicon wafers, remove the PN junction in the laser-cut area; A tunneling layer is grown on the surface of an N-type silicon wafer, a polycrystalline silicon layer is grown on the surface of the tunneling layer, and phosphorus diffusion is performed on the polycrystalline silicon layer on the back side of the N-type wafer. For silicon wafers after phosphorus diffusion, remove the PN junction in the laser-cut area.

2. The method for reducing the efficiency loss during battery cell cutting according to claim 1, characterized in that, For boron-diffused silicon wafers, the PN junction in the laser-cut region is removed, including: On the front side of the boron-diffused silicon wafer, the back gate lines in the laser-cut area are removed, and the removed area is etched to remove the PN junction.

3. The method for reducing the efficiency loss during battery cell cutting according to claim 2, characterized in that, On the back side of the boron-diffused silicon wafer, the back gate lines in the laser-cut area are removed, and the removed area is etched.

4. The method for reducing the efficiency loss during battery cell cutting according to claim 3, characterized in that, Remove the back-side grid lines in the laser-cut area and etch the removed area, including: Laser is used to remove the back grid lines in the cutting area, with a laser spot width of 200-400μm and a laser power of 65%-85%. The removed area was subjected to alkaline polishing etching to a depth of 1-2 μm.

5. The method for reducing the efficiency loss during battery cell cutting according to claim 4, characterized in that, Alkaline polishing corrosion setup: 12-20L NaOH, 70-80℃, 3-6L additives, 450-500L water; The additive components are: surfactant 2-3%, defoamer 2-3%, antifoamer 2-4%, glucose 2-3%, sodium polystyrene sulfonate 2-3%, and water 80-85%; the surfactant is sodium polyoxyethylene ether sulfate, the defoamer is oxypropylene glycerol ether, and the antifoamer is polydimethylsiloxane.

6. The method for reducing the efficiency loss of battery cell cutting according to claim 2 or 3, characterized in that, For phosphorus-diffused silicon wafers, the PN junction in the laser-cut area is removed, including: On the back side of the phosphorus-diffused silicon wafer, the phosphorus-diffused polysilicon layer in the laser-cut area is removed, and the removed area is etched.

7. The method for reducing the efficiency loss during battery cell cutting according to claim 6, characterized in that, For phosphorus-diffused silicon wafers, the PN junction in the laser-cut area is removed, including: On the front side of the phosphorus-diffused silicon wafer, the phosphorus-diffused polysilicon layer in the laser-cut area is removed, and the removed area is etched.

8. The method for reducing the efficiency loss of battery cell cutting according to claim 7, characterized in that, Remove the polysilicon layer in the laser-cut area to expose the surface of the N-type silicon wafer. Etch the removed area to etch the exposed N-type silicon wafer surface to a depth of 4-8 μm. Remove the polysilicon layer in the laser-cut area to expose the surface of the back side of the N-type silicon wafer. Etch the removed area to etch the exposed N-type silicon wafer surface to a depth of 1-2 μm.

9. The method for reducing the efficiency loss during battery cell cutting according to claim 8, characterized in that, The phosphorus-diffused polysilicon layer in the laser-cut area is removed, and the removed area is etched, including: The phosphorus-diffused polycrystalline silicon layer in the cutting area is removed using a laser with a laser spot width of 200-400 μm and a laser power of 50%-70%. The removed area is then subjected to wet chemical etching.

10. The method for reducing the efficiency loss during battery cell cutting according to claim 9, characterized in that, The wet chemical etching setup consists of 16-24L NaOH, 400-500L water, 3-7L additives, and a temperature of 70-85℃.

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