Solar cell and method for manufacturing solar cell

Abstract

The application discloses a solar cell and a manufacturing method thereof. The solar cell comprises a plurality of cell pieces, each of which comprises a silicon wafer, a plurality of first fine grids, a plurality of second fine grids and a plurality of conductive wires. The front surface and the back surface of the silicon wafer are printed with the first fine grids and the second fine grids. On any surface of the silicon wafer, the plurality of first fine grids are arranged on the silicon wafer in a dot-like manner at intervals. The silicon wafer is provided with the second fine grids at two oppositely arranged edges. The plurality of conductive wires are arranged at intervals. Any one of the conductive wires is connected with any plurality of the first fine grids, and the two ends of any one of the conductive wires are connected with the second fine grids at the two ends of the silicon wafer. Any two of the cell pieces are stacked, and the second fine grid on the front surface of one of the silicon wafers at least partially overlaps with the second fine grid on the back surface of the other silicon wafer. The solar cell can not only reduce the manufacturing cost, but also improve the current transmission efficiency of the cell pieces.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more specifically, to a solar cell and a method for manufacturing a solar cell. Background Technology

[0002] As an important renewable energy conversion device, the manufacturing cost and conversion efficiency of solar cells have always been the focus of industry attention. In the traditional manufacturing process of solar cells, fine grid lines and main grid lines are usually printed on silicon wafers. This electrode structure requires a large amount of silver paste material. Silver is a precious metal, and its market price has been high for a long time, resulting in high manufacturing costs for solar cells. In addition, the grid structure of the intersecting fine grid lines and main grid lines will limit the effective light-receiving area of ​​the cell, and the resistance characteristics of the main grid lines will also affect the current extraction efficiency, thus affecting the current transmission efficiency of the cell. Summary of the Invention

[0003] In view of this, the purpose of this application is to overcome the shortcomings of the prior art and provide a solar cell that can not only reduce manufacturing costs but also improve the current transmission efficiency of the cell.

[0004] To achieve the above objectives, the technical solution adopted in this application is as follows: In a first aspect, this application provides a solar cell, the solar cell comprising: a plurality of cells, each cell comprising a silicon wafer, a plurality of first grids, a plurality of second grids, and a plurality of conductive wires, wherein the first grids and the second grids are printed on both the front and back sides of the silicon wafer, wherein the plurality of first grids are dot-spaced on any side of the silicon wafer, and the second grids are disposed at two opposite edges of the silicon wafer, and the plurality of conductive wires are spaced apart, wherein any one conductive wire is connected to any one or more of the first grids, and both ends of any one conductive wire are respectively connected to the second grids at both ends of the silicon wafer; wherein any two cells are stacked, and in any two cells, the second grids on the front side of one silicon wafer at least partially overlap with the second grids on the back side of the other silicon wafer.

[0005] In an optional embodiment, the solar cell has a first orientation and a second orientation; On any side of the silicon wafer, a second fine gate is provided at both ends of the silicon wafer along the second direction, and each second fine gate extends along the first direction; On any side of the silicon wafer, multiple sets of first fine gate groups are spaced apart along the first direction. Each first fine gate group is disposed between the second fine gates at both ends of the silicon wafer along the second direction. Each first fine gate group includes multiple first fine gates spaced apart along the second direction. On any side of the silicon wafer, each of the conductive wires is connected to each of the first fine gates of a first fine gate group, and the two ends of the conductive wires are respectively connected to the second fine gates at both ends of the silicon wafer along the second direction. Wherein, at the same end of any two of the solar cells along the second direction, the second fine grid on the front side of one of the silicon wafers at least partially overlaps with the second fine grid on the back side of the other silicon wafer.

[0006] In an optional embodiment, the first fine gate has a dimension L1 along the first direction and a dimension L2 along the second direction, satisfying: 40μm≤L1≤100μm, 40μm≤L2≤100μm.

[0007] In an optional implementation, the distance between any two of the first fine gates is L3, satisfying: 400μm≤L3≤800μm.

[0008] In an optional embodiment, the second fine gate has a stacked portion and a connecting portion. The stacked portion extends along the first direction, and a plurality of connecting portions are connected to one end of the stacked portion near the interior of the silicon wafer along the second direction. The plurality of connecting portions are spaced apart along the first direction, and each connecting portion is connected to one end of a conductive wire. At the same end of any two solar cells along the second direction, the stacked portion on the front side of one silicon wafer at least partially overlaps the stacked portion on the back side of the other silicon wafer.

[0009] In an optional embodiment, the dimension of the stacked portion along the second direction is L4, satisfying: 200μm≤L4≤400μm.

[0010] In an optional embodiment, the connecting portion protrudes from the stacked portion along the second direction toward the interior of the silicon wafer, the dimension of the connecting portion along the first direction is L5, and the dimension of the connecting portion along the second direction is L6, satisfying: 300μm≤L5≤600μm, 100μm≤L6≤300μm.

[0011] Secondly, this application provides a method for manufacturing a solar cell, used to manufacture a solar cell as described in any of the foregoing embodiments. The method for manufacturing the solar cell includes: printing a plurality of first silver paste layers on the front side of a silicon wafer to form a plurality of first fine grids arranged in a dotted pattern on the front side; printing a plurality of second silver paste layers on the front side to form second fine grids at two opposite edges of the front side; printing a plurality of first silver paste layers on the back side of the silicon wafer to form a plurality of first fine grids arranged in a dotted pattern on the back side; printing a plurality of second silver paste layers on the back side to form second fine grids at two opposite edges of the back side; and printing a plurality of first silver paste layers on the back side of the silicon wafer to form a plurality of first fine grids arranged in a dotted pattern on the back side; and printing a plurality of second silver paste layers on the back side to form second fine grids at two opposite edges of the back side; and printing a plurality of first silver paste layers on the back side of the silicon wafer to form second fine grids at two opposite edges of the back side; and printing a plurality of first silver paste layers on the back side of the silicon wafer to form a plurality of first fine grids arranged in a dotted pattern on the back side; and printing a plurality of second silver paste layers on the back side of the silicon wafer to form second fine grids at two opposite edges of the back side; and printing a plurality of first silver paste layers on the back side of the silicon wafer to form a plurality of first fine grids at a dotted pattern on the back side; and printing a plurality of first silver paste layers on the back side of the silicon wafer to form second fine grids at two opposite edges of the back side of the silicon wafer; and printing a plurality of first silver paste layers on the back side of the silicon wafer to form a plurality of first fine grids at a dotted pattern on ... Conductive adhesive is applied to the first and second fine grids on the front side. Any conductive wire is bonded to any number of the first fine grids through the conductive adhesive, and the two ends of the conductive wire are respectively bonded to the second fine grids at both ends of the front side. The conductive adhesive is applied to the first and second fine grids on the back side. Any conductive wire is connected to any number of the first fine grids through the conductive adhesive, and the two ends of the conductive wire are respectively connected to the second fine grids at both ends of the back side. Any two battery cells are stacked such that the second fine grid on the front side of one battery cell at least partially overlaps the second fine grid on the back side of the other battery cell.

[0012] In an optional embodiment, the method for manufacturing the solar cell further includes: after printing a plurality of first fine grids and a plurality of second fine grids on the front and back sides of the silicon wafer, the solar cell is subjected to high-temperature sintering; wherein the sintering temperature is T1 and the sintering time is t1, satisfying: 750℃≤T1≤800℃, 50s≤t1≤80s.

[0013] In an optional embodiment, the method for manufacturing the solar cell further includes: after bonding conductive wires to the front and back sides of the silicon wafer, curing the conductive adhesive; after curing the conductive adhesive, heating the solar cell; wherein the heating temperature is T2 and the heating time is t2, satisfying: 240℃≤T2≤260℃, 2s≤t2≤5s.

[0014] The solar cell of this application has the following advantages: In the solar cell of this application, a fine grid is used to collect charge carriers inside the silicon wafer and guide them to the outside of the wafer. Since each conductive filament is connected to multiple first fine grids, the conductive filament can be directly connected to the fine grids, thereby directly collecting the charge carriers guided by the fine grids onto the conductive filament, and then transmitting them to the external circuit through the conductive filament. Furthermore, both ends of each conductive filament are connected to second fine grids at both ends of the silicon wafer. In any two cells, the second fine grid on the front of one silicon wafer at least partially overlaps with the second fine grid on the back of the other silicon wafer, thus achieving conduction between the positive and negative electrodes of the cells and electrical connection between any two cells. This allows multiple cells to be stacked to form a shingled module, significantly improving the photoelectric conversion efficiency and space utilization of the module. In the shingled module, since the conductive filament is directly connected to the fine grid, there is no need to set a main grid as a transmission medium between the fine grid and the conductive filament. This not only reduces carrier losses during transmission and improves the current transmission efficiency of the cells, but also reduces light shading of the silicon wafer, thereby improving the photoelectric conversion efficiency. Meanwhile, since the multiple first grids are arranged in a dotted pattern on the silicon wafer, the effective light-receiving area of ​​the cell is maximized, further optimizing the photoelectric conversion performance. Furthermore, this gridless design, combined with the dotted distribution of the first grid structure, can significantly reduce the amount of silver paste used, which not only improves material utilization efficiency but also helps to reduce the overall manufacturing cost of solar cells. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic diagram of the structure of the solar cell in this application is shown; Figure 2 It shows Figure 1 Enlarged structural diagram at point A; Figure 3 A flowchart illustrating the method for fabricating the solar cell described in this application is shown.

[0017] Explanation of key component symbols: 100 - Solar cell; 110 - Silicon wafer; 120 - First grid; 130 - Second grid; 131 - Stacking section; 132 - Connector section; 140 - Conductive wire; x - First direction; y - Second direction. Detailed Implementation

[0018] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0019] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0021] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0022] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0023] Reference Figure 1 as well as Figure 2As shown in the embodiments of this application, the solar cell includes: a plurality of solar cells 100.

[0024] Specifically, each solar cell 100 includes a silicon wafer 110, a plurality of first fine grids 120, a plurality of second fine grids 130, and a plurality of conductive wires 140. The first fine grids 120 and the second fine grids 130 are printed on both the front and back sides of the silicon wafer 110. On any side of the silicon wafer 110, the plurality of first fine grids 120 are arranged in a dotted pattern on the silicon wafer 110. The two opposite edges of the silicon wafer 110 are provided with second fine grids 130. The plurality of conductive wires 140 are arranged at intervals. Any conductive wire 140 is connected to any plurality of first fine grids 120, and the two ends of any conductive wire 140 are respectively connected to the second fine grids 130 at both ends of the silicon wafer 110. Any two solar cells 100 are stacked, and in any two solar cells 100, the second fine grids 130 on the front side of one silicon wafer 110 and the second fine grids 130 on the back side of the other silicon wafer 110 at least partially overlap.

[0025] In the solar cell of this application, a fine grid is used to collect charge carriers inside the silicon wafer 110 and conduct them to the outside of the silicon wafer 110. Since each conductive wire 140 is connected to multiple first fine grids 120, the conductive wire 140 can be directly connected to the fine grid, thereby directly collecting the charge carriers conducted by the fine grid onto the conductive wire 140, and then transmitting them to the external circuit through the conductive wire 140. In addition, both ends of each conductive wire 140 are respectively connected to the second fine grids 130 at both ends of the silicon wafer 110, and in any two solar cells 100, the second fine grid 130 on the front side of one silicon wafer 110 at least partially overlaps with the second fine grid 130 on the back side of the other silicon wafer 110, thus realizing the conduction of the positive and negative electrodes of the solar cells 100 and the electrical connection between any two solar cells 100, enabling multiple solar cells 100 to be stacked to form a shingled module, significantly improving the photoelectric conversion efficiency and space utilization of the module. In shingled modules, the conductive filaments 140 are directly connected to the fine grid, eliminating the need for a main grid as a transmission medium between the fine grid and the conductive filaments 140. This not only reduces carrier losses during transmission and improves the current transmission efficiency of the cell 100, but also reduces light shading on the silicon wafer 110, thereby enhancing photoelectric conversion efficiency. Furthermore, since the multiple first fine grids 120 are arranged in a dotted pattern on the silicon wafer 110, the effective light-receiving area of ​​the cell 100 is maximized, further optimizing photoelectric conversion performance. Moreover, this gridless design, combined with the dotted distribution of the first fine grids 120, significantly reduces the amount of silver paste used, which not only improves material utilization efficiency but also helps reduce the overall manufacturing cost of solar cells.

[0026] Continue to refer to Figure 1 as well as Figure 2As shown, the solar cell has a first direction x and a second direction y; on any side of the silicon wafer 110, a second fine grid 130 is provided at both ends of the silicon wafer 110 along the second direction y, and each second fine grid 130 extends along the first direction x; on any side of the silicon wafer 110, multiple sets of first fine grids 120 are spaced apart along the first direction x, and each set of first fine grids 120 is disposed between the second fine grids 130 at both ends of the silicon wafer 110 along the second direction y. Each includes a plurality of first fine gates 120 spaced apart along the second direction y; on any side of the silicon wafer 110, each conductive wire 140 is connected to each of the first fine gates 120 of a group of first fine gates 120, and the two ends of the conductive wire 140 are respectively connected to the second fine gates 130 at both ends of the silicon wafer 110 along the second direction y; wherein, at the same end of any two solar cells 100 along the second direction y, the second fine gate 130 on the front side of one silicon wafer 110 at least partially overlaps with the second fine gate 130 on the back side of the other silicon wafer 110.

[0027] It should be noted that the first direction x is Figure 1 The direction indicated by x in the middle, and the second direction y is... Figure 1 The direction indicated by y in the middle.

[0028] In this embodiment, each first fine gate 120 of the first fine gate 120 group is used to collect the charge carriers inside the silicon wafer 110 and conduct them to the outside of the silicon wafer 110. Since each conductive wire 140 is connected to each first fine gate 120 of a first fine gate 120 group, the charge carriers collected by the first fine gate 120 group can be gathered through the conductive wire 140 and then transmitted to the external circuit through the conductive wire 140. In addition, since the two ends of the conductive wire 140 are respectively connected to the second fine gates 130 at both ends of the silicon wafer 110 along the second direction y, and in any two solar cells 100 along the second direction y at the same end, the second fine gate 130 on the front side of one silicon wafer 110 and the second fine gate 130 on the back side of the other silicon wafer 110 at least partially overlap, the positive and negative electrodes of the solar cells 100 are connected and the electrical connection between any two solar cells 100 is realized, so that multiple solar cells 100 can be stacked to form a shingled assembly.

[0029] Reference Figure 2 As shown, the first fine gate 120 has a dimension of L1 along the first direction x and a dimension of L2 along the second direction y, satisfying: 40μm≤L1≤100μm, 40μm≤L2≤100μm.

[0030] Specifically, in this embodiment, L1 can be 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, etc.; L2 can be 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, etc.; and the values ​​of L1 and L2 can be the same or different.

[0031] In this embodiment, if L1 < 40 μm, the size of the first fine gate 120 along the first direction x will be too small, which will increase the difficulty of connecting the conductive wire 140 and the first fine gate 120. If L1 > 100 μm, the size of the first fine gate 120 along the first direction x will be too large, which will increase the amount of silver paste used in the first fine gate 120, leading to increased manufacturing costs and increased shading area of ​​the first fine gate 120 on the silicon wafer 110, resulting in reduced photoelectric conversion efficiency. When 40 μm ≤ L1 ≤ 100 μm, the difficulty of connecting the conductive wire 140 and the first fine gate 120 can be reduced, the manufacturing cost can be reduced, and the impact on photoelectric conversion efficiency can be reduced. Similarly, if L2 < 40 μm, the size of the first fine gate 120 along the second direction y will be too small, which will increase the difficulty of connecting the conductive wire 140 and the first fine gate 120. If L2 > 100 μm, the size of the first fine gate 120 along the second direction y will be too large, which will increase the amount of silver paste used in the first fine gate 120, resulting in increased manufacturing costs and increased shielding area of ​​the first fine gate 120 on the silicon wafer 110, resulting in reduced photoelectric conversion efficiency. When 40 μm ≤ L2 ≤ 100 μm, the difficulty of connecting the conductive wire 140 and the first fine gate 120 can be reduced, the manufacturing cost can be reduced, and the impact on photoelectric conversion efficiency can be reduced.

[0032] Reference Figure 1 As shown, the distance between any two first fine gates 120 is L3, which satisfies: 400μm≤L3≤800μm.

[0033] Specifically, in this embodiment, L3 can be 400 μm, 420 μm, 440 μm, 460 μm, 480 μm, 500 μm, 520 μm, 540 μm, 560 μm, 58 0μm, 600μm, 620μm, 640μm, 660μm, 680μm, 700μm, 720μm, 740μm, 760μm, 780μm, 800μm, etc.

[0034] In this embodiment, if L3 > 800 μm, the distance between any two adjacent first fine gates 120 connected to the same conductive wire 140 will be too large, which will reduce the connection stability between the conductive wire 140 and the first fine gate 120 group. If L3 < 400 μm, the distance between any two adjacent first fine gates 120 will be too small, which will increase the number of first fine gates 120, thereby increasing the amount of silver paste used, increasing the manufacturing cost, and increasing the shielding area of ​​the first fine gates 120 on the silicon wafer 110, resulting in a decrease in photoelectric conversion efficiency. When 400 μm ≤ L3 ≤ 800 μm, the connection stability between the conductive wire 140 and the first fine gate 120 group can be improved, the manufacturing cost can be reduced, and the impact on photoelectric conversion efficiency can be reduced.

[0035] Reference Figure 2 As shown, the second fine gate 130 has a stacked portion 131 and a connecting portion 132. The stacked portion 131 extends along a first direction x. A plurality of connecting portions 132 are connected to one end of the stacked portion 131 near the interior of the silicon wafer 110 along a second direction y. The plurality of connecting portions 132 are spaced apart along the first direction x. Each connecting portion 132 is connected to one end of a conductive wire 140. At the same end of any two solar cells 100 along the second direction y, the stacked portion 131 on the front side of one silicon wafer 110 at least partially overlaps with the stacked portion 131 on the back side of the other silicon wafer 110.

[0036] In this embodiment, since the connecting portion 132 of the second fine grid 130 is connected to the conductive wire 140, when the two ends of the conductive wire 140 are respectively connected to the connecting portion 132 of the second fine grid 130 at both ends of the solar cell 100, the positive and negative electrodes of the solar cell 100 can be connected through the conductive wire 140. Furthermore, since the stacking portion 131 extends along the first direction x, and in any two solar cells 100 at the same end along the second direction y, the stacking portion 131 on the front side of one silicon wafer 110 at least partially overlaps with the stacking portion 131 on the back side of another silicon wafer 110, when multiple solar cells 100 are stacked to form a shingled assembly, the stacking portion 131 extending along the first direction x can improve the stability of the electrical connection between any two adjacent solar cells 100, thereby improving the stability of the electrical performance of the solar cell.

[0037] Continue to refer to Figure 2 As shown, the dimension of the stacked portion 131 along the second direction y is L4, which satisfies: 200μm≤L4≤400μm.

[0038] Specifically, in this embodiment, L4 can be 200μm, 220μm, 240μm, 260μm, 280μm, 300μm, 320μm, 340μm, 360μm, 380μm, 400μm, etc.

[0039] In this embodiment, if L4 < 200 μm, the size of the stacked portion 131 along the second direction y will be too small, that is, the width of the stacked portion 131 will be too small. When multiple solar cells 100 are stacked to form a shingled assembly, the overlap rate of the stacked portion 131 of any two adjacent solar cells 100 will be reduced, which will further reduce the stability of the electrical connection between any two adjacent solar cells 100. If L4 > 400 μm, the size of the stacked portion 131 along the second direction y will be too large, that is, the width of the stacked portion 131 will be too large. This will increase the amount of silver paste used in the second fine grid 130, resulting in increased manufacturing costs and increased shading area of ​​the second fine grid 130 on the silicon wafer 110, resulting in reduced photoelectric conversion efficiency. When 200 μm ≤ L4 ≤ 400 μm, the stability of the electrical connection between any two adjacent solar cells 100 can be improved, the manufacturing cost can be reduced, and the impact on photoelectric conversion efficiency can be reduced.

[0040] Continue to refer to Figure 2 As shown, the connecting portion 132 protrudes from the stacked portion 131 along the second direction y toward the interior of the silicon wafer 110. The dimension of the connecting portion 132 along the first direction x is L5, and the dimension of the connecting portion 132 along the second direction y is L6, satisfying: 300μm≤L5≤600μm, 100μm≤L6≤300μm.

[0041] Specifically, in this embodiment, L5 can be 300μm, 330μm, 350μm, 370μm, 390μm, 410μm, 430μm, 450μm, 470μm, 490μm, 510μm, 530μm, 550μm, 570μm, 600μm, etc.; L6 can be 100μm, 120μm, 140μm, 160μm, 180μm, 200μm, 220μm, 240μm, 260μm, 280μm, 300μm, etc.

[0042] In this embodiment, if L5 < 300 μm, the dimension of the connection portion 132 along the first direction x will be too small, which will increase the difficulty of connecting the conductive wire 140 and the connection portion 132. If L5 > 600 μm, the dimension of the connection portion 132 along the first direction x will be too large, which will increase the amount of silver paste used in the second fine gate 130, leading to increased manufacturing costs and increased shading area of ​​the second fine gate 130 on the silicon wafer 110, resulting in reduced photoelectric conversion efficiency. When 300 μm ≤ L5 ≤ 600 μm, the difficulty of connecting the conductive wire 140 and the connection portion 132 can be reduced, the manufacturing cost can be reduced, and the impact on photoelectric conversion efficiency can be reduced. Similarly, if L6 < 100μm, the dimension of the connection portion 132 along the second direction y will be too small, which will increase the difficulty of connecting the conductive wire 140 and the connection portion 132. If L6 > 300μm, the dimension of the connection portion 132 along the second direction y will be too large, which will increase the amount of silver paste used in the second fine gate 130, resulting in increased manufacturing costs and increased shielding area of ​​the second fine gate 130 on the silicon wafer 110, leading to reduced photoelectric conversion efficiency. When 100μm ≤ L6 ≤ 300μm, the difficulty of connecting the conductive wire 140 and the connection portion 132 can be reduced, the manufacturing cost can be reduced, and the impact on photoelectric conversion efficiency can be reduced.

[0043] Reference Figure 3 As shown, the method for manufacturing a solar cell according to the embodiments of this application is used to manufacture the above-mentioned solar cell. The method for manufacturing a solar cell includes: S100: A plurality of first silver paste layers are printed on the front side of silicon wafer 110 to form a plurality of first fine gates 120 arranged in a dotted interval on the front side, and a plurality of second silver paste layers are printed on the front side to form second fine gates 130 at two opposite edges of the front side. Specifically, the plurality of first silver paste layers include a plurality of groups of first silver paste layers spaced apart along the first direction x, and each group of first silver paste layers includes a plurality of first silver paste layers spaced apart along the second direction y; the dimension of each first silver paste layer along the first direction x is L1, the dimension of each first silver paste layer along the second direction y is L2, and the distance between any two first silver paste layers is L3. Specifically, a second silver paste layer is printed at both ends of the front side of the silicon wafer 110 along the second direction y, and each second silver paste layer extends along the first direction x. The second silver paste layer has a stacked portion 131 and a connecting portion 132. The stacked portion 131 extends along the first direction x, and a plurality of connecting portions 132 are connected to one end of the stacked portion 131 near the interior of the silicon wafer 110 along the second direction y. The plurality of connecting portions 132 are spaced apart along the first direction x, and all protrude from the stacked portion 131 in the direction near the interior of the silicon wafer 110 along the second direction y. The dimension of the stacked portion 131 along the second direction y is L4, the dimension of the connecting portion 132 along the first direction x is L5, and the dimension of the connecting portion 132 along the second direction y is L6.

[0044] S200: A plurality of first silver paste layers are printed on the back side of silicon wafer 110 to form a plurality of first fine gates 120 arranged in a dotted interval on the back side, and a plurality of second silver paste layers are printed on the back side to form second fine gates 130 at two opposite edges of the back side. Specifically, the plurality of first silver paste layers include a plurality of groups of first silver paste layers spaced apart along the first direction x, and each group of first silver paste layers includes a plurality of first silver paste layers spaced apart along the second direction y; the dimension of each first silver paste layer along the first direction x is L1, the dimension of each first silver paste layer along the second direction y is L2, and the distance between any two first silver paste layers is L3. Specifically, a second silver paste layer is printed at both ends of the back side of the silicon wafer 110 along the second direction y, and each second silver paste layer extends along the first direction x. The second silver paste layer has a stacked portion 131 and a connecting portion 132. The stacked portion 131 extends along the first direction x, and a plurality of connecting portions 132 are connected to one end of the stacked portion 131 near the interior of the silicon wafer 110 along the second direction y. The plurality of connecting portions 132 are spaced apart along the first direction x, and all protrude from the stacked portion 131 in the direction near the interior of the silicon wafer 110 along the second direction y. The dimension of the stacked portion 131 along the second direction y is L4, the dimension of the connecting portion 132 along the first direction x is L5, and the dimension of the connecting portion 132 along the second direction y is L6.

[0045] S300: Apply conductive adhesive to the first fine grid 120 and the second fine grid 130 on the front side, and bond any one conductive wire 140 to any number of first fine grids 120 through the conductive adhesive, and bond the two ends of the conductive wire 140 to the second fine grids 130 at both ends of the front side respectively. Specifically, each conductive wire 140 is bonded to multiple first fine gates 120 of the same first fine gate 120 group.

[0046] S400: Apply conductive adhesive to the first fine grid 120 and the second fine grid 130 on the back side, connect any one conductive wire 140 to any number of first fine grids 120 through the conductive adhesive, and connect the two ends of the conductive wire 140 to the second fine grids 130 at both ends of the back side respectively. Specifically, each conductive wire 140 is bonded to multiple first fine gates 120 of the same first fine gate 120 group.

[0047] S500: Stack any two battery cells 100 such that the second fine grid 130 on the front side of one battery cell 100 at least partially overlaps with the second fine grid 130 on the back side of the other battery cell 100.

[0048] Specifically, the stacked portion 131 of the second fine grid 130 on the front side of one of the battery cells 100 at least partially overlaps with the stacked portion 131 of the second fine grid 130 on the back side of the other battery cell 100.

[0049] Specifically, in this embodiment, the order of S100 and S200 is not limited, that is, S100 can be performed first and then S200, or S200 can be performed first and then S100. The order of S300 and S400 is not limited, that is, S300 can be performed first and then S400, or S400 can be performed first and then S300.

[0050] In the method for manufacturing a solar cell according to this application, multiple first fine grids 120 are formed by printing multiple first silver paste layers arranged in a dotted pattern. Then, conductive wires 140 are bonded to any number of first fine grids 120 by conductive adhesive, thereby achieving direct connection between the conductive wires 140 and the fine grids. This allows the charge carriers exported from the fine grids to be directly collected onto the conductive wires 140 and then transmitted to an external circuit through the conductive wires 140. Furthermore, a second fine grid 130 can be formed by printing a second silver paste layer, and then conductive wires 140 can be bonded to the two opposite edges of the second fine grid 130 using conductive adhesive, thereby achieving conduction between the positive and negative electrodes of the solar cell 100. Finally, any two solar cells 100 can be stacked to form a shingled module. In this process, the conductive wires 140 are directly connected to the fine grid, so there is no need to set a main grid between the fine grid and the conductive wires 140 as a transmission medium. This not only reduces the loss of charge carriers during transmission and improves the current transmission efficiency of the solar cell 100, but also reduces the light shading of the silicon wafer 110, thereby improving the photoelectric conversion efficiency. At the same time, the multiple first fine grids 120 distributed in a dotted pattern on the silicon wafer 110 can maximize the effective light-receiving area of ​​the solar cell 100, further optimizing the photoelectric conversion performance. Furthermore, this main grid-less design combined with the dotted distribution of the first fine grids 120 structure can significantly reduce the amount of silver paste used, which not only improves the material utilization efficiency, but also helps to reduce the overall manufacturing cost of solar cells.

[0051] The method for manufacturing solar cells also includes: printing multiple first grids 120 and multiple second grids 130 on the front and back sides of silicon wafer 110, and then sintering the cell 100 at high temperature; wherein the sintering temperature is T1 and the sintering time is t1, satisfying: 750℃≤T1≤800℃, 50s≤t1≤80s.

[0052] Specifically, in this embodiment, T1 can be 750℃, 755℃, 760℃, 765℃, 770℃, 775℃, 780℃, 785℃, 790℃, 795℃, 800℃, etc.; t1 can be 50s, 55s, 60s, 65s, 70s, 75s, 80s, etc.

[0053] Specifically, in this embodiment, both the first silver paste layer and the second silver paste layer are made of a mixture of silver powder, glass frit, organic carrier and additives.

[0054] In this embodiment, after printing multiple first fine gates 120 and multiple second fine gates 130 on the front and back sides of the silicon wafer 110, the structural stability of the first fine gates 120 and the second fine gates 130 is improved by high-temperature sintering. The silver paste melts at high temperature to form a good silver-silicon contact, thereby enabling the fine gates to form a good ohmic contact with the silicon wafer 110, so as to improve the current transmission efficiency of the fine gates to the silicon wafer 110. During the high-temperature sintering process, if T1 < 50℃, the sintering temperature will be too low, and the glass components in the silver paste will not be able to corrode the silicon nitride surface layer of the silicon wafer 110, preventing silver and silicon from forming a good ohmic contact and affecting the efficiency of the fine gate in discharging charge carriers. If T1 > 800℃, the sintering temperature will be too high, causing the silver particles in the silver paste to melt excessively and damaging the silicon wafer 110, which will also affect the current transmission efficiency of the fine gate to the silicon wafer 110. When 750℃ ≤ T1 ≤ 800℃, the sintering temperature can be kept within a suitable range, improving the stability of the connection between the fine gate and the silicon wafer 110 and ensuring the current transmission efficiency. Similarly, if t1 < 750℃ or t1 > 800℃, the sintering time will be too short or too long, which will affect the stability of the connection between the fine gate and the silicon wafer 110 and the current transmission efficiency. When 50s ≤ t1 ≤ 80s, the stability of the connection between the fine gate and the silicon wafer 110 can be guaranteed, as well as the current transmission efficiency.

[0055] Methods for manufacturing solar cells also include: After the conductive wires 140 are bonded to the front and back sides of the silicon wafer 110, the conductive adhesive is cured. Specifically, the conductive adhesive is cured by ultraviolet irradiation; After the conductive adhesive is cured, the battery cell 100 is heated. The heating temperature is T2, and the heating time is t2, which satisfy the following conditions: 240℃≤T2≤260℃, 2s≤t2≤5s.

[0056] Specifically, the conductive wire 140 is a tin-plated copper wire. Heating enhances the solidification connection between the tin in the conductive wire 140 and the silver in the fine grid, thereby improving the connection stability between the conductive wire 140 and the fine grid.

[0057] Specifically, T2 can be 240℃, 242℃, 244℃, 246℃, 248℃, 250℃, 252℃, 254℃, 256℃, 258℃, 260℃, etc.; t2 can be 2s, 3s, 4s, 5s, etc.

[0058] In this embodiment, the connection stability between the conductive wire 140 and the fine grid is improved by curing the conductive adhesive. Simultaneously, heating the solar cell 100 further enhances the connection stability between the conductive wire 140 and the fine grid, thereby improving the performance stability of the solar cell. During this process, if T2 < 240°C, the heating time will be too short, preventing the tin in the conductive wire 140 and the silver in the fine grid from achieving a good curing bond, thus affecting the connection stability. If T2 > 260°C, the tin in the conductive wire 140 is easily oxidized at high temperatures. The conductivity of the oxide is much lower than that of metallic tin, leading to a significant increase in the contact resistance between the conductive wire 140 and the fine grid, affecting current transmission efficiency. When 240°C ≤ T2 ≤ 260°C, the connection stability between the conductive wire 140 and the fine grid is ensured while minimizing the impact on current transmission efficiency. Similarly, if t2 < 2s or t2 > 5s, the heating time of the cell 100 will be too short or too long, which will affect the connection stability of the conductive wire 140 and the fine grid as well as the current transmission efficiency. When 2s ≤ t2 ≤ 5s, the connection stability of the conductive wire 140 and the fine grid can be guaranteed, and the impact on the current transmission efficiency can be reduced.

[0059] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0060] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A solar cell, characterized in that, The solar cell includes: Multiple solar cells are provided, each of which includes a silicon wafer, multiple first fine grids, multiple second fine grids, and multiple conductive wires. The first fine grids and second fine grids are printed on both the front and back sides of the silicon wafer. On any side of the silicon wafer, multiple first fine grids are arranged in a dotted pattern. Second fine grids are arranged at the two opposite edges of the silicon wafer. Multiple conductive wires are arranged at intervals. Any one of the conductive wires is connected to any one of the multiple first fine grids, and the two ends of any one of the conductive wires are respectively connected to the second fine grids at both ends of the silicon wafer. In this configuration, any two of the solar cells are stacked together, and in any two solar cells, the second fine grid on the front side of one of the silicon wafers at least partially overlaps with the second fine grid on the back side of the other silicon wafer.

2. The solar cell according to claim 1, characterized in that, The solar cell has a first orientation and a second orientation; On any side of the silicon wafer, a second fine gate is provided at both ends of the silicon wafer along the second direction, and each second fine gate extends along the first direction; On any side of the silicon wafer, multiple sets of first fine gate groups are spaced apart along the first direction. Each first fine gate group is disposed between the second fine gates at both ends of the silicon wafer along the second direction. Each first fine gate group includes multiple first fine gates spaced apart along the second direction. On any side of the silicon wafer, each of the conductive wires is connected to each of the first fine gates of a first fine gate group, and the two ends of the conductive wires are respectively connected to the second fine gates at both ends of the silicon wafer along the second direction. Wherein, at the same end of any two of the solar cells along the second direction, the second fine grid on the front side of one of the silicon wafers at least partially overlaps with the second fine grid on the back side of the other silicon wafer.

3. The solar cell according to claim 2, characterized in that, The first fine gate has a dimension L1 along the first direction and a dimension L2 along the second direction, satisfying: 40μm≤L1≤100μm, 40μm≤L2≤100μm.

4. The solar cell according to claim 2, characterized in that, The distance between any two of the first fine gates is L3, which satisfies: 400μm≤L3≤800μm.

5. The solar cell according to claim 2, characterized in that, The second fine gate has a stacked portion and a connecting portion. The stacked portion extends along the first direction. A plurality of connecting portions are connected to one end of the stacked portion near the interior of the silicon wafer along the second direction. The plurality of connecting portions are spaced apart along the first direction. Each connecting portion is connected to one end of a conductive wire. At the same end of any two solar cells along the second direction, the stacked portion on the front side of one silicon wafer at least partially overlaps the stacked portion on the back side of the other silicon wafer.

6. The solar cell according to claim 5, characterized in that, The dimension of the stacked portion along the second direction is L4, which satisfies: 200μm≤L4≤400μm.

7. The solar cell according to claim 5, characterized in that, The connecting portion protrudes from the stacked portion in the direction close to the interior of the silicon wafer along the second direction. The dimension of the connecting portion along the first direction is L5, and the dimension of the connecting portion along the second direction is L6, satisfying: 300μm≤L5≤600μm, 100μm≤L6≤300μm.

8. A method for manufacturing a solar cell, characterized in that, A method for manufacturing a solar cell as described in any one of claims 1-7, comprising: Multiple first silver paste layers are printed on the front side of the silicon wafer to form multiple first fine gates arranged in a dotted pattern on the front side, and multiple second silver paste layers are printed on the front side to form second fine gates at two opposite edges of the front side. A plurality of first silver paste layers are printed on the back side of the silicon wafer to form a plurality of first fine gates arranged in a dotted pattern on the back side, and a plurality of second silver paste layers are printed on the back side to form second fine gates at two opposite edges of the back side. Apply conductive adhesive to the first and second fine grids on the front side, and bond any one conductive wire to any number of the first fine grids through the conductive adhesive, and bond the two ends of the conductive wire to the second fine grids at both ends of the front side respectively. Apply the conductive adhesive to the first and second fine grids on the back side, connect any one conductive wire to any number of the first fine grids through the conductive adhesive, and connect the two ends of the conductive wire to the second fine grids at both ends of the back side respectively. Any two solar cells are stacked such that the second fine grid on the front side of one solar cell at least partially overlaps with the second fine grid on the back side of the other solar cell.

9. The method for manufacturing a solar cell according to claim 8, characterized in that, The method for manufacturing the solar cell further includes: After printing a plurality of first fine grids and a plurality of second fine grids on the front and back sides of the silicon wafer, the solar cell is sintered at high temperature. The sintering temperature is T1, and the sintering time is t1, satisfying the following conditions: 750℃≤T1≤800℃, 50s≤t1≤80s.

10. The method for manufacturing a solar cell according to claim 8, characterized in that, The method for manufacturing the solar cell further includes: After the conductive wires are bonded to the front and back sides of the silicon wafer, the conductive adhesive is cured. After the conductive adhesive is cured, the battery cell is heated. The heating temperature is T2, and the heating time is t2, which satisfy the following conditions: 240℃≤T2≤260℃, 2s≤t2≤5s.

Images