Frequency calibration method for LED driving chip, LED driving chip and LED lamp

Abstract

The application discloses a frequency calibration method for an LED driving chip, an LED driving chip and an LED lamp, and is applied to the LED driving chip connected with an external host through an I2C bus. The method comprises the following steps: monitoring a serial clock line in real time during normal I2C communication, and generating a calibration window after detecting a self-calibration enabling signal; counting the output pulse of a built-in RC oscillator in the calibration window, and obtaining a single counting value; performing average operation on the single counting values of multiple different calibration windows, and generating a sampling average value; comparing the sampling average value with a pre-stored standard counting value to obtain a frequency error value; and adjusting the tuning control parameter of the RC oscillator to correct the output frequency according to the frequency error value. The application uses the SCL clock signal in the I2C communication as a calibration reference, does not need to add a hardware pin, does not need the host to participate in operation, does not interrupt normal display business, and independently completes dynamic and real-time calibration of the frequency of the RC oscillator in the normal working process of the chip.

Description

Technical Field

[0001] This invention relates to the field of LED technology, and more particularly to a frequency calibration method for LED driver chips, LED driver chips, and LED lamps. Background Technology

[0002] The built-in RC oscillator of LED driver chips is prone to frequency drift due to process variations, voltage fluctuations, and temperature changes. This can lead to abnormal PWM dimming frequencies or jitter in the line scan time during LED matrix displays, affecting the overall display effect and causing LED display flicker. Existing technologies offer various solutions to suppress flicker by adjusting the RC oscillator frequency. While these methods are effective, observations show that a small amount of flicker still exists, which is insufficient for applications requiring extremely high light stability. Summary of the Invention

[0003] This invention provides a frequency calibration method for LED driver chips, an LED driver chip, and an LED lamp to solve the problem of LED display flicker.

[0004] In a first aspect, embodiments of this application provide a frequency calibration method for an LED driver chip, applied to an LED driver chip connected to an external host via an I2C bus, the I2C bus including a serial clock line, comprising the following steps: During normal I2C communication between the LED driver chip and the external host, the clock signal on the serial clock line of the I2C bus is monitored in real time. When the self-calibration enable signal is detected, a calibration window is generated. Within the calibration window, the clock pulses output by the RC oscillator built into the LED driver chip are counted to obtain a single count value; Based on the single count values ​​obtained from multiple calibration windows, an averaging operation is performed to generate a sampled average value. The average value of the samples is compared with the pre-stored standard count value to obtain the frequency error value; Based on the frequency error value, the tuning control parameters of the RC oscillator are adjusted to correct the output frequency of the RC oscillator.

[0005] In some embodiments, the LED driver chip further includes: an effective window counter, wherein generating a calibration window after detecting a self-calibration enable signal specifically includes: After receiving the self-calibration enable signal, the falling edge of the clock on the serial clock line is continuously detected; Each time a falling edge of the clock is detected, the effective window counter is triggered to perform an accumulation count; When the count value of the effective window counter reaches the preset value N, it is reset to zero on the next falling edge of the clock, forming a cyclic counting mechanism from 0 to N. When the count value of the effective window counter is greater than 0, it is determined that the current calibration window is valid, and a high-level valid calibration signal is generated.

[0006] In some embodiments, the preset value N is 8; the calibration valid signal is used to limit the valid timing interval of the count, ensuring that the calibration window is aligned with the standard communication timing of the I2C bus.

[0007] In some embodiments, the step of averaging multiple single count values ​​obtained from different calibration windows to generate a sampled average value specifically includes: It adopts a two-stage counter structure, including a single-frame sampling counter and a round-counting counter; During the effective period of the calibration window, the clock pulses output by the RC oscillator are accumulated and counted by the single-frame sampling counter; During the invalidation period of the calibration window, the count value of the single-frame sampling counter remains latched; The round-counting counter increments automatically at the start of each calibration window, and triggers a sampling termination mechanism when the count value of the round-counting counter reaches the preset sampling round.

[0008] In some embodiments, the LED driver chip further includes: a configuration register, and the triggered sampling termination mechanism includes: Set calibration completion indicator signal; Latch the currently obtained single count value into the configuration register; The single-frame sampling counter and the round statistics counter are synchronously cleared to start the next round of sampling iteration.

[0009] In some embodiments, the preset sampling rounds are 10; the averaging operation is an arithmetic average of the 10 single count values ​​obtained from different independent calibration windows.

[0010] In some embodiments, a calibration enable step is included before the real-time monitoring of the clock signal on the serial clock line of the I2C bus: The LED driver chip has a built-in I2C communication module and a frequency self-calibration module; The I2C communication module receives register configuration instructions from the external host to output a global calibration enable signal to the frequency self-calibration module. The frequency self-calibration module performs the steps of monitoring, generating calibration windows, counting, averaging, comparing, and adjusting only when the global calibration enable signal is valid.

[0011] In some embodiments, the register configuration instruction is a standard I2C register write instruction; during the execution of the monitoring, counting, averaging, comparison and adjustment steps, the frequency self-calibration module performs these steps in parallel with the normal dimming and display services of the LED driver chip, without interrupting the normal I2C communication.

[0012] Secondly, embodiments of this application provide an LED driver chip configured to connect to an external host via an I2C bus and execute the method described in any one of the embodiments of this application.

[0013] Thirdly, embodiments of this application provide an LED lighting fixture, including: The LED driver chip described in any one of the embodiments of this application; and At least one LED light-emitting unit is electrically connected to the LED driver chip and is driven to emit light by the PWM drive signal generated by the LED driver chip.

[0014] In the aforementioned frequency calibration method for LED driver chips, and the solution provided by the LED driver chip and LED luminaire, the method is applied to the LED driver chip, which is connected to an external host via an I2C bus. The I2C bus includes a serial clock line. The method involves: during normal I2C communication between the LED driver chip and the external host, real-time monitoring of the clock signal on the serial clock line of the I2C bus; generating a calibration window upon detecting a self-calibration enable signal; counting the clock pulses output by the built-in RC oscillator within the calibration window to obtain a single count value; averaging multiple single count values ​​obtained from different calibration windows to generate a sampled average value; comparing the sampled average value with a pre-stored standard count value to obtain a frequency error value; and adjusting the tuning control parameters of the RC oscillator according to the frequency error value to correct the output frequency of the RC oscillator. By monitoring the serial clock line in real time during normal I2C communication between the LED driver chip and the external host, and generating a calibration window using multiple consecutive clock cycles, the output pulses of the built-in RC oscillator are counted within the window. The frequency error value is obtained by comparing the average of the count values ​​obtained from multiple independent calibration windows with the pre-stored standard count value. The tuning control parameters of the RC oscillator are then adjusted to correct the output frequency. Thus, dynamic real-time self-calibration of the RC oscillator frequency is achieved without adding hardware pins, interrupting normal display communication, or occupying the computing resources of the external host. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the overall process of an LED driver chip frequency calibration method according to an embodiment of the present invention; Figure 2 yes Figure 1 A schematic diagram of the implementation process of step S10; Figure 3 yes Figure 1 A schematic diagram of the implementation process of step S30; Figure 4 yes Figure 3 A schematic diagram of the implementation process of step S34; Figure 5 This is a schematic diagram of an implementation process of the calibration enabling step in one embodiment of the present invention; Figure 6 yes Figure 1 A schematic diagram of the implementation process of step S50; Figure 7 This is a schematic diagram of the structure of an LED driver chip frequency calibration system according to an embodiment of the present invention; Figure 8 This is a timing diagram of the SCL clock falling edge shift count and calibration valid signal in one embodiment of the present invention; Figure 9 This is a timing diagram of a single-frame sampling counter, a round-counting counter, and a calibration completion flag signal in one embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. It should also be understood that, as used in this specification and the appended claims, the term "and / or" refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0019] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0020] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0021] It should be understood that the sequence number of each step in the following embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0022] To illustrate the technical solution of the present invention, specific embodiments are described below.

[0023] The built-in RC oscillator of LED driver chips is prone to frequency drift due to process variations, voltage fluctuations, and temperature changes. This can lead to abnormal PWM dimming frequencies or jitter in the line scan time during LED matrix displays, affecting the overall display effect and causing LED display flicker. While existing technologies employ various methods to suppress flicker by adjusting the RC oscillator frequency, flicker still exists to a small extent and cannot meet the requirements for applications with extremely high light stability requirements.

[0024] Specifically, during the normal operation of an LED driver chip, the built-in RC oscillator provides a reference clock for the PWM dimming timing, and its frequency stability directly determines the period accuracy of the PWM signal. When the RC oscillator experiences frequency drift due to process deviations, voltage fluctuations, or temperature changes, the PWM modulation frequency shifts accordingly, causing the LED's on-off time ratio to deviate from the preset value, thereby triggering display flicker that is perceptible to the human eye. While existing technologies offer various solutions for suppressing flicker by dynamically adjusting the frequency of an RC oscillator, the frequency adjustment process itself introduces new problems. Each time the capacitor array or bias current inside the RC oscillator is adjusted, the oscillator output clock experiences a phase jump or periodic abrupt change at the moment of adjustment. If this unstable clock signal is directly used as the time base for PWM generation logic, it will cause transient errors in the PWM duty cycle of the current cycle, resulting in unexpected fluctuations in the LED's brightness at the adjustment moment. Since the chip needs to repeatedly perform frequency adjustments to track temperature and pressure changes during operation, this brightness disturbance caused by the adjustment will occur periodically, manifesting as repeated flickering, which cannot meet the application requirements in scenarios with extremely high light stability requirements.

[0025] In addition, in the technical solution of this application, the calibration process and communication are parallel. The calibration process can be implemented in the early configuration stage. The parameters are adjusted before PWM dimming. Except for phase jumps or periodic abrupt changes, the flicker can be basically eliminated, so that the flicker is basically outside the range of human perception.

[0026] To address the aforementioned issues, this application proposes a frequency calibration method for LED driver chips, an LED driver chip, and an LED lamp. During normal I2C communication between the LED driver chip and an external host, the serial clock line is monitored in real time, and a calibration window is generated using multiple consecutive clock cycles. Within the calibration window, the clock pulses output by the built-in RC oscillator are counted, and the average value is obtained by averaging the count values ​​from multiple independent calibration windows. The average value is then compared with a pre-stored standard count value to obtain the frequency error value. Based on this, the tuning control parameters of the RC oscillator are adjusted to correct the output frequency. This ensures that the reference signal required for frequency calibration fully utilizes the existing SCL clock from normal I2C communication, without interrupting normal PWM dimming and display services. The frequency adjustment process and the LED driver control process are decoupled in the time domain. This achieves dynamic frequency calibration of the RC oscillator while avoiding residual flicker caused by transient disturbances to the PWM duty cycle due to frequency adjustment, thus meeting the application requirements of high-light-stability scenarios.

[0027] In one embodiment, such as Figure 1As shown, a frequency calibration method for an LED driver chip is provided, characterized in that it is applied to an LED driver chip, which is connected to an external host via an I2C bus. The I2C bus includes a serial clock line, and includes the following steps: S10-S50.

[0028] S10. During normal I2C communication between the LED driver chip and the external host, the clock signal on the serial clock line of the I2C bus is monitored in real time. When the self-calibration enable signal is detected, a calibration window is generated.

[0029] For example, during normal display data transmission or register read / write communication between the LED driver chip and an external host via the I2C bus, the clock signal carried on the serial clock line of the I2C bus is continuously and uninterruptedly monitored in real time. This monitoring action is completely parallel to any data transmission or reception activity currently taking place on the I2C bus, without interruption. The LED driver chip has an internal frequency self-calibration module, which is controlled by a self-calibration enable signal. This signal is generated by the LED driver chip's built-in I2C communication module after receiving a register configuration command from the external host and is output to the frequency self-calibration module. When the self-calibration enable signal is invalid, the frequency self-calibration module does not perform any calibration-related operations and remains in an idle or low-power state. When the self-calibration enable signal flips to an active state, the calibration window generation logic inside the frequency self-calibration module is activated, and real-time monitoring of the clock signal on the serial clock line begins, cycle by cycle. When the self-calibration enable signal remains active and a clock signal flips on the serial clock line, the frequency self-calibration module automatically generates a calibration window according to a preset window truncation rule. In the specific windowing mechanism, the effective window counter inside the frequency self-calibration module, under the premise that the self-calibration enable signal is valid, cyclically counts the falling edges of the serial clock line. Whenever the count value is greater than 0, a high-level valid calibration signal is generated. The effective timing interval defined by this valid calibration signal is the calibration window. Since the cyclic counting of the effective window counter depends only on the occurrence of the falling edge of the serial clock line, and not on the start and end boundaries of the I2C bus communication frame, during the interval between I2C bus communication frames, as long as the serial clock line remains idle at a high level and no falling edge occurs, the effective window counter pauses counting and maintains the current count value. The valid calibration signal maintains its original level state. Counting resumes when the falling edge of the next communication frame arrives. The generation of the calibration window spans the interval of the I2C communication frames in time, realizing continuous windowing that ignores the frame interval. The clock stretching detection and rejection logic operates in parallel during the calibration window generation process. When the clock stretching detection logic circuit detects that the low-level phase of the serial clock line exceeds the maximum allowable low-level duration of the standard I2C bus clock cycle due to the pull-down action of the slave device, it outputs a clock stretching flag signal. The frequency self-calibration module marks the count value of the corresponding round of the current calibration window as invalid or discards it directly based on the clock stretching flag signal. The generation rhythm of the calibration window itself is not interrupted or reset due to the occurrence of the clock stretching phenomenon. When the serial clock line resumes normal flipping after the clock stretching event ends, the effective window counter continues to count from the current count value state and generates subsequent calibration windows.

[0030] S20. Within the calibration window, count the clock pulses output by the RC oscillator built into the LED driver chip to obtain a single count value.

[0031] For example, the duration during which the calibration window identifier signal is in an active state constitutes a well-defined time interval. Within this time interval, an accumulation and counting operation is initiated on the clock pulses output by the RC oscillator integrated within the LED driver chip. The RC oscillator serves as the on-chip clock source for the LED driver chip, and its output clock pulses are continuous periodic square wave signals. The frequency of this signal is the target object to be calibrated. The counting operation is performed by a sampling counter. During the active period of the calibration window identifier signal, the sampling counter uses each rising or falling edge of the clock pulse output by the RC oscillator as a counting trigger event, accumulating each passed pulse cycle by cycle, recording each complete pulse cycle without omission or repetition. The moment the calibration window identifier signal flips from an active state to an inactive state, the sampling counter immediately stops counting and latches the current accumulation result. This latched accumulation result is the single count value corresponding to this calibration window. During the invalid period of the calibration window identifier signal, the single count value latched in the sampling counter remains unchanged, waiting for the arrival of the next calibration window. The sampling counter will not be reset, and the count value it holds represents the total number of oscillation cycles of the RC oscillator within the time interval consisting of multiple consecutive standard serial clock line clock cycles corresponding to the calibration window.

[0032] S30. Based on multiple single count values ​​obtained from different calibration windows, perform an averaging operation to generate a sampled average value.

[0033] For example, each communication frame transmission on the I2C bus may generate an independent calibration window. These calibration windows are temporally separate and do not overlap. Each calibration window independently generates a single count value according to the aforementioned steps. A round-counting counter is set up, which increments once each calibration window occurs to record the number of valid calibration windows accumulated. When the round-counting counter reaches a preset sampling round value, such as 10, it indicates that 10 single count values ​​generated by different independent calibration windows have been continuously acquired. These 10 single count values ​​correspond to 10 equal-length measurement time intervals consisting of 8 consecutive serial clock line clock cycles. An arithmetic mean is performed on these 10 single count values, i.e., the 10 single count values ​​are summed, and then the sum is divided by 10. The resulting arithmetic mean is the sampled average. This sampling average, calculated by averaging multiple independent measurement data sets, suppresses random counting errors introduced by instantaneous periodic jitter of the serial clock line or short-term frequency fluctuations of the RC oscillator itself in a single measurement, thus improving the representativeness and stability of the frequency measurement results. After the averaging calculation is completed, the round statistical counter and the sampling counter are synchronously reset to zero to start the next round of 10 sampling accumulation cycles.

[0034] S40. Compare the average sample value with the pre-stored standard count value to obtain the frequency error value.

[0035] For example, a standard count value is pre-stored in the non-volatile memory area of ​​the LED driver chip. This standard count value is obtained during the factory testing phase of the LED driver chip by counting the clock pulses output by the built-in RC oscillator of the LED driver chip, based on a reference frequency provided by an external high-precision standard clock source, under the same calibration window conditions, i.e., within an equal-length measurement time interval consisting of eight consecutive standard I2C bus serial clock line clock cycles. This reference count value represents the number of pulses that the RC oscillator should theoretically output within a fixed time window when operating at its nominal design frequency. The sampled average value obtained by averaging the count values ​​from 10 independent calibration windows in step S30 is subtracted from the aforementioned pre-stored standard count value to obtain the difference between the two. This difference is the frequency error value. The absolute value of the frequency error directly reflects the degree of deviation of the actual output frequency of the current RC oscillator from its nominal design frequency. A positive frequency error value indicates that the measured count value is greater than the standard count value, and the corresponding actual output frequency of the RC oscillator is too high; a negative frequency error value indicates that the measured count value is less than the standard count value, and the corresponding actual output frequency of the RC oscillator is too low.

[0036] S50. Adjust the tuning control parameters of the RC oscillator according to the frequency error value to correct the output frequency of the RC oscillator.

[0037] For example, the tuning control parameters include coarse-tuning control codes and fine-tuning control codes, which respectively act on different frequency adjustment units within the RC oscillator. The coarse-tuning control code adjusts the output frequency of the RC oscillator in a step-like manner with a larger frequency step value. The frequency change caused by a single adjustment is relatively large, suitable for quickly correcting large frequency deviations caused by factors such as process variations. The fine-tuning control code adjusts the output frequency of the RC oscillator in micro-steps with a smaller frequency step value. The frequency change caused by a single adjustment is relatively small, suitable for accurately compensating for small frequency drifts caused by factors such as operating voltage fluctuations and ambient temperature changes. The frequency step values ​​corresponding to the coarse-tuning and fine-tuning control codes are determined during the chip design stage based on the tuning characteristics of the RC oscillator. The frequency step value corresponding to the coarse-tuning control code is greater than that corresponding to the fine-tuning control code. Together, they achieve graded frequency adjustment from rapid convergence over a large range to fine correction over a small range. A coarse-tuning threshold and a fine-tuning threshold are preset, with the absolute value of the coarse-tuning threshold being greater than the absolute value of the fine-tuning threshold. When the absolute value of the frequency error calculated in step S40 is greater than the coarse adjustment threshold, it is determined that the current frequency deviation of the RC oscillator has exceeded the coarse adjustment calibration range. The coarse adjustment control code is adjusted according to the positive or negative direction of the frequency error value: when the frequency error value is positive, the coarse adjustment control code is decreased to reduce the oscillation frequency; when the frequency error value is negative, the coarse adjustment control code is increased to increase the oscillation frequency. When the absolute value of the frequency error value is between the fine adjustment threshold and the coarse adjustment threshold, it is determined that the current frequency deviation of the RC oscillator is in a small deviation state. The fine adjustment control code is adjusted according to the positive or negative direction of the frequency error value: when the frequency error value is positive, the fine adjustment control code is decreased to slightly decrease the oscillation frequency; when the frequency error value is negative, the fine adjustment control code is increased to slightly increase the oscillation frequency. When the absolute value of the frequency error value is not greater than the fine adjustment threshold, it is determined that the current output frequency of the RC oscillator meets the design accuracy requirements, and the current settings of the coarse and fine adjustment control codes remain unchanged. The output frequency of the RC oscillator, after being corrected by the tuning control parameters, serves as the system clock of the LED driver chip and the reference clock for the PWM dimming timing, generating a corresponding PWM drive signal to drive the LED light-emitting unit. During the subsequent normal I2C communication between the LED driver chip and the external host, steps S10 to S50 are continuously executed in a loop, performing uninterrupted dynamic real-time calibration of the RC oscillator's output frequency throughout the chip's entire operating cycle.

[0038] In the aforementioned frequency calibration method for LED driver chips, and the solution provided by the LED driver chip and LED luminaire, the method is applied to the LED driver chip, which is connected to an external host via an I2C bus. The I2C bus includes a serial clock line. The method involves: during normal I2C communication between the LED driver chip and the external host, real-time monitoring of the clock signal on the serial clock line of the I2C bus; generating a calibration window when multiple consecutive clock cycles are detected; counting the clock pulses output by the RC oscillator built into the LED driver chip within the calibration window to obtain a single count value; averaging multiple single count values ​​obtained from different calibration windows to generate a sampled average value; comparing the sampled average value with a pre-stored standard count value to obtain a frequency error value; and adjusting the tuning control parameters of the RC oscillator according to the frequency error value to correct the output frequency of the RC oscillator. By monitoring the serial clock line in real time during normal I2C communication between the LED driver chip and the external host, and generating a calibration window using multiple consecutive clock cycles, the output pulses of the built-in RC oscillator are counted within the window. The frequency error value is obtained by comparing the average of the count values ​​obtained from multiple independent calibration windows with the pre-stored standard count value. The tuning control parameters of the RC oscillator are then adjusted to correct the output frequency. Thus, dynamic real-time self-calibration of the RC oscillator frequency is achieved without adding hardware pins, interrupting normal display communication, or occupying the computing resources of the external host.

[0039] In one embodiment, such as Figure 2 As shown, step S10, which involves generating a calibration window after detecting a self-calibration enable signal, specifically includes the following steps: S11. After receiving the self-calibration enable signal, continuously detect the falling edge of the clock on the serial clock line.

[0040] S12. Each time a falling edge of the clock is detected, the effective window counter is triggered to perform an accumulation count.

[0041] S13. When the count value of the effective window counter reaches the preset value N, it is reset to zero on the next falling edge of the clock, forming a cyclic counting mechanism from 0 to N.

[0042] S14. When the count value of the effective window counter is greater than 0, it is determined that the current calibration window is valid, and a high-level valid calibration signal is generated.

[0043] During normal display grayscale data transmission or control register read / write operations between the LED driver chip and the external host via the I2C bus, a periodic clock signal driven by the external host is continuously generated on the serial clock line. This clock signal experiences a complete high-level phase and a complete low-level phase during the transmission of each data bit, thus forming a continuous clock cycle sequence. In step S11, the signal level transitions on the serial clock line are detected in real time cycle by cycle. The trigger event for detection is the falling edge of the serial clock line transitioning from high to low. Each falling edge marks the end of one clock cycle and the beginning of a new clock cycle. In step S12, the effective window counter increments its internally stored binary value by 1 each time a falling edge of the serial clock line is detected. The bit width of the effective window counter is sufficient to accommodate the binary representation of the preset value N. The accumulation operation of this register is driven by the falling edge of the serial clock line, and the accumulation action is edge-synchronized with the actual transition of the serial clock line. In step S13, when the current count value of the effective window counter accumulates to the preset value N, the count value indicates that N complete clock cycles have passed continuously. The next detected falling edge of the clock triggers two actions simultaneously: clearing the count value of the effective window counter to 0, and taking the count value 0 as the starting state of a new round of cyclic counting cycle, forming a periodic cyclic counting mode that increments from 0 to N and then returns to zero. This cyclic counting mode operates synchronously with the continuous serial clock signal on the I2C bus. In step S14, the numerical range of the effective window counter's count value from 0 to N is used as the basis for determining whether the current period is within an effective calibration window. When the count value is 0, it indicates that the current period is between calibration windows or the moment when the calibration window has just ended, and the calibration effective signal remains in a low-level invalid state. When the count value is greater than 0, it indicates that the current period is within the internal timing interval of a calibration window, and the calibration effective signal flips to a high-level effective state. The calibration effective signal becomes effective from the falling edge of the clock when the count value becomes 1 and continues until the falling edge of the clock when the count value returns to zero. During the duration of the high-level effective signal, a precise effective measurement time interval is defined.

[0044] In this embodiment, an effective window counter is used to perform edge-synchronized cyclic counting of the falling edge of the serial clock line. The count value of the effective window counter is used as the criterion for determining the calibration window. When the count value is between 1 and N, a high-level valid calibration signal is continuously output. The high-level duration of this valid calibration signal exactly covers N complete serial clock line clock cycles. The start and end boundaries of the calibration window are strictly aligned with the falling edge of the serial clock line, providing an effective timing interval with a fixed time length and precise edge position for subsequent pulse counting operations. From the timing generation level, the deterministic correspondence between the calibration window and the I2C bus standard communication timing is guaranteed, eliminating the counting time reference error introduced by the fuzzy window boundary.

[0045] In one embodiment, the preset value N is 8. The effective window counter increments its internal count by 1 each time a falling edge of the serial clock line is detected. Starting from reset state 0, the count increases to 8 after eight consecutive falling edges of the serial clock line. At the arrival of the ninth falling edge, the effective window counter resets its count from 8 to 0, starting a new cycle. Each integer value of the effective window counter from 1 to 8 corresponds to the first to eighth complete serial clock line clock cycles within the calibration window. The calibration valid signal remains high for the duration of these eight clock cycles. The rising edge of the calibration valid signal occurs at the falling edge of the clock line where the count changes from 0 to 1, and the falling edge occurs at the falling edge of the clock line where the count changes from 8 to 0. The total duration of the valid timing interval defined by the valid calibration signal is the sum of the durations of 8 consecutive serial clock line clock cycles. The duration of the calibration window is consistent with the duration of 8 standard clock cycles required for the I2C bus to transmit one byte of data. The opening and closing times of the calibration window are locked to the standard communication timing nodes of the I2C bus.

[0046] In this embodiment, the preset value N is set to 8 so that the time length of the calibration window corresponds to the number of standard clock cycles for transmitting one byte of data on the I2C bus. The boundary of the calibration window naturally coincides with the timing boundary of the I2C bus byte transmission. The effective timing interval defined by the calibration valid signal exactly covers the time span of 8 consecutive standard clock cycles on the I2C bus. This makes it possible to form a precise match in terms of time length and phase relationship between the time base of the pulse counting operation and the standard byte transmission timing generated by the external host in the I2C bus communication. This provides a standardized time window that is deeply coupled with the I2C bus communication protocol for the measurement of the RC oscillator output frequency.

[0047] In one embodiment, such as Figure 3As shown, step S30, which involves averaging multiple single count values ​​obtained from different calibration windows to generate a sampled average, specifically includes the following steps: S31. A two-stage counter structure is adopted, with a single-frame sampling counter and a round-counting counter configured.

[0048] S32. During the valid period of the calibration window, the clock pulses output by the RC oscillator are accumulated and counted by the single-frame sampling counter.

[0049] S33. During the invalid period of the calibration window, the count value of the single-frame sampling counter remains latched.

[0050] S34. The round-counting counter is triggered to increment at the beginning of each calibration window. When the count value of the round-counting counter reaches the preset sampling round, the sampling termination mechanism is triggered.

[0051] In step S31, the frequency self-calibration module internally sets up two independent and functionally separate digital counters: a single-frame sampling counter and a round-counting counter. The single-frame sampling counter is responsible for accumulating the clock pulses output by the RC oscillator cycle by cycle within a single calibration window. The round-counting counter is responsible for recording the cumulative number of completed valid calibration windows. The two counters are independent in terms of counting objects, triggering conditions, and data usage, and work together through timing coordination to complete the multi-round sampling and statistics function. In step S32, when the calibration valid signal is in a high-level valid state, it indicates that the current time is within the time interval of a valid calibration window. The single-frame sampling counter uses the rising or falling edge of the clock pulse output by the RC oscillator as the counting trigger event, and performs an accumulation operation once for each complete pulse cycle. The count value of the single-frame sampling counter monotonically increases as the RC oscillator clock pulse continues to flip, and the rate of increase of the count value is equal to the actual oscillation frequency of the RC oscillator. The counting process continues throughout the entire valid calibration window without interruption or pause. In step S33, when the calibration valid signal flips from a high-level valid state to a low-level invalid state, it indicates that the current calibration window has ended. The single-frame sampling counter immediately stops its accumulation counting operation, and its current accumulated count value is latched and held. This latched value is the total number of complete clock pulse cycles output by the RC oscillator within the current calibration window. During the invalid period of the calibration window, the single-frame sampling counter does not perform counting, does not reset, and does not lose the latched count value. The latched count value is stably held until the arrival of the next calibration window or until the sampling termination mechanism is triggered and read for use. In step S34, the round-counting counter uses the rising edge of the calibration valid signal as the trigger clock event for auto-incrementing. The rising edge of the calibration valid signal marks the official start of a new calibration window. Each time the rising edge of the calibration valid signal occurs, the round-counting counter increments its internal count value by 1. This count value dynamically reflects the cumulative number of independent calibration windows that have been experienced. When the count value of the round-counting counter accumulates to the value of the preset sampling round, the sampling termination mechanism is triggered. The sampling termination mechanism takes effect at the rising edge of the next calibration valid signal and performs termination operations such as data latching, counter reset, and status flag update at the end of the current complete sampling cycle.

[0052] In this embodiment, a two-stage counter structure consisting of a single-frame sampling counter and a round-based statistical counter clearly separates the pulse accumulation operation within the calibration window from the count value holding operation during the interval between calibration windows in terms of counting timing. The single-frame sampling counter performs accumulation during the valid calibration signal period and latches during the invalid period. The time interval between I2C bus communication frames will not cause the loss or confusion of the single-frame sampling counter count value. The round-based statistical counter uses the rising edge of the valid calibration signal as the self-incrementing trigger condition, and strings together multiple independent calibration windows that are separated in time into a complete statistical cycle with a defined number of sampling rounds. This provides multiple sets of original count value data with clear sources, fixed quantities, and standardized timing for subsequent averaging calculations.

[0053] In one embodiment, such as Figure 4 As shown, step S34, which triggers the sampling termination mechanism, specifically includes the following steps: S341, Position calibration complete indicator signal.

[0054] S342. Latch the currently obtained single count value to the configuration register.

[0055] S343. Reset the single-frame sampling counter and the round statistics counter to zero simultaneously to start the next round of sampling iteration.

[0056] When the count value of the round statistics counter reaches the preset sampling round, at the rising edge of the next valid calibration signal, the timing control logic inside the frequency self-calibration module synchronously triggers the execution of the sampling termination mechanism. In step S341, the calibration completion flag signal is an internal status indication signal, which is set to a high level when the calibration termination mechanism is triggered. The high level of the calibration completion flag signal indicates to the averaging unit and comparison judgment unit inside the frequency self-calibration module that the current round of complete multi-window sampling process has ended and the valid sampling data available for reading is ready. After detecting that the calibration completion flag signal is in a high level valid state, the averaging unit starts reading and calculating the accumulated multiple sets of single count values. In step S342, the currently obtained single-count value is the count value accumulated and latched by the single-frame sampling counter within the current last calibration window. This count value is latched from the output of the single-frame sampling counter to the data storage unit of the configuration register when the calibration termination mechanism is triggered. The configuration register provides a stable parallel data output interface for the subsequent averaging unit and comparison judgment unit to read the count value at any time. After the latching action is completed, the data stored in the configuration register remains stable until the next round of sampling termination mechanism updates its content again. In step S343, the single-frame sampling counter and the round statistics counter are synchronously cleared to zero within the same clock cycle of the sampling termination mechanism execution. The count value of the single-frame sampling counter is reset from the current latched value to 0, and the count value of the round statistics counter is reset from the preset sampling round to 0. Both counters return to their initial state simultaneously, providing a clean counting starting point for the sampling accumulation process of the 10 independent calibration windows in the next round. The next round of sampling iteration automatically starts at the rising edge of the first calibration valid signal after clearing.

[0057] In this embodiment, the sampling completion mechanism seamlessly connects the data output of the previous sampling cycle with the initialization of the next sampling cycle through three operations: setting the calibration completion flag signal, latching the single count value to the configuration register, and synchronously clearing the two-stage counters. The calibration completion flag signal provides a clear data ready indication for the averaging unit, the configuration register provides a stable hardware carrier for storing and reading multiple sets of count values, and the synchronous clearing of the counters ensures the state independence and timing continuity between adjacent sampling cycles. The entire multi-round sampling process forms a closed-loop working mode that is connected end to end and iteratively cycles.

[0058] In one embodiment, the preset sampling round is 10 times, and the averaging operation is performed by averaging the 10 single count values ​​obtained from different independent calibration windows. During normal I2C communication between the LED driver chip and the external host, the external host periodically sends display grayscale data frames or register read / write instruction frames to the LED driver chip. During each independent I2C communication frame transmission, multiple consecutive standard clock cycles appear on the serial clock line. The frequency self-calibration module extracts a calibration window consisting of 8 consecutive clock cycles from the serial clock line signal of each communication frame and performs a pulse counting operation within this calibration window to obtain a single count value. This process is repeated in 10 independent I2C communication frame transmissions, accumulating 10 single count values. These 10 single count values ​​correspond to the RC oscillator output pulse counting results within 10 calibration windows of equal time length and separated from each other on the time axis. These 10 single count values ​​are fed into the sampling buffer averaging unit. The sampling buffer averaging unit has a built-in accumulator that adds the 10 single count values ​​sequentially to obtain a sum. Then, the sum is divided by 10, and the quotient is the sampled average value. This sampled average value is obtained by performing an arithmetic average of the count values ​​within 10 independent equal-length measurement windows. This ensures that random counting deviations caused by the instantaneous periodic jitter of the serial clock line or the short-term frequency fluctuations of the RC oscillator itself in each measurement are canceled out during the summation process. The averaged result is closer to the count value corresponding to the true average output frequency of the RC oscillator under the current operating conditions.

[0059] In this embodiment, the preset sampling round is 10 times. By arithmetically averaging the single count values ​​of 10 calibration windows that are independent in time and have the same measurement conditions, and taking advantage of the statistical characteristic that random errors follow a normal distribution and have an expected value of zero in multiple independent measurements, the positive and negative random deviations caused by the instantaneous jitter of the serial clock line or the short-term fluctuations of the RC oscillator in each measurement are canceled out in the averaging calculation. The standard deviation of the random error of a single measurement converges to about one-third of the original standard deviation after averaging 10 sets. The stability and representativeness of the sampled average value are improved, providing a higher confidence level for frequency deviation assessment for subsequent comparison with the standard count value.

[0060] In one embodiment, such as Figure 5 As shown, before step S10, that is, before real-time monitoring of the clock signal on the serial clock line of the I2C bus, the method also includes a calibration enable step, which specifically includes the following steps: S01. The I2C communication module built into the LED driver chip receives register configuration instructions sent by the external host.

[0061] The S02 and I2C communication modules output a global calibration enable signal to the frequency self-calibration module according to the register configuration instructions.

[0062] S03. When the global calibration enable signal is valid, the frequency self-calibration module performs the steps of monitoring, generating calibration windows, counting, averaging, comparing, and adjusting.

[0063] At any time during the power-on or normal operation of the LED driver chip, an external host can send a register configuration command to the LED driver chip via the I2C bus. This register configuration command is a standard I2C register write command, and its format includes the LED driver chip's I2C slave address, the internal address of the target register, and the configuration data to be written. Specific positions or fields in the configuration data are used to control the enabling or disabling of the frequency self-calibration function. In step S01, the I2C communication module built into the LED driver chip parses the address and data information on the serial data line according to the I2C bus protocol specification. When the received slave address matches the LED driver chip's own preset address and the subsequently received register address points to the frequency calibration control register, the I2C communication module writes the corresponding bit value from the configuration data into the corresponding bit field of the frequency calibration control register. In step S02, the I2C communication module has a hardware signal interface with the frequency self-calibration module. When a valid value is written to the bit field corresponding to the frequency self-calibration enable in the frequency calibration control register, the I2C communication module outputs a global calibration enable signal to the frequency self-calibration module through the hardware signal interface. The global calibration enable signal is a continuously high-level enable control signal. The high-level state of the global calibration enable signal indicates that the frequency self-calibration function has been authorized and enabled by the external host, and the low-level state of the global calibration enable signal indicates that the frequency self-calibration function has been disabled by the external host or has not yet been enabled. In step S03, after the frequency self-calibration module receives the global calibration enable signal as being in a high-level active state, its internal SCL pulse capture unit, RC pulse counting unit, sampling buffer averaging unit, and threshold judgment and tuning control unit all enter an active working state, start real-time monitoring of the clock signal on the I2C bus serial clock line, and execute a complete closed-loop calibration process according to the steps described in the previous embodiment, including calibration window generation, pulse counting, multi-window averaging, standard count value comparison, and tuning control parameter adjustment. The functional units inside the frequency self-calibration module continuously and cyclically execute the above calibration process throughout the entire time period during which the global calibration enable signal remains high.

[0064] In this embodiment, the activation and deactivation of the frequency self-calibration function are remotely controlled at the software level by an external host sending standard register configuration instructions via the I2C bus. The LED driver chip does not need to add additional enable pins or dedicated control interfaces. The I2C communication module and the frequency self-calibration module transmit the enable state through an internal global calibration enable signal. The frequency self-calibration module only enters the working state when the global calibration enable signal is valid, and is in a low-power inactive state when the global calibration enable signal is invalid. This configurable control mechanism allows the external host to flexibly choose to enable or disable the frequency self-calibration function according to the actual working scenario and display quality requirements of the LED lamp. Disabling this function in application scenarios where frequency calibration is not required can reduce the dynamic power consumption of the LED driver chip.

[0065] In one embodiment, the register configuration instruction is a standard I2C register write instruction. The transmission format of this register configuration instruction on the I2C bus consists of a start condition, the slave address byte of the LED driver chip, the register address byte, the configuration data byte, and a stop condition. This transmission format is completely consistent at the bus transmission level with the instruction format of the external host writing grayscale data to the LED driver chip and the instruction format of the external host reading the LED driver chip's status register. It does not require the external host's I2C controller to generate any non-standard timing waveforms or dedicated instruction codes. When the SCL pulse capture unit inside the frequency self-calibration module monitors the clock signal on the serial clock line in real time, its monitoring circuit is only connected to the output of the serial clock line's input buffer using a high input impedance detection method. It does not generate any pull-up or pull-down drive on the serial clock line and does not affect the level state or timing slope of the serial clock line. When the RC pulse counting unit performs pulse counting operations, its counting clock comes from the output of the RC oscillator inside the LED driver chip, and it is isolated from the I2C bus's data transmission and reception logic in the clock domain. The addition and division operations performed by the sampling buffer averaging unit during averaging are all completed within the digital logic circuitry of the LED driver chip, without involving any read or write access to the I2C bus signals. The threshold judgment and tuning control unit updates the coarse and fine tuning control codes via the LED driver chip's internal register bus, which is physically independent of the I2C bus. All operations of the frequency self-calibration module form an independent background processing channel within the LED driver chip, communicating in parallel with the I2C bus. During calibration, the LED driver chip's PWM dimming signal generation logic continuously generates a fixed-frequency or modulated PWM drive signal based on the current RC oscillator output frequency. The LED driver chip's drive output to the LED light-emitting unit does not experience timing interruptions or amplitude abrupt changes due to the operation of the frequency self-calibration module.

[0066] In this embodiment, the register configuration instruction adopts the standard I2C register writing format that is completely consistent with the normal display data writing instruction. The I2C communication software protocol stack of the external host does not need to develop a dedicated instruction interface for the frequency self-calibration function. The signal monitoring, pulse counting, averaging and parameter adjustment operations of the frequency self-calibration module are all executed in parallel in the background within the LED driver chip in a pure background mode without occupying the I2C bus bandwidth, interfering with the I2C bus level state, or interrupting the I2C communication frame transmission. The LED driver chip maintains continuous output of the PWM drive signal of the LED light-emitting unit during the calibration process, realizing the hardware-level parallel coexistence of the frequency calibration function and the LED display driving service. This eliminates the problem of momentary abnormalities in the LED display screen caused by the calibration process occupying the communication bus or interrupting the display service in traditional calibration schemes.

[0067] In one embodiment, such as Figure 6 As shown, step S50, which involves adjusting the tuning control parameters of the RC oscillator based on the frequency error value, specifically includes the following steps: S51. Preset coarse adjustment threshold and fine adjustment threshold, where the absolute value of the coarse adjustment threshold is greater than the absolute value of the fine adjustment threshold.

[0068] S52. Compare the absolute value of the frequency error with the coarse adjustment threshold and the fine adjustment threshold.

[0069] S53. When the absolute value of the frequency error is greater than the coarse adjustment threshold, the coarse adjustment control code is increased or decreased; when the absolute value of the frequency error is between the fine adjustment threshold and the coarse adjustment threshold, the fine adjustment control code is increased or decreased; when the absolute value of the frequency error is not greater than the fine adjustment threshold, the current settings of the coarse adjustment control code and the fine adjustment control code remain unchanged.

[0070] In this embodiment, a hierarchical closed-loop calibration logic is established by setting two-level judgment intervals consisting of a coarse adjustment threshold and a fine adjustment threshold. When the absolute value of the frequency error is greater than the coarse adjustment threshold, the coarse adjustment control code is activated to achieve rapid convergence of a large range of frequency deviations. When the absolute value of the frequency error is between the fine adjustment threshold and the coarse adjustment threshold, the fine adjustment control code is activated to achieve precise correction of small deviations. When the absolute value of the frequency error is not greater than the fine adjustment threshold, the current tuning control parameters are kept unchanged. This avoids introducing clock jitter and frequency fluctuations due to unnecessary parameter fine-tuning when the frequency already meets the accuracy requirements, thus balancing the convergence speed and steady-state accuracy of frequency calibration.

[0071] In one embodiment, the coarse adjustment control code controls the number of capacitor branches connected in the switched capacitor array inside the RC oscillator, adjusting the oscillation frequency in steps with a first step value. Each step corresponds to a relatively large frequency change, which can cover a large range of initial frequency deviations caused by semiconductor process variations. The fine adjustment control code controls the output current of the adjustable bias current source inside the RC oscillator, or controls the bias voltage across the varactor diode, adjusting the oscillation frequency in microsteps with a second step value. Each step corresponds to a relatively small frequency change, which can finely compensate for small frequency drifts caused by fluctuations in operating voltage and changes in ambient temperature. The first step value is greater than the second step value, allowing the coarse adjustment control code to quickly bring the output frequency of the RC oscillator closer to the nominal frequency in fewer adjustment steps. After the coarse adjustment, the fine adjustment control code corrects the remaining deviation with a finer granularity. The differentiated design of the adjustment step size between the two levels of adjustment achieves a balance between convergence speed and adjustment accuracy.

[0072] In one embodiment, the specific values ​​of the coarse adjustment threshold and the fine adjustment threshold are set based on the statistical distribution data of batch process deviations of RC oscillators in an uncalibrated state. Frequency testing is performed on batch-produced RC oscillator samples at the same process node. The actual output frequency distribution range of the RC oscillator in the uncalibrated state is typically 80% to 120% of the nominal frequency, with a maximum single frequency deviation reaching ±20% of the nominal frequency. Based on this statistical distribution characteristic, the coarse adjustment threshold is set to ±5% of the standard count value corresponding to the nominal frequency. When the measured average deviation from the standard count value exceeds 5%, it is determined that the RC oscillator has a significant process deviation, and the coarse adjustment control code is activated for adjustment. The fine adjustment threshold is set to ±1.5% of the standard count value corresponding to the nominal frequency. When the measured average deviation from the standard count value is between 1.5% and 5%, it is determined that the RC oscillator has a small deviation, and the fine adjustment control code is activated for adjustment. When the measured average deviation from the standard count value is no greater than 1.5%, it is determined that the output frequency of the RC oscillator meets the design accuracy requirements, and the current tuning control parameters remain unchanged.

[0073] In one embodiment, after performing a coarse adjustment or a fine adjustment using a control code, a preset calibration cooling cycle is initiated. The duration of this calibration cooling cycle can be set according to the setup time required for the RC oscillator's output frequency to reach a stable state after the tuning control parameters are updated. During the calibration cooling cycle, even if the LED driver chip and the external host perform a new round of I2C communication and recalculate a new frequency error value according to the aforementioned steps, and the absolute value of this new frequency error value exceeds the corresponding coarse or fine adjustment threshold, the frequency self-calibration module will not perform the next coarse or fine adjustment operation until the calibration cooling cycle ends. The normal response to the frequency error value will only resume after the calibration cooling cycle has finished. The calibration cooling cycle avoids the instantaneous count fluctuations caused by the RC oscillator's output frequency not yet stabilizing during the frequency setup transition after the tuning control parameters are updated being misjudged as new frequency deviations and triggering unnecessary repeated adjustments. This suppresses clock jitter introduced by frequent switching of tuning control parameters and ensures that the RC oscillator's output frequency can smoothly transition to a steady state after the parameter update.

[0074] In one specific embodiment, the LED driver chip integrates a frequency self-calibration module. This frequency self-calibration module is integrated at the digital logic level of the chip within the clock domain of the I2C slave interface circuit. It is divided into four sub-modules: an SCL pulse capture unit, an RC pulse counting unit, a sampling buffer averaging unit, and a threshold judgment and RC tuning control unit. The sub-modules are connected through an internal data bus and control signal lines to collaboratively complete the complete closed-loop calibration process from calibration window generation to tuning control code output.

[0075] The input terminal of the SCL pulse capture unit is connected to the internal signal node of the I2C serial clock line input pin of the LED driver chip via the input buffer. The SCL pulse capture unit performs real-time monitoring of the clock signal transmitted on the serial clock line cycle by cycle. The SCL pulse capture unit contains a clock stretch detection logic circuit and a timing window generation state machine. The clock stretch detection logic circuit continuously monitors the duration of the low-level phase of the serial clock line in each clock cycle. When it detects that the low-level phase of the serial clock line exceeds the maximum allowable low-level duration of the standard I2C bus clock cycle due to the pull-down action of the slave device on the I2C bus, the clock stretch detection logic circuit determines that there is a clock stretch phenomenon in the current clock cycle and outputs a clock stretch flag signal. This clock stretch flag signal marks the sampling qualification of the current calibration window as invalid. The SCL pulse capture unit abandons the timing enable signal output of the current window, ensuring that only the standard I2C communication phase without clock stretch and without interruption is selected as the calibration reference time interval. When the timing window generation state machine detects eight consecutive complete serial clock line clock cycles without clock stretching, it generates a timing enable signal of fixed duration. The high-level active phase of this timing enable signal precisely covers the time interval formed by the aforementioned eight consecutive standard clock cycles.

[0076] The input of the RC pulse counting unit is connected to the timing enable signal output of the SCL pulse capture unit, and the input of the RC pulse counting unit is connected to the clock output buffer of the built-in RC oscillator of the LED driver chip. During the duration of the timing enable signal being high, the binary counter inside the RC pulse counting unit uses the rising edge of the clock pulse output by the RC oscillator as the counting trigger event, performing an accumulation count operation for each complete RC oscillator clock cycle. The bit width of the counter meets the requirement of counting the total number of pulses at the highest output frequency of the RC oscillator without overflow within the maximum possible duration of the calibration window. When the timing enable signal flips from high to low, the RC pulse counting unit stops counting and latches the current accumulated count value into a buffer register connected to the output of the RC pulse counting unit. The RC count value stored in this buffer register within a single window is read by the sampling buffer averaging unit in subsequent steps.

[0077] The data input of the sampling buffer averaging unit is connected to the output of the buffer register of the RC pulse counting unit via an internal data bus. The sampling buffer averaging unit has a sampling register array with a depth of 10 groups. Each group of registers in this array sequentially stores the RC count value generated within a single window of the independent calibration window. The sampling buffer averaging unit also includes write pointer control logic. The write pointer increments after each update of the buffer register data in the RC pulse counting unit, sequentially storing the RC count values ​​of the 10 independent calibration windows into the 1st to 10th groups of the sampling register array. Once all 10 storage locations in the sampling register array have been written with valid data, the adder tree inside the sampling buffer averaging unit performs parallel summation of the 10 count values. The sum is then fed into a divider for division by 10. The quotient output by the divider is the sampled average value, which represents the arithmetic mean of the number of RC oscillator output pulses within 10 equal-length measurement time windows.

[0078] The input terminal of the threshold judgment and RC tuning control unit is connected to the average value output terminal of the sampling buffer averaging unit. The input terminal of the threshold judgment and RC tuning control unit is also connected to the standard count value output interface of the non-volatile memory of the LED driver chip. This non-volatile memory stores the standard count value corresponding to the RC oscillator at the nominal design frequency within the same calibration window, as well as the allowable coarse and fine adjustment thresholds. The subtractor inside the threshold judgment and RC tuning control unit subtracts the average value from the standard count value to obtain the frequency error value. The digital comparator inside the threshold judgment and RC tuning control unit compares the absolute value of the frequency error value with the coarse and fine adjustment thresholds step by step. When the absolute value of the frequency error value is greater than the coarse adjustment threshold, the threshold judgment and RC tuning control unit outputs an updated coarse adjustment control code to the switched capacitor array control terminal of the RC oscillator to adjust the oscillation frequency in larger steps. When the absolute value of the frequency error is between the fine-tuning threshold and the coarse-tuning threshold, the threshold judgment and RC tuning control unit outputs an updated fine-tuning control code to the control terminal of the adjustable bias current source or varactor diode of the RC oscillator, adjusting the oscillation frequency in small steps. When the absolute value of the frequency error is not greater than the fine-tuning threshold, the threshold judgment and RC tuning control unit maintains the current output values ​​of the coarse-tuning control code and the fine-tuning control code unchanged, and does not perform tuning.

[0079] In this embodiment, the frequency self-calibration module divides the SCL pulse capture, RC pulse counting, sampling buffer averaging, and threshold judgment and tuning control into four functionally independent hardware sub-modules. Each sub-module forms a clear data flow path and control flow path at the digital logic level. The clock stretching and elimination logic of the SCL pulse capture unit ensures the stability of the calibration reference time interval from the window generation source. The gated counting mechanism of the RC pulse counting unit ensures the accurate correspondence between the single count value and the calibration window duration. The hardware structure of the 10-group deep sampling register array and the parallel summation and averaging of multiple groups of data in the sampling buffer averaging unit suppresses random errors in single sampling in a statistical averaging manner. The two-level threshold comparison and coarse and fine tuning control code split output mechanism of the threshold judgment and RC tuning control unit realizes the hierarchical closed-loop adjustment of the RC oscillator frequency deviation. The collaborative work of the four sub-modules enables the frequency self-calibration module to form a complete independent calibration hardware path within the LED driver chip, which does not rely on external chip resources.

[0080] In a specific embodiment, such as Figure 7 , Figure 8 and Figure 9 As shown, this application provides a specific implementation of a frequency calibration method for an LED driver chip. In this embodiment, the LED driver chip communicates with an external host via an I2C bus (including a serial clock line SCL and a serial data line SDA), and a frequency self-calibration module is integrated inside the chip.

[0081] During normal I2C communication between the LED driver chip and the external host, the chip's internal frequency self-calibration module monitors the clock signal on the serial clock line (SCL) of the I2C bus in real time. Specifically, during normal communication timing, it continuously detects the falling edge of the clock on the serial clock line. Each time a falling edge of the SCL clock is detected, the chip's internal effective window counter (SCL_cnt) is triggered to accumulate the count.

[0082] When the effective window counter (SCL_cnt) reaches a preset value N, the register is reset to zero upon the next falling edge of the SCL clock, thus forming a cyclic counting mechanism from 0 to 8. In this embodiment, the preset value N is 8, meaning that 8 consecutive standard SCL clocks in each frame of IIC communication are fixed as the reference timing window.

[0083] When the effective window counter (SCL_cnt) counts from 0 to 7, it is determined that the current calibration window is active, and a high-level valid calibration signal (calibe_vaild) is generated. While the valid calibration signal (calibe_vaild) is high, the effective timing interval of the calibration count is limited to ensure that the sampling window is fully aligned with the standard communication timing of the I2C bus; when the count reaches 0, the valid calibration signal (calibe_vaild) goes low.

[0084] Provided that a valid calibration signal is generated, the chip's built-in frequency self-calibration module uses a two-stage counter structure to achieve stable multi-cycle sampling. The two-stage counter includes a single-frame sampling counter (cnt) and a round statistics counter (vaild_cnt).

[0085] Specifically, during the period when the calibration valid signal (calibe_vaild) is high, the single-frame sampling counter (cnt) is driven by the clock pulse output from the internal RC oscillator of the chip to accumulate counts cycle by cycle; during the period when the calibration valid signal (calibe_vaild) is low, the current count value of the single-frame sampling counter (cnt) is latched and resumed counting when the next valid calibration window arrives, thereby ensuring the integrity of the count within each valid timing window.

[0086] Meanwhile, the round count counter (vaild_cnt) is triggered to increment only on the rising edge of each valid calibration signal (calibe_vaild), and is used to count the number of independent valid calibration sampling rounds that have been completed.

[0087] When the round count counter (vaild_cnt) accumulates to 9, the rising edge of the next valid calibration signal (calibe_vaild) will trigger the sampling termination mechanism. The sampling termination mechanism specifically includes: Set the calibration completion flag signal (cnt_done); latch the currently obtained single count value into the chip's internal configuration register (compare_data); then synchronously clear the single frame sampling counter (cnt) and the round statistics counter (vaild_cnt) to start the next round of sampling iteration.

[0088] Since the round-counting counter (vaild_cnt) accumulating to 9 indicates that sampling for 10 independent and valid calibration windows has been completed, based on this mechanism, the chip's sampling buffer averaging unit can perform a summation and averaging operation on the single-count values ​​(or real-time outputs) latched in the configuration register to obtain a stable sampling average value. That is, in this embodiment, the single-count values ​​of 10 valid communication cycles are continuously collected, and the random error of a single sampling is eliminated by using an arithmetic mean.

[0089] Before executing the calibration window generation and counting logic described above, the I2C communication module built into the LED driver chip receives a standard register configuration instruction from the external host. This instruction is used to control the start and stop of the frequency self-calibration module, specifically by outputting a global calibration enable signal (iic_calibe_en) to the frequency self-calibration module.

[0090] The frequency self-calibration module only performs the above-mentioned steps of SCL falling edge monitoring, calibration window generation, multi-cycle counting, and averaging calculation when the global calibration enable signal (iic_calibe_en) is valid.

[0091] Furthermore, throughout the entire process, all logical operations of the frequency self-calibration module are executed in parallel with the normal business communication of the LED driver chip (such as driving LED display dimming, SRAM data reading and writing, etc.). The calibration operation does not interrupt normal LED display and I2C communication services, and the dynamic real-time calibration of the RC oscillator frequency can be completed in the background while the chip is working normally.

[0092] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0093] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0094] In the embodiments provided in this application, it should be understood that the disclosed apparatus / devices and methods can be implemented in other ways. For example, the apparatus / device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0095] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0096] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A frequency calibration method for LED driver chips, characterized in that, This technology is applied to LED driver chips, which are connected to an external host via an I2C bus. The I2C bus includes a serial clock line and an effective window counter. During normal I2C communication between the LED driver chip and the external host, the clock signal on the serial clock line of the I2C bus is monitored in real time. After receiving the self-calibration enable signal, the falling edge of the clock on the serial clock line is continuously detected. Each time a falling edge is detected, the effective window counter is triggered to perform an accumulation count. When the count value of the effective window counter reaches a preset value N, it is reset to zero on the next falling edge of the clock, forming a cyclic counting mechanism from 0 to N. When the count value of the effective window counter is greater than 0, it is determined that the current calibration window is active, and a high-level valid calibration signal is generated. The effective window counter's cyclic counting depends only on the occurrence of the falling edge of the clock on the serial clock line, and not on the start and end boundaries of the I2C bus communication frame. During the interval between frames of I2C bus communication, when the serial clock line remains idle at a high level and no falling edge occurs, the effective window counter pauses counting and maintains its current count value. The calibration effective signal maintains its original level and resumes counting when the falling edge of the clock of the next communication frame arrives, so that the generation of the calibration window spans the interval of the I2C communication frames in time, realizing continuous window interception that ignores the frame interval. Within the calibration window, the clock pulses output by the RC oscillator built into the LED driver chip are counted to obtain a single count value; A two-stage counter structure is adopted, including a single-frame sampling counter and a round-counting counter. During the valid period of the calibration window, the single-frame sampling counter accumulates the clock pulses output by the RC oscillator. During the invalid period of the calibration window, the count value of the single-frame sampling counter is latched. The round-counting counter is triggered to increment at the beginning of each calibration window. When the count value of the round-counting counter reaches the preset number of sampling rounds, a sampling termination mechanism is triggered. The average value of the samples is obtained by averaging the count values ​​of the single-frame sampling counter and the round-counting counter. The average value of the samples is compared with the pre-stored standard count value to obtain the frequency error value; Based on the frequency error value, the tuning control parameters of the RC oscillator are adjusted to correct the output frequency of the RC oscillator.

2. The method according to claim 1, characterized in that, The preset value N is 8; the calibration valid signal is used to limit the valid timing interval of the count, ensuring that the calibration window is aligned with the standard communication timing of the I2C bus.

3. The method according to claim 1, characterized in that, The LED driver chip further includes: a configuration register; the trigger sampling termination mechanism includes: Set calibration completion indicator signal; Latch the currently obtained single count value into the configuration register; The single-frame sampling counter and the round statistics counter are synchronously cleared to start the next round of sampling iteration.

4. The method according to claim 3, characterized in that, The preset sampling rounds are 10; the averaging operation is an arithmetic average of the 10 single count values ​​obtained from different independent calibration windows.

5. The method according to claim 1, characterized in that, Before the real-time monitoring of the clock signal on the serial clock line of the I2C bus, a calibration enable step is also included: The LED driver chip has a built-in I2C communication module and a frequency self-calibration module; The I2C communication module receives register configuration instructions from the external host to output a global calibration enable signal to the frequency self-calibration module. The frequency self-calibration module performs the steps of monitoring, generating calibration windows, counting, averaging, comparing, and adjusting only when the global calibration enable signal is valid.

6. The method according to claim 5, characterized in that, The register configuration instruction is a standard I2C register write instruction; during the execution of the monitoring, counting, averaging, comparison and adjustment steps, the frequency self-calibration module performs these steps in parallel with the normal dimming and display services of the LED driver chip, without interrupting the normal I2C communication.

7. An LED driver chip, characterized in that, It is configured to connect to an external host via an I2C bus and perform the method of any one of claims 1 to 6.

8. An LED lighting fixture, characterized in that, include: The LED driver chip according to claim 7; as well as At least one LED light-emitting unit is electrically connected to the LED driver chip and is driven to emit light by the PWM drive signal generated by the LED driver chip.

Images