RC oscillator circuit

Abstract

The invention discloses an RC oscillator circuit, relates to the technical field of integrated circuits, and provides the RC oscillator circuit for solving the problem that an existing RC oscillator cannot flexibly adjust the duty ratio of output square wave signals, and the RC oscillator circuit is characterized in that an adjustable capacitor is connected to the output end of a square wave signal generation module through a first switch; when a square wave signal output by the square wave signal generation module is in a certain level stage, the first switch is closed to enable the adjustable capacitor to be connected to the output end of the square wave signal generation module, and the connected adjustable capacitor enables the square wave signal to generate time delay when the square wave signal is turned from the current level to another level; due to the fact that the capacitance value of the adjustable capacitor is adjustable, time delay generated when the level of the square wave signal is overturned is adjustable, and the effect that the duty ratio of the square wave signal can be freely adjusted is achieved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to an RC oscillator circuit. Background Art

[0002] An oscillator can generate repetitive waveforms and has a wide range of applications in many scenarios such as digital or analog circuits, data transmission, and wireless communication fields. Currently, oscillators can be classified into three types: harmonic oscillators, relaxation oscillators, and ring oscillators. Among them, relaxation oscillators and ring oscillators can be classified as resistor-capacitor (RC) oscillators. RC oscillators have the advantages that the output frequency can be clearly determined, the circuit structure is diverse so that the output frequency can be flexibly set, and the frequency range can cover from more than a dozen Hertz (Hz) to dozens of MHz. Moreover, various techniques for reducing frequency drift indicate that RC oscillators have good prospects in terms of frequency stability and are also easy to integrate on-chip. These advantages make on-chip RC oscillators highly competitive.

[0003] However, current RC oscillators also have some disadvantages that need to be overcome. One of the more critical problems is that it is inconvenient to adjust the duty cycle of the RC oscillator, and the duty cycle of the square wave signal output by the RC oscillator cannot be freely adjusted according to actual needs, which further limits the application of the RC oscillator.

[0004] Therefore, those skilled in the art now urgently need an RC oscillator circuit to provide a solution for an RC oscillator with a flexibly adjustable duty cycle. Summary of the Invention

[0005] The purpose of this application is to provide an RC oscillator circuit to solve the problem that the duty cycle of the output square wave signal of the current RC oscillator cannot be flexibly adjusted.

[0006] To solve the above technical problems, this application provides an RC oscillator circuit, including: an OSC reference generation module, a square wave signal generation module, a tunable capacitor, and a first switch;

[0007] Among them, the OSC reference generation module is connected to the square wave signal generation module and is used to generate a reference current and a first reference voltage;

[0008] The square wave signal generation module is used to generate a square wave signal based on the reference current and the first reference voltage;

[0009] The tunable capacitor is connected to the output end of the square wave signal generation module through the first switch, and the first switch is closed when it is in a certain level stage in each cycle of the square wave signal and is turned off when it is in another level stage.

[0010] In an alternative embodiment, the OSC reference generation module includes: a first operational amplifier, a second operational amplifier, a chopper circuit, a first resistor, a second resistor, a third resistor, a first PMOS transistor, and an NMOS transistor;

[0011] Wherein, the non-inverting terminal of the first operational amplifier is used to access an initial reference voltage; the inverting terminal of the first operational amplifier is connected to the source electrode of the NMOS transistor and grounded through the first resistor, and the voltage at the inverting terminal of the first operational amplifier serves as the first reference voltage;

[0012] The first end of the second resistor is connected to a power supply voltage, and the second end of the second resistor is connected to the first input terminal of the chopper circuit. The voltage at the second end of the second resistor serves as the second reference voltage;

[0013] The output terminal of the first operational amplifier is connected to the gate electrode of the NMOS transistor; the drain electrode of the NMOS transistor is connected to the second input terminal of the chopper circuit and connected to the power supply voltage through the third resistor to provide a third reference voltage;

[0014] The two output terminals of the chopper circuit are respectively connected to the non-inverting terminal and the inverting terminal of the second operational amplifier; the two controlled terminals of the chopper circuit are respectively connected to two complementary chopper clock signals;

[0015] The second end of the second resistor is further connected to the source electrode of the first PMOS transistor, and the gate electrode of the first PMOS transistor is connected to the output terminal of the second operational amplifier; the drain electrode of the first PMOS transistor is connected to the square wave signal generation module to provide the reference current.

[0016] In an alternative embodiment, the first resistor and the second resistor are adjustable resistors;

[0017] This circuit further includes: a resistor trimming module;

[0018] The first resistor and the second resistor include: a plurality of resistors connected in series, and a third switch is connected in parallel across each resistor; the controlled terminals of each third switch are respectively connected to the output terminal of the resistor trimming module.

[0019] In an alternative embodiment, it further includes: a capacitor trimming module;

[0020] The adjustable capacitor includes a plurality of capacitors connected in parallel, and a second switch is connected in series in each parallel branch where a capacitor is located; the controlled terminals of each second switch are respectively connected to the output terminal of the capacitor trimming module.

[0021] In an alternative embodiment, the square wave signal generation module includes: a comparator and a time-varying voltage generation circuit;

[0022] Wherein, the time-varying voltage generating circuit is used to generate a time-varying voltage, and includes: two groups of transmission gates, a fourth switch, and a charge-discharge capacitor;

[0023] The first ends of each of the transmission gates are commonly connected and connected to the reference current, and the common end of each of the transmission gates serves as the output end of the time-varying voltage generating circuit;

[0024] The second ends of each of the transmission gates are respectively connected to the first ends of the corresponding charge-discharge capacitors, the second ends of each of the charge-discharge capacitors are grounded, and corresponding fourth switches are respectively connected in parallel across both ends of each of the charge-discharge capacitors;

[0025] Two control ends of the first group of the transmission gates are respectively connected to the first clock signal and the inverted signal of the first clock signal; two control ends of the second group of the transmission gates are respectively connected to the second clock signal and the inverted signal of the second clock signal; and the first clock signal and the second clock signal are opposite in phase;

[0026] The control end of the fourth switch corresponding to the first group of the transmission gates is connected to the inverted signal of the first clock signal; the control end of the fourth switch corresponding to the second group of the transmission gates is connected to the inverted signal of the second clock signal;

[0027] The inverting input end of the comparator is connected to the time-varying voltage, the non-inverting input end of the comparator is connected to the first reference voltage, and the output end of the comparator serves as the output end of the square-wave signal generating circuit for outputting a square-wave signal.

[0028] In an optional embodiment, the first clock signal and the second clock signal are a set of complementary signals with a dead time between them.

[0029] In an optional embodiment, it further includes: a two-phase non-overlapping clock module;

[0030] The input end of the two-phase non-overlapping clock module is connected to the output end of the square-wave signal generating module, and is used to generate a first clock signal, the inverted signal of the first clock signal, a second clock signal, the inverted signal of the second clock, and two complementary chopping clock signals according to the square-wave signal.

[0031] In an optional embodiment, the square-wave signal generating module further includes: an even number of inverters and a buffer;

[0032] The even number of inverters are connected in series at the output end of the comparator, and the buffer is connected in series at the output end of the comparator;

[0033] And the adjustable capacitor is connected to the output end of the square-wave signal generating module through the first switch, including:

[0034] The first end of the adjustable capacitor is connected to the output end of the comparator through the first switch, and the second end of the adjustable capacitor is connected to the output end of the i-th inverter in series; where i is any even number less than the total number of inverters.

[0035] In an optional embodiment, the first switch is a transmission gate, and the first switch is closed when it is in the high-level stage and turned off when it is in the low-level stage in each cycle of the square wave signal;

[0036] The two controlled ends of the first switch are respectively connected to a first gate control signal and a second gate control signal with opposite phases; the first gate control signal is generated by the first inverter connected in series at the output end of the comparator, and the second gate control signal is generated by the second inverter connected in series at the output end of the comparator.

[0037] In an optional embodiment, it further includes: a second PMOS transistor;

[0038] The source of the second PMOS transistor is connected to the power supply voltage, the drain of the second PMOS transistor is connected to the first end of the adjustable capacitor, and the gate of the second PMOS transistor is connected to the first gate control signal.

[0039] In an optional embodiment, it further includes: a bandgap reference module;

[0040] The bandgap reference module is connected to the non-inverting input end of the first operational amplifier for providing the initial reference voltage.

[0041] In an optional embodiment, it further includes: an LDO module;

[0042] The output voltage of the LDO module serves as the power supply voltage of the RC oscillator circuit.

[0043] In the RC oscillator circuit provided by the present application, an adjustable capacitor is connected through a first switch at the output end of the square wave signal generation module; when the square wave signal output by the square wave signal generation module is in a certain level (for example, high level) stage, the first switch is closed to connect the adjustable capacitor to the output end of the square wave signal generation module, and the connected adjustable capacitor will cause a delay when the square wave signal flips from the current level to another level (such as from high level to low level); since the capacitance value of the adjustable capacitor is adjustable, the delay generated when the square wave signal flips levels is adjustable, thereby achieving the effect of freely adjusting the duty cycle of the square wave signal. This circuit can flexibly adjust the duty cycle of the square wave signal output by the RC oscillator circuit, broaden the applicable scenarios of the RC oscillator, and further improve the competitiveness of the RC oscillator. Description of the Drawings

[0044] To more clearly illustrate the embodiments of the present invention, the accompanying drawings required for use in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0045] Figure 1 It is the circuit schematic diagram of a typical RC oscillator circuit;

[0046] Figure 2 It is the structural diagram of an RC oscillator circuit provided by the present invention;

[0047] Figure 3 It is the structural diagram of an adjustable capacitor provided by the present invention;

[0048] Figure 4 It is the structural diagram of a trimming module provided by the present invention;

[0049] Figure 5 It is the circuit schematic diagram of an RC oscillator circuit provided by the present invention;

[0050] Figure 6 It is the structural diagram of a first resistor with adjustable resistance value provided by the present invention;

[0051] Figure 7 It is the structural diagram of a second resistor with adjustable resistance value provided by the present invention;

[0052] Figure 8 It is the structural diagram of a two-phase non-overlapping clock module provided by the present invention;

[0053] Among them, 10 is the OSC reference generation module, 20 is the square wave signal generation module, 21 is the comparator, 22 is the time-varying voltage generation circuit, 30 is the adjustable capacitor, 40 is the first switch, 50 is the trimming module, 51 is the resistor trimming module, 52 is the capacitor trimming module, 60 is the two-phase non-overlapping clock module, 70 is the bandgap reference module, and 80 is the LDO module. Specific Embodiments

[0054] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0055] The core of the present invention is to provide an RC oscillator circuit.

[0056] To enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0057] At present, common resistor-capacitor (RC) oscillator (OSC) circuits have advantages such as a wide output frequency range, which can reach from more than a dozen Hertz (Hz) to dozens of MHz, and are easy to integrate on-chip. A typical RC oscillator circuit is as Figure 1 shown. However, there are still some problems to be solved in the current RC oscillators. For example, it is inconvenient to adjust the duty cycle, which limits the application scenarios of the RC oscillator and cannot meet the different needs in more diverse scenarios.

[0058] To solve the above problems, the present application provides an RC oscillator circuit, as Figure 2 shown, including: an OSC reference generation module 10, a square wave signal generation module 20, a tunable capacitor 30 (C1), and a first switch 40.

[0059] Among them, the OSC reference generation module 10 is connected to the square wave signal generation module 20 and is used to generate a reference current I2 and a first reference voltage VREF1.

[0060] The square wave signal generation module 20 is used to generate a square wave signal VOUT based on the reference current I2 and the first reference voltage VREF1.

[0061] The tunable capacitor 30 is connected to the output end of the square wave signal generation module 20 through the first switch 40. The first switch 40 is closed when the square wave signal VOUT is in the high-level stage in each period and is turned off when it is in the low-level stage.

[0062] It should be noted that in this embodiment, the main parts for realizing the adjustable duty cycle of the square wave signal are the above-mentioned tunable capacitor 30 and the first switch 40, and the remaining parts are used to realize the basic functions of the RC oscillator. Therefore, in this embodiment, the remaining circuit parts other than the tunable capacitor 30 and the first switch 40 are not restricted for the time being and can be implemented by using the solutions in the current common RC oscillator circuit designs. For example, the reference circuit can adopt a bandgap reference circuit, and the optional implementation manners of the remaining circuit parts will not be elaborated.

[0063] And it should be emphasized that an adjustable capacitor 30 is added to the output end of the square wave signal in this circuit. According to the basic characteristics of the capacitor, if a capacitor is connected to the output end of the square wave signal, the square wave signal will have a delay when flipping, and the delay time is related to the capacitance value of the capacitor. Further, if the capacitance value of the capacitor is adjustable, the delay generated when the square wave signal flips can also be adjusted.

[0064] Based on the above principle, in this circuit, the first switch 40 controls when the adjustable capacitor 30 is connected to the output terminal of the square-wave signal. Specifically, the square-wave signal has two states, high level and low level, within one period. If the first switch 40 is closed only at one level state and turned off at the other level state, the following two situations will occur:

[0065] 1. The first switch 40 is closed during the high-level stage and turned off during the low-level stage;

[0066] In this case, the first switch 40 is closed during the high-level stage (i.e., logic "1") in each period of the square-wave signal. That is, at this time, the adjustable capacitor 30 is connected to the output terminal of the square-wave signal, and a delay will occur due to the connection of the adjustable capacitor 30 when the square-wave signal flips next time. In one period of the square-wave signal, the moment when the square-wave signal flips from the high-level state to the low-level state is delayed (i.e., the end moment of the high-level stage is delayed). And the first switch 40 is turned off during the low-level stage (i.e., logic "0") in each period of the square-wave signal. That is, at this time, the adjustable capacitor 30 is not connected to the output terminal of the square-wave signal, and no delay will be generated when the square-wave signal flips from the low level to the high level next time, and the moment when the square-wave signal flips from the low-level state to the high-level state in one period is not delayed (i.e., the start moment of the high-level stage remains unchanged). By controlling the flipping moments of the two level states in one period of the square-wave signal as described above, the duration of the high-level stage of the square-wave signal in one period can be freely extended.

[0067] Based on the definition of the duty cycle, freely extending the duration of the high-level stage of the square-wave signal in one period is also to achieve free adjustment of increasing the duty cycle of the square-wave signal. When the initial duty cycle of the square-wave signal is set to a small value, the free adjustment of the duty cycle of the square-wave signal can also be achieved only through this one-way adjustment scheme of freely increasing the duty cycle.

[0068] 2. The first switch 40 is closed during the low-level stage and turned off during the high-level stage;

[0069] Similarly to the above Case 1, the first switch 40 is closed when it is at the low level stage (i.e., logic "0") in each cycle of the square wave signal. That is, at this time, the adjustable capacitor 30 is connected to the output end of the square wave signal, and a delay will occur due to the connection of the adjustable capacitor 30 when the square wave signal flips next time. In one cycle of the square wave signal, the moment when the square wave signal flips from the low level state to the high level state is delayed (i.e., the start moment of the high level stage is delayed). And the first switch 40 is open when it is at the high level stage (i.e., logic "1") in each cycle of the square wave signal. That is, at this time, the adjustable capacitor 30 is not connected to the output end of the square wave signal, and no delay will be generated when the square wave signal flips from the high level to the low level next time, and the moment when the square wave signal flips from the high level state to the low level state in one cycle will not be delayed (i.e., the end moment of the high level stage remains unchanged). By controlling the flip moments of the two level states in one cycle of the square wave signal as described above, it is possible to freely shorten the duration of the square wave signal at the high level stage in one cycle.

[0070] Also, based on the definition of the duty cycle, freely shortening the duration of the square wave signal at the high level stage in one cycle is also to achieve free adjustment of reducing the duty cycle of the square wave signal. And when the initial duty cycle of the square wave signal is set to a relatively large value, only through this one-way adjustment scheme of freely reducing the duty cycle, it is also possible to achieve free adjustment of the duty cycle of the square wave signal.

[0071] As can be seen from the above, no matter which of the above two cases the first switch 40 works in, free adjustment of the duty cycle of the square wave signal can be achieved. And in an optional implementation scheme, if the first switch 40 can freely switch between the above two cases, bidirectional free adjustment of increasing and decreasing the duty cycle of the square wave signal can also be achieved. However, this implementation scheme has higher control requirements for the first switch 40, and generally, free adjustment of the duty cycle is still achieved through the one-way adjustment method.

[0072] In summary, based on the fact that in a certain level state stage in one cycle of the square wave signal, the adjustable capacitor 30 is connected to the output end of the square wave signal, so as to delay the moment when the square wave signal flips to the next level state. At the same time, since the delay duration is related to the capacitance value of the capacitor connected to the output end of the square wave signal, and the adjustable capacitor 30 with adjustable capacitance value is connected in this circuit. Therefore, free adjustment of the duty cycle of the square wave signal can be achieved, enabling the RC oscillator circuit to be applied in a wider range of application scenarios and further improving the competitiveness.

[0073] Further, as described above, the duty cycle of this circuit is adjusted by adjusting the capacitance value of the adjustable capacitor 30 connected to the square-wave signal output terminal. There is no limitation on the specific implementation of the adjustable capacitor 30 in this embodiment. It can be implemented by using currently mature adjustable capacitor 30 products, or by using a circuit structure of an adjustable capacitor 30 provided in this embodiment. As Figure 3 shown, this embodiment provides an implementation scheme of the adjustable capacitor 30:

[0074] The adjustable capacitor 30 includes a plurality of capacitors connected in parallel, and a second switch is connected in series on each parallel branch where the capacitor is located.

[0075] Further, this embodiment also provides a corresponding implementation scheme for how to adjust the capacitance value of the adjustable capacitor 30. As Figure 4 shown, this circuit further includes: a capacitance trimming module 52, and the controlled terminals of each second switch are respectively connected to the output terminal of the capacitance trimming module 52.

[0076] Combined with Figure 3 and Figure 4 it can be known that the signal T_C1 output by the capacitance trimming module 52 is a set of signals, and the number of signals it contains is the same as the number of second switches (or parallel capacitors) C11~C1N included in the adjustable capacitor 30 module. Assuming that the adjustable capacitor 30 includes N second switches, then the signal T_C1 includes a total of N signals T_C11~T_C1N, which are respectively output to the controlled terminals of the corresponding second switches to control their switching states.

[0077] Further, according to the parallel principle of capacitors, the more capacitors connected in parallel in the adjustable capacitor 30, the larger the total capacitance value of the adjustable capacitor 30. Therefore, the adjustment of the capacitance value of the adjustable capacitor 30 can be achieved by changing the number of capacitors connected in parallel to the circuit, that is, by changing the number of second switches in the adjustable capacitor 30 that are in the closed state.

[0078] The circuit structure provided in this embodiment is simple and reliable, and the requirement for control is also very low. It can effectively realize the free adjustment of the capacitance value of the adjustable capacitor 30 and is very easy to implement.

[0079] On the other hand, as can be seen from the above embodiments, the circuit part in this circuit that can adjust the duty cycle of the square-wave signal is mainly the adjustable capacitor 30 and the first switch 40. The rest of the circuit part is for realizing the basic functions of the RC oscillator circuit. Therefore, the rest of the RC oscillator circuit is not limited in the above embodiments and can be implemented by any existing scheme. However, in the currently common ones, including Figure 1In the shown RC oscillator circuit, there is also a problem of insufficient noise immunity. The current RC oscillator circuit cannot eliminate the influence of the operational amplifier offset on the square wave signal, resulting in insufficient accuracy of the generated square wave signal.

[0080] Based on this, this embodiment provides an alternative embodiment for the above-mentioned OSC reference generation module 10. As Figure 5 shown, the OSC reference generation module 10 includes: a first operational amplifier AMP1, a second operational amplifier AMP2, a chopper circuit (MP1~MP4), a first resistor R1, a second resistor R2, a third resistor R3, a first P-type field effect transistor (PMOS transistor) MP5, and an N-type field effect transistor (NMOS transistor) MN1.

[0081] Among them, the non-inverting terminal of the first operational amplifier AMP1 is used to access the initial reference voltage VREF; the inverting terminal of the first operational amplifier AMP1 is connected to the source of the NMOS transistor MN1 and grounded through the first resistor R1, and the voltage at the inverting terminal of the first operational amplifier AMP1 is used as the first reference voltage VREF1.

[0082] The first end of the second resistor R2 is connected to the power supply voltage VDD, and the second end of the second resistor R2 is connected to the first input terminal of the chopper circuit. The voltage at the second end of the second resistor R2 is used as the second reference voltage VREF2.

[0083] The output terminal of the first operational amplifier AMP1 is connected to the gate of the NMOS transistor MN1; the drain of the NMOS transistor MN1 is connected to the second input terminal of the chopper circuit and connected to the power supply voltage VDD through the third resistor R3 to provide the third reference voltage VREF3.

[0084] The two output terminals of the chopper circuit are respectively connected to the non-inverting terminal and the inverting terminal of the second operational amplifier AMP2; the two sets of controlled terminals of the chopper circuit are respectively connected to two complementary chopper clock signals CLK3 and CLK4.

[0085] The second end of the second resistor R2 is also connected to the source of the first PMOS transistor MP5. The gate of the first PMOS transistor MP5 is connected to the output terminal of the second operational amplifier AMP2; the drain of the first PMOS transistor MP5 is connected to the square wave signal generation module 20 to provide the reference current I2.

[0086] It should be noted that in the OSC reference generation module 10 provided in this embodiment, the first operational amplifier and the second operational amplifier form a negative feedback structure. Therefore, at this time, the operational amplifier is in the "virtual short" state, and the voltages at the two input terminals are kept the same, constituting a voltage follower design. Specifically, in combination with the above-mentioned connection relationship and Figure 5As shown, the voltages at the non-inverting terminal and the inverting terminal of the first operational amplifier are kept the same. Therefore, the first reference voltage VREF1 at the inverting terminal of the first operational amplifier is the same as the reference voltage VREF connected to its non-inverting terminal. Thus, the following relationship can be obtained:

[0087] I1 = VREF / R1;

[0088] where I1 is the current value of the current flowing through the first resistor; R1 is the resistance value of the first resistor.

[0089] Similarly, the voltages at the non-inverting terminal and the inverting terminal of the second operational amplifier are also kept the same, that is:

[0090] VREF2 = VREF3;

[0091] And from the above connection relationship and Figure 5 the third reference voltage VREF3 can be obtained as shown in the following formula:

[0092] VREF3 = VDD - I1 × R3;

[0093] where VDD is the power supply voltage value; R3 is the resistance value of the third resistor.

[0094] Furthermore, the reference current generated by the OSC reference generation module 10 is also the current I2 flowing through the second resistor, and the expression of the current I2 is as shown below:

[0095] I2 = (VDD - VREF2) / R2;

[0096] Therefore, substituting the relationship of the above second reference voltage VREF2 into the above formula, the expression of the reference current I2 can be obtained as follows:

[0097] I2 = VREF × R3 / (R1 × R2);

[0098] It should be noted that in this embodiment, a chopping structure is adopted at the input terminal of the second operational amplifier, combined with the method of periodically switching the input signal, to reduce the influence of the operational amplifier offset. That is, the OSC reference generation module 10 provided in this embodiment eliminates the offset voltage of the operational amplifier through the chopping modulation technology, reduces the influence of low-frequency noise on the square wave signal, and improves the noise immunity of the RC oscillator circuit.

[0099] Furthermore, this embodiment also provides a further implementation based on the OSC reference generation module 10 provided in the above embodiment: the first resistor and the second resistor are adjustable resistors.

[0100] And as Figure 4 shown, this circuit further includes: a resistor trimming module 51.

[0101] As Figure 6 and Figure 7 shown, both the first resistor and the second resistor include: a plurality of resistors connected in series (R11~R1N, and R21~R2N), and a third switch (TR11~TR1N, and TR21~TR2N) is connected in parallel across each resistor; the controlled terminals of the respective third switches are respectively connected to the output terminal of the resistor trimming module 51. Among them, Figure 6 is the structure of the first resistor, Figure 7 is the structure of the second resistor.

[0102] That is to say, in this embodiment, both the first resistor and the second resistor in the above OSC reference generation module 10 are adjustable resistors. From the expression of the reference current I2 in the above embodiment, it can be seen that the resistance values of the first resistor and the second resistor can affect the current value of the reference current I2. And I2 is used as the reference current for generating the square wave signal, and the change of its current value will affect the frequency of the generated square wave signal. That is, in this embodiment, by adjusting the resistance values of the first resistor and the second resistor in the OSC reference generation module 10, the frequency of the square wave signal generated by the RC oscillator circuit can be adjusted, further improving the application range of the RC oscillator circuit.

[0103] In addition, this embodiment also provides a specific implementation scheme for the adjustable resistor. By connecting a corresponding third switch in parallel across a plurality of resistors connected in series, the short-circuit of a specific resistor can be achieved. And the short-circuited circuit is equivalent to not being connected in series in the circuit, and the total resistance value of the adjustable resistor has nothing to do with it. In other words, by controlling the number of resistors connected in series in the adjustable resistor, the resistance value of the adjustable resistor can be adjusted, so as to meet the above requirements for adjusting the frequency of the square wave signal.

[0104] Similar to the control of the above adjustable capacitor 30, the adjustment of the adjustable resistor in this embodiment is also achieved through a group of signals related to the number of switches (third switches). Such as Figure 6 the signal group T_R1 composed of T_R11~TR1N in Figure 7 and the signal group T_R2 composed of T_R21~TR2N in

[0105] Further, in this embodiment, the solution of the adjustable first resistor and second resistor can be implemented together with the specific implementation of the adjustable capacitor 30 provided in the above embodiment. At this time, whether it is the trimming of the adjustable capacitor 30 or the first resistor and the second resistor, the purpose is to trim the parameters of the square wave signal generated by the RC oscillator circuit. Adjusting the capacitance value of the adjustable capacitor 30 can adjust the duty cycle of the square wave signal, and adjusting the resistance values of the first resistor and the second resistor can adjust the frequency of the square wave signal. Therefore, as Figure 2 and Figure 4 shown, the capacitor trimming module 52 and the resistor trimming module 51 in this circuit can be combined into a trimming module 50 for generating control signals T_R1, T_R2, and T_C1 for adjusting the capacitance value of the adjustable capacitor 30 and the resistance values of the first resistor and the second resistor.

[0106] On the other hand, this embodiment also provides an optional implementation for the specific implementation of the above square wave signal generation module. As Figure 5 shown, the square wave signal generation module includes: a comparator 21 and a time-varying voltage generation circuit 22.

[0107] Among them, the time-varying voltage generation circuit 22 is used to generate a time-varying voltage VC, including: two sets of transmission gates (MP7 and MN2, and MP8 and MN4 two sets of transmission gates), a fourth switch (MN3, MN5), and charge and discharge capacitors (C2, C3);

[0108] The first ends of each transmission gate are connected together and connected to a reference current I2, and the common end of each transmission gate is used as the output end of the time-varying voltage generation circuit 22;

[0109] The second ends of each transmission gate are respectively connected to the first ends of the corresponding charge and discharge capacitors, the second ends of each charge and discharge capacitor are grounded, and corresponding fourth switches are connected in parallel at both ends of each charge and discharge capacitor;

[0110] The two controlled ends of the first set of transmission gates are respectively connected to the first clock signal CLK1 and the inverted signal CLK1N of the first clock signal; the two controlled ends of the second set of transmission gates are respectively connected to the second clock signal CLK2 and the inverted signal CLK2N of the second clock signal; and the first clock signal CLK1 and the second clock signal CLK2 are out of phase with each other;

[0111] The controlled ends of the fourth switches corresponding to the first set of transmission gates are connected to the inverted signal CLK1N of the first clock signal; the controlled ends of the fourth switches corresponding to the second set of transmission gates are connected to the inverted signal CLK2N of the second clock signal;

[0112] The inverting input terminal of the comparator 21 is connected to the time-varying voltage VC, the non-inverting input terminal of the comparator 21 is connected to the first reference voltage VREF1, and the output terminal of the comparator 21 is used as the output terminal of the square wave signal generation circuit for outputting a square wave signal.

[0113] In this embodiment, the comparator 21 generates a square wave signal based on the first reference voltage VREF1 output by the OSC reference generation circuit and the time-varying voltage VC output by the time-varying voltage generation circuit 22. The time-varying voltage VC generated by the time-varying voltage generation circuit 22 in this embodiment is a signal whose voltage value changes with time. It can be a triangular wave. The voltage value is greater than the first reference voltage VREF1 during a specific period within the cycle, and less than the first reference voltage VREF1 during the remaining period within the cycle. Thus, whenever the magnitude relationship between the time-varying voltage VC and the first reference voltage VREF1 changes, the signal output by the comparator 21 will flip, thereby generating a square wave signal.

[0114] Moreover, the reference current output by the OSC reference generation circuit is used to charge the charge and discharge capacitors C2 and C3 in the time-varying voltage generation circuit 22. The first clock signal CLK1 and its inverted signal CLK1N are used to control the transmission gate and the fourth switch corresponding to the capacitor C2, and the second clock signal CLK2 and its inverted signal CLK2N are used to control the transmission gate and the fourth switch corresponding to the capacitor C3. CLK1 and CLK2 are also two opposite signals, thereby ensuring that only one of the capacitors C2 and C3 is in the charging state and the other is in the discharging state at the same time, and C2 and C3 alternate in charging and discharging. Thus, a voltage waveform that rises and falls at a specific slope in a cycle is generated at the VC point, that is, the time-varying voltage VC is obtained.

[0115] In addition, the structure given for the square wave signal generation module in this embodiment is only a basic solution. In actual applications, other devices or structures can be added to the above square wave signal generation module according to needs. For example Figure 5 the set-reset (SR) latch and the PMOS transistor MP6 in are unnecessary for implementing the square wave signal generation module. And to ensure that the reference current I2 can charge the charge and discharge capacitors C2 and C3, the voltage VS at the set terminal (S terminal) of the SR latch needs to be 0V so that its output voltage is always 0V, thereby controlling MP6 to be always in the conducting state.

[0116] Based on this, this embodiment further provides a further implementation solution on the basis of the square wave signal generation module provided in the above embodiment, as Figure 5 shown, the square wave signal generation module further includes: an even number of inverters and buffers.

[0117] An even number of inverters are connected in series at the output terminal of the comparator 21, and the buffer is connected in series at the output terminal of the comparator 21.

[0118] And the adjustable capacitor 30 is connected to the output terminal of the square wave signal generation module 20 through the first switch 40, including:

[0119] The first end of the adjustable capacitor 30 is connected to the output end of the comparator 21 through the first switch 40, and the second end of the adjustable capacitor 30 is connected to the output end of the i-th inverter in series; where i is an even number less than the total number of inverters.

[0120] It is not difficult to understand that both the inverter and the buffer play a shaping role in this embodiment. Among them, the reason why the number of inverters is an even number is to ensure that the square wave signal output after shaping is not inverted. However, if the RC oscillator circuit considers that the output of the comparator 21 is opposite to the square wave signal of the final output at the beginning of the design, then the shaping and inversion can also be performed by an odd number of inverters, and this embodiment does not limit this. In addition, for the selection of the buffer, in an alternative embodiment, it can be implemented by a Schmitt trigger.

[0121] It should also be noted that, as can be seen from the above embodiments, the control of whether the adjustable capacitor 30 is connected to the output end of the square wave signal generation module needs to be determined based on the current state of the square wave signal. That is, the control signal for controlling the on-off state of the first switch 40 is related to the square wave signal. And for the capacitor, an alternative implementation of the first switch 40 for controlling its on-off is a transmission gate, which requires two opposite signals for control, that is Figure 3 VA and VB in

[0122] Based on this, in addition to shaping the square wave signal, the added inverter in this embodiment also has an additional function, that is, to generate two opposite signals VA and VB for controlling the on-off state of the first switch 40.

[0123] In an alternative embodiment, the first switch 40 is a transmission gate, and the first switch 40 is closed during the high-level stage and turned off during the low-level stage in each cycle of the square wave signal.

[0124] Then as Figure 5 shown, the two controlled ends of the first switch 40 are respectively connected to the first gate control signal VA and the second gate control signal VB with opposite phases; the first gate control signal VA is generated by the first inverter connected in series at the output end of the comparator 21, and the second gate control signal VB is generated by the second inverter connected in series at the output end of the comparator 21.

[0125] It is not difficult to see that when the square wave signal VOUT output by the square wave signal generation module is at a high level, VA is at a low level and VB is at a high level. At this time, the first switch 40 is closed, and the adjustable capacitor 30 is connected to the output end of the comparator 21, thereby delaying the next flip of the output of the comparator 21. Similarly, when the output of the comparator 21 flips, that is, when VOUT flips to a low level, VA is at a high level and VB is at a low level. At this time, the first switch 40 is disconnected, and the adjustable capacitor 30 is not connected to the output end of the comparator 21, and will not affect the next flip of the output of the comparator 21, thus meeting the above control requirements.

[0126] It can be seen from this that the solution provided in this embodiment does not require an additional controller or signal source to generate a signal for controlling the conduction state of the first switch 40, and can be obtained by multiplexing the original inverter for square wave signal shaping. Moreover, it can ensure that the control of the conduction state of the first switch 40 is strongly correlated with the current level state of the square wave signal, ensuring the accuracy of the duty cycle adjustment of the square wave signal.

[0127] In addition, based on the setting of the inverter in the above embodiment, both ends of the adjustable capacitor 30 can be directly connected in parallel to both ends of an even number of series-connected inverters. At this time, the first switch 40 only needs to be set at one end of the adjustable capacitor 30 to realize the control of whether the adjustable capacitor 30 is connected to the output of the comparator 21, reducing the number of first switches 40 that need to be set. However, when the first switch 40 is turned off, one end of the adjustable capacitor 30 will be floating, which will bring some negative effects, which generally need to be avoided in actual circuit design. For this reason, this embodiment also provides a corresponding implementation scheme, such as Figure 5 As shown, this circuit further includes: a second PMOS transistor MP9.

[0128] The source of the second PMOS transistor MP9 is connected to the power supply voltage VDD, the drain of the second PMOS transistor MP9 is connected to the first end of the adjustable capacitor 30, and the gate of the second PMOS transistor MP9 is connected to the first gate control signal VA.

[0129] Based on the generation method of the first gate control signal VA in the above embodiment, when VOUT is at a high level, VA is at a high level; at this time, the first switch 40 is turned on, the adjustable capacitor 30 is connected to the output end of the comparator 21, and MP9 is turned off, which will not affect the adjustment of the duty cycle of the square wave signal by the adjustable capacitor 30. When VOUT is at a low level, VA is at a low level; at this time, the first switch 40 is turned off, and the first end of the adjustable capacitor 30 is not connected to the output end of the comparator 21; but at this time, MP9 is turned on, connecting the first end of the adjustable capacitor 30 to the power supply VDD to avoid it from floating.

[0130] In this embodiment, a switching transistor controlled by a first gate control signal VA to conduct is used to simply and conveniently connect one end of the adjustable capacitor 30 to the power supply when it is not connected to the output end of the comparator 21, avoiding floating, that is, avoiding the adverse effects brought thereby. The entire circuit structure is simple and the control is convenient, which is extremely easy to implement and can also improve the reliability and safety of the entire RC oscillator circuit.

[0131] Further, in an optional embodiment, in addition to being opposite signals, there is a certain dead time between the first clock signal and the second clock signal. That is, the first clock signal and the second clock signal form a set of complementary signals.

[0132] Based on the setting of the dead time, when C2 and C3 are alternately charging and discharging, the charged capacitor can first discharge and then start the charging process of another capacitor. Thus, it can be avoided that at the same moment, one capacitor is charging and the other is discharging, which may lead to the problem that the voltage at the VC point cannot change as expected.

[0133] Furthermore, in the above embodiment, there is no limitation on how CLK1, CLK1N, CLK2, CLK2N, and the two complementary chopper clock signals CLK3 and CLK4 are generated. They can be obtained through a specific signal generator or can be realized by reusing the devices in the existing RC oscillator circuit. For the latter, this embodiment provides an optional implementation scheme. As Figure 2 and Figure 3 shown, this circuit further includes: a two-phase non-overlapping clock module 60.

[0134] The input end of the two-phase non-overlapping clock module 60 is connected to the output end of the square wave signal generation module 20, and is used to generate the first clock signal CLK1, the inverted signal CLK1N of the first clock signal, the second clock signal CLK2, the inverted signal CLK2N of the second clock, and the two complementary chopper clock signals CLK3 and CLK4 according to the square wave signal.

[0135] The two-phase non-overlapping clock circuit is a circuit that generates two clock signals with complementary phases and non-overlapping, and can be used to generate complementary CLK1 and CLK2, as well as CLK3 and CLK4. In this embodiment, it is also necessary to further generate the inverted signal CLK1N of CLK1 and the inverted signal CLK2N of CLK2, which can be realized by adding inverters.

[0136] Specifically, an optional circuit structure of the above two-phase non-overlapping clock module 60 is as Figure 8As shown, based on the square wave signal VCLK output by the square wave signal generation module, after passing through a divide-by-two circuit composed of D flip-flops, square wave signals VQ and VQN with doubled periods are obtained. Then, after VQ and VQN are delayed by inverters and buffers, square wave signals with a certain dead time can be generated, namely CLK1 to CLK4. And CLK1N and CLK2N can also be obtained through inverters.

[0137] In addition, in an alternative embodiment, the signals CLK1 to CLK4, CLK1N, and CLK2N generated based on the square wave signal VCLK also satisfy that the period is twice that of the VCLK period, so that a time-varying voltage with a period consistent with the expectation of VCLK is generated based on the time-varying voltage generation circuit 22 provided in the above embodiment.

[0138] Exemplarily, assuming that the initial state is that CLK1 is at a high level and CLK2 is at a low level, then at this time CLK2N is at a high level, and the voltage of the upper plate of the C2 capacitor is 0V; while CLK1N is at a low level, and at this time the circuit charges the capacitor C3 until the VC voltage exceeds VREF1, and the output result of the comparator 21 circuit flips. At this time, the signals output by the two-phase non-overlapping clock circuit all change, CLK1 becomes low level, and CLK2 becomes high level. And because there is a dead time between CLK1 and CLK2, the CLK1N signal will change before the CLK2N signal, so CLK1N first becomes high level and quickly discharges the charge on the C3 capacitor, and the VC voltage decreases. Then CLK2N becomes low level, and at the same time the C2 capacitor channel is opened and the charging channel of the C3 capacitor is closed. Then the circuit charges the C2 capacitor and the VC voltage rises until the voltage exceeds VREF1, and then the foregoing actions are performed, thereby forming a square wave signal VCLK at the output end.

[0139] It can be seen that the two-phase non-overlapping clock module 60 provided in this embodiment can generate the above various complementary and opposite signals by means of the existing square wave signal CLK, and can complete the switching control of each device in the above RC oscillator circuit without introducing an additional signal source, ensuring that the square wave signal is generated as expected.

[0140] On the other hand, in addition to the above-mentioned disadvantage of difficult duty cycle adjustment, the currently common RC oscillator circuit also has the problem of insufficient accuracy, and the square wave signal generated by it is easily affected by power supply and temperature changes. To solve this problem, the present application also provides a corresponding solution, such as Figure 2 As shown, this circuit further includes: a bandgap reference module 70.

[0141] The bandgap reference module 70 is connected to the non-inverting input terminal of the first operational amplifier and is used to provide an initial reference voltage VREF.

[0142] As can be seen from the embodiments of the OSC reference generation module 10 described above, the OSC reference generation module 10 requires an initial reference signal to generate the reference current I2 and the first reference voltage VREF1. And in the above embodiments, this initial reference signal is connected to the non-inverting terminal of the first operational amplifier. Therefore, the initial reference signal is a voltage signal, that is, the initial reference voltage VREF. In this embodiment, the initial reference voltage VREF is generated by the bandgap reference module 70. The initial reference voltage VREF generated by the bandgap reference module 70 is insensitive to temperature changes, thus solving the problem that the current RC oscillator circuit is easily affected by temperature changes and resulting in low accuracy.

[0143] Similarly, for the problem that the current RC oscillator circuit is also easily affected by power supply voltage fluctuations and results in low accuracy, this embodiment also provides a corresponding solution, such as Figure 2 shown, this circuit further includes: a low dropout regulator (LDO) module 80.

[0144] The output voltage of the LDO module 80 serves as the power supply voltage of the RC oscillator circuit.

[0145] In this embodiment, by using the output voltage of the LDO module 80 as the power supply voltage VDD of the entire RC oscillator circuit, the influence of power supply voltage fluctuations on the output square wave signal of the RC oscillator circuit can be reduced, thereby further improving the accuracy of the RC oscillator circuit.

[0146] The above has introduced the RC oscillator circuit provided by the present invention in detail. The various embodiments in the specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

[0147] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

Claims

1. An RC oscillator circuit, characterized in that, Comprising: an OSC reference generation module, a square wave signal generation module, a tunable capacitor, and a first switch; wherein, the OSC reference generation module is connected to the square wave signal generation module for generating a reference current and a first reference voltage; the square wave signal generation module is configured to generate a square wave signal based on the reference current and the first reference voltage; the tunable capacitor is connected to the output end of the square wave signal generation module through the first switch, and the first switch is closed at a certain level stage in each cycle of the square wave signal and turned off at another level stage.

2. The RC oscillator circuit according to claim 1, characterized in that, The OSC reference generation module includes: a first operational amplifier, a second operational amplifier, a chopper circuit, a first resistor, a second resistor, a third resistor, a first PMOS transistor, and an NMOS transistor; wherein, the non-inverting input terminal of the first operational amplifier is used for accessing an initial reference voltage; the inverting input terminal of the first operational amplifier is connected to the source electrode of the NMOS transistor and grounded through the first resistor, and the voltage at the inverting input terminal of the first operational amplifier serves as the first reference voltage; the first end of the second resistor is connected to a power supply voltage, and the second end of the second resistor is connected to the first input terminal of the chopper circuit, and the voltage at the second end of the second resistor serves as a second reference voltage; the output terminal of the first operational amplifier is connected to the gate electrode of the NMOS transistor; the drain electrode of the NMOS transistor is connected to the second input terminal of the chopper circuit and connected to the power supply voltage through the third resistor for providing a third reference voltage; the two output terminals of the chopper circuit are respectively connected to the non-inverting input terminal and the inverting input terminal of the second operational amplifier; the two control terminals of the chopper circuit are respectively connected to two complementary chopper clock signals; the second end of the second resistor is further connected to the source electrode of the first PMOS transistor, and the gate electrode of the first PMOS transistor is connected to the output terminal of the second operational amplifier; the drain electrode of the first PMOS transistor is connected to the square wave signal generation module for providing the reference current.

3. The RC oscillator circuit according to claim 2, wherein, The first resistor and the second resistor are adjustable resistors; This circuit further includes: a resistor trimming module; The first resistor and the second resistor include: a plurality of resistors connected in series, and a third switch is connected in parallel across each resistor; the control terminals of each of the third switches are respectively connected to the output terminal of the resistor trimming module.

4. The RC oscillator circuit according to claim 1, wherein, Further comprising: a capacitor trimming module; The tunable capacitor includes a plurality of capacitors connected in parallel, and a second switch is connected in series in each parallel branch where a capacitor is located; the control terminals of each of the second switches are respectively connected to the output terminal of the capacitor trimming module.

5. The RC oscillator circuit according to claim 2, characterized in that, The square wave signal generation module includes: a comparator and a time-varying voltage generation circuit; wherein, the time-varying voltage generation circuit is configured to generate a time-varying voltage and includes: two transmission gates, a fourth switch, and a charge-discharge capacitor; the first ends of each of the transmission gates are commonly connected and connected to the reference current, and the common terminal of each of the transmission gates serves as the output terminal of the time-varying voltage generation circuit; The second ends of the respective transmission gates are respectively connected to the first ends of the corresponding charge-discharge capacitors, the second ends of the respective charge-discharge capacitors are grounded, and the two ends of the respective charge-discharge capacitors are respectively shunted with the corresponding fourth switches; The two controlled ends of the first group of the transmission gates are respectively connected to the first clock signal and the inverted signal of the first clock signal; the two controlled ends of the second group of the transmission gates are respectively connected to the second clock signal and the inverted signal of the second clock signal; and the first clock signal and the second clock signal are out of phase with each other; The controlled ends of the fourth switches corresponding to the first group of the transmission gates are connected to the inverted signal of the first clock signal; the controlled ends of the fourth switches corresponding to the second group of the transmission gates are connected to the inverted signal of the second clock signal; The inverting input end of the comparator is connected to the time-varying voltage, the non-inverting input end of the comparator is connected to the first reference voltage, and the output end of the comparator serves as the output end of the square-wave signal generating circuit for outputting a square-wave signal.

6. The RC oscillator circuit according to claim 5, characterized in that The first clock signal and the second clock signal are a set of complementary signals with a dead time between them.

7. The RC oscillator circuit according to claim 6, characterized in that, It further includes: A two-phase non-overlapping clock module; The input end of the two-phase non-overlapping clock module is connected to the output end of the square-wave signal generating module for generating a first clock signal, the inverted signal of the first clock signal, a second clock signal, the inverted signal of the second clock, and two complementary chopping clock signals according to the square-wave signal.

8. The RC oscillator circuit according to claim 5, characterized in that, The square-wave signal generating module further includes: an even number of inverters and buffers; The even number of inverters are connected in series at the output end of the comparator, and the buffer is connected in series at the output end of the comparator; And the adjustable capacitor is connected to the output end of the square-wave signal generating module through the first switch, which includes: The first end of the adjustable capacitor is connected to the output end of the comparator through the first switch, and the second end of the adjustable capacitor is connected to the output end of the i-th inverter in series; where i is an even number less than the total number of the inverters.

9. The RC oscillator circuit according to claim 8, characterized in that, The first switch is a transmission gate, and the first switch is closed when in the high-level stage and turned off when in the low-level stage in each cycle of the square-wave signal; The two controlled ends of the first switch are respectively connected to a first gate control signal and a second gate control signal with opposite phases; the first gate control signal is generated by the first inverter connected in series at the output end of the comparator, and the second gate control signal is generated by the second inverter connected in series at the output end of the comparator.

10. The RC oscillator circuit according to claim 9, characterized in that, It further includes: A second PMOS transistor; The source of the second PMOS transistor is connected to the power supply voltage, the drain of the second PMOS transistor is connected to the first end of the adjustable capacitor, and the gate of the second PMOS transistor is connected to the first gate control signal.

11. The RC oscillator circuit according to claim 2, characterized in that, It further includes: A bandgap reference module; The bandgap reference module is connected to the non-inverting input end of the first operational amplifier for providing the initial reference voltage.

12. The RC oscillator circuit according to any one of claims 1 to 11, characterized in that, It further includes: An LDO module; The output voltage of the LDO module serves as the power supply voltage of the RC oscillator circuit.

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