A semiconductor device and a method of fabricating the same

Abstract

The application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, a semiconductor body located on one side of the substrate, wherein the semiconductor body comprises a drift region, a body region and a first region, and a first groove is arranged in the middle region of the semiconductor body; along a first direction, the body region and the first region are located on both sides of the first groove; the first direction is parallel to the substrate; a shielding gate and a control gate are located in the first groove and are spaced apart in a direction perpendicular to the substrate; a source, a drain and a gate are located on the side of the semiconductor body away from the substrate; and a diode structure is located on both sides of the control gate along a second direction; the gate is connected with the positive electrode of the diode structure, and the shielding gate is connected with the negative electrode of the diode structure; the second direction is parallel to the substrate, and the first direction is perpendicular to the second direction. The application can reduce the on-resistance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] As an advanced power semiconductor device, the shielded gate metal-oxide-semiconductor transistor (MOSFET) has achieved a significant performance breakthrough through core structural innovation, while inheriting the advantages of traditional power MOSFETs such as fast switching speed and simple driving.

[0003] The shielding gate is connected to the source. For N-channel shielded gate MOSFETs, the shielding gate potential is always fixed at a low potential, while for P-channel shielded gate MOSFETs, the shielding gate potential is always fixed at a high potential. This results in the shielding gate sidewalls not being able to form a carrier accumulation layer when the device is turned on, increasing the on-resistance of the device. Summary of the Invention

[0004] This invention provides a semiconductor device and its fabrication method to solve the problem of high on-resistance in current shielded gate power MOSFET devices.

[0005] In a first aspect, the present invention provides a semiconductor device, the semiconductor device comprising: The substrate is configured with the first conductivity type; A semiconductor body is located on one side of a substrate. The semiconductor body includes a drift region, a body region, and a first region. The drift region is configured with a first conductivity type and is located on the side of the semiconductor body closer to the substrate. The body region is configured with a second conductivity type and is located on the side of the drift region farther from the substrate. The first region is configured with a first conductivity type and is located on the side of the body region farther from the substrate. The first conductivity type is different from the second conductivity type. A first trench is also provided in the middle region of the semiconductor body. The first trench penetrates the first region and the body region and extends to the drift region. Along a first direction, the body region and the first region are located on both sides of the first trench. The first direction is parallel to the substrate. The shielding gate and the control gate are located in a direction perpendicular to the substrate, with the shielding gate and the control gate spaced apart within the first trench; the shielding gate is located between the substrate and the control gate. The semiconductor body has a source, a drain, and a gate. The source and gate are spaced apart on the side of the semiconductor body away from the substrate, and the gate surrounds the source. The drain is located on the side of the substrate away from the semiconductor body. The source is connected to the first region, and the gate is connected to the control gate. The diode structure, along the second direction, is located on both sides of the control gate, and at least a portion of the diode structure is located within the first trench; the gate is connected to the positive terminal of the diode structure, and the shielding gate is connected to the negative terminal of the diode structure; the second direction is parallel to the substrate, and the first direction is perpendicular to the second direction.

[0006] Optionally, the shielding grid includes an N-type shielding grid; The diode structure includes a first N-type semiconductor layer and a first P-type semiconductor layer; the first N-type semiconductor layer and the first P-type semiconductor layer are stacked and disposed between a shielding gate and a gate along a direction perpendicular to the substrate; the shielding gate is connected to the first N-type semiconductor layer, and the gate is connected to the first P-type semiconductor layer; Alternatively, the diode structure includes a second N-type semiconductor layer and a Schottky metal layer; the second N-type semiconductor layer and the Schottky metal layer are stacked and disposed between the shielding gate and the gate along a direction perpendicular to the substrate; the shielding gate is connected to the second N-type semiconductor layer, and the gate is connected to the Schottky metal layer.

[0007] Optionally, the doping concentration of the first N-type semiconductor layer is lower than the doping concentration of the shielding gate, and the doping concentration of the second N-type semiconductor layer is lower than the doping concentration of the shielding gate.

[0008] Optionally, the semiconductor device further includes: a second region; The second region is configured with a second conductivity type. The second region is located on the side of the body region away from the substrate, and the second region is located on the side of the first region away from the first trench. The source electrode is in contact with the second region.

[0009] Optionally, the semiconductor device further includes: a shielding gate insulating layer, an isolation insulating layer, and a control gate insulating layer; The shielding gate insulating layer is located at the bottom of the first trench and at least a portion of the sidewalls near the substrate, with the shielding gate located on the side of the shielding gate insulating layer away from the substrate; the isolation insulating layer is located on the side of the shielding gate away from the substrate. Along the first direction, the control gate insulating layer is located on the sidewall of the first trench that is not covered by the shielded gate insulating layer and the isolation insulating layer; along the second direction, the control gate insulating layer is also located on the sidewall of the diode structure away from the semiconductor body; the control gate is located on the side of the isolation insulating layer away from the substrate, and on the side of the control gate insulating layer away from the semiconductor body.

[0010] Optionally, along the second direction, the length of the control gate is less than the length of the shielding gate; the diode structures located on both sides of the control gate are located on the side of the control gate insulating layer away from the control gate; Along the second direction, the shielding gate insulating layer is located on the entire sidewall of the first trench, the diode structure is located between the control gate insulating layer and the shielding gate insulating layer, and the vertical projection of the diode structure onto the substrate covers the vertical projection of the shielding gate onto the substrate.

[0011] Optionally, the semiconductor device further includes: a first insulating layer; The first insulating layer is located on the side of the semiconductor body away from the substrate, and both the source and the gate are located on the side of the first insulating layer away from the substrate. Along the first direction, source contact holes are provided on both sides of the first insulating layer, and the vertical projection of the source contact holes onto the substrate covers a portion of the vertical projection of the source onto the substrate; the source extends to the source contact holes and contacts the first region. Along the second direction, first gate contact holes are provided on both sides of the first insulating layer. The vertical projection of the first gate contact holes onto the substrate covers part of the gate and part of the control gate onto the substrate. The gate extends into the first gate contact holes and connects to the control gate. Along the second direction, a second gate contact hole is also provided on the side of the first insulating layer away from the first gate contact hole. The vertical projection of the second gate contact hole onto the substrate covers a portion of the gate and at least a portion of the diode structure onto the substrate. The gate extends to the second gate contact hole and is connected to the first P-type semiconductor layer, which is connected to the first N-type semiconductor layer; or, a Schottky metal is disposed in the second gate contact hole, which is connected to the second N-type semiconductor layer.

[0012] Secondly, the present invention provides a method for fabricating a semiconductor device, the method comprising: A substrate is provided, and the substrate is configured with a first conductivity type; A semiconductor body is formed on one side of a substrate. The semiconductor body includes a drift region, a body region, and a first region. The drift region is configured with a first conductivity type and is located on the side of the semiconductor body closer to the substrate. The body region is configured with a second conductivity type and is located on the side of the drift region farther from the substrate. The first region is configured with a first conductivity type and is located on the side of the body region farther from the substrate. The first conductivity type is different from the second conductivity type. A first trench is also provided in the middle region of the semiconductor body. The first trench penetrates the first region and the body region and extends to the drift region. Along a first direction, the body region and the first region are located on both sides of the first trench. The first direction is parallel to the substrate. A shielding gate and a control gate are formed within a first trench; the shielding gate and the control gate are spaced apart within the first trench along a direction perpendicular to the substrate; the shielding gate is located between the substrate and the control gate; A diode structure is formed on both sides of the control gate along a second direction; and at least a portion of the diode structure is located within a first trench; the second direction is parallel to the substrate, and the first direction is perpendicular to the second direction; A source and a gate are formed on the side of the semiconductor body away from the substrate, with the source and gate spaced apart and the gate surrounding the source; the source is connected to a first region, and the gate is connected to a control gate; the gate is connected to the positive terminal of the diode structure, and the shielding gate is connected to the negative terminal of the diode structure. A drain is formed on the side of the substrate away from the semiconductor body.

[0013] Optionally, the semiconductor device further includes a shielding gate insulating layer, an isolation insulating layer, and a control gate insulating layer; forming a semiconductor body on one side of the substrate, forming a shielding gate and a control gate in a first trench, and forming a diode structure on both sides of the control gate, including: An epitaxial layer of a first conductivity type is formed on one side of the substrate; a first trench is provided in the middle region of the epitaxial layer; A shielding grid insulation layer is formed at the bottom of the first trench and along its entire sidewall; A shielding gate is formed on the side of the shielding gate insulating layer away from the substrate, and within the first trench; A first N-type semiconductor layer is formed on the side of the shielding gate away from the substrate, and a first P-type semiconductor layer is formed on the side of the first N-type semiconductor layer away from the substrate; the side of the first P-type semiconductor layer away from the substrate is on the same horizontal plane as the side of the epitaxial layer away from the substrate; or, a second N-type semiconductor layer is formed on the side of the shielding gate away from the substrate; the side of the second N-type semiconductor layer away from the substrate is on the same horizontal plane as the side of the epitaxial layer away from the substrate. Etch the first N-type semiconductor layer and the first P-type semiconductor layer, retaining the first N-type semiconductor layer and the first P-type semiconductor layer at both sides of the shielding gate along the second direction; or, etch the second N-type semiconductor layer, retaining the second N-type semiconductor layer at both sides of the shielding gate along the second direction. Remove the shielding grid insulation layer from a portion of the sidewall of the first trench along the first direction; An insulating layer is formed on the side of the shielding gate away from the substrate; Along a first direction, a control gate insulating layer is formed on a portion of the sidewall of the first trench, and along a second direction, a control gate insulating layer is formed on the sidewall of the diode structure away from the epitaxial layer. A control gate is formed on the side of the isolation insulating layer away from the substrate and on the side of the control gate insulating layer away from the epitaxial layer; Along the first direction, a body region and a first region are formed on both sides of the first trench using a doping process; the undoped epitaxial layer serves as a drift region.

[0014] Optionally, before forming the source and gate on the side of the semiconductor body away from the substrate, the method further includes: A first insulating layer is formed on the side of the semiconductor body away from the substrate; along a first direction, source contact holes are provided on both sides of the first insulating layer, and the vertical projection of the source contact holes onto the substrate covers a portion of the vertical projection of the source onto the substrate; along a second direction, first gate contact holes are provided on both sides of the first insulating layer, and the vertical projection of the first gate contact holes onto the substrate covers a portion of the gate and a portion of the vertical projection of the control gate onto the substrate; along the second direction, a second gate contact hole is also provided on the side of the first insulating layer away from the first gate contact hole, and the vertical projection of the second gate contact hole onto the substrate covers a portion of the gate and at least a portion of the vertical projection of the diode structure onto the substrate. A source electrode is formed on the side of the semiconductor body away from the substrate, including: A source electrode is formed in a portion of the first insulating layer on the side away from the substrate, and within the source contact hole; the source electrode extends to the source contact hole and contacts the first region; The diode structure includes a first N-type semiconductor layer and a first P-type semiconductor layer, with a gate formed on the side of the semiconductor body away from the substrate, including: A gate is formed in the remaining portion of the first insulating layer on the side away from the substrate, and in the first gate contact hole and the second gate contact hole; the gate extends into the first gate contact hole to connect with the control gate, and the gate extends into the second gate contact hole to connect with the first P-type semiconductor layer; Alternatively, the diode structure includes a second N-type semiconductor layer and a Schottky metal layer, forming a diode structure on both sides of the control gate and a gate on the side of the semiconductor body away from the substrate, including: A Schottky metal layer is formed in the second gate contact hole and is connected to the second N-type semiconductor layer; a gate is formed in the remaining portion of the first insulating layer on the side away from the substrate and in the first gate contact hole; the gate extends into the first gate contact hole and is connected to the control gate, and the gate is connected to the Schottky metal layer.

[0015] In this embodiment of the invention, a diode structure is disposed between the gate and the shielding gate. The gate can be connected to the anode of the diode structure, and the shielding gate can be connected to the cathode of the diode structure. That is, the shielding gate is connected to the gate through the diode structure, and the shielding gate is not connected to the source. When the device is forward-biased, an electron accumulation layer with high carrier concentration is formed on the sidewall of the shielding gate insulating layer of the N-channel shielded gate MOSFET device, and a hole accumulation layer with high carrier concentration is formed on the sidewall of the shielding gate insulating layer of the P-channel shielded gate MOSFET device, thereby effectively reducing the forward conduction resistance of the device.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a top view schematic diagram of a semiconductor device provided in an embodiment of the present invention; Figure 2 This is a schematic cross-sectional view of a cell structure of a semiconductor device provided in an embodiment of the present invention; Figure 3 This is a schematic cross-sectional view of the cell structure of another semiconductor device provided in an embodiment of the present invention; Figure 4 This is a schematic cross-sectional view of the cell structure of another semiconductor device provided in an embodiment of the present invention; Figure 5 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention; Figures 6-9 This is a schematic diagram of some steps in a method for fabricating a semiconductor device provided in an embodiment of the present invention; Figure 10 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention; Figures 11-27 This is a schematic diagram of some steps in another method for fabricating a semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] Figure 1 This is a top view schematic diagram of a semiconductor device provided in an embodiment of the present invention. Figure 2 This is a schematic cross-sectional view of a cell structure of a semiconductor device provided in an embodiment of the present invention. Figure 3This is a schematic cross-sectional view of a cell structure of another semiconductor device provided in an embodiment of the present invention. Figure 4 This is a schematic cross-sectional view of a cell structure of another semiconductor device provided in an embodiment of the present invention. Figure 2 yes Figure 1 The cross-sectional structure obtained by cutting cell 30 along the dashed line AB. Figure 3 yes Figure 1 A cross-sectional structural diagram obtained by cutting cell 30 along the dashed line CD. Figure 4 yes Figure 1 Another cross-sectional structure obtained by cutting cell 30 along the dashed line CD, as shown below. Figures 1-4 As shown, the semiconductor device includes: a substrate 11, configured with a first conductivity type; and a semiconductor body 2, located on one side of the substrate 11. The semiconductor body 2 includes a drift region 21, a body region 22, and a first region 23. The drift region 21 is configured with the first conductivity type and is located on the side of the semiconductor body 2 closest to the substrate 11; the body region 22 is configured with the second conductivity type and is located on the side of the drift region 21 furthest from the substrate 11; the first region 23 is configured with the first conductivity type and is located on the side of the body region 22 furthest from the substrate 11; the first conductivity type and the second conductivity type are different. A first trench 25 is also provided in the middle region of the semiconductor body 2, the first trench 25 penetrating the first region 23 and the body region 22 and extending to the drift region 21. Along a first direction X, the body region 22 and the first region 23 are both located on both sides of the first trench 25; the first direction X is parallel to the substrate 11. A shielding gate 31 and a control gate 32 are located in a first trench 25, spaced apart from each other, along a direction perpendicular to the substrate 11. The shielding gate 31 is situated between the substrate 11 and the control gate 32. A source 41, a drain 42, and a gate 43 are located on the side of the semiconductor body 2 away from the substrate 11, with the source 41 and gate 43 surrounding the source 41. The drain 42 is located on the side of the substrate 11 away from the semiconductor body 2. The source 41 is connected to the first region 23, and the gate 43 is connected to the control gate 32. A diode structure 6 is located along a second direction Y, on both sides of the control gate 32, with at least a portion of the diode structure 6 situated within the first trench 25. The gate 43 is connected to the anode of the diode structure 6, and the shielding gate 31 is connected to the cathode of the diode structure 6. The second direction Y is parallel to the substrate 11, and the first direction X is perpendicular to the second direction Y.

[0022] Specifically, the semiconductor device may include a terminal region 10 and an active region 20. The periphery of the semiconductor device is the terminal region 10, which surrounds the active region 20. The active region 20 may be composed of multiple repeating identical strip cells 30.

[0023] The semiconductor devices provided in this embodiment of the invention may include shielded gate MOSFET devices. It should be noted that the shielded gate MOSFET devices may include N-channel shielded gate MOSFET devices and P-channel shielded gate MOSFET devices. For the N-channel shielded gate MOSFET device, the first conductivity type is N-type, the second conductivity type is P-type, the substrate 11 is an N-type substrate, the drift region 21 is an N-type drift region, the body region 22 is a P-type body region, and the first region 23 is an N++ doped region. For the P-channel shielded gate MOSFET device, the first conductivity type is P-type, the second conductivity type is N-type, the substrate 11 is a P-type substrate, the drift region 21 is a P-type drift region, the body region 22 is an N-type body region, and the first region 23 is a P++ doped region.

[0024] The middle region of the semiconductor body 2 may be provided with a first trench 25, which may penetrate the first region 23 and the body region 22 and extend into the drift region 21.

[0025] Along a direction perpendicular to the substrate 11, a shielding gate 31 and a control gate 32 may be provided at intervals and insulated within the first trench 25. The shielding gate 31 may be located between the control gate 32 and the drain 42. Along the second direction Y, diode structures 6 may be provided on both sides of the control gate 32. The gate 43 may be connected to the positive terminal of the diode structure 6, and the shielding gate 31 may be connected to the negative terminal of the diode structure 6. That is, the shielding gate 31 is connected to the gate 43 through the diode structure 6, and the shielding gate 31 is not connected to the source 41.

[0026] For an N-channel shielded gate MOSFET device, a diode structure 6 is disposed between the gate 43 and the shielding gate 31. When the device is forward-biased, the drain 42 is connected to a high potential, the source 41 is connected to a low potential, and the gate 43 is connected to a high potential. The diode structure 6 can conduct in the forward direction and has a very low forward voltage drop. The potential of the shielding gate 31 is raised to the voltage of the gate 43 minus the forward voltage drop of the diode structure 6. At this time, under the action of the control gate 32, an inversion layer channel is formed in the body region 22 near the sidewall of the control gate 32, enabling the device to conduct in the forward direction. Electrons flow from the source 41 through the conduction channel to the drain 42. Since the potential of the shielding gate 31 is effectively raised, an electron accumulation layer with a high carrier concentration is formed on the sidewall of the shielding gate insulating layer 33, thereby effectively reducing the forward conduction resistance of the device, i.e., effectively reducing the forward conduction voltage drop of the device. When the device is reverse-blocked, drain 42 is connected to a high potential, source 41 is connected to a low potential, and gate 43 is connected to a low potential. Diode structure 6 is reverse-blocked, and the potential of shielding gate 31 drops to a low potential, causing lateral depletion of the drift region 21. Shielding gate 31 couples with the drift region 21, inducing a space charge region in the drift region 21, forming a lateral depletion region extending laterally along the device. This lateral depletion region effectively widens the depletion region width under reverse-blocking conditions, homogenizes the electric field distribution within the drift region 21, eliminates electric field spikes at the edge of control gate 32, thereby significantly improving the device's breakdown voltage and suppressing parasitic leakage current, achieving excellent reverse-blocking characteristics. When the device is reverse-blocked, the breakdown voltage principle of the device is far from the same as that of a conventional shielded gate MOSFET, and the reverse-blocking characteristics of the device provided in this embodiment are unaffected.

[0027] For a P-channel shielded gate MOSFET device, a diode structure 6 is disposed between the gate 43 and the shielded gate 31. When the device is forward-biased, the drain 42 is connected to a low potential, the source 41 is connected to a high potential, and the gate 43 is connected to a low potential. The diode structure 6 is reverse-biased and cut off, at which time the potential of the shielded gate 31 is low. At this time, under the action of the control gate 32, an inversion layer channel is formed in the body region 22 near the sidewall of the control gate 32, enabling the device to conduct forward. Holes flow from the source 41 through the conduction channel to the drain 42. Since the potential of the shielded gate 31 is low, a hole accumulation layer with a high carrier concentration is formed on the sidewall of the shielded gate insulating layer 33, thereby effectively reducing the forward conduction resistance of the device, that is, effectively reducing the forward conduction voltage drop of the device. When the device is reverse-blocked, drain 42 is connected to a low potential, source 41 is connected to a high potential, and gate 43 is connected to a high potential. Diode structure 6 can conduct in the forward direction. Diode structure 6 has a very low forward voltage drop. The potential of shielding gate 31 is raised to the voltage obtained by subtracting the forward conduction voltage drop of diode structure 6 from the voltage of gate 43. Shielding gate 31 induces lateral depletion in drift region 21. Shielding gate 31 couples with drift region 21, inducing a space charge region in drift region 21, forming a lateral depletion region extending laterally along the device. This lateral depletion region effectively widens the depletion region width in the reverse-blocking state, homogenizes the electric field distribution within drift region 21, eliminates electric field spikes at the edge of control gate 32, thereby significantly improving the breakdown voltage of the device and suppressing parasitic leakage current, achieving excellent reverse-blocking characteristics. When the device is reverse-blocked, the breakdown voltage principle of the device is far from the breakdown voltage of a conventional shielded gate MOSFET, and the reverse-blocking characteristics of the device provided in this embodiment are not affected.

[0028] By setting a diode structure 6 between the gate 43 and the shielding gate 31, the gate-drain capacitance of the device is formed by the barrier capacitance of the diode structure 6 and the capacitance of the shielding gate insulating layer 33 between the shielding gate 31 and the drain 42, connected in series. The capacitance of the shielding gate insulating layer 33 between the shielding gate 31 and the drain 42 is relatively large, and its reciprocal is a very small number, so it can be eliminated. Finally, the total capacitance between the gate 43 and the drain 42 is the barrier capacitance of the diode structure 6. The barrier capacitance of the diode structure 6 is low. Therefore, this embodiment of the invention can effectively reduce the on-resistance of the device while also enabling the device to have a low gate-drain capacitance. Furthermore, since the shielding gate 31 is not connected to the source 41, this embodiment of the invention can also effectively reduce the gate-source capacitance, achieving a good trade-off between dynamic and static losses.

[0029] In this embodiment of the invention, a diode structure 6 is disposed between the gate 43 and the shielding gate 31. The gate 43 can be connected to the anode of the diode structure 6, and the shielding gate 31 can be connected to the cathode of the diode structure 6. That is, the shielding gate 31 is connected to the gate 43 through the diode structure 6, and the shielding gate 31 is not connected to the source 41. When the device is forward-biased, an electron accumulation layer with high carrier concentration is formed on the sidewall of the shielding gate insulating layer 33 of the N-channel shielded gate MOSFET device, and a hole accumulation layer with high carrier concentration is formed on the sidewall of the shielding gate insulating layer 33 of the P-channel shielded gate MOSFET device, thereby effectively reducing the forward conduction resistance of the device.

[0030] Optionally, based on the above embodiments, refer to... Figures 1-4 The shielding grid 31 includes an N-type shielding grid. For example... Figure 3 As shown, the diode structure 6 includes a first N-type semiconductor layer 61 and a first P-type semiconductor layer 62. Along a direction perpendicular to the substrate 11, the first N-type semiconductor layer 61 and the first P-type semiconductor layer 62 are stacked between the shielding gate 31 and the gate 43. The shielding gate 31 is connected to the first N-type semiconductor layer 61, and the gate 43 is connected to the first P-type semiconductor layer 62. Alternatively, as... Figure 4 As shown, the diode structure 6 includes a second N-type semiconductor layer 63 and a Schottky metal layer 64. Along a direction perpendicular to the substrate 11, the second N-type semiconductor layer 63 and the Schottky metal layer 64 are stacked between the shielding gate 31 and the gate 43; the shielding gate 31 is connected to the second N-type semiconductor layer 63, and the gate 43 is connected to the Schottky metal layer 64.

[0031] Specifically, such as Figure 3 As shown, the diode structure 6 may include a first N-type semiconductor layer 61 and a first P-type semiconductor layer 62. For example, the first N-type semiconductor layer 61 may include a first N-type polysilicon layer, and the first P-type semiconductor layer 62 may include a first P-type polysilicon layer. The first N-type semiconductor layer 61 and the first P-type semiconductor layer 62 may be disposed between the shielding gate 31 and the gate 43, and the first N-type semiconductor layer 61 and the first P-type semiconductor layer 62 may be located within the first trench 25. The first N-type semiconductor layer 61 may be located on the side of the first P-type semiconductor layer 62 closest to the shielding gate 31, and the first N-type semiconductor layer 61 may be connected to the shielding gate 31, thereby connecting the shielding gate 31 to the negative electrode of the diode structure 6. The first P-type semiconductor layer 62 may be located on the side of the first N-type semiconductor layer 61 closest to the gate 43, and the first P-type semiconductor layer 62 is connected to the gate 43, thereby connecting the gate 43 to the anode of the diode structure 6.

[0032] like Figure 4As shown, the diode structure 6 may include a second N-type semiconductor layer 63 and a Schottky metal layer 64. Exemplarily, the second N-type semiconductor layer 63 may include a second N-type polysilicon layer, and the Schottky metal layer 64 may include a metal capable of forming a Schottky contact with the second N-type semiconductor layer 63. The second N-type semiconductor layer 63 and the Schottky metal layer 64 may be disposed between the shielding gate 31 and the gate 43. The second N-type semiconductor layer 63 may be located within the first trench 25, and the Schottky metal layer 64 may be located on the side of the first trench 25 away from the substrate 11. The second N-type semiconductor layer 63 may be located on the side of the Schottky metal layer 64 closest to the shielding gate 31, and the second N-type semiconductor layer 63 may be connected to the shielding gate 31, thereby connecting the shielding gate 31 to the negative electrode of the diode structure 6. The Schottky metal layer 64 may be located on the side of the second N-type semiconductor layer 63 closest to the gate 43, and the Schottky metal layer 64 is connected to the gate 43, thereby connecting the gate 43 to the anode of the diode structure 6. The Schottky metal layer 64 and the second N-type semiconductor layer 63 form a Schottky contact, so that there is a Schottky diode between the gate 43 and the shielding gate 31, that is, the diode structure 6 includes a Schottky diode at this time.

[0033] Optionally, based on the above embodiments, refer to... Figures 1-4 The doping concentration of the first N-type semiconductor layer 61 is lower than that of the shielding gate 31, and the doping concentration of the second N-type semiconductor layer 63 is lower than that of the shielding gate 31.

[0034] Specifically, the diode structure 6 may include a first N-type semiconductor layer 61 and a first P-type semiconductor layer 62. The doping concentration of the first N-type semiconductor layer 61 can be lower than the doping concentration of the shielding gate 31, i.e., the doping concentration of the first N-type semiconductor layer 61 is set to be relatively low. The potentials of the shielding gate 31 and the gate 43 are similar. The diode structure 6 introduced between the gate 43 and the shielding gate 31 has a PN junction barrier capacitance. The total capacitance between the gate 43 and the drain 42 can be formed by connecting the barrier capacitance between the first N-type semiconductor layer 61 and the first P-type semiconductor layer 62, and the capacitance of the shielding gate insulating layer 33 between the shielding gate 31 and the drain 42 in series. The formula for calculating the total capacitance between the gate 43 and the drain 42 is:

[0035] in, This refers to the total capacitance between the gate 43 and the drain 42 when the diode structure 6 consists of a first N-type semiconductor layer 61 and a first P-type semiconductor layer 62. This is the barrier capacitance between the first N-type semiconductor layer 61 and the first P-type semiconductor layer 62. The capacitance of the shielding gate insulating layer 33 between the shielding gate 31 and the drain 42 is relatively large. Taking its reciprocal results in a very small number, which can be eliminated. The final total capacitance between the gate 43 and the drain 42 is the barrier capacitance between the first N-type semiconductor layer 61 and the first P-type semiconductor layer 62. Since the doping concentration of the first N-type semiconductor layer 61 is low, the barrier capacitance between the first N-type semiconductor layer 61 and the first P-type semiconductor layer 62 is extremely low. Therefore, the gate-drain capacitance of the semiconductor device provided in this embodiment is extremely low. Compared with conventional shielded-gate MOSFET devices, since the shielding gate 31 is not connected to the source 41, this embodiment can effectively reduce the gate-source capacitance. Since the input capacitance of the device is the sum of the gate-source capacitance and the gate-drain capacitance, this embodiment can also effectively reduce the input capacitance of the device. The novel structure of the semiconductor device provided in this embodiment achieves a trade-off between forward conduction characteristics and capacitance characteristics, thereby obtaining a lower figure of merit (FOM).

[0036] The diode structure 6 may include a second N-type semiconductor layer 63 and a Schottky metal layer 64. The doping concentration of the second N-type semiconductor layer 63 can be lower than the doping concentration of the shielding gate 31, i.e., the doping concentration of the second N-type semiconductor layer 63 is set to be relatively low. The potentials of the shielding gate 31 and the gate 43 are similar. The Schottky diode introduced between the gate 43 and the shielding gate 31 has a PN junction barrier capacitance. Therefore, the total capacitance between the gate 43 and the drain 42 can be formed by the barrier capacitance of the Schottky diode and the capacitance of the shielding gate insulating layer 33 between the shielding gate 31 and the drain 42, connected in series. The formula for calculating the total capacitance between the gate 43 and the drain 42 is:

[0037] in, This refers to the total capacitance between the gate 43 and the drain 42 when the diode structure 6 consists of a second N-type semiconductor layer 63 and a Schottky metal layer 64. This is the barrier capacitance of a Schottky diode. The capacitance of the shielding gate insulating layer 33 between the shielding gate 31 and the drain 42 is relatively large. Taking its reciprocal results in a very small value, which can be eliminated. The final total capacitance between the gate 43 and the drain 42 is the barrier capacitance of the Schottky diode. Furthermore, due to the low doping concentration of the second N-type semiconductor layer 63, the barrier capacitance of the Schottky diode is extremely low. Therefore, the gate-drain capacitance of the semiconductor device provided in this embodiment is extremely low. Compared to conventional shielded-gate MOSFET devices, since the shielding gate 31 is not connected to the source 41, this embodiment can effectively reduce the gate-source capacitance. Since the input capacitance of the device is the sum of the gate-source capacitance and the gate-drain capacitance, this embodiment can also effectively reduce the input capacitance of the device, thus improving the device's capacitance characteristics. The novel structure of the semiconductor device provided in this embodiment achieves a trade-off between forward conduction characteristics and capacitance characteristics, thereby obtaining a lower figure of merit (FOM).

[0038] Optionally, based on the above embodiments, refer to... Figures 1-4 The semiconductor device further includes a second region 24. The second region 24 is configured with a second conductivity type and is located on the side of the body region 22 away from the substrate 11, and on the side of the first region 23 away from the first trench 25. The source electrode 41 is in contact with the second region 24.

[0039] Specifically, the cell 30 of the semiconductor device may further include a second region 24. For an N-channel shielded gate MOSFET device, the second region 24 is a P++ doped region; for a P-channel shielded gate MOSFET device, the second region 24 is an N++ doped region. The doping concentration of the second region 24 can be greater than that of the body region 22, allowing it to form a good ohmic contact with the source 41.

[0040] Optionally, based on the above embodiments, refer to... Figures 1-4 The semiconductor device further includes a shielding gate insulating layer 33, an isolation insulating layer 34, and a control gate insulating layer 35. The shielding gate insulating layer 33 is located at the bottom of the first trench 25 and at least a portion of the sidewalls near the substrate 11. The shielding gate 31 is located on the side of the shielding gate insulating layer 33 away from the substrate 11. The isolation insulating layer 34 is located on the side of the shielding gate 31 away from the substrate 11. Along a first direction X, the control gate insulating layer 35 is located on the sidewalls of the first trench 25 not covered by the shielding gate insulating layer 33 and the isolation insulating layer 34; along a second direction Y, the control gate insulating layer 35 is also located on the sidewalls of the diode structure 6 away from the semiconductor body 2. The control gate 32 is located on the side of the isolation insulating layer 34 away from the substrate 11 and on the side of the control gate insulating layer 35 away from the semiconductor body 2.

[0041] Specifically, the cell 30 of the semiconductor device may further include a shielding gate insulating layer 33, an isolation insulating layer 34, and a control gate insulating layer 35. For example... Figure 2 As shown, along the first direction X, the shielding gate insulating layer 33 may be located at the bottom of the first trench 25 and a portion of the sidewall of the first trench 25 near the substrate 11. Figure 3 and Figure 4 As shown, along the second direction Y, the shielding gate insulating layer 33 can be located on both sides of the first trench 25. The shielding gate 31 can be located on the side of the shielding gate insulating layer 33 away from the substrate 11.

[0042] The isolation insulating layer 34 can be located on the side of the shielding gate 31 away from the substrate 11. Along the first direction X, the isolation insulating layer 34 can extend to cover the shielding gate 31 and the shielding gate insulating layer 33. Along the second direction Y, the isolation insulating layer 34 can cover a portion of the shielding gate 31.

[0043] Along the first direction X, the control gate insulating layer 35 can be located on the sidewall of the first trench 25 not covered by the isolation insulating layer 34 and the shielding gate insulating layer 33. Along the second direction Y, the length of the control gate 32 is less than the length of the shielding gate 31. Along the second direction Y, the shielding gate insulating layer 33 can be located on the entire sidewall of the first trench 25. The diode structure 6 can be located on the side of the shielding gate insulating layer 33 closest to the control gate 32. The control gate insulating layer 35 can be located on the sidewall of the diode structure 6 closest to the control gate 32. That is, the diode structure 6 is located between the control gate insulating layer 35 and the shielding gate insulating layer 33, and on the side of the control gate insulating layer 35 furthest from the control gate 32. The vertical projection of the diode structure 6 onto the substrate 11 can partially cover the vertical projection of the shielding gate 31 onto the substrate 11.

[0044] Optionally, based on the above embodiments, refer to... Figures 1-4The semiconductor device further includes a first insulating layer 51. The first insulating layer 51 is located on the side of the semiconductor body 2 away from the substrate 11, and both the source electrode 41 and the gate electrode 43 are located on the side of the first insulating layer 51 away from the substrate 11. Along the first direction X, source contact holes 511 are provided on both sides of the first insulating layer 51, and the vertical projection of the source contact holes 511 onto the substrate 11 covers a portion of the vertical projection of the source electrode 41 onto the substrate 11. The source electrode 41 extends to the source contact holes 511 and contacts the first region 23. Along the second direction Y, first gate contact holes 512 are provided on both sides of the first insulating layer 51, and the vertical projection of the first gate contact holes 512 onto the substrate 11 covers a portion of the gate electrode 43 and a portion of the vertical projection of the control gate 32 onto the substrate 11. The gate electrode 43 extends into the first gate contact holes 512 and connects to the control gate 32. Along the second direction Y, a second gate contact hole 513 is further provided on the side of the first insulating layer 51 away from the first gate contact hole 512. The vertical projection of the second gate contact hole 513 onto the substrate 11 covers a portion of the gate 43 and at least a portion of the diode structure 6 onto the substrate 11. The gate 43 extends to the second gate contact hole 513 and connects to the first P-type semiconductor layer 62, which in turn connects to the first N-type semiconductor layer 61. Alternatively, a Schottky metal layer 64 is provided within the second gate contact hole 513, and the Schottky metal layer 64 connects to the second N-type semiconductor layer 63.

[0045] Specifically, the cell 30 of the semiconductor device may also include a first insulating layer 51, which may be located on the side of the semiconductor body 2 away from the substrate 11, and the source 41 and the gate 43 may be spaced apart on the side of the first insulating layer 51 away from the substrate 11.

[0046] like Figure 2 As shown, source contact holes 511 can be provided on both sides of the first insulating layer 51 along the first direction X. The source contact holes 511 can be located between the source electrode 41 and the semiconductor body 2. The source electrode 41 can extend to the source contact holes 511 to contact the first region 23 and the second region 24.

[0047] like Figure 3 and Figure 4 As shown, along the second direction Y, first gate contact holes 512 can also be provided on both sides of the first insulating layer 51. The first gate contact holes 512 can be located between the gate 43 and the control gate 32. The gate 43 can extend into the first gate contact hole 512 and contact the control gate 32.

[0048] like Figure 3As shown, along the second direction Y, two second gate contact holes 513 are also provided on the side of the first insulating layer 51 away from the first gate contact hole 512. The second gate contact holes 513 are located between the gate 43 and the diode structure 6. The gate 43 can extend into the second gate contact holes 513 and connect to the first P-type semiconductor layer 62, that is, the gate 43 is connected to the positive electrode of the diode structure 6.

[0049] like Figure 4 As shown, along the second direction Y, two second gate contact holes 513 are also provided on the side of the first insulating layer 51 away from the first gate contact hole 512. The second gate contact holes 513 are located between the gate 43 and the second N-type semiconductor layer 63. A Schottky metal layer 64 may be disposed within the second gate contact hole 513, and the Schottky metal layer 64 forms a Schottky contact with the second N-type semiconductor layer 63. The gate 43 is in contact with the Schottky metal layer 64 within the second gate contact hole 513, that is, the gate 43 is connected to the positive electrode of the diode structure 6.

[0050] Figure 5 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. Figures 6-9 This is a schematic diagram of some steps in a method for fabricating a semiconductor device according to an embodiment of the present invention, as shown below. Figure 5 As shown, the preparation method includes: S100: Provides a substrate, which is configured as a first conductivity type.

[0051] Specifically, such as Figure 6 As shown, a substrate 11 is first provided. For an N-channel shielded gate MOSFET device, the substrate 11 is an N-type substrate, and for a P-channel shielded gate MOSFET device, the substrate 11 is a P-type substrate.

[0052] S110: A semiconductor body is formed on one side of a substrate. The semiconductor body includes a drift region, a body region, and a first region. The drift region is configured with a first conductivity type and is located on the side of the semiconductor body closer to the substrate. The body region is configured with a second conductivity type and is located on the side of the drift region farther from the substrate. The first region is configured with a first conductivity type and is located on the side of the body region farther from the substrate. The first conductivity type is different from the second conductivity type. A first trench is also provided in the middle region of the semiconductor body. The first trench penetrates the first region and the body region and extends to the drift region. Along a first direction, the body region and the first region are located on both sides of the first trench. The first direction is parallel to the substrate.

[0053] Specifically, such as Figure 6As shown, a semiconductor body 2 is formed on one side of a substrate 11. An epitaxial layer can be formed first on one side of the substrate 11, with the doping type of the epitaxial layer matching that of the substrate 11. Then, processes such as doping and annealing, or etching and deposition, are used to form a body region 22, a first region 23, and a second region 24. The untreated epitaxial layer serves as a drift region 21. For an N-channel shielded gate MOSFET device, drift region 21 is an N-type drift region, body region 22 is a P-type body region, first region 23 is an N++ doped region, and second region 24 is a P++ doped region. For a P-channel shielded gate MOSFET device, drift region 21 is a P-type drift region, body region 22 is an N-type body region, first region 23 is a P++ doped region, and second region 24 is an N++ doped region. Then, a first trench 25 is formed in the middle region of the semiconductor body 2 using photolithography and etching processes.

[0054] S120: A shielding gate and a control gate are formed in the first trench; the shielding gate and the control gate are spaced apart in the first trench along a direction perpendicular to the substrate; the shielding gate is located between the substrate and the control gate.

[0055] Specifically, such as Figure 7 As shown, a shielding gate 31 and a control gate 32 are formed in the first trench 25. Along the direction perpendicular to the substrate 11, the shielding gate 31 and the control gate 32 can be provided insulatedly at intervals inside the first trench 25. The shielding gate 31 can be located between the control gate 32 and the drain 42.

[0056] S130: A diode structure is formed on both sides of the control gate along the second direction; and at least a portion of the diode structure is located in the first trench, the second direction is parallel to the substrate, and the first direction is perpendicular to the second direction.

[0057] Specifically, such as Figure 8 and Figure 9 As shown, diode structures 6 can be formed on both sides of the control gate 32 along the second direction Y, and the shielding gate 31 can be connected to the negative terminal of the diode structure 6. The diode structure 6 can be located inside the first trench 25, or a portion of the diode structure 6 can be located inside the first trench 25, with the remainder extending outside the first trench 25.

[0058] S140: A source and a gate are formed on the side of the semiconductor body away from the substrate, the source and the gate are spaced apart, and the gate surrounds the source; the source is connected to the first region, the gate is connected to the control gate; and the gate is connected to the positive terminal of the diode structure, and the shielding gate is connected to the negative terminal of the diode. Specifically, such as Figures 1-4As shown, a source 41 and a gate 43 are formed at intervals on the side of the semiconductor body 2 away from the substrate 11. The gate 43 can be connected to the positive terminal of the diode structure 6, that is, the shielding gate 31 is connected to the gate 43 through the diode structure 6, and the shielding gate 31 is not connected to the source 41.

[0059] S150: A drain is formed on the side of the substrate away from the semiconductor body.

[0060] Specifically, such as Figures 1-4 As shown, a drain 42 is formed on the side of the substrate 11 away from the semiconductor body 2.

[0061] For an N-channel shielded gate MOSFET device, a diode structure 6 is disposed between the gate 43 and the shielding gate 31. When the device is forward-biased, the drain 42 is connected to a high potential, the source 41 is connected to a low potential, and the gate 43 is connected to a high potential. The diode structure 6 can conduct in the forward direction and has a very low forward voltage drop. The potential of the shielding gate 31 is raised to the voltage of the gate 43 minus the forward voltage drop of the diode structure 6. At this time, under the action of the control gate 32, an inversion layer channel is formed in the body region 22 near the sidewall of the control gate 32, enabling the device to conduct in the forward direction. Electrons flow from the source 41 through the conduction channel to the drain 42. Since the potential of the shielding gate 31 is effectively raised, an electron accumulation layer with high carrier concentration is formed on the sidewall of the shielding gate insulating layer 33, thereby effectively reducing the forward conduction resistance of the device, i.e., effectively reducing the forward conduction voltage drop of the device. When the device is reverse-blocked, drain 42 is connected to a high potential, source 41 is connected to a low potential, and gate 43 is connected to a low potential. Diode structure 6 is reverse-blocked, and the potential of shielding gate 31 drops to a low potential, causing lateral depletion of the drift region 21. Shielding gate 31 couples with the drift region 21, inducing a space charge region in the drift region 21, forming a lateral depletion region extending laterally along the device. This lateral depletion region effectively widens the depletion region width under reverse-blocking conditions, homogenizes the electric field distribution within the drift region 21, eliminates electric field spikes at the edge of control gate 32, thereby significantly improving the device's breakdown voltage and suppressing parasitic leakage current, achieving excellent reverse-blocking characteristics. When the device is reverse-blocked, the breakdown voltage principle of the device is far from the same as that of a conventional shielded gate MOSFET, and the reverse-blocking characteristics of the device provided in this embodiment are unaffected.

[0062] For a P-channel shielded gate MOSFET device, a diode structure 6 is disposed between the gate 43 and the shielded gate 31. When the device is forward-biased, the drain 42 is connected to a low potential, the source 41 is connected to a high potential, and the gate 43 is connected to a low potential. The diode structure 6 is reverse-biased and cut off, at which time the potential of the shielded gate 31 is low. At this time, under the action of the control gate 32, an inversion layer channel is formed in the body region 22 near the sidewall of the control gate 32, enabling the device to conduct forward. Holes flow from the source 41 through the conduction channel to the drain 42. Since the potential of the shielded gate 31 is low, a hole accumulation layer with a high carrier concentration is formed on the sidewall of the shielded gate insulating layer 33, thereby effectively reducing the forward conduction resistance of the device, that is, effectively reducing the forward conduction voltage drop of the device. When the device is reverse-blocked, drain 42 is connected to a low potential, source 41 is connected to a high potential, and gate 43 is connected to a high potential. Diode structure 6 can conduct in the forward direction. Diode structure 6 has a very low forward voltage drop. The potential of shielding gate 31 is raised to the voltage obtained by subtracting the forward conduction voltage drop of diode structure 6 from the voltage of gate 43. Shielding gate 31 induces lateral depletion in drift region 21. Shielding gate 31 couples with drift region 21, inducing a space charge region in drift region 21, forming a lateral depletion region extending laterally along the device. This lateral depletion region effectively widens the depletion region width in the reverse-blocking state, homogenizes the electric field distribution within drift region 21, eliminates electric field spikes at the edge of control gate 32, thereby significantly improving the breakdown voltage of the device and suppressing parasitic leakage current, achieving excellent reverse-blocking characteristics. When the device is reverse-blocked, the breakdown voltage principle of the device is far from the breakdown voltage of a conventional shielded gate MOSFET, and the reverse-blocking characteristics of the device provided in this embodiment are not affected.

[0063] Optionally, based on the above embodiments, Figure 10 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention. Figures 11-27 This is a schematic diagram of some steps in another method for fabricating a semiconductor device provided in this embodiment of the invention, as shown below. Figure 10 The preparation method includes: S200: Provides a substrate, which is configured as a first conductivity type.

[0064] S210: An epitaxial layer of a first conductivity type is formed on one side of the substrate; a first trench is provided in the middle region of the epitaxial layer.

[0065] Specifically, such as Figure 11 and Figure 12 As shown, an epitaxial layer 26 of the first conductivity type is formed on one side of a highly doped first conductivity type substrate 11. The doping concentration of the epitaxial layer 26 is determined by the device breakdown voltage. A first trench 25 is etched in the epitaxial layer 26 using processes such as photolithography and etching.

[0066] S220: A shielding grid insulation layer is formed at the bottom of the first trench and along the entire sidewall.

[0067] Specifically, such as Figure 13 and Figure 14 As shown, a shielding grid insulation layer 33 is formed on the entire sidewall of the first trench 25 by deposition or thermal oxidation.

[0068] S230: A shielding gate is formed on the side of the shielding gate insulating layer away from the substrate and within a first trench.

[0069] Specifically, such as Figures 15-18 As shown, a shielding gate 31 is formed on the side of the shielding gate insulating layer 33 away from the substrate 11 and within the first trench 25.

[0070] S240: A first N-type semiconductor layer is formed on the side of the shielding gate away from the substrate, and a first P-type semiconductor layer is formed on the side of the first N-type semiconductor layer away from the substrate; the side of the first P-type semiconductor layer away from the substrate is on the same horizontal plane as the side of the epitaxial layer away from the substrate; or, a second N-type semiconductor layer is formed on the side of the shielding gate away from the substrate; the side of the second N-type semiconductor layer away from the substrate is on the same horizontal plane as the side of the epitaxial layer away from the substrate.

[0071] Specifically, such as Figure 15 and Figure 16 As shown, the diode structure 6 may include a first N-type semiconductor layer 61 and a first P-type semiconductor layer 62. The first N-type semiconductor layer 61 is formed on the side of the shielding gate 31 away from the substrate 11, and the first P-type semiconductor layer 62 is formed on the side of the first N-type semiconductor layer 61 away from the substrate 11. For example, the first trench 25 is sequentially filled with highly doped N-type polysilicon as the shielding gate 31, lightly doped N-type polysilicon as the first N-type semiconductor layer 61, and highly doped P-type polysilicon as the first P-type semiconductor layer 62.

[0072] like Figure 17 and Figure 18 As shown, the diode structure 6 may include a second N-type semiconductor layer 63 and a Schottky metal layer, with the second N-type semiconductor layer 63 formed on the side of the shielding gate 31 away from the substrate 11. The side of the second N-type semiconductor layer 63 away from the substrate 11 may be at the same horizontal plane as the side of the epitaxial layer 26 away from the substrate 11. For example, highly doped N-type polysilicon is sequentially filled in the first trench 25 as the shielding gate 31 and lightly doped N-type polysilicon as the second N-type semiconductor layer 63.

[0073] S250: Etch the first N-type semiconductor layer and the first P-type semiconductor layer, retaining the first N-type semiconductor layer and the first P-type semiconductor layer at both sides of the shielding gate along the second direction; or, etch the second N-type semiconductor layer, retaining the second N-type semiconductor layer at both sides of the shielding gate along the second direction.

[0074] Specifically, such as Figure 19 and Figure 20 As shown, the first N-type semiconductor layer 61 and the first P-type semiconductor layer 62 are etched, while the first N-type semiconductor layer 61 and the first P-type semiconductor layer 62 along the two sides of the second direction Y-shielding gate 31 are retained. For example, using photolithography and polysilicon etch-back, only the low-doped N-type polysilicon and the high-doped P-type polysilicon at the edges of the strip cell are retained, while the low-doped N-type polysilicon and the high-doped P-type polysilicon in the remaining areas of the strip cell are etched away.

[0075] Or, such as Figure 19 and Figure 21 As shown, the second N-type semiconductor layer 63 is etched, and the second N-type semiconductor layer 63 is retained on both sides of the shielding gate 31 along the second direction Y.

[0076] S260: Remove the shielding grid insulation layer from a portion of the sidewall of the first trench along the first direction.

[0077] Specifically, such as Figure 22 As shown, the shielding grid insulation layer 33 of part of the sidewalls of the first trench 25 along the first direction X is removed by photolithography and etching processes.

[0078] S270: An insulating layer is formed on the side of the shielding gate away from the substrate.

[0079] Specifically, such as Figures 23-25 As shown, an isolation oxide layer 34 is formed between the shielding gate 31 and the control gate using processes such as thermal oxidation. Along the first direction X, the isolation insulation layer 34 can extend to cover the shielding gate 31 and the shielding gate insulation layer 33, and along the second direction Y, the isolation insulation layer 34 can cover a portion of the shielding gate 31.

[0080] S280: Along a first direction, a control gate insulating layer is formed on a portion of the sidewall of the first trench, and along a second direction, a control gate insulating layer is formed on the sidewall of the diode structure away from the epitaxial layer.

[0081] Specifically, such as Figures 23-25 As shown, using processes such as thermal oxidation, a control gate insulating layer 35 is formed on a portion of the sidewall of the first trench 25 along the first direction X, and a control gate insulating layer 35 is formed on the sidewall of the diode structure 6 away from the epitaxial layer 26 along the second direction Y.

[0082] The epitaxial layer 26 can be made of doped single-crystal silicon, and the first N-type semiconductor layer 61 and the first P-type semiconductor layer 62, or the second N-type semiconductor layer 63, can be made of doped polycrystalline silicon, such as... Figure 23 As shown, along the first direction X, a portion of the control gate insulating layer 35 can be formed by thermally oxidizing the epitaxial layer 26 of the sidewall of the first trench 25. For example... Figure 24 As shown, along the second direction Y, the remaining portion of the control gate insulating layer 35 can be formed by thermally oxidizing the first N-type semiconductor layer 61 and the first P-type semiconductor layer 62, or, as... Figure 25 As shown, along the second direction Y, the remaining portion of the control gate insulating layer 35 can be formed by thermally oxidizing the second N-type semiconductor layer 63.

[0083] Since the thermal oxidation rate of polycrystalline silicon is faster than that of monocrystalline silicon, the thickness of the control gate insulating layer 35 formed by thermal oxidation of the sidewall of the diode structure 6 along the second direction Y is greater than the thickness of the control gate insulating layer 35 formed by thermal oxidation of the epitaxial layer 26 along the first direction X.

[0084] S290: A control gate is formed on the side of the isolation insulating layer away from the substrate and on the side of the control gate insulating layer away from the epitaxial layer.

[0085] Specifically, such as Figure 26 and Figure 27 As shown, a control gate 32 is formed on the side of the isolation insulating layer 34 away from the substrate 11 and on the side of the control gate insulating layer 35 away from the epitaxial layer 26. Exemplarily, control gate polysilicon is deposited and chemical mechanical polishing (CMP) is performed on the chip surface to remove the exposed polysilicon layer, thereby forming the control gate 32.

[0086] Along the first direction X, the control gate insulating layer 35 can be located on the sidewall of the first trench 25 that is not covered by the isolation insulating layer 34 and the shielding gate insulating layer 33. Along the second direction Y, the length of the control gate 32 is less than the length of the shielding gate 31. Along the second direction Y, the shielding gate insulating layer 33 can be located on the entire sidewall of the first trench 25. The diode structure 6 can be located on the side of the shielding gate insulating layer 33 that is close to the control gate 32. The control gate insulating layer 35 can be located on the sidewall of the diode structure 6 that is close to the control gate 32. That is, the diode structure 6 is located between the control gate insulating layer 35 and the shielding gate insulating layer 33. The diode structure 6 is located on the side of the control gate insulating layer 35 that is away from the control gate 32.

[0087] S291: Along the first direction, a body region and a first region are formed on both sides of the first trench using a doping process; the undoped epitaxial layer serves as a drift region.

[0088] Specifically, such as Figure 7As shown, bulk region 22, first region 23, and second region 24 are formed through processes such as photolithography and ion implantation. The undoped epitaxial layer serves as drift region 21.

[0089] S292: A first insulating layer is formed on the side of the semiconductor body away from the substrate; along a first direction, source contact holes are provided on both sides of the first insulating layer, and the vertical projection of the source contact holes onto the substrate covers a portion of the vertical projection of the source onto the substrate; along a second direction, a first gate contact hole is provided on both sides of the first insulating layer, and the vertical projection of the first gate contact hole onto the substrate covers a portion of the gate and a portion of the vertical projection of the control gate onto the substrate; along the second direction, a second gate contact hole is also provided on the side of the first insulating layer away from the first gate contact hole, and the vertical projection of the second gate contact hole onto the substrate covers a portion of the gate and at least a portion of the vertical projection of the diode structure onto the substrate.

[0090] Specifically, such as Figures 2-4 As shown, a first insulating layer is deposited on the side of the semiconductor body 2 away from the substrate 11, and source contact hole 511, first gate contact hole 512 and second gate contact hole 513 are formed by photolithography and etching processes.

[0091] S293: A source electrode is formed in a portion of the first insulating layer on the side away from the substrate, and within the source contact hole; the source electrode extends to the source contact hole and contacts the first region.

[0092] Specifically, such as Figures 2-4 As shown, metal is deposited and source electrode 41 is formed using processes such as photolithography and etching. The source electrode extends to the source electrode contact hole and contacts the first region.

[0093] S294: A gate is formed in the remaining portion of the first insulating layer on the side away from the substrate, and in the first gate contact hole and the second gate contact hole; the gate extends into the first gate contact hole and is connected to the control gate, and the gate extends into the second gate contact hole and is connected to the first P-type semiconductor layer; or, a Schottky metal layer is formed in the second gate contact hole, and the Schottky metal layer is connected to the second N-type semiconductor layer; a gate is formed in the remaining portion of the first insulating layer on the side away from the substrate, and in the first gate contact hole; the gate is connected to the Schottky metal layer.

[0094] Specifically, such as Figures 2-4 As shown, the diode structure 6 may include a first N-type semiconductor layer 61 and a first P-type semiconductor layer 62. Metal is deposited therein, and a gate 43 is formed using processes such as photolithography and etching. The gate 43 extends into the first gate contact hole 512 and is connected to the control gate 32. The gate 43 extends into the second gate contact hole 513 and is connected to the first P-type semiconductor layer 62.

[0095] The diode structure 6 may include a second N-type semiconductor layer 63 and a Schottky metal layer 64. The Schottky metal layer 64 is formed within the second gate contact hole 513 and is connected to the second N-type semiconductor layer 63. Metal is deposited, and a gate 43 is formed using photolithography and etching processes. The gate 43 extends into the first gate contact hole 512 and connects to the control gate 32, and is also connected to the Schottky metal layer 64.

[0096] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0097] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A semiconductor device, characterized in that, include: The substrate is configured with the first conductivity type. A semiconductor body is located on one side of the substrate; the semiconductor body includes a drift region, a body region, and a first region; the drift region is configured with a first conductivity type and is located on the side of the semiconductor body closer to the substrate; the body region is configured with a second conductivity type and is located on the side of the drift region farther from the substrate; the first region is configured with the first conductivity type and is located on the side of the body region farther from the substrate; the first conductivity type is different from the second conductivity type; a first trench is further provided in the middle region of the semiconductor body, the first trench penetrating the first region and the body region and extending to the drift region; along a first direction, the body region and the first region are both located on both sides of the first trench; the first direction is parallel to the substrate; A shielding gate and a control gate are located within the first trench, spaced apart along a direction perpendicular to the substrate. The shielding gate is located between the substrate and the control gate; The semiconductor body includes a source, a drain, and a gate, wherein the source and the gate are spaced apart on the side of the semiconductor body away from the substrate, and the gate surrounds the source. The drain is located on the side of the substrate away from the semiconductor body; the source is connected to the first region, and the gate is connected to the control gate; A diode structure, along a second direction, is located on both sides of the control gate, and at least a portion of the diode structure is located within the first trench; the gate is connected to the positive terminal of the diode structure, and the shielding gate is connected to the negative terminal of the diode structure; the second direction is parallel to the substrate, and the first direction is perpendicular to the second direction.

2. The semiconductor device according to claim 1, characterized in that, The shielding grid includes an N-type shielding grid; The diode structure includes a first N-type semiconductor layer and a first P-type semiconductor layer; the first N-type semiconductor layer and the first P-type semiconductor layer are stacked and disposed between the shielding gate and the gate along a direction perpendicular to the substrate; the shielding gate is connected to the first N-type semiconductor layer, and the gate is connected to the first P-type semiconductor layer; Alternatively, the diode structure includes a second N-type semiconductor layer and a Schottky metal layer; the second N-type semiconductor layer and the Schottky metal layer are stacked between the shielding gate and the gate along a direction perpendicular to the substrate; the shielding gate is connected to the second N-type semiconductor layer, and the gate is connected to the Schottky metal layer.

3. The semiconductor device according to claim 2, characterized in that, The doping concentration of the first N-type semiconductor layer is lower than that of the shielding gate, and the doping concentration of the second N-type semiconductor layer is lower than that of the shielding gate.

4. The semiconductor device according to claim 1, characterized in that, Also includes: Second area; The second region is configured with a second conductivity type, and the second region is located on the side of the body region away from the substrate, and the second region is located on the side of the first region away from the first trench; the source electrode is in contact with the second region.

5. The semiconductor device according to claim 1, characterized in that, Also includes: Shielding barrier insulation layer, isolation insulation layer, and control barrier insulation layer; The shielding gate insulating layer is located at the bottom of the first trench and at least a portion of the sidewalls near the substrate, with the shielding gate located on the side of the shielding gate insulating layer away from the substrate; the isolation insulating layer is located on the side of the shielding gate away from the substrate. Along the first direction, the control gate insulating layer is located on the sidewall of the first trench that is not covered by the shielding gate insulating layer and the isolation insulating layer; along the second direction, the control gate insulating layer is also located on the sidewall of the diode structure away from the semiconductor body; the control gate is located on the side of the isolation insulating layer away from the substrate, and on the side of the control gate insulating layer away from the semiconductor body.

6. The semiconductor device according to claim 5, characterized in that, Along the second direction, the length of the control gate is less than the length of the shielding gate; the diode structures located on both sides of the control gate are located on the side of the control gate insulating layer away from the control gate; Along the second direction, the shielding gate insulating layer is located on the entire sidewall of the first trench, the diode structure is located between the control gate insulating layer and the shielding gate insulating layer, and the vertical projection of the diode structure on the substrate covers a portion of the vertical projection of the shielding gate on the substrate.

7. The semiconductor device according to claim 2, characterized in that, Also includes: First insulating layer; The first insulating layer is located on the side of the semiconductor body away from the substrate, and both the source and the gate are located on the side of the first insulating layer away from the substrate; Along the first direction, source contact holes are provided on both sides of the first insulating layer, and the vertical projection of the source contact holes on the substrate covers a portion of the vertical projection of the source electrode on the substrate; the source electrode extends to the source contact holes and contacts the first region; Along the second direction, first gate contact holes are provided on both sides of the first insulating layer. The vertical projection of the first gate contact holes on the substrate covers a portion of the gate and a portion of the vertical projection of the control gate on the substrate. The gate extends into the first gate contact holes and connects to the control gate. Along the second direction, a second gate contact hole is further provided on the side of the first insulating layer away from the first gate contact hole, and the vertical projection of the second gate contact hole on the substrate covers a portion of the gate and at least a portion of the vertical projection of the diode structure on the substrate. The gate extends to the second gate contact hole and is connected to the first P-type semiconductor layer, and the first P-type semiconductor layer is connected to the first N-type semiconductor layer; or, the Schottky metal is disposed in the second gate contact hole and is connected to the second N-type semiconductor layer.

8. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate being configured with a first conductivity type; A semiconductor body is formed on one side of the substrate. The semiconductor body includes a drift region, a body region, and a first region. The drift region is configured with a first conductivity type and is located on the side of the semiconductor body closer to the substrate. The body region is configured with a second conductivity type and is located on the side of the drift region farther from the substrate. The first region is configured with the first conductivity type and is located on the side of the body region farther from the substrate. The first conductivity type is different from the second conductivity type. A first trench is also provided in the middle region of the semiconductor body. The first trench penetrates the first region and the body region and extends to the drift region. Along a first direction, the body region and the first region are located on both sides of the first trench. The first direction is parallel to the substrate. A shielding gate and a control gate are formed within the first trench; the shielding gate and the control gate are spaced apart within the first trench along a direction perpendicular to the substrate; The shielding gate is located between the substrate and the control gate; Along a second direction, diode structures are formed on both sides of the control gate; and at least a portion of the diode structures are located within the first trench; The second direction is parallel to the substrate, and the first direction is perpendicular to the second direction; A source and a gate are formed on the side of the semiconductor body away from the substrate, the source and the gate are spaced apart, and the gate surrounds the source; the source is connected to the first region, the gate is connected to the control gate; and the gate is connected to the positive terminal of the diode structure, and the shielding gate is connected to the negative terminal of the diode structure. A drain is formed on the side of the substrate away from the semiconductor body.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The semiconductor device further includes a shielding gate insulating layer, an isolation insulating layer, and a control gate insulating layer; a semiconductor body is formed on one side of the substrate, a shielding gate and a control gate are formed in the first trench, and a diode structure is formed on both sides of the control gate, including: An epitaxial layer of a first conductivity type is formed on one side of the substrate; the first trench is provided in the middle region of the epitaxial layer; The shielding grid insulation layer is formed at the bottom and along the entire sidewall of the first trench; The shielding gate is formed on the side of the shielding gate insulating layer away from the substrate, and within the first trench; A first N-type semiconductor layer is formed on the side of the shielding gate away from the substrate, and a first P-type semiconductor layer is formed on the side of the first N-type semiconductor layer away from the substrate; the side of the first P-type semiconductor layer away from the substrate is on the same horizontal plane as the side of the epitaxial layer away from the substrate; or, a second N-type semiconductor layer is formed on the side of the shielding gate away from the substrate; the side of the second N-type semiconductor layer away from the substrate is on the same horizontal plane as the side of the epitaxial layer away from the substrate. Etch the first N-type semiconductor layer and the first P-type semiconductor layer, retaining the first N-type semiconductor layer and the first P-type semiconductor layer at both sides of the shielding gate along the second direction; or, etch the second N-type semiconductor layer, retaining the second N-type semiconductor layer at both sides of the shielding gate along the second direction. Remove the shielding grid insulation layer from a portion of the sidewall of the first trench along the first direction; The insulating layer is formed on the side of the shielding gate away from the substrate; Along the first direction, the control gate insulating layer is formed on a portion of the sidewall of the first trench, and along the second direction, the control gate insulating layer is formed on the sidewall of the diode structure away from the epitaxial layer; The control gate is formed on the side of the isolation insulating layer away from the substrate, and on the side of the control gate insulating layer away from the epitaxial layer; Along the first direction, the body region and the first region are formed on both sides of the first trench using a doping process; the undoped epitaxial layer serves as the drift region.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, Before forming the source and gate on the side of the semiconductor body away from the substrate, the method further includes: A first insulating layer is formed on the side of the semiconductor body away from the substrate; along the first direction, source contact holes are provided on both sides of the first insulating layer, and the vertical projection of the source contact holes on the substrate covers a portion of the vertical projection of the source electrode on the substrate; along the second direction, a first gate contact hole is provided on both sides of the first insulating layer, and the vertical projection of the first gate contact hole on the substrate covers a portion of the gate electrode and a portion of the vertical projection of the control gate on the substrate; along the second direction, a second gate contact hole is also provided on the side of the first insulating layer away from the first gate contact hole, and the vertical projection of the second gate contact hole on the substrate covers a portion of the gate electrode and at least a portion of the vertical projection of the diode structure on the substrate; A source electrode is formed on the side of the semiconductor body away from the substrate, including: The source electrode is formed in a portion of the first insulating layer on the side away from the substrate, and within the source contact hole; the source electrode extends to the source contact hole and contacts the first region; The diode structure includes a first N-type semiconductor layer and a first P-type semiconductor layer, with a gate formed on the side of the semiconductor body away from the substrate, including: The gate is formed in the remaining portion of the first insulating layer on the side away from the substrate, and in the first gate contact hole and the second gate contact hole; the gate extends into the first gate contact hole to connect with the control gate, and the gate extends into the second gate contact hole to connect with the first P-type semiconductor layer; Alternatively, the diode structure includes a second N-type semiconductor layer and a Schottky metal layer, with the diode structure formed on both sides of the control gate and a gate formed on the side of the semiconductor body away from the substrate, including: A Schottky metal layer is formed within the second gate contact hole, the Schottky metal layer being connected to the second N-type semiconductor layer; the gate is formed in the remaining portion of the first insulating layer on the side away from the substrate, and within the first gate contact hole; the gate extends into the first gate contact hole and is connected to the control gate, the gate being connected to the Schottky metal layer.

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